charge to digital converter with constant resolution · charge to digital converter with constant...
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Charge to digital converterwith constant resolution
A. NascettiDepartment of Aerospace and Astronautics Engineering
11th Topical Seminar onInnovative Particle and Radiation Detectors
(IPRD08) 1 - 4 October 2008 Siena, Italy
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Summary
Fractional Packet Counting
Constant Relative Resolution ADC
Implementation and results
Conclusions
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Charge Packet Counting Current to frequency conversion technique
Highly integrable Poor resolution at low current levels
CPC + measure of time between the first and the last packet Relative resolution almost constant Tsamp ≠ Teff = f(Iframe)
Post-processing needed: Iframe = (Qpacket x Npackets) / Teff
Readout of large amount of data/pixel
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Fractional Packet Counting Quantification of the last incomplete charge packet Signal charge expressed as a fractional number of packets
The signal integration time is constant and does not depend on the signal level
fractional part
0
integer part
11 0000000 0 1 1
conversion time
last incomplete charge packet
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
FPQ Conceptual Implementation CPC unit coupled to an ADC to quantify the last incomplete packet If ADC input range is equal to ∆Vpacket then the fractional representation
of the packet number is achieved Dynamic range = 22N Resolution: LSB = 2-N of a charge packet
integer part register
11 0000000
fractional part register
00 1 100 1 1
2N 2(N-1) … 21 20
2-1 2-2 … 2-(N-1) 2-N
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Consideration If two registers, one for the integer part and one for the
fractional part, are used a constant absolute resolution is achieved… however in applications like X-ray imaging this does not make sense because at high current levels (large number of integer counts) the signal quantum noise would affect the least significant bits while at low current levels the integer counts register would be almost emptyin addition this solution would require extra chip area and power, impacting on the design of a pixelated readout chip with a significant number of channelsalso the readout speed would be affected by the transmission of a large amount of useless data
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Constant number of significant digits A single output register can be used
Chip area benefit Readout benefit
The resolution of the fractional part ADC has to change according to the value of the input signal
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Binary point register
Additional register to store the position of the binary point to decode the output string correctly
The size of the binary point register is:BPbits=log2(Outputbits)
… hence N+log2N bits are required Dynamic range = 22N Resolution: LSB = 2-N of the MSB
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
FPQ sequence Count the complete charge packets Determine the number of bits “occupied” by the
integer part at the end of the sampling time Store the binary point position Change the fractional part ADC resolution
according to the number of “free” cells in the output register
A/D conversion of the last incomplete packet
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Counting complete charge packetsSwitched Integrator
Comparator with hysteresis
Counter
Integrator reset
feedback
Conventional folded cascode with feedback capacitor and reset switchComparator with hysteresis that determines the charge packet sizeFeedback loop to reset the integrator after each complete charge packetIt is actually the output register
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Determination of the binary point Localization of the most significant “1” in the integer part
Combinatory logic approaches require a lot of chip area
0 0 0 1 10 1 01Bits available for the
fractional part
N bits register
Encoder N : log2 N
log2 N bitsbinary point
register
N bits bus
log2 N bits bus
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Binary point sequential logic A very compact solution requires only:
an N bits output register with left shifting capability a counter as binary point register a logic AND-gate
0 0 0 1 10 1 0
0 00
LEFT SHIFT
INCR
N bits output register
log2 N bits binary point register
AND-gate
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Binary point logic operation At the end of the sampling time
the output register contains the number of complete charge packets
Shift actions are executed and counted until most significant “1” reaches the MSB position
The number of bits available for the fractional part is stored in the binary point register
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Binary point logic: comment Extremely compact solution that can be easily
implemented in each pixel using a global shift signal
The integer part occupies the MSBs positions
The binary point register in directly available
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Output register Synchronous counter
architecture Additional logic for T-type
to D-type flip-flop configuration switching and control of the input signal of each stage
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Fractional part ADC The fractional-part ADC must be able to change its resolution
dynamically Successive approximation approach Using a cyclic ADC each bit of the fractional part can be calculated
and stored during the shifting operation
0 1 1 1 00 0
0 10
cyclic ADC
Vlastpulse
from the first stage
start conversion(preparing the output
for the next step)
serialoutput
0/1
shift
0 0 0 1 10 1 0
0 00
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Cyclic ADC with threshold variation
Vth is compared with the Vlastpulse: the results represents the next bit and is used to set-up the next Vth
Vth-increment subcircuit
Vth-decrement subcircuit
Vth-accumulatorVlastpulse
Comparator
OutputShift
Register
The Vth generation sub-circuits perform voltage division by sharing a charge between two identical capacitors and adding or subtracting it on a storage capacitor
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Operation Storage capacitor reset
Vth=(Vmax+Vmin)/2 a) Vlastpulse compared to Vth
b) First bit of the fractional part calculated c) Next Vth generated
At the each clock the bit is shifted in the output register and next bit is prepared
At the end the fractional part is in the LSBs of the output register which now contains the fractional representation of the input signal
Vmax/4
Vmax/8Vmax/16
Vmax/32
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Results The circuit has
been implemented in TSMC035 technology
Simulations have been performed with Simetrix using BSIM3 models
The circuit performs correctly generating the right threshold valued
0000000100100011
111111101101110010111010100110000111011001010100
IRPD08 – A. Nascetti – School of Aerospace Engineering – Sapienza University of Rome
Conclusions A novel charge to digital converter has been presented The circuit relies on the fractional packet counting and
allows for constant relative resolution conversion This has been achieved using a single output register
in a dynamic way and adding a binary point register for the correct decoding of the output signal
A compact solution has been found to set the binary point register and at the same time calculate the fractional part by successive approximations using a cyclic ADC