characterization of gan- based hemts for power electronics
TRANSCRIPT
IN DEGREE PROJECT ENGINEERING PHYSICS,SECOND CYCLE, 30 CREDITS
, STOCKHOLM SWEDEN 2020
Characterization of GaN-based HEMTs for power electronics
XIAOMIN LIANG
KTH ROYAL INSTITUTE OF TECHNOLOGYSCHOOL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
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This master thesis project was performed in collaboration with
KTH Royal Institute of Technology Research Institutes of Sweden
Characterization of GaN-based HEMTs for
power electronics
XIAOMIN LIANG
Master of Science Thesis
Supervisor: Dr. Qin Wang (RISE)
Academic supervisor: Prof. Anders Hallén (KTH)
Examiner: Prof. Mattias Hammar (KTH)
School of Electrical Engineering and Computer Science (EECS)
Royal Institute of Technology (KTH)
Stockholm, Sweden
September 2020
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Abstract
Gallium nitride (GaN) based high electron mobility transistors (HEMTs) are promising for
power electronic applications due to their high breakdown voltage and power efficiency
compared to Si-based power devices. As known, the design of the HEMT has high impact
on the performance of the devices. In this project various GaN HEMTs on SiC substrate
with different design configurations are characterized and investigated. These HEMTs are
designed and fabricated by the Research Institutes of Sweden (RISE).
The important properties of the HEMTs such as contact resistance, current density,
capacitance, and breakdown voltage are characterized and emphasized. The uniformity of
the contact resistance of the devices located across a 4ââ wafer is investigated, which
reveals the lowest contact resistance of 4.3Ω·mm at the center of the wafer. The highest
maximum current density of the devices is 1.15A/mm, and the maximum current scales
with the gate dimensions of the devices. The gate capacitance of the devices is between
0.1 and 0.6pF under 1MHz. The gate insulation breakdown voltage of the devices is above
40V and the drain to source breakdown voltage is higher than 360V. Based on the results,
discussions about the effects of the designs on the device performance are provided.
Suggestions for further improvement of the device performance are given.
Keywords: Gallium nitride, high electron mobility transistor, gate designs, power
electronics
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Sammanfattning
Galliumnitrid (GaN) baserade högelektronmobilitetstransistorer (HEMTs) Àr lovande för
kraftelektroniska applikationer pÄ grund av deras höga nedbrytningsspÀnning och
effektivitet jÀmfört med Si-baserade kraftenheter. Som kÀnt har designen av HEMT stor
inverkan pÄ enheternas prestanda. I detta projekt karakteriseras och undersöks olika GaN
HEMTs pÄ SiC-substrat med olika designkonfigurationer. Dessa HEMTs Àr designade och
tillverkade av Sveriges forskningsins titut (RISE).
De viktiga egenskaperna hos HEMTs sÄsom kontaktmotstÄnd, strömtÀthet, kapacitans och
nedbrytningsspÀnning karakteriseras och betonas. Enhetligheten i kontaktmotstÄndet för
enheterna som Àr placerade över en 4'' skiva undersöks, vilket avslöjar det lÀgsta
kontaktmotstÄndet pÄ 4.3 Ω·mm i mitten av skivan. Den högsta maximala strömtÀtheten för
enheterna Àr 1.15A/mm, och den maximala strömskalan med enheternas grindmÄtt. Portens
kapacitans för enheterna Àr mellan 0.1 och 0.6pF under 1MHz. EnhetsspÀnningen för
grindisoleringen för enheterna Àr över 40V och avloppsspÀnningen till kÀllan Àr högre Àn
360V. Baserat pÄ resultaten ges diskussioner om designens effekter pÄ enhetens prestanda.
Förslag för ytterligare förbÀttring av enhetens prestanda ges.
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Acknowledgements
To start with, I am very grateful for the help of Dr. Qin Wang. It is a great experience for me
to participate in this project offered by RISE. For most of the problems I encountered in the
project, the careful and detailed guidance of Dr. Qin Wang helped me solve them and
inspired me to develop my ways of thinking. It is a fortune for me to be supervised by Dr.
Qin Wang, not only in the project but also in how to deal with all kinds of situations, which is
an invaluable life experience. Thank you, Dr. Wang, for your patience and guidance, I will
keep it in mind no matter where I am.
Sincerely, I would like to thank Prof. Mattias Hammar, the program director, and the examiner
of this project. Never in my life have I experienced such a colorful two-year journey in
learning and developing myself. The opportunities offered by the Nanotechnology program
allow me to get in touch with the advanced ideas on education and technology, broaden my
horizon and figure out where my future might be. The experience from these two years of
study helps me accomplish the project. Thank Prof. Mattias again for your guidance
throughout the master program study and the detailed suggestions on the thesis and
presentation for completing the project.
Thank Prof. Anders Hallén for co-supervising the project and the suggestions during the
project. The experience in the RBS lab helps me understand when I read topics about
radiation damage on GaN-based HEMTs.
Special thanks to Nina Werner, the Nanotechnology program coordinator. The help on
registration of the project and the application for extended residence permit allows me to
focus on the project.
Particularly I would like to thank Patric Elf, we worked together at the early stage for similar
topics and discussed a lot for understanding and advancing the project. Though we came
from very different cultural backgrounds, we shared similar understandings on the project.
Thank Jang-Kwon Lim on guidance for the characterizations of the devices, thank you for
sharing the expertise on experiments and the meticulous explanations when I felt confusing.
Thanks to Olof Ăberg and Ălle-Linda Talts for the fabrication work, the work contributes a
lot to the progress of the project and your suggestions are valuable for the development of
the project. Thank Dr. Ingemar Petermann, Dr. Mietek Bakowski, Dr. Konstantin Kostov,
Christian Alkzair, Carl Fredrik Ă slund, and Clara Johansen Ăh for your advice and help on
the project.
Additionally, I would like to thank my family and my friends in China, your support and
encouragement help me finish the project.
COVID-19 makes this year unusual for everyone, it is fortunate that I can finish the project.
I wish everyone I know is in good health and wish you all the best for the future.
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Table of contents
Table of Contents ........................................................................... v
List of figures ................................................................................ vii
List of Acronyms ......................................................................... iix
1. Introduction ................................................................................ 1
1.1 Introduction of GaN-based HEMTs ............................................................................. 1
1.2 Fabrication techniques and processes of GaN-based HEMTs ................................... 3
1.3 Applications of GaN-based HEMTs in power electronics ............................................ 5
1.4 Overview of this project .............................................................................................. 6
2. Background ................................................................................ 8
2.1 Heterostructures and 2DEG in GaN-based HEMTs ................................................... 8
2.2 Working principles of GaN-based HEMTs ................................................................. 9
2.3 Leakage mechanisms of GaN-based HEMTs .......................................................... 10
3. Device configurations and experimental settings ................ 12
3.1 Structures and dimension parameters of the HEMTs devices ................................. 12
3.2 Contact resistance measurements ........................................................................... 13
3.3 IV measurements of the devices ............................................................................. 14
3.4 Capacitance measurements of the devices ............................................................. 14
3.5 Breakdown measurements of the devices ............................................................... 15
4. Results and discussion .......................................................... 16
4.1 Evaluation of uniformity and quality of contacts ....................................................... 16
4.2 IV characterizations of the devices .......................................................................... 17
4.2.1 IV behaviour of the basic HEMT device ............................................................. 17
4.2.2 IV behavior of the devices with different gate structures ................................... 19
4.2.3 IV behavior of the devices with different gate width ........................................... 21
4.2.4 IV behavior of the devices with different gate length ......................................... 23
4.2.5 IV behavior of the devices with different gate to drain distance ......................... 24
4.2.6 IV behavior of the devices with a large dimension ............................................ 25
4.3 CV characterizations of the devices ......................................................................... 26
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4.3.1 CV behavior of the basic HEMT device ............................................................. 26
4.3.2 CV behavior of the devices with different gate length ........................................ 27
4.3.3 CV behavior of the devices with different gate to drain distance ....................... 27
4.4 Breakdown characterizations of the devices ............................................................ 28
4.4.1 Gate insulation breakdown of the devices ......................................................... 28
4.4.2 Drain to source breakdown of the devices ........................................................ 29
5. Conclusion ............................................................................... 31
References ................................................................................... 33
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List of figures
1.1 Properties of GaN compared with Si and SiC [1] © 2016 IEEE ..................................... 1
1.2 Schematic view of a GaN-based MIS-HEMT ................................................................ 3
1.3 Schematic view of a conventional GaN-based HEMT [4] ............................................... 4
2.1 Schematic view of Ga-face and N-face GaN [33] .......................................................... 8
2.2 Band diagram of a conventional GaN-based HEMT ..................................................... 9
2.3 Band diagram of a GaN-based MIS-HEMT using SiNx as the insulator ...................... 11
3.1 The design map of the wafers ..................................................................................... 12
3.2 Schematic of the devices with different gate widths .................................................... 12
3.3 Schematic of the devices with different gate to drain distance and different gate lengths
........................................................................................................................................... 13
3.4 Pictures of the parameter analyser and the probe station ........................................... 14
3.5 Schematic of the TLM structure .................................................................................. 14
4.1 Resistance of areas in (a) wafer 1, (b) wafer 2, (c) wafer 3, and (d) wafer 4; (e) contact
resistance of wafer 4 ......................................................................................................... 17
4.2 ID versus VDS of the basic HEMT device of wafer 4 ...................................................... 18
4.3 ID versus VGS of the basic HEMT device of wafer 4 ...................................................... 19
4.4 ID versus VDS of the basic HEMT device of wafer 2 ...................................................... 20
4.5 (a) comparison of the ID versus VGS curves of the basic HEMT devices in wafer 2 and
4, (b) ID versus VGS of the basic HEMT device of wafer 2 (to 5V) ....................................... 21
4.6 ID versus VDS curves of (a) 1x100, (b) 1x200, (c) 1x500, (d) 6x100, (e) 1x1000, and (f)
6x200 dimension devices in wafer 4 .................................................................................. 22
4.7 Maximum current and maximum current density of the devices in wafer 4 .................. 22
4.8 ID versus VDS curves of the devices with different gate lengths of (a) 1.5um, (b) 3um in
wafer 4 ............................................................................................................................... 23
4.9 ID versus VGS curves of the devices with different gate lengths in wafer 4 ................... 23
4.10 ID versus VDS curves of the devices with different gate to drain distances of (a) 10um,
(b) 12um, (c) 15um in wafer 4 ............................................................................................ 24
4.11 ID versus VGS curves of the devices with different gate to drain distances in wafer 4 . 25
4.12 ID versus VDS curves of the device with a large dimension ........................................ 25
4.13 Capacitance of the basic HEMT device in wafer 4 ..................................................... 26
4.14 (a) CGS, (b) CGD of the devices with different gate lengths in wafer 4 ......................... 27
4.15 (a) CGS, (b) CGD of the devices with different gate to drain distance in wafer 4 .......... 27
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4.16 Gate breakdown of Basic HEMT device in wafer 4 .................................................... 28
4.17 Gate breakdown of devices with different gate to drain distance in wafer 4 ............... 29
4.18 Gate breakdown of devices with different gate length in wafer 4 ............................... 29
4.19 ID versus VDS of devices with different gate to drain distance under -15V bias at the
gate .................................................................................................................................... 30
4.20 Drain to source breakdown of the basic HEMT device performed at Ascatron ......... 30
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List of Acronyms
2DEG Two-dimensional electron gas
ALD Atomic layer deposition
CGD Gate to drain capacitance
CGS Gate to source capacitance
CTE Coefficient of thermal expansion
CVD Chemical vapor deposition
CVU Capacitance-voltage units
DC Direct current
D-mode Depletion mode
E-mode Enhancement mode
EPC Efficient Power Conversion Corporation
EV Electric vehicle
GND Ground unit
HEMT High electron mobility transistor
ID (or IDS) Drain to source current
LGD Gate to drain distance
LPMOCVD Low pressure metalorganic chemical vapor deposition
MBE Molecular beam epitaxy
MESFET Metal-semiconductor field effect transistor
MIS Metal-insulator-semiconductor
MOCVD Metalorganic chemical vapor deposition
MOSFET Metal-oxide-semiconductor field effect transistor
SMU Source measure units
TEA Triethylaluminium
TEG Triethylgallium
TLM Transmission line measurement
VDS Drain to source voltage
VGS Gate to source voltage
VPE Vapor phase epitaxy
x
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1. Introduction
1.1 Introduction of GaN-based HEMTs
The research target of this project is gallium nitride-based high electron mobility transistors
(GaN-based HEMTs). As its name indicates, the main component of the transistors is GaN,
the three-five compound semiconductor material. Gallium nitride is one of the most
promising candidate materials for the application of power electronics. As is known to all,
the electronics market is mainly occupied by Si-based devices due to their relatively low cost.
Compared with Si, GaN has a larger bandgap, a higher breakdown field as well as higher
electron mobility [1]. Therefore, the Gallium Nitride based device has the potential to serve
under higher voltage with a lower resistance compared with Silicon-based devices. The
excellent properties of Gallium Nitride enable it for wide application in high-power electronics.
Fig. 1.1: Properties of GaN compared with Si and SiC [1] © 2016 IEEE
The design concepts of HEMTs (high electron mobility transistors) were first published and
demonstrated by Mimura et.al in 1979 [2]. The first HEMT utilized the GaAs/ AlxGa1-xAs
heterostructures to obtain an electron layer (two-dimensional electron gas) at the interface
and the measured electron mobility increased 30% compared to GaAs MESFET (metal-
semiconductor field effect transistor) at room temperature [3]. Since then the research on
HEMTs emerges and the HEMT devices are applied to all kinds of fields [2].
In 1993, Khan et al. reported the first HEMT based on GaN/AlGaN heterostructure [4]. The
GaN/AlGaN heterostructure was grown on the sapphire substrate by LPMOCVD (low-
pressure metalorganic chemical vapor deposition) and the measured carrier mobility in the
heterostructure is as high as 1517cm2/(V·s) at 77k [4]. Among the GaN-based transistors, it
was found the GaN-based HEMTs have the best carrier mobility due to the presence of
2DEG (two-dimensional electron gas) and this finding led to a breakthrough in the
development of GaN-based or even Nitride based devices [5].
Though the GaN-based HEMT device is demonstrated, and it showed promising properties,
there are many problems to be solved for the application. One of the problems that limit the
performance of the GaN-based HEMTs is the CTE (coefficient of thermal expansion) and
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the lattice mismatch of the GaN and the foreign substrates, the latter of which will cause a
large concentration of defects [5]. Since the bulk GaN substrates are of high cost and not
practical for real applications, research interests have been focused on improving the quality
of the layers by using different substrates. There are three main kinds of materials for
substrates that are sapphire, SiC, and Si. In these substrates, sapphire substrates are the
first to be used and have the best availability for epitaxial growth, while SiC substrates have
the best power-related performance and Si substrates have the advantage of large size and
mass production [6]. The GaN on SiC HEMTs has an advantage of superior high-power
performance due to the large thermal conductivity of SiC substrates (>330W/m·K) that
dissipate the high power efficiently, avoiding the large self-heating that cause the
degradation of the device performance [6].
Apart from the choice of the substrates, to improve the device performance, the designs of
the device structures have also been a direction for the development of GaN-based HEMTs.
Features such as buffer layer, gate structures, field plate structures, and the passivation
layers are designed to improve the performance of GaN-based HEMTs.
To alleviate the lattice mismatch between the substrate, a buffer layer between the
substrates and the GaN/AlGaN heterostructure was constructed. With a good combination
of the thickness, the material, and the doping of the buffer layer, the density of the dislocation
caused by mismatch can be largely reduced, the GaN layer of higher quality and a device
with a higher breakdown voltage can be obtained [7]. To decrease the leakage current under
the gate, an MIS (metal-insulator-semiconductor) gate structure was designed differently
from the conventional gate metal-AlGaN Schottky gate structure. The GaN-based MIS-
HEMT using Si3N4 films as an insulator can obtain a gate leakage current of four order
magnitude lower than a conventional GaN-based HEMT [8]. The field plate structure at the
gate can adjust the distribution of the electric field between the terminals to achieve a higher
breakdown voltage of the device [9]. Passivation layers on the surface of the GaN-based
HEMTs can also improve the performance, a Si3N4 passivation layer has better effects in
improving the maximum current and transconductance while a SiO2 layer has better effects
in improving the breakdown characteristics [10]. Also, the designed dimension of the
terminals such as gate length, gate width, and distance between the terminals are important
parameters for the devices and their effects may differ depending on different device
structures.
Another kind of device structure employed is the vertical GaN-based device (drain is at the
substrate and the current flow from the drain to source vertically), which normally requires a
GaN substrate of high quality, there are some reports on GaN on Si vertical devices with
promising properties but they are still under development [1]. Additionally, the GaN-based
HEMTs developed based on a similar structure as the conventional HEMTs are called lateral
GaN-based HEMTs to distinguish with the vertical device. With the findings and perfections
of the device structures, the performance of GaN-based HEMTs improved and started to be
used for the application.
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Fig. 1.2: Schematic view of a GaN-based MIS-HEMT
The GaN-based HEMTs are normally on devices due to the 2DEG that is formed naturally
at the heterostructure. To close the channel, a negative bias voltage needs to be applied to
the gate to deplete the 2DEG. Thus, the GaN-based HEMTs without special modification for
threshold voltage are d-mode (depletion mode) devices. For real applications, normally-off
e-mode (enhancement mode) devices are preferred as they are more stable, and they
consume less power. There are two main kinds of methods to obtain the e-mode GaN-based
HEMTs, one is to connect the source of d-mode GaN-based HEMT to the drain of e-mode
Si-based MOSFET in the cascode structure for a positive overall threshold voltage, the other
is to modify the gate structure to shift the threshold voltage to positive [1]. The gate
modification techniques include using p-type doped GaN or AlGaN thin films under the gate,
recessed gate structures, gate insulators, and plasma treatment to where the gate metal
contacts the AlGaN interface [1].
Through these research efforts on GaN-based HEMTs of the past decades, there are some
commercially available devices, one of which has a voltage rating of 650V and a current
rating of 60A [1]. For future development, commercial devices would focus on 1200V voltage
application using CTE matched polycrystalline AlN substrates [11].
Above all, the features, history, and development of the GaN-based HEMTs that are
investigated by this project are introduced. The detailed structure and fabrication process
will be introduced in the next section.
1.2 Fabrication techniques and processes of GaN-based HEMTs
The fabrication techniques and processes mainly depend on the design structure and the
material type of each layer. To fully present the differences that exist in different devices, the
conventional device will be first introduced and alternative techniques for each fabrication
step will be discussed. Then the fabrication of some updated devices will be presented.
In the very beginning, how to deposit the AlGaN/GaN layer with good quality is the first task
to be solved. Methods such as MBE (molecular beam epitaxy), VPE (vapor phase epitaxy),
and MOCVD were investigated but most of the cases the grown AlGaN layer will have a high
doping density and the carrier mobility is low due to the impurity scattering [12]. Additionally,
for high-frequency applications, the traps at the AlGaN interface will charge and raise the
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on-state resistance, causing the well-known current collapse phenomenon in the GaN
device.
The first GaN-based HEMT used the LPMOCVD techniques with optimized growth
conditions and succeeded in demonstrating the device [4]. The sapphire substrate was
degreased and etched to be prepared for the epitaxial growth, then triethylaluminium (TEA)
triethylgallium (TEG) and ammonia (NH3) were used for source materials [12]. The growths
were carried out under a pressure of 76torrs in a hydrogen ambient, a thin AlN buffer layer
(0.1um) was grown on the substrate at 1050â prior to the growth of AlGaN/GaN, then the
GaN layer (0.6um) and the AlGaN layer (0.1um) were grown at a temperature of 875 and
775â, the flux of each source materials was adjusted in the grown process for the ideal
composition of each layer [12].
After the growth of each layer, the proton implantation was used to form the mesa isolation
between each device, evaporation followed by lift-off procedures were used to deposit the
metal block for each terminal [4]. The drain and source terminals used Ti/Au (2.5nm/150nm)
and an annealing process (250â for 1 min) was used to form the Ohmic contact of the
terminals [4]. The gate contact metal used TiW and similar procedures as the deposition
process of the drain and the source terminals.
Fig. 1.3: Schematic view of a conventional GaN-based HEMT [4]
The recent reports on GaN-based HEMTs have different detailed settings on the fabrication
processes, but MOCVD is commonly used for the growth of the AlGaN/GaN heterostructure
[13]-[19]. The choice of substrates was Si or SiC. For the buffer layer, apart from the
conventional thin AlN layer (1nm to 50nm), transition GaN layers (1.5um to 4um) with C or
Fe doping(1018 cm-3) were used in combination to reduce the leakage current and increase
the breakdown voltage [13], [14], [17], [18]. In some reports, a thin GaN cap layer (2nm to
3nm) was grown on the AlGaN barrier layer before the deposition of gate metal to improve
the performance [13], [14], [16], [17], [19]. SiNx passivation layer was commonly used and
deposited before the metals [13]-[19]. The formation of mesa isolation includes ion
implantation, plasma dry etching, and reactive ion etching, the breakdown voltage of the
device differs with the mesa isolation depth in some reports [13]-[19]. Normally the drain and
source electrodes were deposited using the electron beam evaporation together with lift-off
procedures. Annealing processes were used to form Ohmic contact of the drain and source,
the procedures depend on the material of metal layers, relatively lower annealing
temperature (550 - 650â) and longer time (5-14 min) was used for Ta/Al/Ta contacts while
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higher temperature (850 - 880â) and shorter time (30s-1min rapid thermal annealing) for
Ti/Al/Ni/Au contacts [13]-[18]. MIS gate structures were also employed in some devices,
electron beam lithography was first used to define the insulator layer under the gate, then
some devices used CVD (chemical vapor deposition) to deposit SiNx as the gate insulator,
one that used ALD (atomic layer deposition) to deposit Al2O3 gate insulator was also reported
[13]-[17], [19]. Gate metals were deposited by evaporation and gate field plates were also
used in some devices [13]-[19]. A special case of the device designed with the tri-gate
structure used electron-beam lithography to define the gate metal in the shape of nanowires
for optimized device performance [19].
To summarize, the growth and device fabrication of a typical GaN-based HEMT starts with
the etching and clean of the substrates if needed. Then the buffer layer with or without
doping is grown on the substrate using MOCVD. GaN/AlGaN heterostructure is also grown.
A thin GaN cap layer may be grown on the AlGaN layer depending on the design. The
passivation layer of SiNx can be grown by CVD on the top layer. Then the mesa isolation
between the devices is achieved by different lithography and etching processes. If an MIS
gate structure is employed, electron beam lithography is used to define the location of the
insulator beneath the gate. The gate insulator could be a SiNx layer by CVD or an Al2O3
layer by ALD. The drain and source metals are deposited by the evaporation method and
lift-off processes. An annealing process is used to form the Ohmic contact of the drain and
source. Finally, the gate metal is deposited using a similar sequence to the other two
terminals.
1.3 Applications of GaN-based HEMTs in power electronics
The earliest power electronic application of GaN-based HEMTs can be dated back to the
early 2000s when there are reports of the devices specified for power inverters [20]. GaN-
based HEMT devices with a working range of 600V/2.5A and switching time of 30ns, a
working range of 370V/20A, and switching time of 10ns are reported [21], [22]. However, the
reliability of these devices is an important issue to be solved, the device temperature
increases significantly as the dissipated power increases [21].
In 2009, the first e-mode GaN-based HEMTs were demonstrated by EPC (Efficient Power
Conversion Corporation) [23]. The EPC devices can work up to 200V with a higher DC-DC
conversion efficiency than commercial Si power MOSFETs, the on-state resistance of the
devices remain stable after 1000h stress tests under 150â and after 2300 cycles of
temperature tests from 0 to 100â [23]. For the design of the devices, the p-type doped GaN
gate is utilized to achieve a positive threshold voltage and the overall design is similar to the
conventional HEMTs [23]. Si substrates are used for the devices and the problems due to
the lattice constant and CTE mismatch are well solved for the devices to be stable for
commercial uses.
The first commercial high voltage e-mode GaN-based HEMTs is reported by Transphorm in
2015, the devices are demonstrated as 600V power switches with a reliability of over one
million hours at 175â [24]. For the design of the device, the normally-on high voltage GaN-
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based MIS-HEMT is connected to the low voltage Si MOSFET in a cascode configuration to
achieve a positive threshold voltage [24]. The on-state resistance of the devices is as small
as 0.15Ω and remain stable until 1000V [24].
Following the trend, e-mode GaN-based HEMT commercial devices up to 600V are also
released by Panasonic and Infineon [11], [25], [26]. They all employed the p-type doped
GaN and recessed gate structure for positive threshold voltage, the p GaN beneath the gate
metal is recessed into the AlGaN layer for adjusting the threshold voltage [11], [25], [26]. In
particular, the devices from Panasonic exhibited long lifetime and good stability under 600V
for 1000h [25], [26].
Using those commercial GaN-based HEMT devices, AC-to-DC adaptor, telecom rectifier,
three-phase inverter, and EV battery charger with ultra-high-power density and high
efficiency can be designed [27]- [31]. The development of GaN-based HEMTs emerges as
the commercial products are applied in wider areas.
1.4 Overview of this project
This project is a small part of the huge UltimateGaN EU project which aims to develop the
next generation GaN-based devices sufficient to meet the requirements of commercial
products in the next five years. As the first project related to GaN-based power HEMTs in
recent years at RISE, the main interest of this work is to design and demonstrate the GaN-
based HEMT devices, to compare and understand the effects of different design variations
on the performance of the GaN-based devices. The design and fabrication work are mostly
done by RISE. This project is responsible for testing and setting up the characterizations,
providing explanations for unexpected phenomena, and analyze the results based on the
design differences of the devices. As there are numerous devices, the project will focus on
the devices with better power-related performance such as current density and breakdown
voltage.
Because the final goal of the devices is for power electronics application, important
properties of the devices related to high power applications such as contact resistance,
current density, transconductance, capacitance, and breakdown voltage are key results that
should be obtained. Based on these initiatives, the objectives of this project are
characterizing these power-related properties of the devices and evaluating the
performance of the devices based on estimated values. The measurements include
evaluation of the uniformity and quality of the contacts, compare and extract useful
information from the IV characteristics of the devices with different gate designs, measure
the capacitance values, and test the breakdown limit of the devices regarding gate insulation
and drain to source breakdown. According to the study on former reports, a contact
resistance below 1Ω ·mm would be ideal, a maximum current density above 0.1A/mm would
be promising, the capacitance values are expected to be in the 10-13F range, the gate
insulation breakdown voltage is expected to be above 30V, drain to source leakage current
at off-state should be as low as possible and a drain to source breakdown voltage above
200V would be good enough for the devices. Based on these expected values, the
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performance of the devices can be evaluated and discussions on how to further improve the
devices for power electronics can be provided.
This work starts with the contact resistance measurements, the TLM (transmission line
measurements) are chosen as they could give accurate contact resistance value if the
results showed a linear pattern. And it is universally used in research, which will help
evaluate the results by comparing it with the work from others. However, it is found that the
uniformity and quality of the contact resistance in the wafers are unsatisfactory. The areas
located at the centers of the wafer have lower contact resistance than the areas far from the
centers. But the lowest contact resistance is 4.3 Ω ·mm, much higher than an ideal value.
The most possible reason is that the temperature for the annealing processes is not high
enough and the unbalanced distribution of temperature caused the poor uniformity.
IV measurements with specified ranges for the devices are carried out. The voltage ranges
and current ranges are adjusted to obtain the full behavior of each device. The maximum
current density is in the range of (0.6, 0.8) A/mm for MIS-HEMT devices with different gate
width, which is promising as it proves the devices designed with larger width will have a
higher current rating. Then the high-power device is achievable by increasing the dimension.
Threshold voltages and transconductance of the devices are also evaluated.
CV measurements to obtain the capacitance values are taken. The capacitance change as
the devices are turned on. The results show the gate capacitance is in the range of (0.1, 0.4)
pF, which will be a good reference for the devices to be developed for the high-frequency
applications. Gate breakdown measurements show that the gate breakdown voltage
depends on the designed gate to drain distance and the gate is stable up to 40V range. For
drain to source breakdown voltage, the devices are stable up to 200V. High voltage test
indicates the drain to source breakdown voltage is in the range of (360, 400) V. Drain to
source breakdown measurements also indicate the leakage current of the devices are too
high (20mA), how to reduce the leakage by optimizing the design and fabrication process
will be the main task for the future work of the project.
In all, the GaN-based HEMT devices from RISE are characterized in terms of application for
power electronics. Results show that the annealing processes need to be modified for
forming better contact at the terminals. Excellent maximum current density is obtained and
designs with large dimension parameters are encouraged for high power performance.
Capacitance values are also obtained and may be used as a reference for high-frequency
applications in the future. Breakdown characteristics of the device show the reliability of the
devices remains an important issue. Optimized structures and fabrication processes of the
devices can be proposed based on the results of this project. Through these modifications,
the performance of the GaN-based HEMTs will be improved and one step closer to the real
application.
8
2. Background
In this chapter, the basic work principles of GaN-based HEMTs are introduced. The essential
core of the design of GaN-based HEMTs, the origin and formation of 2DEG in the
AlGaN/GaN heterostructure is explained. The physical properties of the GaN-based HEMTs
during operation are presented. The possible mechanisms for the leakage current are briefly
discussed.
2.1 Heterostructures and 2DEG in GaN-based HEMTs
Two-dimensional electron gas (2DEG), as its name indicates, is the electron gas that can
move freely in two dimensions and confined for the third dimension. This phenomenon is
commonly found in semiconductor heterostructures, in which the edges of the conduction
band form a quantum well to confine the electron gases. For different heterostructures, the
density of the 2DEG varies and the related electron mobility is different.
The crystal structure of Wurtzite-type GaN is hexagonal and the hexagonal column in the
axial direction ([0001]) is called c-axis. There are two kinds of the c-planes ((0001)) at the
surface of GaN crystals, either composed of Ga or N atoms. MOCVD is usually used to
obtain Ga-face GaN crystals while MBE can be used to obtain N-face GaN crystals [32].
Due to the asymmetry of the atoms in the interfaces, the spontaneous polarization is
generated and its effect along the c-axis (for AlGaN/GaN structure) depends on the
structural parameters (c/a ratio) [33]. Apart from the spontaneous polarization, the lattice
mismatch of the AlGaN/GaN structure will induce the strain and the piezoelectric polarization
at the interface. The spontaneous polarization and piezoelectric polarization both contribute
to the background carrier density in the AlGaN/GaN structure and by adjusting the Al
composition, different carrier concentrations can be obtained [33].
Fig. 2.1: Schematic view of Ga-face and N-face GaN [33]
The high background carrier concentration of AlGaN/GaN makes it promising to construct
2DEG of high quality even if the materials are not intentionally doped [33]. And the electron
mobility is expected to be better as it is free from impurity scattering. As shown in Fig. 2.2,
the conduction band edges of AlGaN and GaN form a quantum well to confine the 2DEG.
9
The device is normally-on and negative bias voltage at the gate is needed to deplete the
2DEG. To obtain a normally-off device, the work function of the gate should increase, or the
thickness and composition of AlGaN should be adjusted for a steeper band edge, then a
positive bias voltage at the gate is needed to activate the channel for 2DEG.
Fig. 2.2: Band diagram of a conventional GaN-based HEMT
2.2 Working principles of GaN-based HEMTs
The DC operation of GaN-based HEMTs involves the forward-bias operation and the transfer
operation. In the forward-bias operation, a bias voltage(or zero voltage) is applied to the
gate and the device is on (larger than the threshold voltage) or off(smaller than the threshold
voltage) depends on the voltage value, the drain to source current that change with the drain
to source voltage during operation is an important quantity for evaluating the devices. The
drain to source currents of the devices at off-state should be as low as possible, if it is too
high, then the devices have the leakage problem or are broken down. High voltages could
be applied to the drain to test the breakdown limit of the devices. For transfer operation, a
constant bias voltage is applied to the drain to source, and the drain current that changes
with different gate voltage is an important quantity, transconductance is an effective quantity
for evaluating the changes.
As introduced in the former section, the conventional GaN-based HEMT device is naturally
normally-on due to the characteristics of 2DEG, it forms a channel for conducting without
bias voltage. By applying a negative voltage at the gate, the Fermi level at the AlGaN/GaN
interface decreases, and the channel is pinched-off. The threshold voltage depends on the
built-in voltage of the gate to heterostructure, the thickness and composition of the AlGaN
layer, and the interface properties [34].
When the gate bias voltage is larger than the threshold voltage, the devices work under
forward-bias operation which include a linear region and a saturation region. In the linear
forward operation region of the device, a formula for the drain current is given by [35]:
đŒđ· = đ€đđđđ
In which ID (or IDS) denotes the drain to source current, w is the width of the gate, q is the
electron charge, Ό is the carrier mobility and nS is the sheet charge density. The carrier
mobility of the device could be a sophisticated function related to the electrical field of the
channel and the sheet charge density depends on the voltage difference of gate and the
threshold [35]. When drain voltage is high and the device works in the saturation region, the
10
current is saturated as the carriers reach the saturation velocity which denotes the maximum
current level [35].
For the transfer characteristics, the transconductance of the device is defined as the current
change divided by the gate voltage change with a constant drain to source voltage. And the
formula can be calculated by:
đđ =đđŒđ·đđđș
In which gm denotes the transconductance and VG is the gate voltage.
For high frequency operation, the cut-off frequency is an important quantity as it indicates
the working range of the devices. It depends on the capacitance of the devices and can be
calculated if the transconductance and the capacitance values of the devices are known.
However, depends on the design of the GaN-based HEMTs, the capacitance could be
different due to the different layer properties. It is reported than the gate capacitance is
related to the 2DEG density, if the 2DEG density is small, the gate capacitance is mainly
determined by the layers, if the 2DEG density is large, then the 2DEG provides shielding to
the channel and the gate capacitance depends on the 2DEG density [36]. Therefore, the
gate capacitance will change around the threshold voltage, which is an important indicator
of the function of the gate. Normally the gate capacitance is linearly proportional to the
dielectric constant, surface area of the gate, and inverse proportional to the thickness of the
layers under the gate.
2.3 Leakage mechanisms of GaN-based HEMTs
There are two kinds of leakage that cause problems for the reliability of the GaN-based
HEMT devices during DC operation. One is the gate leakage problem and the other is the
drain to source leakage problem.
For the gate leakage problem, the gate current should be as low as possible(10-9A or even
less) during operation or the function and the behavior of the devices will be abnormal and
it is difficult to switch the device. Operation with high voltage may cause the break of the
layers under the gate and the devices will reach the breakdown limit. The gate leakage
problem can be solved by employing the MIS gate structure which uses an insulator under
the gate. With a thin Si3N4 insulator layer, the gate leakage could be suppressed, and the
gate current could be four orders of magnitude smaller than a conventional Schottky gate
HEMT [8]. Recent reports used SiNx as the insulator, the band diagram is shown in Fig. 2.3,
the insulator raises the potential barrier and prevent the gate leakage [16]. The drawback of
the MIS gate is the complicated fabrication processes for the insulation layer.
11
Fig. 2.3: Band diagram of a GaN-based MIS-HEMT using SiNx as the insulator
The drain to source leakage problem refers to the high drain to source current when the
devices are off. Normally a drain to source current at off state in normal operation range
should be in the micron amperes range or even less, or there will be problems for the devices
such as extra power consumption, lower lifetime, and less stability for high-voltage high-
frequency application. During the forward-bias operation, when the drain voltage is high the
drain current could increase steeply from the saturation current level to a very high current
level and the device may be burned, the voltage when the current increase to a certain
level(1mA/mm for example) is called the drain to source breakdown voltage.
The most common drain to source leakage current that causes the device breakdown is the
leakage through the channel region in AlGaN/GaN. This phenomenon can be identified if
the breakdown voltage increases scale with the gate to drain distance [37]. Other possible
mechanisms for the leakage could be the leakage through the surface passivation layer or
through the buffer layer [38], [39]. In all cases, the quality of the layers is the core to prevent
leakage and improve the devices regarding breakdown characteristics.
12
3. Device configurations and experimental settings
In this chapter, the wafers investigated in this project are introduced. The different gate
structures employed for the wafers are explained. The dimension parameters of the
measured devices are listed. Principles and settings for TLM measurements are presented.
The equipment and detailed settings of the DC and capacitance measurements are shown.
3.1 Structures and dimension parameters of the HEMTs devices
The wafers used in this project are provided by RISE. All the wafers are GaN on SiC
structure. For the HEMT devices, wafer 1 and 2 use the Schottky gate structure while wafer
3 and 4 use the MIS gate structure. Wafer 1 and 3 use a thin AlN layer while wafer 2 and 4
use a thicker AlN layer for the buffer layer. For the MIS gate structure, SiNx is used as the
insulator material for wafer 3 and 4. Passivation layers composed of SiNx and SiO2 are used
in all wafers. Ti/Al/Ni/Au metals are used for forming the drain and source terminals and
Ni/Au are used for gate metals. The areas and the structure of the devices in every area are
the same in the four wafers. As shown in Fig. 3.1, there are 25 rows of areas in the wafers
and the maximum columns in one row are in the middle from A to Y. An area such as N19
indicates the area is in the N column of the 19th row.
Fig. 3.1: The design map of the wafers
13
The length and width of each area are 3.9mm. If the left side of the wafer is the starting point
with a coordinate of 0, then the coordinate of the rightmost area in the middle row(Y13) is
97.5mm. Structures of the devices involved in the project are also shown in Fig. 3.1.
There are two main types of HEMT devices in the wafers, one type has a single gate finger
and the other has multiple fingers. It is shown in Fig. 3.2, the upper four devices are single-
finger devices with gate widths of 100, 200, 500, and 1000um. The lower two devices are
multiple-finger devices with a dimension parameter of 6x100 and 6x200um separately. All
six devices have a gate length of 1.5um and gate to drain length of 10um.
Fig. 3.2: Schematic of the devices with different gate widths
Devices with different gate to drain distance and gate length are also used for measurements.
As shown in Fig. 3.3, the upper three devices have a gate to drain of 10, 12, and 15um
separately. The gate to drain distance of the lower one is 10um. The gate length of the upper
three is 1.5um and the gate length of the lower one is 3um. All four devices have one gate
finger with a width of 100um.
Fig. 3.3: Schematic of the devices with different gate to drain distance and different gate
lengths
In addition, the basic device refers to the device with the smallest dimension, which has a
gate length of 1.5um, gate width 100um, gate to source distance of 3um, and gate to drain
distance of 10um.
3.2 Contact resistance measurements
The Tektronix parameter analyser 4200A-SCS together with a probe station are used to
perform most of the tests in this project, a picture of them is shown in Fig. 3.4.
14
Fig. 3.4: Pictures of the parameter analyser and the probe station
Transmission line measurements (TLM) are used to test the contact resistance of areas in
the wafer. The measurements were carried out in areas with TLM test structures (shown in
Fig 3.5) in the wafers. The contact areas (black parts) of the TLM structure is 200umx50um
and the gaps between the contacts are 10, 20, 30, 40, and 50um. TLM structures are located
in the 13th row of the wafers, areas include TLM structures are C13, F13, I13, L13, O13,
R13, and U13 of the wafers from left to right.
Fig. 3.5: Schematic of the TLM structure
For two terminal-resistor tests, two probes are separately connected to SMU (Source
measure unit) 1 and GND (ground) of the parameter analyser. Then the two probes are
loaded onto the two terminals. The settings of the voltage and current for measurements are
completed in the Clarius software of the parameter analyser.
To obtain the contact resistance, the total resistance between the 10, 20, 30, 40, and 50um
gap are measured. The applied voltage is set to sweep from -0.2V to 0.2V between two
terminals with a 0.02V voltage step. The overall resistance is calculated by taking the
average value of voltage divided by the measured current. Then a linear approximation is
used on the resistance-gap curves to obtain the contact resistance, which equals to the
intercept of the line with the resistance axis divided by 2 and multiplies by the length of the
contact (200 um) [40].
3.3 IV measurements of the devices
For three terminal-transistor tests, three probes are separately connected to SMU 1, SMU
2, and GND of the parameter analyser. Then probes connected to SMU 1 and SMU 2 are
loaded onto the gate and drain terminals of the device. The probe connected to GND is
loaded on the source terminal. The settings of the voltage and current for measurements
are completed in the Clarius software of the parameter analyser.
15
For ID (drain to source current) versus VDS (drain to source voltage) measurements, a bias
voltage from -15V to 5V with a step of 1V is applied to the gate. Under each bias voltage,
VDS is swept from 0 to 25V with a step of 1V (0 to 20 V to the devices with a large width, see
in 4.2.3). Then ID is measured and the ID versus VDS curves are plotted. The current density
is calculated as ID divided by the gate width of the device.
For ID versus VGS (gate to source voltage) measurements, a bias voltage of 10V is applied
to the gate. VGS is swept from -20 to 0V with a step of 1V (-20 to 5V for the device of Schottky
gate, see in 4.2.2). Then ID is measured and the ID versus VGS curves are plotted. The
transconductance is calculated by differentiating ID versus VGS and plotted.
3.4 Capacitance measurements of the devices
The capacitance measurements utilize the CVU (capacitance-voltage units) of the
parameter analyser. Two probes are separately connected to CVHs and CVLs of the
parameter analyser. The probe connected to CVLs is loaded on the gate while the probe
connected to CVHs is loaded on the drain or source terminal depending on whether to
measure CGD or CGS. The measure units are calibrated of open-loop and close-loop settings
before measurement. The settings of the voltage, capacitance, and frequency for
measurements are completed in the Clarius software of the parameter analyser.
The voltage at the gate is swept from -20 V to 0V with a step of 0.5V and the frequency is
set at 1MHz. The capacitance between the gate to source or gate to drain terminals are then
measured and plotted versus voltage.
3.5 Breakdown measurements of the devices
The gate breakdown measurement is similar to a two-terminal test. Two probes are
connected to SMU1 and GND. Then the probe connected to SMU1 is loaded on the gate
and the probe connected to GND is loaded on the drain terminal. The current compliance is
set to 0.1 A.
The voltage at the gate is swept from 0V to 50V with a step of 0.5V. And the current is
measured and plotted versus the gate voltage.
The drain to source breakdown measurement is similar to the IV measurements. Three
probes are separately connected to SMU 1, SMU 2, and GND of the parameter analyser.
Then probes connected to SMU 1 and SMU 2 are loaded onto the gate and drain terminals
of the device. The probe connected to GND is loaded on the source terminal. The settings
of the voltage and current for measurements are completed in the Clarius software of the
parameter analyser.
A bias voltage of -15V is applied to the gate to keep the device at off-state. Then the VDS is
swept from 0 to 200V with a step of 1V. The voltage of the parameter analyser is limited up
to 210V and is too low to reach the breakdown limit of most devices.
16
4. Results and discussion
In this chapter, the results obtained from measurements are analysed and discussed. The
contact resistance of different areas is compared to evaluate the quality as well as the
uniformity of the contacts. ID versus VDS curves and ID versus VGS of different gate structures
and dimension factors are evaluated, the contrasts of performance in devices of different
designs are analysed and discussed. Capacitance results measured between terminals of
the devices are presented. Breakdown characteristics measured with different methods are
investigated.
4.1 Evaluation of uniformity and quality of contacts
Forming contacts of fine quality at drain and source terminals are preconditions required for
fabricating devices with prominent properties such as high current density and low on-
resistance. The contact resistance results measured of areas in each wafer are shown in
Fig. 4.1. Areas showed irregular high resistance, for example, C13 of wafer 3 with resistance
in the range of (1400, 2500) Ω, is not presented in the figure.
From the results, it can be inferred that the areas located far from the center of the wafer
showed larger resistance than the areas near the center except wafer 1. Namely, it can be
assumed that the areas in the middle of the wafers have better contacts than the others in
wafer 2, 3, and 4.
To verify the assumption and evaluate the quality of the contacts, the resistances of the
metal layers of the terminals are measured and it can be found that the resistance of the
metal layers is similar in each area. Then it is evident that the difference in the total
resistance of the TLM structures depends largely on the quality of contacts between metal
layers and contacts between the metal layer and heterostructure interface.
According to previous studies on the contact resistance of the electrodes and
heterostructure interface, the annealing temperature of the contacts plays an important role
[40]. High annealing temperature helps in forming contacts of good quality. However, it was
reported that high-temperature processes (larger than 850 â) will cause the reduction of
the 2DEG carrier density and lead to an increase in the resistance [40]. In the fabrication
processes of the devices in this work, the annealing temperature is under 600â. In this
range, the dominant factor is the quality of contacts, which indicates that the areas with
higher annealing temperature will exhibit lower resistances. Based on the results, it can be
assumed that the areas near the center underwent higher annealing temperatures during
the annealing processes. For improving the uniformity of the quality of the contacts,
balanced distributions of temperature at all areas of the wafer in the annealing process
would be effective.
17
Fig. 4.1 Resistance of areas in (a) wafer 1, (b) wafer 2, (c) wafer 3, and (d) wafer 4; (e)
contact resistance of wafer 4
4.2 IV characterizations of the devices
The maximum current density, on-off ratio, transconductance, and threshold voltage are
important parameters in the evaluation of the HEMT devices for application. To extract these
parameters, IV measurements of ID-VDS and ID-VGS are carried out.
4.2.1 IV behaviour of the basic HEMT device
To set criteria for the performance of IV, the results of the basic device (smallest dimension)
are presented. As discussed in the former section, wafer 4 exhibits better quality in the
contacts, therefore the basic HEMT device as a standard is chosen from this wafer. The
(a) (b)
(c) (d)
(e)
18
device is designed with an expectation of threshold voltage in the range of (-10V, -15V). To
characterize the full ID-VDS forward characteristics of the HEMT device from off-state to on-
state with maximum current density, the gate voltage was set from -15V to 5V with a step of
1V, while the drain to source voltage was swept from 0 to 25V. The results are shown in Fig
4.2.
Fig. 4.2 ID versus VDS of the basic HEMT device of wafer 4
According to the results of ID-VDS, when the gate voltages are lower than -11V, the HEMT
device shows off behaviour. As the gate voltages decrease to lower than -11V, the changes
in the curve are rather small compared with the changes of the gate voltage from -11V to
higher voltage. The threshold voltage can be estimated to be near -11V, which is in the
expected range.
For the HEMT device that is on-state (with VGS higher than -11V), as the drain to source
voltage increases from 0 to about 10V, the current first increases linearly with the voltage.
Then the slope of IV decrease and as it approaches the saturation region, and the current
density reaches the maximum. However, it can be observed that the slope of the IV curves
is not zero after the device reaches saturation. This phenomenon might be caused by the
channel length modulation, which originated from the displacement of the pinch-off point,
the actual channel length becomes shorter and leads to the increment of the current. The
maximum drain current of the device is 68mA, as it is the smallest dimension with a gate
width of 100um, the maximum current density should be 0.68A/mm.
The drain current on-off ratio of the device is near 8, less than one order of magnitude. The
on-off ratio is an important parameter for power electronics as it not only represents the
highest current level as well as the highest power level, but also the leakage current that will
heavily influence the real application of the device. A high leakage current will cause large
power consumption as well as potential failure in the operation. Devices with excellent
performance often present a high on-off ratio that could be 106 or even larger. It is reported
that the HEMT device using a similar structure as in this work can reach an on-off ration as
19
high as 109 [16]. Further investigations on the drain to source leakage will be discussed in
5.4.
To obtain the exact value of the threshold voltage and verify the function of the gate, ID-VGS
measurement results on the transfer characteristics are shown in Fig 4.3. As known from
previous ID-VDS results, a drain to source voltage bias of 10V is suitable for the device to
reach the maximum current. In the ID-VGS measurements, the gate to source voltage was
swept from -20V to 0V with the drain voltage bias. The current density of drain current
remains around 0.1A/mm at off state. When the gate voltage is larger than the threshold,
the current first increases linearly and then turns flat. The red line is the linear fit of the IV
curve from -10V to -3V, the intercept of it with the voltage axis indicates the threshold voltage,
which is -12.3V. However, as the drain to source leakage is quite high (0.1A/mm), the
threshold voltage should be higher and near -11V.
Fig. 4.3 ID versus VGS of the basic HEMT device of wafer 4
4.2.2 IV behavior of the devices with different gate structures
There are two kinds of gate structures in this work. Namely, the device measured in the
previous section has a gate structure of MIS (metal-insulator-semiconductor), with a thin
layer of Si3N4 for gate insulation under the gate metal. In the other kind of structure, the gate
metal contacts the semiconductor directly, forming a Schottky gate structure. To compare
the IV characteristics of the devices with different structures, the basic device from wafer 2
is chosen as wafer 2 has exactly the same layers as wafer 4 except the gate structure. The
basic device of the Schottky gate structure is measured with the same set up for IV
characteristics, the result is shown in Fig 4.4.
20
Fig. 4.4 ID versus VDS of the basic HEMT device of wafer 2
Different from the MIS gate device, the Schottky gate device was designed with an expected
threshold voltage in the range of -5V to 0V. The ID-VDS curve was obtained by sweeping VDS
from 0 to 25V with a gate bias voltage vary from -15V to 5V. From the curves, the device is
at off state until the gate voltage surpasses 0V. As the gate voltage increases from 0 to 5V,
the current level starts to show an obvious increase. The pattern of the curve is similar to
the MIS gate device, first the current increase linearly with the voltage and then the curve
turns and enters the saturation region. The maximum drain to source current is 50mA and
the maximum current density is 0.5A/mm.
When the device is on-state, there is a current from the source to drain when the drain to
source voltage is 0V. This current increases with the gate voltage, which means it could be
the leakage current from the gate. The gate structure does not have a good function well as
it influences the drain to source current once the device is on. The only difference between
these devices is the insulation layer under the gate metal. In the Schottky gate device, the
absence of the gate insulation layer leads to the leakage current from the gate to source
when the device is turned on.
The transfer characteristics of the Schottky gate device are also tested and shown in Fig.
4.5. As compared with the MIS gate device, the MIS gate device showed an obvious turn-
on behaviour at about -10V. To characterize the full characteristic of the Schottky device, the
gate to source voltage was swept up to 5V and shown in Fig. 4.5 (b). With a linear fit of the
curve from 0 to 2V, the threshold voltage is estimated to be near -2.1V. Similar to the former
results, the threshold voltage should be larger because of the high background leakage
current level.
21
Fig. 4.5 (a) comparison of the ID versus VGS curves of the basic HEMT devices in wafer 2
and 4, (b) ID versus VGS of the basic HEMT device of wafer 2 (to 5V)
4.2.3 IV behavior of the devices with different gate width
For applications of the HEMT devices in power electronics, the current rating, or the
maximum current density is one of the most important factors for the device performance. A
large maximum current indicates that the device can work with large power when the working
voltage is fixed. To improve the maximum current, the gate dimension parameters are
essential in designing and optimizing the device characteristics.
There are several gate dimension parameters including the gate length, the gate width, the
number of gate fingers, and the length between the gate and the other terminals. Among
these parameters, the maximum current is largely influenced by the gate width and the
number of gate fingers. To study the effects of these two parameters, devices of gate
dimension parameters 1x100, 1x200, 1x500, 6x100, 1000, and 6x200 are selected and IV
measurements are performed. In these parameters, 1x100 means there is one gate finger,
and the gate width is 100um. These devices are from the wafer 4, they have the same gate
length of 1.5um and the same designed distance of gate to the other terminals. The drain to
source voltage is swept from 0 to 20V, which is enough for observing the maximum current.
The results are shown in Fig. 4.6.
(a) (b)
(a) (b)
22
Fig. 4.6 ID versus VDS curves of (a) 1x100, (b) 1x200, (c) 1x500, (d) 6x100, (e) 1x1000, and
(f) 6x200 dimension devices in wafer 4
From the results, the maximum current increases as the product of the number of fingers
and the gate width increases. And the current scale is in coordination with the dimension. In
the 6x200 device, distortion in the curves is observed. A possible explanation is the overheat
of the device due to the high current leads to the distortion. To present the relation between
the maximum current and the parameters more straightforward, maximum currents at VDS
of 20V are taken and drawn in Fig. 4.7.
Fig. 4.7 Maximum current and maximum current density of the devices in wafer 4
(c) (d)
(e) (f)
23
4.2.4 IV behavior of the devices with different gate length
Apart from the width and the number of gate fingers, the gate length also plays a role in the
maximum current. As shown in Fig. 4.8, the IV behaviors of the two devices with one gate
finger and 100um gate width but different gate lengths are measured. Their overall
performance is similar. The maximum current density increases from 0.68A/mm to 1.06
A/mm as the gate length increase from 1.5 to 3um, showing an increase of 56%.
Fig. 4.8 ID versus VDS curves of the devices with different gate lengths of (a) 1.5um, (b)
3um in wafer 4
The transfer characteristics of the device will change according to different design variations
of the gate. After certain tests, it is found that the changes in the transfer characteristics due
to different finger numbers and gate width are very small compared to the change in the
gate width. By contrast, the transfer characteristics change obviously with the gate length
as shown in Fig. 4.9.
Fig. 4.9 ID versus VGS curves of the devices with different gate lengths in wafer 4
The device with a gate length of 1.5um showed a maximum transconductance of
58.7mS/mm while the device with 3um gate length showed a larger maximum
transconductance of 71mS/mm. The estimated threshold voltage decreases a little bit from
-12.3V to -12.5V as the gate length increases.
(a) (b)
24
4.2.5 IV behavior of the devices with different gate to drain distance
While the dimensions of the gate are important for the performance, the location of the gate
regarding the other two terminals are also of importance. To investigate the effects of the
distance between the gate and the other two terminals, the single finger devices are
designed with the same drain to source distance(LGS) of 3um and three different gate to
drain distances (LGD ) including 10um, 12um, and 15um. The ID-VDS results are shown in Fig
4.10.
As LGD increases from 10 to 12um, the maximum current density showed an increase from
0.68A/mm to 1.15A/mm. It is a significant increase since the current density increases 69%.
However, as LGD continue increasing from 12um to 15um, the maximum current density
decreases to 1.12A/mm. To reach a maximum current density, an optimized design of LGD
between 12um and 15um could be further investigated.
Fig. 4.10 ID versus VDS curves of the devices with different gate to drain distances of (a)
10um, (b) 12um, (c) 15um in wafer 4
The transfer characteristics of the device also depends on the gate to drain distance. The
results of the ID-VGS for different LGD are shown in Fig. 4.11.
(a) (b)
(c)
25
Fig. 4.11 ID versus VGS curves of the devices with different LGD in wafer 4
As LGD increases from 10um to 12um, there is an apparent shift in the IV curve and
transconductance curve. The estimated threshold voltage decreases from -12.3V to -13.9V.
And the maximum transconductance increase from 60mS/mm to 80mS/mm. Further
increase of LGD from 12 to 15um leads to a slight decrease in the current and the
transconductance.
4.2.6 IV behavior of the devices with a large dimension
Additionally, an ID-VDS measurement of a large device (20x600) was performed to check if
the maximum current would still increase with the dimension ration and shown in Fig. 4.12.
This measurement was carried out using the curve tracer which can measure the current
that is over 1A with a power limit of 50W.
Fig. 4.12 ID versus VDS curves of the device with a large dimension
Based on the result of Fig. 4.7, the estimated current density of the device at VGS of 5V is
(0.6, 0.8) A/mm. And the corresponding maximum current of this device is in the range of
26
(7.2, 9.6) A. Since the gate length is 3um, the maximum current is expected to be even larger.
But the experimental maximum current is 3.5A, less than half of the expected value. It could
be the high on-resistance of the large dimension device that leads to the degradation of the
maximum current density.
4.3 CV characterizations of the devices
The input capacitance of the HEMT devices is a significant value for the application in high
frequency. The input capacitance is mainly influenced by the gate to drain capacitance (CGD)
and the gate to source capacitance (CGS), these two values can be experimentally measured
to check the function of the gate as well as give a reference for the future optimization of the
devices for high-frequency application.
4.3.1 CV behavior of the basic HEMT device
The CV measurements started with the device with the smallest dimension (gate length
1.5um, gate width 100um) of wafer 4. After certain tests, it was found the CV curves showed
a step-like feature in the working region of the device under 1MHz frequency. The results
from the basic device are shown in Fig. 4.13.
Fig. 4.13 Capacitance of the basic HEMT device in wafer 4
The patterns of the CGS and CGD curves of the basic device are similar. As the gate voltage
increases from -20V to near -12.5V, the capacitance stays at about 0.19pF. And then the
capacitances sharply to a level of 0.33pF. According to the previous study on the gate
capacitance, there are three regions in the results, in the first region the capacitance mainly
depends on the capacitance of the buffer layer, then the 2DEG density increases
exponentially with the gate voltage in the second region and remains constant in the third
region, the strong 2DEG provides shielding and the gate capacitance is equal to the gate to
channel capacitance that is depending on the 2DEG density [36]. The results showed similar
behaviour with three regions, a detailed modelling and theoretical discussion of the gate
27
capacitance of one particular device could be a direction for the future project, in this work
the focus is on the characterization of devices with various designs. The difference between
the two curves of Fig. 4.13 is the voltage that the capacitance starts to increase. The CGS
and CGD curves are assumed to be identical and this shift could be related to the asymmetry
of the drain and source terminals
4.3.2 CV behavior of the devices with different gate length
Theoretically, the capacitance of the devices will increase with the surface area of the gate
finger. To check it in the devices, devices with gate length 1.5um (basic device) and 3um are
measured and compared.
Fig. 4.14 (a) CGS, (b) CGD of the devices with different gate lengths in wafer 4
The capacitance levels increase with the length of the gate. The lower levels increase from
0.19pF to 0.21pF, the higher levels increase from 0.33pF to 0.52pF. There is also a shift in
the curves which corresponds to the shift of the threshold voltage (shown in 4.2.4).
4.3.3 CV behavior of the devices with different gate to drain distance
To investigate if the capacitance is influenced by the distance between different terminals,
CV measurements of the devices of the different gate to drain distance are carried out and
shown in Fig. 4.15.
Fig. 4.15 (a) CGS, (b) CGD of the devices with different gate to drain distance in wafer 4
(a) (b)
(a) (b)
28
As the gate to drain distance increases from 10 to 15um, both CGS and CGD curves shift to
the left and the capacitance stays at the same level. This phenomenon corresponds to the
shift of threshold voltages (shown in 4.2.5) caused by the change of gate to drain distance.
4.4 Breakdown characterizations of the devices
The breakdown characterizations of the devices consist of two parts. In the first part, the
integrity of the gate insulation is tested by increasing the positive voltage at the gate and the
breakdown voltage of the gate insulation is obtained. In the second part, a high drain to
source voltage is applied to the devices at off state and the lateral breakdown characteristics
of the devices are obtained.
4.4.1 Gate insulation breakdown of the devices
The gate insulation breakdown tests were performed on the devices from wafer 4 (with a
silicon nitride insulation layer under the gate). After several tests, it was found the breakdown
voltage of the gate insulation is in the range of (40, 50) V. The results of the basic device are
shown in Fig. 4.16.
Fig. 4.16 Gate breakdown of Basic HEMT device in wafer 4
The initial gate current is at a range of 10-14 to 10-12 A. As the gate voltage increases, the
gate current gradually increases to 10-6A. From around 37V, the current remains at 10-6A
range until the voltage reaches the breakdown point and the current raise to the compliance
of 0.1A. The breakdown voltage is about 44V. After the test, the gate will be leaking, and the
gate current will reach compliance with a small voltage.
The effects of the gate to drain distance on the breakdown voltage are shown in Fig. 4.17.
The patterns of the curves are similar, while the breakdown voltage of the devices with a
larger gate to drain distance has a slightly larger breakdown voltage. The device with LGD of
12um shows a breakdown voltage of 46V and the device with LGD of 15um shows a
breakdown voltage of 47V.
29
Fig. 4.17 Gate breakdown of devices with different gate to drain distance in wafer 4
The effects of the gate length on the breakdown voltage are also investigated and shown in
Fig. 4.18. The device with a gate length of 3um shows a larger initial current of near 10-11 A,
and the breakdown voltage is still about 44V.
Fig. 4.18 Gate breakdown of devices with different gate length in wafer 4
In all the results the gate currents stay at around 10-5 to 10-6A as the gate voltages increase
to around 37V and suddenly rise to 0.1A at the breakdown voltage. These phenomena could
be related to the settings of sweeping the gate voltages, different sweeping speed of the
gate breakdown measurements could be tested for further investigation. In this work, the
gate breakdown voltages in the range of (40, 50) V are promising results that show the
devices are stable regarding the insulation of the gate.
4.4.2 Drain to source breakdown of the devices
To obtain the drain to source breakdown characteristics of the devices, a -15V gate to source
voltage is applied to the device to close the channel. The drain to source voltage is increased
30
as high as possible. However, due to the limit of the parameter analyser, the maximum
voltage applied to the device is limited to 200V. The results from devices of the different gate
to drain distance are shown in Fig. 4.19. The devices show a normal behavior until 200V
except a high leakage current level of near 20mA.
Fig. 4.19 ID versus VDS of devices with different gate to drain distance under -15V bias at
the gate
Since the voltage is limited to 200V and the drain to source breakdown voltage cannot be
obtained, a high voltage test was performed at Ascatron and the result is shown in Fig. 4.20.
The voltage step is large, and a snapback is observed at above 360V. The drain to source
breakdown voltage can be estimated to be in the range of (360, 400) V.
Fig. 4.20 Drain to source breakdown of the basic HEMT device performed at Ascatron
31
Conclusion
The GaN-based HEMT devices with different design variations were characterized regarding
performance for power electronics.
First the contact resistance in most areas of the wafers is high and nonuniform. Most of the
areas in the wafers have a contact resistance that is larger than 5 Ω·mm which could be
caused by the insufficient annealing process. The areas located closer to the center have a
relatively smaller resistance (4.3 Ω ·mm), and this phenomenon indicates the temperature
distribution of the wafers is uneven during the annealing processes which leads to the non-
uniformity of the contact resistance.
IV measurements were performed for obtaining the characteristics of the devices under
forward bias. Basic devices with different gate designs are compared. The basic MIS-HEMT
device has a threshold voltage of -12.3V, a maximum current density of 0.68A/mm, and a
maximum transconductance of 62 mS/mm. The basic device with a Schottky gate has higher
threshold voltage of -2.1V, there is large leakage at the gate and the maximum current
density as well as transconductance are lower than the MIS-HEMT. For MIS-HEMT devices
with different gate widths, the maximum current density is in the range of (0.6, 0.8) A/mm.
By increasing the gate length from 1.5um to 3um, the maximum current density increases
to 1.06A/mm. The distance of gate to drain also has effects on the maximum current density,
the device with 12um gate to drain distance shows higher current density (1.15 A/mm) than
devices with 10um and 15um.
Gate capacitance of the MIS-HEMT devices were measured. The capacitance increases
from 0.19pF to 0.33pF as the gate voltage increases from -20V to 0V. Around the threshold
voltage, the device is turned on and the capacitance increases. By increasing the gate length
from 1.5um to 3um, the maximum capacitance increases from 0.33pF to 0.52pF. Variations
in the gate to drain distance have little effect on the capacitance.
Breakdown characterizations reveal the gate insulation SiNx layer of the MIS-HEMT devices
is stable up to 40V. Devices with a larger gate to drain distance have a larger gate breakdown
voltage. The leakage current of the devices is as high as 20mA. The large leakage may be
due to the surface leakage in the passivation layer. High voltage test indicates the drain to
source breakdown voltage is in the (360, 400) V range.
Above all, the power-related performance of the devices with different designs are compared.
Contact resistance of the electrodes are high and the annealing processes should be
modified for forming better contacts. The MIS-HEMT device has a larger current density and
less gate leakage than the Schottky gate device. The maximum current scales with the
widths of the gate. By optimizing the parameters of the gate dimension and distance
between the terminals, a higher maximum current can be obtained. The gate capacitance
values of the devices are in (0.3, 0.5) pF. Gate breakdown voltages are in (40, 50) V range
and vary with the gate to drain distance. Drain to source breakdown voltage is estimated in
(360, 400) V. The leakage current of the devices is 20mA, making them unreliable for
32
application, quality of the layers should be improved to settle the problem. Based on these
results, the design and fabrication processes of the GaN-based HEMT devices can be
further optimized for real application.
33
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