characterization and modeling of complex chip ......discontinuidades introducidas por los paquetes,...
TRANSCRIPT
CHARACTERIZATION AND MODELING OF COMPLEX
CHIP-TO-CHIP INTERCONNECTION CHANNELS ON PRINTED CIRCUIT BOARDS USING HIGH-FREQUENCY
TECHNIQUES
By
Gaudencio Hernández-Sosa.
A thesis submitted in partial fulfillment of the requirements for the degree of M. Sc. in Electronics
Supervisors:
Dr. Reydezel Torres Torres Instituto Nacional de Astrofísica, Óptica y Electrónica.
Dr. Gerardo Romo Luévano
Intel – Systems Research Center Mexico
Tonantzintla, Pue.
August 2008
©INAOE 2008
All rights reserved The author hereby grants to INAOE permission to
reproduce and to distribute copies of this thesis document in whole or in parts
iii
Abstract
For many years, the electrical interconnection between chips has been
implemented using interconnects and packages fabricated with Printed Circuit
Board (PCB) technology. However, higher speed and higher density
electronic devices required in current technologies have pushed the
performance of the chip-to-chips interconnection channels fabricated with
PCB technology to its limits. The main limiting factors at high-frequency of the
chip-to-chip channels are the electrical discontinuities introduced by
packages, vias, sockets and connectors that form the channel. In
consequence, the development of interconnects and packages capable of
guiding broadband signals without degrading the signal integrity to
unacceptable levels is necessary to obtain reliable high-frequency/speed
chip-to-chip interconnection channel.
Thus, due to the importance of PCB technology in advanced electronic
systems, an exhaustive study of the most relevant characterization and
modeling techniques used in this area is presented in this thesis. For this
reason, several chip-to-chip prototypes channels were designed,
implemented, and measured using state-of-the-art simulation software and
test equipment. This allowed that the results obtained in this thesis are
supported with rigorous theoretical and experimental analyses. Among the
contributions that the reader will find in this document are several alternative
characterization methods based on time and frequency domain data,
improved models for the electrical transitions occurring in an actual
interconnection channel, and physical explanations about the origin of each
effect occurring as a signal propagates through these interconnects.
v
Resumen
Durante muchos años, la interconexión eléctrica entre chips ha sido
implementada usando paquetes y conectores fabricados en tarjetas de
circuito impreso (PCB). Sin embargo, las densidades y velocidades más altas
en los dispositivos electrónicos requeridos en las tecnologías actuales han
empujado el desempeño de los canales de interconexión chip a chip
fabricados con tecnología PCB a sus límites. Los principales factores que
limitan a altas frecuencias los canales de interconexión chip a chip son las
discontinuidades introducidas por los paquetes, vias, sockets y conectores
que forman el canal. En consecuencia, el diseño de paquetes y conectores
capaces de guiar señales de banda ancha sin degradar la integridad de la
señal a niveles inaceptables es necesario para obtener canales de
interconexión chip a chip de alta velocidad confiables.
Así debido a la importancia de la tecnología PCB en sistemas
electrónicos avanzados, un estudio exhaustivo de las técnicas más
relevantes de caracterización y modelado usadas en esta área es presentado
en esta tesis. Por esta razón, algunos canales de interconexión prototipos se
diseñaron, fabricaron y midieron usando software de simulación, de diseño y
equipo de medición modernos. Esto permitió que los resultados obtenidos en
esta tesis sean soportados por análisis teóricos y experimentales rigurosos.
Entre las contribuciones que el lector encontrara en este documento son
algunos métodos de caracterización alternativos basados en datos en el
dominio del tiempo y frecuencia, mejores modelos para las transiciones
eléctricas que se encuentran en un canal de interconexión avanzado y
explicaciones físicas acerca del origen de algunos efectos que ocurre cuando
una señal se propaga a través de este tipo de interconexiones.
vii
Acknowledgments
I would like to thank Dr. Reydezel Torres Torres and Dr. Gerardo
Romo Luévano for having given me the opportunity to work with them.
Thanks for their friendship, patience, guidance and help through the course of
the work.
I thank Intel for the opportunity they gave me approving my internship
stay at the Systems Research Center Mexico (SRC-M). I also express my
gratitude to the people who made it possible, especially to Jim Noval and
Genoveva Maciel. I would also like to thank the Advanced Signaling
Technologies Group of SRC-M: Adán Sánchez and Luis F. Armenta for the
valuable help and friendship during my stay at Intel.
I thank all my friends, especially to Eric Mario Silva Cruz, Ignacio
Rocha Canales, Julio César Vázquez Hernández, David Ernesto Troncoso,
Miriam Guadalupe Cruz Jiménez, Isaías Zagoyas Mellado (and colleagues at
INAOE) who are great friends in my work and my life.
Finally, I thank INAOE and CONACYT Mexico for the economic
support and facilities used during the realization of this work.
DEDICATION
To my parents and brothers who mean the world to me and have been on my side in making my imaginings come true… Thanks for your love
and patience
To my future wife, I know that you will make me feel good and
happy the rest of my life…. I love you wherever you are…..
xi
Contents
Abstract iii
Resumen v
Acknowledgments vii
Preface xv
1. Overview for Chip-to-Chip Interconnection Channels
Fabricated on Printed Circuit (PCB) Technology…………. 1 1.1 Introduction ……………………….……………………………………..…1
1.2 Description of a Typical Chip-to-Chip Interconnection Channel on
PCB…………………………………………………………………………. 4
1.2.1 The IC Package …………………………….………………..…5
1.2.2 Transmission Lines ……………………………….………………..7
1.2.3 Other Components (Vias, Microvias, Solder Bumps, Sockets,
etc.)…………………………………………………………………...8
1.2.3.1 Vias and Microvia………….………………..9
1.2.3.2 Solder Bumps and Sockets………………10
1.3 Expected Bandwidth Demand of Chip-to-Chip Interconnection
Channels ……………………………………………………………….12
1.4 Limiting Factors in the Performance of Chip-to-Chip Channels on PCB
at High-Frequency...……………………………………………………....14
1.5 Challenges in the Characterization and Modeling of High-Frequency
and High-Speed Interconnections …………….…………………………17
1.6 Purpose of this Thesis…….……………………………………………....18
xii
2. Electrical Characterization and Modeling Techniques for IC Packages and Interconnects …………………… …………19
2.1 Introduction …………………………….…………………………………19
2.2 Electrical Characterization Using Frequency-Domain Measurements20
2.3 Electrical Characterization Using Time-Domain Measurements..……26
2.4 Calibration and De-embedding Processes in Frequency and Time-
Domain………………………………………………………...……………31
2.5 Comparison Between Frequency and Time-Domain Approaches...…36
2.6 Equivalent Circuit Modeling of Interconnect ………………...………....38
2.6.1 Model Extraction from S-Parameters Measurements…………39
2.6.2 Model Extraction from TDR/T Measurements …….…………44
2.7 Electromagnetic Modeling Approach …………….…………………46
2.8 Conclusions ……………………………………….………………………48
3. Electrical Characterization and Equivalent Circuit Modeling of CPW-Microstrip (CPW-M) Transition… …49
3.1 Introduction ……….………………………………………………………49
3.2 A New Characterization Method for Electrical Transitions Using
Transmission Line Measurements ………………………….……51
3.3 Application of the New Characterization Method to a CPW-M
Transition…………………………..……………………………………….59
3.4 Validation of the New Characterization Method: Frequency and Time-
Domain Correlations to Measurements …………………….…………64
3.5 A New Equivalent Circuit Topology to Modeling CPW-Microstrip
Transition…………………………………………………………………...67
3.6 Analytical Extraction of the Lumped Elements Values for the CPW-M
Equivalent Circuit Topology …………………………….…………74
xiii
3.7 Validation of Equivalent Circuit Topology and Extracted Values:
Frequency and Time-Domain Correlations to Measurements ……….84
3.8 Conclusions …………………………………….…………………………87
4. Electrical Characterization and Equivalent Circuit Modeling of Prototype Chip-to-Chip Interconnection Channels ……………………………………………………………….89
4.1 Introduction ……….………………………………………………………89
4.2 Description of Prototype Chip-to-Chip Interconnection Channels……89
4.3 Electrical Characterization of Prototype Chip-to-Chip Interconnection
Channels……………………………………………………………………94
4.3.1 Cascade Model for a Prototype Chip-to-Chip Interconnection
Channel……………………………………………………………..97
4.3.2 Determination of S-parameter Model for the Cascade Model
Using Thru-Reflect-Line (TRL) Calibration Technique ….……97
4.3.3 Validation of the Characterization Process Using Frequency and
Time-Domain Correlations to Measurements………..……….104
4.4 Equivalent Circuit Modeling of Prototype Interconnection
Channels………………………………………………………………….107
4.4.1 Equivalent Circuit Modeling of the Thick Channel…….…….109
4.4.2 Validation of Equivalent Circuit Topology for Thick Package.112
4.5 Conclusions …………………….……………………………………….114
5. Future Developments …………………….…………………….…115
5.1 Introduction …………………………….……………………………….115
5.2 Issues Under Investigation ………………………………….………….116
xiv
5.2.1 Simulation of the Resonance in the Thin Package: Full-Wave
Solvers…………………………………………………………….117
5.2.2 Parallel Plate Propagation Modes (PPM) in Thin Package…120
5.2.3 Performance of a Simple Via Transition with PPM Effects…125
5.3 Future Research ……………………………………………………..128
5.3.1 Challenges in the Development of a PPM Experimental
Characterization Methodology……...…………………………..128
5.4 Conclusions ……………………………………………………………..132
6. General Conclusions ………………………………………..……135
Appendix A ……………………………………………………..139
List of Figures ……………………………………………………………..145
List of Tables ………………………………………………..……………150
Bibliography ……………………………………………………………..151
xv
Preface
Technology trends toward higher speed and higher density devices have
pushed the performance of current chip to chip interconnection channels to its
limits. In fact, the clock rates of modern personal computers are within the
GHz range since the data rate requirements are usually at some tens of
Gbps. Thus, the fabrication of interconnects and packages capable of guiding
broadband signals without degrading the signal integrity to unacceptable
levels is necessary. For instance, in the case of data rates of 20 Gbps, the
minimum bandwidth necessary to transmit digital signals is about 30 GHz
because the most significant frequency content extends up to the third
harmonic.
While the chip design and fabrication technology have undergone a
tremendous evolution, the package design has lagged considerably. In fact,
the delay associated with the package is reaching unacceptable levels within
the system timing budget and has become the bottleneck when designing
high-speed interconnection channels. Then, the package performance at high
frequencies has to be improved, which can be achieved by identifying the
critical effects degrading the corresponding electrical performance. In
consequence, behavior of the package at high frequencies has to be
accurately known, so that its negative influence on the channel performance
can be reduced. In order to do this, equivalent circuit models of the package
can be used in the analysis to perform time-efficient and accurate channel
simulations, as well as to carry out an optimization of the interconnection
channel.
Several methodologies and techniques for characterizing and
modeling electronic packages have been previously reported. However, most
xvi
of these techniques were developed at relatively low-frequency ranges,
becoming inaccurate for the current operation frequencies of interconnection
channels. For this reason, detailed analyses of package structures and the
corresponding performance up to frequencies of at least 30 GHz have been
carried out in this project. In addition, equivalent circuit topologies to
represent packages and other transitions within this frequency range have
been exhaustively analyzed, proposed and verified. Thus, one of the steps in
the analysis process is the determination of the experimental data associated
with the transitions using typical characterization approaches: frequency and
time domain data processing. The validity and physical significance of the
extracted data and developed models is verified by an exhaustive correlation
of simulations and measurements in both, time and frequency domains.
1
CHAPTER I Overview for Chip-to-Chip Interconnection Channels Fabricated on Printed Circuit Board (PCB) Technology
1.1 INTRODUCTION
There are two categories of electronic products that can be considered the
most important in the market of electronics: one is influenced primarily by the
requirement for high-performance, and the other by size and cost. The first
category includes high-performance/reliability products (e.g., those used for
avionics, space, medical and military applications), whereas the second one
is represented by high-volume and low cost products (such as personal
computers and cell phones). The life cycle of many of these products,
particularly those within the high-volume consumer category, is on the order
of one year or less. Thus, in order to achieve product marketability, every new
product model must be “smaller, better, and cheaper”.
Along years, the demand for electronic products with these properties
has experienced a tremendous increase in the number, variety and the
availability. Hence, all these products have taken advantage of the ever-
increasing performance potential of the integrated circuit. Nevertheless, to
fulfill this increasing demand, an electronic product requires a cost-efficient
manufacturing process (well-known as electronics manufacturing process or
simply EMP) in order to achieve the expected performance. On the other
hand, the EMP must allow the fabrication of “smaller, better and cheaper”
products. Currently, this requirement represents one of the most important
factors influencing the electronics industry. In consequence, every section
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Level Description
0.0 Gate-to-Gate and Gate-to-I/O pads connections are included in this
level of interconnection. This level is known as on-chip connections
also.
1.0 Here, the interconnection of chip to a package is done and when
multiple chips are connected to a package is known as Level 1.5 (In
fact is a “pseudo level”).
2.0 This level refers to the interconnection of multiples packages
through a substrate interconnection. This is typically a Printed Circuit
Board (PCB).
3.0 Interconnection of multiple Level 2.0 Boards through connectors
(cables, backplanes, etc). The resulting set of assembled boards is
known as Motherboard.
Table 1.1 Description of EMP’s interconnection levels [1].
Thus, in order to reach the highest possible performance in the final product,
special attention must be paid to the following points:
• electrical, mechanical, and thermal requirements inherent in the IC,
and
• accommodating these requirements to the EMP so that cost-effective
products can be obtained.
When these two requirements are fulfilled, the EMP is successful, and
marketable and competitive products are obtained. Therefore, a successful
EMP must evolve together with IC technology since the ICs have changed
significantly over the years and will continue to do so. In consequence,
changes in the packaging and assembly processes are necessary and they
have to be continuously improved. This suggests that analyzing the projected
requirements of the future ICs is important when implementing successful
manufacturing processes.
4
Through years, successful EMPs have been accomplished using
several interconnection and assembly technologies to fulfill the requirements
inherent to IC-based electronic systems. The interconnection technology
used in current EMPs is known as printed circuit board (PCB) technology and
allows interfacing several IC’s mounted in a dielectric substrate (i.e. the
board) using transmission lines and other interconnects. Nonetheless, higher-
speed and higher-density ICs have pushed the performance of this
interconnection technology to its limits because this kind of devices demands
high-speed interconnections that preserve the integrity of the propagated
signals. Up until now, however, current interconnection technology has
survived to large changes in IC technology. In order to extend the applicability
of the PCB technology, new signaling schemes have been developed, such
as differential signaling schemes (two wires per one signal) [2, 3]. With this
type of techniques, the implementation of chip-to-chip interconnection
channels working at higher data rates than those using singled-ended
schemes (one wire per signal) is possible. Unfortunately, this is not enough
when data rates are within the tens of giga-bits-per-second (Gbps).
Furthermore, at high-data-rates the interconnection channels present
undesirable effects that have to be minimized (or suppressed if possible) in
order to fulfill the requirements of a successful EMP. In the next section, a
chip-to-chip interconnection channel in current PCB interconnection channel
is described.
1.2 DESCRIPTION OF A TYPICAL CHIP-TO-CHIP CHANNEL ON PRINTED CIRCUIT BOARD (PCB)
The purpose of an interconnection channel is providing electrical
interconnection between the input/output (I/O) terminals of two silicon chips
(i.e., ICs) to establish a communication path that allows information data
interchange. However, the optimal electrical interconnection of chips is not
5
the only requirement of a chip-to-chip interconnection channel; the thermal
and mechanical specifications inherent to the IC must also be accomplished
to reach the highest possible performance of the final product. In order to
accomplish these requirements, a chip-to-chip interconnection channel is
designed to be composed by the following parts:
• IC Packages
• Transmission Lines
• Others components (vias, microvias, bumps, sockets).
The role of each component in a complex interconnection channel and some
of the most important corresponding properties are described below.
1.2.1 The IC Package
An IC package serves as an electrical interface between the chip and the rest
of the system but also has the function of providing mechanical support and
protection to the IC, as well as serving as a thermal dissipation medium.
Mechanically, a package allows the functionality of the device to be fully
accessed and to be assembled and electrically interconnected to other
devices (Level 2.0). As an enclosure it provides protection from physical
damage and a supportive and controlled operating environment for the
device, whereas from the thermal point of view allows the heat dissipation.
Physically, the package has suffered many changes responding to the needs
of the IC, the final product, and certainly to cost considerations. Ideally the
key guidelines for package design are:
• providing a package that fully supports the IC, responding to inherent
thermal, mechanical and electrical requirements,
6
• reducing as much as possible the negative impact of the package in
the system overall performance,
• making the package as small as possible, and finally,
• providing a cost-effective package (i.e., achieve that the package’s
cost does not represent a substantial percentage of the final device’s
selling price).
Through years, the packages have evolved to fulfill these guidelines. In
this evolution, several changes in the package structure and fabrication
materials have taken place. Figure 1.2 graphically shows the industry’s past
history and current trends in IC packages. In particular, this figure illustrates
the evolution as the IC’s I/O terminals increase and the dimensions shrink.
Figure 1.2 IC package history and trends [1].
The package miniaturization has been influenced by the continuing
demand for high-performance and small products. Additionally,
miniaturization is marked not only by a smaller package, but also by the
7
improvement of the packaging efficiency (PE) which is defined as the ratio of
the area occupied by the active device, i.e. the chip and the area required to
attach the packaged device to the next level of interconnect, the PCB. Thus,
higher PE results in improved device performance at Level 1 and Level 2. At
Level 2, the smaller packages yield a significant increase in the number of
components that can be placed within a given board area.
1.2.2 Transmission Lines Transmission lines are used to carry information (as electromagnetic energy)
from one point to other. In these lines, the electromagnetic waves have
specific electromagnetic field patterns which confer special properties. Along
years, transmission lines have been developed to work at higher frequency
and as a result, there are many types of transmission lines, each one with
particular electromagnetic field patterns.
The most popular transmission lines used in chip-to-chip
interconnection channels on PCB are microstrips, coplanar waveguides
(CPW) (see Figure 1.3), striplines and some variants of these (e.g. cover
backed coplanar waveguides or CB-CPW). The main reason why these kinds
of transmission lines are used is because their easy manufacture with planar
lithographic processes such as transistor fabrication process. Furthermore,
transmission lines fabricated with planar lithographic process have certain
properties (such as mechanical stability, thermal dissipation facility, low cost,
etc.) that represent attractive advantages over other kinds of waveguides.
Thus, in spite of the fact that some types of waveguides have higher
bandwidth than conventional transmission lines on PCB, the physical
structure of waveguides is not compatible with conventional PCB fabrication
processes, with some exceptions [4].
8
Figure 1.3 Microstrip and CPW lines with their corresponding electromagnetic
field pattern.
Today, the research efforts on transmission lines are focused on:
a) substrates fabricated with new materials in order to reduce the
insertion loss and therefore increasing the bandwidth [5],
b) new types of transmission lines with several advantages (less
dispersion, lower losses, and lower effective dielectric constant [6])
and
c) improving bandwidth of existing transmission lines by means of new
signaling techniques such as differential signaling [2] and other
techniques [7].
1.2.3 Other Components (Vias, Microvias, Solder Bumps, Sockets, etc.)
In addition to transmission lines, other components are necessary to
implement chip-to-chip interconnection channels. Among these, there are
vias, microvias, bumps, etc. Their function is to provide electrical
interconnection between different layers in a multilayered PCB or package
9
(for the case of vias and microvias). In the case of bumps, the corresponding
function is basically to interconnect a chip to the package (Level 1.0), the
package to the PCB (Level 2.0). The following lines describe briefly each one
of these components. Some details about these components are discussed
hereafter.
1.2.3.1 Vias and Microvias
A via is a vertical transition in a multilayered environment and it provides
interconnection between different layers. Generally, vias are used in
multilayered PCBs to reach high-density interconnection. Depending on the
physical configuration there exist three distinct types of vias:
• through-hole
• blind, and
• buried via.
These are illustrated in Figure 1.4. The type of via influences the
substrate size of a multilayered PCB and because of this the use of each type
determines important properties of it such as substrate size, interconnection
density and others.
Figure 1.4 Through-hole, blind and buried via.
10
The most common way to fabricate vias is using mechanical drill.
However, mechanically drilled vias are limited to diameters down to
approximately 150 µm (6 mils). Below this diameter, the production cost
becomes very costly due in part to the deterioration of the drill bit. Alternative
methods for the generation of vias include:
• wet or dry (plasma) etching,
• laser drilling (ablation),
• photo-imaging, and
• conductive ink-formed vias.
These processes are depicted in chapter 15 of the reference [1]. All these
processes are readily capable of producing vias that are very much less than
150 µm in diameter down to the desired 25 to 50 µm diameter and pitch
range. The Association Connecting Electronic Industries have defined any via
that is equal or less than 150 µm (6 mils) in diameter as a “microvia” [8].
Generally, microvias are used in package fabrication because they
offer advantages over plated through-holes, for example when the chip I/O
pad pitch is very small, microvias allow high-density interconnect for these
types of chips. As a result, a new emergent interconnection technology
known as high density interconnection (HDI) is using microvias to achieve
large interconnection density in thin and thick film substrates.
1.2.3.2 Solder Bumps and Sockets
Solder bumps is a special component in a chip-to-chip interconnection
channel. Essentially, a solder bump is a conductor portion with a ball shape
and it is used in current interconnection technology to provide electrical
connection between a package and the IC or between a package and the
11
PCB. Figure 1.5 shows graphically the solder bump function. In emergent
interconnection technologies solder bumps are not always present in a chip-
to-chip interconnection channel. However, along years solder bumps have
been used successfully and at this time these components still are using in
current interconnection channels.
Figure 1.5 Solder bump serving as an electrical interface between an IC and
the package.
Sometimes solder bumps are not used as electrical interfaces between
packages and the PCB. Instead of solder bumps, sockets are used to
establish electrical connection. The use of each one of these (solder bumps
or sockets) is related to the kind of electrical interconnection. Solder bumps
are used when the package is permanently connected to the PCB, as a result
the package is irremovable by means of simple mechanical force. In contrast,
sockets provide temporary connection to the PCB and allow removing the
package by means of simple mechanical force. Thus, a temporary connection
to the PCB opens the possibility of replacing old ICs by new ICs when it is
necessary.
All the components previously described are shown in a simplified
cross-sectional view of a chip-to-chip interconnection channel (Figure 1.6).
12
Figure 1.6 Simplified cross-sectional view of a typical interconnection
channel.
1.3 EXPECTED BANDWIDTH DEMAND OF CHIP-TO-CHIP
INTERCONNECTION CHANNELS
In the last decades, most of the electronic products were based on analog
systems. Even though analog systems are still used in many applications,
digital systems are the principal type of electronic products in the market
these days. Currently, many digital electronic products use a microprocessor
and memory chips and this type of systems are well-known as
microprocessor-based systems.
The future microprocessor-based systems demand reliable high-speed
interconnection channels to support high-data rates. Today, higher-speed
silicon chips are available as a result of the continuous improvement of the
fabrication processes, new fabrication materials, miniaturization, etc.
Consequently, CPUs present higher speed and are more powerful than their
predecessors substantially increasing the system performance. Nevertheless,
as the CPUs become more powerful, the data transmission rates between
chips increase. Thus, the required channel bandwidth also increases in order
to obtain maximum performance. For this reason, current interconnection
technology has evolved to fulfill bandwidth requirements and also competitive
and marketable requirements.
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7 shows th
future year
d to be clo
mory a high
digital signa
tion. When
ast the thi
tained in th
ain bandwid
cated that
al signal of
croprocess
terconnectio
xpected da
n technolo
and physic
erials used
13
in
he
rs.
se
her
als
n a
ird
he
dth
a
f X
sor
on
ata
gy
cal
in
14
multilayered PCBs (e.g., FR4 and cooper) have physical limitations at high-
frequencies. Moreover, the physical structure of a whole interconnection
channel is very complex and introduces unwanted electromagnetic
phenomena causing inappropriate channel operation. Some techniques have
been developed to increase the bandwidth, such as new signaling schemes
(the way the signal is sent over transmission lines with a specific
electromagnetic field pattern). In Figure 1.7 it can be noticed that a differential
signaling scheme is used in current processor’s interfaces. Although new
signaling schemes have been designed to reach higher bandwidths with
current interconnection technology, it is not enough to obtain higher
bandwidths and research about unwanted electromagnetic phenomena is
required also. Nowadays, there is a continuous effort in the development and
introduction of new materials and new designs in order to achieve better chip-
to-chip interconnection channels and furthermore fulfill future bandwidth
requirements.
1.4 LIMITING FACTORS IN THE PERFORMANCE OF CHIP-TO-CHIP CHANNELS ON PCB AT HIGH-FREQUENCY
In the previous section, the expected bandwidth requirements for
microprocessor-based systems were shown. Thus, it is clear that high-
frequency and high-speed interconnection channels are required to support
the expected bandwidth. In order to understand the main limiting factors in a
high-frequency and high-speed interconnection channel on PCBs, the terms
high-frequency and high-speed interconnect must be defined. The term “high-
speed” can be defined in terms of the frequency content of the signal. If the
frequency content of a “high-speed signal” propagating throughout an
interconnection is considerable, then the term high-frequency can be applied
as an adjective to describe the interconnection. On the other hand, the term
“high-frequency” is relative and generally applied to describe the microwave
15
region of the electromagnetic spectrum (within GHz range). In order to
understand the previous discussion, a brief elaboration on this context is
presented afterwards.
At low frequencies an interconnection (for example a cooper wire) will
effectively connect two points in an electrical circuit, and it can be thought of
as a short-circuit. However, this is not the case at higher frequencies. The
same wire, which is effective as a communication channel at low frequencies
for connection purposes, presents much inductive/capacitive effects to
function as an electrical short when it operates at higher frequencies. Thus, if
a fast time-varying signal with sharper slew rate is propagating throughout an
interconnection, the frequency content related to this signal will tend to grow.
In consequence, the wire that serves as interconnection will need to support a
wider frequency bandwidth and therefore the capacitive/inductive effect will
affect the integrity of the signal. In this case, it can be said that the
interconnection is working at a high-frequency.
Figure 1.8 High-speed interconnection effects [11].
There are several limiting factors for a high-speed interconnection on a
PCB. As a simple example, a wire used as a high-speed interconnection
presents unwanted effects. Moreover, the layout of an actual complex PCB
16
involves also a large number of components such as connectors, unusual
terminations, bends, presence of packages, via holes, line crossing, etc. All of
these components are electrical discontinuities and their presence causes
some “high-speed effects,” yielding signal distortion. Among the “high-speed
effects” there exist radiation, delay, rise time degradation, attenuation,
crosstalk, skin effect, overshoots, undershoots, ringing, and reflection. A
detailed explanation of each one of these effects can be found in [11]. As can
be seen, the degradation of the signal quality is due to these effects, having a
direct impact on the functionality of the digital devices mounted on a PCB.
As it was mentioned before, differential signaling schemes are
considered as an alternative signaling scheme for microprocessor-based
systems because they offer several advantages. However, the high-speed
effects caused by the electrical discontinuities also affect the differential
signaling scheme and the main weakness of this signaling scheme is the
creation of common mode components. In [12], a complete explanation about
the common mode components for differential signaling and the
corresponding impact on the signal integrity is presented. Generally, common
mode components are usually very small in magnitude and their effects on
the signal quality are minor. However, when the amount of common mode
current increases, it can significantly increase the level of electromagnetic
interference (EMI), degrading the system performance from an
electromagnetic compatibility (EMC) point of view. The understanding of the
physical phenomena occurring on a board for the presence of discontinuities,
which is responsible for common mode creation for the case of differential
signaling (or conversion to other undesired propagation modes for singled-
ended signaling), directly helps the understanding of the physical nature of
several effects.
17
1.5 CHALLENGES ON THE CHARACTERIZATION AND MODELING OF HIGH-FREQUENCY AND HIGH-SPEED INTERCONNECTIONS
As a result of the negative impact of high-speed effects caused by the
electrical discontinuities in the signal integrity for high-frequency/performance
applications, a continuous effort is ongoing in the characterization and
modeling of these electrical transitions in order to minimize or suppress their
effects. Thus, the evaluation of the electrical performances of the electrical
discontinuities and their impact on the signals is an essential step at the
design stage of a board and therefore of reliable high-frequency/speed chip-
to-chip interconnection channel. Besides, the evaluation of the impact of the
discontinuities on the channel performance allows to extract equivalent circuit
models that can be included as part of more complex circuits representing a
system implemented on PCB. Circuit simulators are then relatively fast and
predict signals accurately. From these signal integrity (SI) quantities, it is
possible to anticipate board’s related EMI.
The most popular way to evaluate the performance of a discontinuity is
performed in terms of scattering parameters (S-parameters). These
parameters can be obtained from numerical simulations (3D Modeling) or
from measurements. The numerical simulations must capture the correct
distribution of the electromagnetic field in order to take into account all the
significant effects associated with a discontinuity, but significant CPU time
and memory is required. On the other hand, from a measurement point of
view, at the frequencies of interest, it is generally not possible to get access
to the structure without impacting the measurement being made. A typical
example is the experimental characterization of a via hole in which the
presence of feeding parts (traces, adapters, or pads) connecting the
instrument’s ports to the via must always be present. To overcome the above-
18
mentioned difficulties, it has become standard practice to characterize the
effects of the test access ports, feeding lines, or adapters and then to
separate them from the measurement relative to the complete structure: the
remaining data are those associated to the electrical behavior of the device
under test of interest. This procedure is known as de-embedding. In recent
years, a number of de-embedding methods have been reported in the
literature and their references give useful hints for modeling and
measurements. All these approaches used to characterize and modeling
electrical transitions will be detailed in the second chapter of this thesis.
1.6 PURPOSE OF THIS THESIS
The aim of this thesis is to carry out a research project about the electrical
behavior of interconnects at the levels 1.0 and 2.0 explained in this chapter.
In other words, singled-ended chip-to-chip channels which are composed by
packages (Level 1.0) and interconnections between them (Level 2.0) will be
studied. Since the interconnection between packages is carried out by means
of transmission lines implemented on PCB technology, several measurement-
based and simulation-based techniques are applied. For instance, by using
de-embedding techniques the electrical behavior of discontinuities in a
complex interconnection channel will be evaluated and later on, equivalent
circuit topologies are proposed for each transition presented in an actual chip-
to-chip link.
19
CHAPTER II
Electrical Characterization and Modeling Techniques for Integrated Circuit (IC) Packages and Interconnects
2.1 INTRODUCTION
In the previous chapter, details about the increased demand for miniaturized,
high-frequency and high-performance products were presented. This demand
makes system-level signal integrity to be a major issue commonly addressed
by means of electrical simulations during the design cycle of the final product.
In order to obtain accurate system simulations, accurate electrical models of
single components and interconnects are necessary. Among the components
that have to be modeled there are IC packages, transmission lines,
connectors and other transitions. However, obtaining accurate electrical
models within the GHz range, for example of a miniaturized IC package, is
not a trivial task. Thus, due to the importance of accurate models for
packages and interconnects at high frequencies, much work in this field is
currently ongoing in industry as well as in the academy. For instance, for the
case of microprocessor-based systems, a proper optimization of the
corresponding platforms is not possible without the aid of accurate models
and characterization techniques for interconnects.
This chapter is focused in analyzing current methodologies used for
measuring and characterizing packages and interconnections. Thus, three
approaches will be discussed: measurement-based analysis in the frequency
domain, measurement-based analysis in the time domain, and analysis
through full-wave simulations. As is well known, measured/simulated data
can be used to define models with the purpose of performing simulations in
20
SPICE-like circuit simulators. In addition to the modeling approaches based
on measurements, full-wave simulations can be used in parallel with
measurements frequently when electromagnetic field analysis of device
(package and interconnects) is required due to the complexity of the
structure. In this case, electrical measurements are used to support full-wave
designs, analysis and theories.
2.2 ELECTRICAL CHARACTERIZATION USING FREQUENCY-DOMAIN MEASUREMENTS
As it was mentioned in the introduction, when applied in a systematic way,
electrical modeling approaches are very helpful in predicting the performance
of packages and interconnects. Thus, package and interconnect electrical
models are usually needed before the actual physical chip-to-chip
interconnection channels are available. In order to obtain electrical models
from measurements, there are two popular approaches: a) based on
frequency-domain measurements and b) based on time domain
measurements [13]. In this section, the electrical characterization using
frequency-domain measurements is described.
When an electrical circuit operates at relatively low frequencies it can
be represented by means of lumped passive/active elements with unique
voltages and currents defined at any point in the circuit. This assumption is
valid when the circuit dimensions are small relative to the wavelength. Under
this condition, the electromagnetic fields associated to the electrical circuit
can be considered as transversal electromagnetic (TEM) fields supported by
two conductors and Maxwell’s equations have a quasi-static solution. This
solution is well-known as the Kirchhoff Voltage and Current Laws. In contrast,
when the dimensions of the electrical circuit are not small when compared
with the signal wavelength, the quasi-static solutions of the Maxwell’s
21
equations are not applicable anymore and a further analysis is required.
Nonetheless, in order to carry out the corresponding analysis in this case, the
equivalent voltages and currents for non-TEM waves propagating along the
electrical circuit can be defined, as well as the equivalent impedance for non-
TEM waves [14]. Once the equivalent voltage and currents are defined,
powerful and useful set of techniques for analyzing low frequency circuits can
be used for developing new techniques to be applied to microwave circuits,
i.e. high-frequency circuits.
Low-frequency techniques to describe electrical circuits as N-port
networks use a matrix representation involving the voltages and currents
related to each port. Depending on the relation form between the voltages
and currents, the resulting matrix is known either as impedance, admittance
or transmission matrix, and this type of representation leads to the
development of equivalent circuits which are useful in the design of electronic
systems. For the case of microwave circuits, equivalent voltages and currents
are used in the definition of these impedance, admittance or transmission
matrices.
Figure 2.1 An arbitrary N-port network [14].
22
Figure 2.1 shows an arbitrary N-port network in which each port may be fed
by any type of transmission line or waveguide with TEM or non-TEM
propagation modes. At a specific point on the n-th port, a terminal plane, nt ,
is defined in order to provide a phase reference of incident and reflected
waves for the equivalent voltages ( +nV , −
nV ) and currents ( +nI , −
nI ). Thus, at
each terminal or port, the total voltage and current is given by:
−+ += nnn VVV (2.1)
−+ += nnn III (2.1)
Then, the impedance matrix Z of the microwave network which relates the
equivalent voltages (V) and currents (I) is given by the equation (2.3).
Similarly, the admittance matrix Y for the same network is defined by the
equation (2.4). As can be noticed, the Z and Y matrices are reciprocal of each
other and this reciprocity allows the determination of either Z or Y when the
reciprocal matrix is known respectively.
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡=
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡
nnnn
n
n I
I
ZZ
ZZ
V
VM
L
MOM
L
M1
1
1111
(2.3)
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡=
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡
nnnn
n
n V
V
YY
YY
I
IM
L
MOM
L
M1
1
1111
(2.4)
The previous equations can be rewritten in a compact form (matrix form). The
corresponding equations for Z and Y matrix are given by (2.5) and (2.6),
respectively.
V = Z ⋅ I (2.5) I = Y ⋅V (2.6)
23
As can be seen, the definition of the impedance and admittance matrices for
microwave circuits is similar to the corresponding definition for low-frequency
circuits. In this case, however, the voltages and currents are associated with
non-TEM waves. By inspecting the equation (2.3), it can be demonstrated
that the elements of Z can be found by measuring/computing the voltage-
current relations at each port under certain open-circuit conditions. In a
similar way, the elements of Y can be obtained, but establishing the
corresponding short-circuit conditions. Hence, to evaluate the response of a
device under test (DUT) at high-frequencies (unless otherwise stated in this
thesis the acronym DUT refers to interconnections and packages) either the
impedance or admittance matrix must be obtained.
There are some difficulties to directly measure the impedance and
admittance matrices for a microwave circuit. One of these is the difficulty to
define voltages and currents when non-TEM waves are present in microwave
circuits. For instance, a “conventional” voltage-current relation for defining the
impedance of a rectangular waveguide is not possible since this structure
presents a transversal electric (TE) fundamental propagation mode, i.e., a
non-TEM mode is present in the rectangular waveguide. As it is well known,
non-TEM propagation modes are not conservative fields and the
corresponding definitions of voltage and current depend on the integration
path, yielding different impedance definitions. In consequence, when the
propagation takes place in a non-TEM mode, the definition of voltage and
current is not unique since it is dependent on the integration path, just as it
was mentioned before. On the contrary, TEM waves are conservative fields
and the voltage and current definitions are independent of the integration
path. On the other hand, a practical problem exists when trying to measure
voltage and current at high-frequencies because direct measurements usually
involve the magnitude (inferred from power) and phase of a traveling wave in
a given direction. At high-frequencies it is more convenient directly relating
24
measurements with the idea of incident, reflected, and transmitted power
waves. In order to overcome the previously mentioned problems, the
generalized scattering matrix S is used at high-frequencies and it is defined in
relation to the incident and reflected waves in the network as:
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡=
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡
nnnn
n
n b
b
SS
SS
b
aM
L
MOM
L
M1
1
1111
(2.7)
Where nnn ZVa 0/+= and nnn ZVb 0/−= with nZ0 = characteristic impedance
at port n. In matrix form
a = S ⋅b (2.8)
Currently, an S-parameter data set can be acquired through measurements
using a vector network analyzer (VNA). From the surveyed literature, S-
parameters have become the most popular parameter set used to
characterize various interconnects such as packages and transmission lines
[15-28], coplanar silicon transmission lines [29], and high-density connectors
[30,31]. Moreover, S-parameter measurements have been used for
characterizing differential signaling scheme structures [32-36] and for
researching high-speed effects such as crosstalk [37]. Although several
methodologies have been published using different parameter sets, such as
Y and ABCD [38-40], the corresponding matrices are obtained from S-
parameter data sets using conversion formulas [14].
The S-parameter data set associated with a device allows the
determination of the corresponding typical high-frequency figures-of-merit and
parameters such as gain, loss, and reflection coefficient (Figure 2.2).
Furthermore, the measured S-parameters of multiple devices can be
c
a
a
t
a
e
t
cascaded t
are commo
H, Y, Z, T analytical fo
that the nu
(passive or
a two-port
parameters
emerges, a
is a measu
power stim
S11), a refle
Figure
Forw
magnitude
the output
impedance
S11 is equi
to calculate
only used i
and ABCDormulas pre
umber of e
r active) is e
device has
s is that the
and the sec
ure of powe
mulus to por
ection meas
e 2.2 Comm
ward S-par
and phase
is terminat
e Zo of the
valent to th
e overall sy
n both line
D paramete
esented, fo
elements in
equal to the
s four S-pa
e first numb
cond numbe
er emergin
rt 1 and wh
surement is
mon terms
rameters ar
e of the inci
ed in a loa
test system
he input co
stem perfo
ar and non
ers can be
or instance
n the S-pa
e square of
arameters.
ber following
er is the por
g from por
hen the nu
s indicated.
for high-fre
re determin
dent, reflec
ad that is pr
m. In the c
omplex refl
rmance. In
nlinear circu
derived fro
in [41]. It is
arameter m
f the numbe
The numb
g the S is t
rt at which
rt 2 as a re
mbers are
equency cha
ned comple
cted, and tr
recisely eq
ase of a s
ection coef
addition, S
uit simulatio
om S-para
s necessary
matrix for a
er of ports.
bering conv
the port at w
energy ente
esult of app
the same
aracterizati
etely by m
ransmitted
ual to the c
imple two-p
fficient, wh
S-paramete
on tools, an
meters usin
y to point o
a given DU
For examp
vention for
which energ
ers. Thus S
plying an R
(for examp
on [42].
measuring th
signals whe
characteris
port networ
ile S21 is th
25
ers
nd
ng
out
UT
le,
S-
gy
S21
RF
ple
he
en
tic
rk,
he
f
a
c
t
s
e
2
T
t
t
26
forward co
at the outpu
is possible
S22 is equ
impedance
coefficient.
there are o
solvers an
equations (
Figure
2.3 ELEDO
The secon
time-domai
(TDT) an
measureme
transmissio
mplex trans
ut port of th
to measur
uivalent to
e of the D
Additiona
other ways
nd computa
(they will be
2.3 Forwar
ECTRICAMAIN ME
d approach
in measure
nd time-do
ents are us
on of a pu
smission co
he DUT and
re the other
the outpu
DUT while
lly to freq
for obtainin
ation using
e described
rd and reve
AL CHAEASUREM
h for evalu
ements. Th
omain ref
sed to dete
ulse signa
oefficient (F
d terminatin
r two (reve
ut complex
S12 is th
uency-dom
ng the S-pa
g spectral
d in the sect
rse S-param
ARACTERMENTS
ating the re
hese includ
flectometry
ermine the
l through
Figure 2.3)
ng the input
rse) S-para
x reflection
e reverse
main measu
arameters
domain t
tion 2.7).
meters for a
RIZATION
esponse of
de both tim
y (TDR)
effect that
it, and TD
). By placin
t port in a p
ameters. Th
n coefficie
complex
urements w
such as us
technique
a two-port D
N USIN
f a DUT is
me-domain
measurem
t a network
DR is a m
ng the sour
perfect load
he paramet
nt or outp
transmissio
with a VN
sing full-wav
and integr
DUT [42].
G TIME
carrying o
transmissio
ments. TD
k has on th
measureme
ce
, it
ter
put
on
A,
ve
ral
E-
out
on
DT
he
ent
27
technique for evaluating the impedance of transmission line systems and/or
components such as connectors, packages, sockets, etc. The most popular
time-domain test signals used in TDR/TDT are the step and impulse
response. When a time-domain test signal is applied to the DUT, the resulting
response waveform presents amplitude, polarity, delay, rise/fall time, impulse
duration, exponential rise/decay, ringing, etc., which allows identifying the
internal nature of the DUT. The most popular time-domain measurement is
TDR and this is a technique based on transmission line theory. In order to
understand how TDR measurements can be a useful tool in the electrical
characterization of interconnection devices, theory and basics of this type of
measurements are briefly described hereafter.
The classical transmission line model is assumed to consist of a
cascade of R, L, C, and G lumped elements [43]. If the transmission line is
infinitely long, the impedance at the input of the transmission line is give as:
0ZCjGLjRZin =
++
=ωω (2.9)
where 0Z is the characteristic impedance of the transmission line. A voltage
waveform applied at the input of an infinitely long transmission line will require
a finite time to travel down the line to a point X. The voltage waveform at
point X will have a phase shift (β) and attenuation (α) with respect to the input
voltage waveform (Figure 2.4). These two quantities are related to the
propagation constant (γ), which is a fundamental parameter of a transmission
line. The phase shift and attenuation are defined by the propagation constant
and related to the RLCG elements as:
))(( CjGLjRj ωωβαγ ++=+= (2.10)
28
where β is given in radians per unit length, whereas α presents units of
nepers per unit length. The propagation constant can be used to define the
voltage and current at any point X in an infinitively long transmission line (see
equations 2.11 and 2.12).
l
inX eVV γ−= (2.11)
linX eII γ−= (2.12)
Figure 2.4 Voltage waveform after traveling from the input to point X in an
infinitely transmission line.
Since the voltage and current are related at any point by the characteristic
impedance of the line Z0, it is possible to write:
inin
inl
in
lin Z
IV
eIeVZ === −
−
γ
γ
0 (2.13)
where Vin and Iin are the incident voltage and current, respectively. On the
other hand, when a transmission line is finite and terminated in a load whose
impedance is equal to the characteristic impedance of the transmission line,
the voltage and current relationships are satisfied by equations (2.13).
29
However, when the transmission line is terminated with a load different from
Z0, the previous equations are not valid and a second wave, traveling in
backward direction (i.e. a reflected wave), has to be considered. Figure 2.5
shows a schematic representation where a transmission line is terminated in
a load with impedance ZL.
Figure 2.5 Transmission line terminated with different impedance to Z0.
The voltage at point A in Figure 2.5 can be written as
SSin
inA V
ZZZV+
= (2.14)
where ZS is the impedance of the voltage generator VS. In this case, the input
impedance Zin is a function of the characteristic impedance of the
transmission line (Z0), the load impedance (ZL), the propagation constant (γ),
and the position of the observation point (l); mathematically:
)tan()tan(
0
00 lZZ
lZZZZL
Lin γ
γ++
= (2.15)
As can be seen, the measured voltage at point A includes information
about changes in impedance. Moreover, the measured voltage also includes
additional information about propagation along the transmission line because
Z
s
d
w
g
o
T
s
t
a
d
30
Zin is a fun
measureme
simple ma
displayed i
which inclu
generator p
The
impedance
back to th
inferred fro
oscilloscop
The nature
size and sh
the DUT (s
nature (res
and wheth
losses. All
display. Si
meaningful
nction of γ.
ent tool use
athematical
n graphic f
udes a fast
produces an
Figure
idea behi
e discontinu
he monitori
om the tim
pe (along w
e and magn
hape of the
see Figure
sistive, indu
er attenuat
of this info
ince the fa
l informatio
A time-dom
ed to obtai
transform
form. Basic
t pulse gen
n incident p
2.6 Functio
nd TDR m
uity, a portio
ing oscillos
me at whic
ith the prop
nitude of th
e reflected p
2.7). There
uctive, or ca
tion in a tr
rmation is i
ast pulse
n concernin
main reflect
n the volta
ation the
cally, a TD
nerator in
pulse that is
onal block d
measureme
on of the fo
scope. The
ch the refle
pagation ve
he disconti
pulse comp
e exist ana
apacitive) o
ransmission
immediatel
step stimu
ng the broa
tometer (al
age at point
impedance
R is a very
the picose
s applied to
diagram for
nts is that
orward-trav
e position
ected sign
elocity of the
nuity can b
pared to the
alysis techn
of each disc
n system i
y available
ulus is bro
adband resp
so known
t A, and by
e profile o
y fast GHz
conds rang
o the DUT (
r a TDR [44
whenever
veling pulse
of the dis
al arrives
e pulse with
be determin
e original pu
niques to d
continuity a
is from ser
from the o
oadband, a
ponse of a
as TDR) is
y means of
of a DUT
oscilloscop
ge. The ste
Figure 2.6)
4].
r there is a
e will be se
scontinuity
back at th
hin the DUT
ned from th
ulse sent in
determine th
along the lin
ries or shu
oscilloscope
a TDR giv
DUT.
s a
f a
is
pe
ep
).
an
ent
is
he
T).
he
nto
he
ne
unt
e’s
es
31
Figure 2.7 Capacitive and inductive discontinuities calculated from TDR
waveforms.
Time domain measurements (TDR/TDT) have been widely used to
characterize packages [45-49] and interconnections [50-53] and, depending
on the configuration of the input source and the DUT, TDR/TDT
measurements can be single-ended, multiport, or differential. An introduction
to the fundamentals of differential TDR/TDT can be found in [54]. The
advantage of TDR measurements is that the individual components of the
DUT appear at separate time slots in a direct relation to their location.
Although the time-domain analysis of the TDR waveforms is simple and
straightforward, it is usually difficult to accurately determine closely electrical
discontinuities because the TDR resolution is limited mainly by the step
generator. In the section 2.5 a comparison between frequency and time-
domain techniques with their respective advantages and disadvantages will
be presented.
2.4 CALIBRATION AND DE-EMBEDDING PROCESS IN FREQUENCY AND TIME-DOMAIN
Ideally, it can be assumed that the high-frequency/speed response of a DUT
can be directly measured. However, the actual response of a DUT cannot be
measured without using test structures (e.g. pads, interconnection lines,
32
connectors, etc.) that allow accessing the points where the stimulus is applied
and the response is measured. These structures introduce unwanted effects
that have to be taken into consideration when obtaining the experimental data
associated with the actual DUT. An example of the additional structures that
have to be included in a practical setup for frequency/time measurement
systems is depicted in Figure 2.8.
Figure 2.8 Setup for performing high-frequency/high-speed measurements.
In the literature, the additional structures between the measurement
equipment and the actual DUT are referred to as test fixtures and their
function is to provide mechanical/electrical compatibility with the
measurement hardware. For instance, when using a VNA setup, this
hardware consists of the measurement equipment, cables, connectors and
probe tips which serve as mechanical/electrical medium between the test
fixtures and the VNA’s ports in order to feed the desired power to the device.
The test fixtures and the measurement hardware provide mechanical features
that yield the measurement facility. As can be seen in Figure 2.8, the DUT is
embedded between the test fixtures and the measurement hardware and
unfortunately, when measuring, unwanted effects are introduced outside the
DUT. Therefore, to obtain the actual response for the DUT, removing these
33
undesirable effects is necessary. In this section, a brief overview about this
topic is presented.
Most of the high-frequency and high-speed equipments have coaxial
connectors in their ports and therefore, the structure formed by DUT plus the
test fixtures must be connected to the VNA/TDR ports. Commonly, the
interconnection between the VNA/TDR ports and the test fixtures are
composed by coaxial cables and connectors, but sometimes probe-tips can
be used. In this case, removing the effect of the cables, connector and other
transitions between the equipment and the test fixture is known as calibration
process.
Figure 2.9 Shifting of the measurement reference plane through a
calibration process.
The calibration process allows removing the effects of the electrical
transitions from the equipment to the test fixture by shifting the reference
plane of the measurements from VNA ports to the beginning of this fixture. In
Figure 2.9, a simplified sketch illustrating the calibration process is shown.
The shifting of the reference plane is carried out by measuring structures
34
called “calibration standards” and using a mathematical algorithm that
corrects the measurements from the unwanted effects external to the test
fixture.
Along years, several calibration techniques have been reported such
as short-open-load-thru (SOLT), thru-reflect-line (TRL), and line-reflect-
match (LRM); the theory about these well-known calibration processes can
be found in [55]-[56], respectively. All of these calibration processes allow
shifting the reference plane and the majority are based on a key assumption:
the waveguides/transmission lines used as part of the measurement setup
must propagate only one mode at the measurement reference planes. Most
waveguides/transmission lines are designed so that only one dominant mode
is present. If some evanescent modes are excited at the electrical
discontinuities between the equipment’s ports and the test fixture, the
reference planes are chosen suitably far enough away so that their amplitude
can be neglected. However, when the discontinuities excite other propagation
modes which cannot be neglected, conventional calibration techniques are
not valid. For example, the TRL calibration theory has been extended to
taking account higher order propagation modes and it is known as multimode
TRL [57]. As can be seen, the calibration processes have to be applied in
both frequency and time-domain measurement systems in order to remove
the response of the electrical transitions outside the test fixture.
Although the calibration process in a measurement system removes
the undesired effects associated with the transitions external to the test
structure, the DUT is still embedded between the test fixtures, such as
microstrip, striplines, and other structures/transitions. Thus, the calibrated
measurements still do not correspond to the actual experimental data of the
DUT. In consequence, additional processing of the measurements is
necessary. In this case, the electrical characterization of the DUT requires the
35
separation of the additional networks. Unfortunately, this cannot always be
done by means of calibration procedures. The separation of the effects of a
portion of a structure with respect to another portion is known as “de-
embedding”
Figure 2.10 Shifting of the reference plane after the de-embedding process.
The de-embedding process is a mathematical process that removes
the effects of some parts (test fixture or unwanted portions of the structure)
that are embedded in the measured data (see Figure 2.10). In fact, calibration
and de-embedding processes are essentially the same since in both cases
unwanted responses are removed; however, in the case of the de-embedding
process, the effects introduced by the test fixtures are those that are
removed. The de-embedding process shifts the reference plane of the
measurements to the end of the test fixtures and there are primarily two
methods to accomplish this: a) using empirical models from measured data
(also known as S-parameter models) and b) simulation based models; which
are usually performed by means of representations obtained from
electromagnetic (EM) simulations. De-embedding literature has been
reported for both frequency-domain [58-65] and time-domain [66] and the
vast majority of the de-embedding processes for frequency-domain are based
36
on matrix manipulation of wave cascade matrix (WCM) or in ABCD matrix
manipulation. The ABCD and WCM matrices are obtained from S-parameter
data sets which have been measured or computed. In the case of time-
domain analysis, the de-embedding process is carried out in a different way.
In the time-domain the response is separated in time, the de-embedding
process uses normalization and gating to window out unwanted fixture
effects.
2.5 COMPARISON BETWEEN FREQUENCY AND TIME-DOMAIN APPROACHES
In Sections 2.2 and 2.3, two popular approaches to perform electrical
characterization were presented and detailed. A comparison between these
approaches pointing out the main advantages and disadvantages in each
case are presented hereafter. The first approach, i.e., the frequency-domain
measurements, associates an n-port network to the DUT and the
measurements correspond to a set of parameters that fully describe this
network. As it has been already mentioned in previous sections, the most
popular parameter set used at high-frequencies is the S-parameter data set,
which can be measured with high-accuracy using a VNA. The second
approach (time-domain measurements) uses a well-known technique called
TDR, which measures the high-speed transient performance of the DUT. A
TDR system is based on the measurement of the reflection coefficient at a
given point, providing information about the impedance discontinuities
associated with the internal structures of the DUT. Commonly, TDR
measurements are referred to as the impedance profile of the structure.
In accordance with the previous discussion, the information about the
electrical behavior of the DUT can be obtained either from the measured S-
parameters data set or from the impedance profile. However, there is an
37
advantage when using a TDR system since the impedance profile shows the
discontinuities at different points along the DUT in a sequential way. This
allows identifying the response associated with the different components of
the DUT. Additionally, when compared with frequency domain responses
such as S-parameters, TDR data is more intuitive and visual. In this case, the
TDR data resolution (i.e. minimum distinguishable distance between two
impedance discontinuities) is very important, and it is related to the rise time
of the input step signal applied by the measurement system. Unfortunately, in
current high-frequency/speed interconnections such as packages (where
internal structures have micrometer dimensions), the ability of the TDR to
resolve closely a spaced impedance discontinuity is strongly limited by the
resolution. Thus, when characterizing very small structures/discontinuities, a
TDR system with a very short rise time is necessary and not always is
available. A summary of the advantages and disadvantages of frequency and
time-domain measurements for electrical characterization task is shown in the
Table 2.1.
Frequency-domain
measurements Time-domain
measurements Instrument: VNA TDR
Output Data: S-Parameters Impedance profile
Advantage: Accurate measurements
at high-frequency
DUT response separate in
time, intuitive and visual
Disadvantage: Not intuitive, hard to
analyze
Rise-time limits the
resolution
Table 2.1 Summary of frequency and time-domain measurements issues.
Hence, the time-domain approach is only useful when DUT
dimensions are in the millimeter range or when relatively low-frequency
38
characterization and modeling is required. For example, for a TDR which has
a rise-time of 40 picoseconds, the corresponding frequency content of this
signal is approximately 20 GHz (Note that time and frequency domains are
equivalent and they are related by the Fourier transformation). Bearing this
consideration in mind, the frequency-domain approach is more adequate to
characterize and model high-frequency devices, because magnitude and
phase of the transmitted and reflected signals (S-parameters) within the GHz
range can be accurately measured with a VNA.
2.6 EQUIVALENT CIRCUIT MODELING
Once a data set has been obtained through frequency-domain, time-domain
measurements or simulations, a de-embedding process has to be carried out
for obtaining the actual response of the DUT. Finally, an equivalent electrical
model of the DUT can be extracted (from the data obtained after the de-
embedding process), which can be used in circuit level simulators. With the
information obtained from the circuit level simulator, optimization of the DUT
can be carried out if desired.
Depending on the nature of the DUT (passive or active such as an
interconnect of a microwave amplifier), this can be electrically modeled by a
single lumped element, a transmission line with fixed impedance and time
delay, a lumped element section, by a distributed circuit, or by means of a
combination of these. The choice of the model depends on the electrical
length of the DUT. In consequence, a criterion is required for determining
which model is appropriate. Reference [11] presents a criterion based on the
definition of “electrically long” or “electrically short” condition. In accordance
with [11] a DUT is considered to be electrically short if, at the highest
operating frequency of interest, the DUT’s length is physically shorter than
approximately one-tenth of the wavelength (i.e., length of the DUT divided by
39
1.0≈λ where f/υλ = ). Otherwise, the DUT is referred to as electrically
long. Hence, a DUT can be modeled using a lumped element circuit if it is
shown to be electrically short while distributed models are required to model
electrically long DUTs.
Additionally, when the model needs to be parameterized (in order to
investigate single components of the DUT), each impedance discontinuity
along the signal propagation path needs to be accounted for using a
physically-based representation. As result, depending on the complexity of
the model, the determination of self-capacitances, inductances, resistances,
and mutual coupling associated with the proposed equivalent circuit may be
necessary. The determination of the lumped element values is known as
equivalent circuit extraction. So, multiple techniques for the extraction of
equivalent circuits of a DUT (in general for electrical discontinuities) have
been reported in the scientific literature. These techniques are grouped into
two categories: model extraction techniques using S-parameters, which can
be obtained from measurements, and model extraction techniques using
TDR/TDT measurements. In the next section a brief overview about these
techniques is elaborated.
2.6.1 Model Extraction from S-Parameters Measurements
As it was mentioned previously, several extraction techniques to obtain
electrical equivalent circuit models have been reported. In [67], a procedure
based on Vector Fitting (VF) of network parameters is used to synthesize
equivalent circuits from measurements. This algorithm calculates a least
squares rational approximation of a vector of frequency-domain responses
using a common set of stable poles [68]. A brief explanation of the above-
mentioned algorithm is presented hereafter.
40
The VF’s objective is to approximate a frequency response with a
rational function given as [69]:
sedas
rsfN
m m
m ++−
=∑=1
)( (2.1)
where the terms d and e are optional, and s is a complex variable. Thus, the
VF first identifies the poles of )(sf by solving in the least squares sense, the
next linear problem expressed by the equation (2.2).
)()()( sfssp σ= (2.2)
In this case, the )(sσ is a scalar and )(sp is generally a vector which
represents the set of poles. These quantities are presented in equation (2.3)
and (2.4), respectively.
1~
)(1
+−
=∑=
N
m m
m
qsrsσ (2.3)
sedqs
rspN
m m
m ++−
=∑=1
)( (2.4)
Here,{ }mq is a set of initial poles and mr~ is the residue. In accordance with
[69], the poles of )(sf must be equal to the zeros of )(sσ which can be
calculated as the eigenvalues of a matrix:
{ } )cb -(A eig T⋅=ma (2.5)
According to (2.5), { }ma is a diagonal matrix which has the initial poles { }mq , b
is a column vector of ones and cT is a row vector with the residues mr~ . This
procedure can be applied in an iterative manner where the equations (2.2) to
(2.5) are solved repeatedly with the new poles { }ma replacing the previous
41
poles { }mq . This procedure is called pole relocation. When the poles have
been identified, the residues of the equation (2.1) are finally calculated by
solving the corresponding linear system problem with the known poles.
As it was mentioned before, VF works with any frequency response
and initially the measured S-parameters related to the DUT can be used as
input of this algorithm. However, when S-parameters are used as input, the
results are not adequate to synthesize an equivalent circuit. A better option to
synthesize equivalent circuits is using Y or Z matrices because the resulting
poles and residues obtained with VF can be related to RLC-networks.
Therefore, to use the measured S-parameters corresponding to the DUT, a
conversion of S to Z or Y-parameters is required. A computer code to
implement VF and equivalent circuit synthesis was reported in [67]. This code
was written in MATLAB and it is capable of generating equivalent circuits
from measured data. Unfortunately, when using this type of techniques,
sometimes the resulting equivalent circuits have no physical meaning and
therefore, there are severe difficulties in associating the model parameters
with physical phenomena. In consequence, these techniques are not
appropriate for optimizing complex DUTs like a package.
Before the VF technique was introduced, there exist several
techniques based on the use of rational functions to fit measured vs.
simulated data followed by association of an equivalent circuit to poles and
residues [70-73]. The key idea behind these techniques is essentiality the
same as that used on VF. On the other hand, there exist other extraction
techniques based on simulation-measurement correlations. In these
techniques, elements of a proposed equivalent circuit are calculated using
optimization tools [74-75]. Afterwards, simulation of the equivalent circuit
topology is carried out in order to correlate this model to measurements. If the
correlation results are good, the proposed equivalent circuit topology is
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42
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43
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44
As can be noticed, because of the regression application to the
determination of values, these types of methodologies are also known as
regression methods. There are other methodologies similar to the above-
described [77]. Unfortunately, the application of analytical methods is often
limited to simple equivalent circuits in order to simplify the analytical formulas.
In consequence, analytical extraction procedures associating physical
meaning with circuits for complex structures are still under research. In the
next table a summary of the described extraction techniques is presented.
Method Advantages Disadvantages
VF-like methods
Accurate and computer-aided
synthesis of equivalent circuit of
any experimental frequency
response within any frequency
range.
The resulting equivalent circuit is very
complex (sometimes without physical
meaning) and hard to analyze when
carrying out optimization procedures.
Optimization Methods
Flexibility to propose the
equivalent circuit. It presents
similar advantages to VF-like
methods.
Similar to VF-like methods,
additionally the parameterization of
the model is not often possible.
Analytical Methods
Straightforward and simple, uses
analytical closed-formulas. The
equivalent circuit topology has
physical meaning.
Applicable to relatively simple
equivalent DUTs/circuits.
Table 2.2 Summary of typical S-parameter measurement-based model extraction methods.
2.6.2 Model Extraction from TDR/TDT Measurements
TDR/T measurements can be used to extract equivalent circuit elements. The
extracted models, as in the frequency-domain case, can be lumped or
distributed in nature depending on the desired accuracy, the electrical length
of the interconnect, and the measurement method. In the case where
45
coupling is not an issue, a single-ended measurement can be used to create
a model which will account for propagation delays, characteristic impedance,
and any impedance discontinuities in the signal path. This is done by
inspection of the resulting impedance profile. The extracted equivalent circuit
can be obtained by partitioning the impedance profile into either excess
reactance or transmission line structures with fixed characteristic impedance
and propagation delay. Time windowing can be used to calculate the initial
values of the model circuit elements. In order to show how an equivalent
circuit model is derived from TDR measurements, an example is described in
the following lines.
In [52] a procedure to extract an equivalent circuit for high-density
connectors is presented. In accordance with this paper, a continuous TDR
waveform as shown in Figure 2.7 which represents an inductive or capacitive
discontinuity can be used to determine their corresponding values. In this
case, the inductance or capacitance of the pin connector under investigation
is calculated using the following equations which are presented in [53].
∫= 2
1
)(21
0
tl
tldttZL ∫=
2
1 0 )(21 tc
tcdttZC (2.9)
where )(0 tZ is the time variation of the characteristic impedance, tl1 and tl2
are the instantaneous time corresponding to the time window of positive
glitches, and tc1 and tc2 correspond to the negative glitches. Since the
experimental data from TDR provide sampled time intervals; the
implementation of the equations (2.9) is done by means of rewriting these
equations in discrete form. The equations (2.9) are largely dependent on the
time window and the rise time and can lead to inaccurate results. In
consequence, as in the case of frequency-domain model extraction, the
circuit element values can be optimized to best fit the measured response.
46
This method can be easily implemented and, from the published literature, it
has been adopted to model package, printed circuit board interconnects and
connectors [52-53], [78]. Unfortunately, the application of time-domain
extraction techniques to complex interconnections like packages, is limited by
rise-time of the TDR primarily, but there are other problems associated to
these techniques.
2.7 ELECTROMAGNETIC MODELING APPROACH
In the previous sections, modeling approaches based on experimental
measurement have been presented. However, simulations are often used in
parallel with measurements for completeness. This section briefly describes
numerical approaches to modeling the electromagnetic performance of
interconnects.
There are several transmission line geometries (such as microstrip
lines, striplines, spherical waveguides) and their corresponding impedance
discontinuities which have been characterized using analytical approaches.
The results are empirical and closed-form formulas which can be used to
calculate impedance, propagation delay, capacitance, and inductance from
the geometric properties of an interconnection. From the literature [79-83],
quasi-static analysis, empirical, and analytical formulas have been shown to
be sufficient for analyzing many different interconnection structures. However,
these expressions are limited because several assumptions are done in order
to reduce the complexity of the problem. Among the included assumptions
there are, for example that an interconnection is surrounded by homogenous
dielectric material, the structure is planar or the mode of propagation is quasi-
transverse electromagnetic (quasi-TEM). Therefore, this approach is often not
suitable for complex arbitrary three-dimensional (3-D) interconnects.
47
In contrast to the previous approach, numerical methods based on
Maxwell’s equations are tools that can be used in the modeling process of
more complex problems. In the case of electrically short and/or
inhomogeneous 3-D interconnects, such as connectors and IC packages,
electromagnetic effects are much more difficult to analyze using closed-form
equations. Instead of closed-form equations, electromagnetic (EM) simulators
(such as HFSS, CST Microwave Studio, Microwave Office, etc.) that solve
Maxwell’s equations are applied to calculate the high-frequency/high-speed
transient response of a DUT. An EM simulator solves either the differential or
the integral form of the Maxwell’s equations subject to the problem setup.
To resolve differential equations in an EM simulator, the methods that
are mainly used are the finite-difference and the finite-element techniques.
Finite-difference methods perform electromagnetic analysis by placing a grid
over the volume of interest and solving Maxwell’s equations at each node of
the grid. On the contrary, the finite element method divides the full problem
space into thousands of smaller regions and represents the field in each sub-
region (element) with a local function. For example in HFSS, the geometric
model is automatically divided into a large number of tetrahedra, where a
single tetrahedron is a four-sided pyramid. This collection of tetrahedra is
referred to as the finite element mesh.
On the other hand, integral equation methods formulate EM problems
using the electric or magnetic field integral equation. In this case, the method
of moments (MoM) is used to solve these equations [84]. Finite-element,
finite-difference, and MoM methods are used to solve problems in the
frequency domain. For time-domain EM analysis, the finite-difference time
domain (FDTD) and the transmission line matrix (TLM) have been developed.
In recent years, better algorithms have been developed to implement more
efficient numerical methods, both in frequency and time-domain. These new
48
algorithms are applied to solve multilayered high-density interconnection
problems [85-90].
Unfortunately, as in the case of equivalent circuit modeling, there are
several disadvantages related to electromagnetic simulations and the most
important is the computational effort required to simulate complex structures.
However, there are significant advantages such as prediction of the response
of interconnects before their fabrication, identification of undesirable effects
by means of analysis of electromagnetic field distribution, etc. As it was
mentioned before, the full-wave simulations are used frequently as
complementary tools in the development of new interconnection technologies.
2.8 CONCLUSIONS
In this chapter, an overview about electrical characterization and modeling
techniques for IC packages and interconnects has been presented. As it was
mentioned in the introduction of this chapter, the accurate electrical
characterization of interconnects and IC packages is an essential element in
the design and development of high-frequency and miniaturized electronic
systems. Therefore, the development of new techniques for electrical
characterization and modeling is necessary to attain high-performance
systems in the near future with marketable and competitive properties.
49
CHAPTER III
Electrical Characterization and Equivalent Circuit Modeling of CPW-Microstrip (CPW-M) Transition 3.1 INTRODUCTION An overview on PCB interconnection technology, characterization and
modeling of IC packages and interconnects was shown in Chapter I and
Chapter II, respectively. As it was previously mentioned, a complex chip-to-
chip interconnection channel presents several electrical transitions or
discontinuities. Among these discontinuities there are vias, microvias, solder
bumps, etc. Furthermore, additional electrical transitions are required when
the electrical characterization of a channel is carried out by means of
measurements (time or frequency-domain measurements).
There exist different types of transitions that can be used to measure a
two-port DUT using a VNA such as CPW-microstrip, CPW-stripline, coaxial-
microstrip, etc. These electrical transitions are used to probe the microwave
circuits fed by transmission lines and their main function is to provide
electrical interconnection and mechanical compatibility between the DUT and
the VNA’s ports. Unfortunately, the electrical transitions have an undesirable
impact on the resulting experimental data because the measurements include
the DUT and the effects associated with the test fixture. Thus,
characterization techniques for removing undesirable test fixture effects are
necessary in order to determine the actual response of the DUT.
In Chapter II, characterization techniques for removing undesirable
(but necessary) test fixture effects were presented (the so-called de-
50
embedding techniques). As a first approach, these techniques could be
applied to de-embed the test fixture from measurements in order to determine
the experimental data of the DUT. However, the development of new
characterization methodologies is necessary because there are
disadvantages in the typical de-embedding techniques presented in Chapter
II. For example, in the frequency-domain, the TRL-based characterization
technique has several problems: the TRL calibration family uses
measurements of a through connection (T) and an inserted line (L) to
determine the propagation constant of the line. This is typically used with
measurements of a reflect standard to characterize the test fixture response.
Subsequently, the S-parameters of a DUT can be de-embedded, but
measurement uncertainties occur at frequencies where the length of the line
standard is an odd multiple of a half-wavelength. Hence, when these
measurements are employed to determine the complex propagation constant,
there are errors in the determination of this important parameter. These errors
affect the whole characterization of the test fixture response and
subsequently de-embedded measurements.
On the other hand, in the time-domain the characterization of test
fixtures is intuitive and easy because the measured response is separated in
time allowing the use of normalization and gating to window out unwanted
effects. This process can be used to eliminate the fixture and adaptors which
may be required for the measurements. Thus, the time-domain-based
characterization process separates the device under test from its
environment. However, time-domain characterization has a limited bandwidth,
and for high-frequency and high-speed characterization often it is not the best
choice.
In the present chapter, a new characterization technique for
determining the experimental ABCD matrix of an electrical transition will be
51
described. This technique is formulated from the experimental
voltage−current chain (ABCD) parameters of two transmission lines with
different lengths and terminated with the discontinuity to be characterized.
After presenting the development of this technique, it is applied to
characterize a CPW- microstrip transition and later a validation process is
done to verify the correctness of the technique. Afterwards, an equivalent
circuit topology is associated to the experimental data obtained for the CPW-
microstrip transition and by means of full-wave simulations in HFSS; the
physical meaning of this equivalent circuit topology is supported. Moreover,
an analytical extraction process to determine the element values of the
equivalent circuit is developed and also a validation process for this circuit is
carried out by means of a simulation-measurement correlation in the
frequency and in the time domain. Finally, the conclusions are presented with
remark in the excellent results observed within the tens of GHz range of the
proposed technique.
3.2 A NEW CHARACTERIZATION METHOD FOR ELECTRICAL TRANSITIONS USING TRANSMISSION LINE MEASUREMENTS [91]
In recent years, several methods have been developed to extract the
experimental data associated to electrical transitions. However, these
methods often require full-wave simulations and parameter optimization to
carry out a detailed characterization [13, 72, 92, 93], which becomes
increasingly difficult and time-inefficient for complex structures. Other
approaches use equivalent circuit models to represent the transitions [94, 95,
96]. In this case, however, analytical parameter determination methods for
circuit elements have not been reported. An alternative methodology for
determining the network parameters of electrical discontinuities was reported
in [97], where coaxial connectors are characterized directly from experimental
52
data. The formulation of this method, however, uses Z-parameters, which is
not the best choice when characterizing transmission line-based channels
since it considerably complicates the calculation of the model parameters. In
this section a new analytical and simple extraction process is developed
using measurements carried out to two transmission lines of different length.
The electrical transitions can be considered as propagation mode
adapters that introduce discontinuities in the electrical path of the signal.
Thus, an actual transmission line-based test structure can be represented by
means of the block model of Figure 3.1. In this case, a uniform transmission
line (UTL) featuring a length l, a complex propagation constant γ, and
characteristic impedance Z0, is considered to be embedded between two
passive adapters. In accordance to this model, the matrix associated with the
ABCD parameters of this structure is given by:
RTLT nXn = (3.1)
Fig. 3.1 Cascade model for a transmission line embedded between two
electrical discontinuities.
where L and R are the matrices associated with the left and right adapters
respectively, nT is the matrix of the UTL and the subscript n is added to
distinguish between the parameters of lines with different length used later.
The complex values for γ and Z0 of the UTL can be determined using
previously reported methods [98]-[99], nT can be easily obtained for a given
uniform transmission
line
l, , Zγ 0
left adapter right adapter
L Rport 1 port 2
53
line length. Thus, using transmission line theory nT can be expressed as:
⎥⎦
⎤⎢⎣
⎡= − )cosh()sinh(
)sinh()cosh(1
0
0
nn
nnn llZ
lZlT
γγγγ
(3.2)
And for the case of the adapters, L and R are respectively expressed as:
⎥⎦
⎤⎢⎣
⎡=
εδβα
L (3.3)
⎥⎦
⎤⎢⎣
⎡=
αδβε
R (3.4)
Notice in equations (3.3) and (3.4) that the adapters are assumed to be
identical and reciprocal, but one is rotated 180° with respect to the other. At
this point, it is necessary to mention that the electrical transitions represented
by means of the adapters are fully characterized once α, β, δ and ε are
determined. Substituting equations (3.2), (3.3) and (3.4) in (3.1) yields
⎥⎦
⎤⎢⎣
⎡⎥⎦
⎤⎢⎣
⎡⎥⎦
⎤⎢⎣
⎡= − αδ
βεγγγγ
εδβα
)cosh()sinh()sinh()cosh(
10
0
nn
nnXn llZ
lZlT (3.5)
Expanding equation (3.5) gives as result equation (3.6)
⎥⎦
⎤⎢⎣
⎡++++
=⎥⎦
⎤⎢⎣
⎡=
)sinh()cosh()sinh()cosh()sinh()cosh()sinh()cosh(11
00 nnnn
nnnn
nn
nnXn lqlplmlk
lhlglfleZDC
BAZ
Tγγγγγγγγ
(3.6)
where the corresponding coefficients e, f, g, h, k, m, p and q are given by:
0)( Ze βδαε += (3.7)
54
20Zf αδβε += (3.8)
02 Zg αβ= (3.9)
220
2 βα += Zh (3.10)
02 Zk δε= (3.11)
220
2 εδ += Zm (3.12)
0)( Zp αεβδ += (3.13)
20Zq αδβε += (3.14)
Then, the ABCD matrices associated to transmission lines with length 1l and
2l including transitions L and R respectively are determined by (3.15) and
(3.16)
⎥⎦
⎤⎢⎣
⎡++++
=⎥⎦
⎤⎢⎣
⎡=
)sinh()cosh()sinh()cosh()sinh()cosh()sinh()cosh(11
1111
1111
011
11
01 lqlplmlk
lhlglfleZDC
BAZ
TX γγγγγγγγ
(3.15)
⎥⎦
⎤⎢⎣
⎡++++
=⎥⎦
⎤⎢⎣
⎡=
)sinh()cosh()sinh()cosh()sinh()cosh()sinh()cosh(11
2222
2222
022
22
02 lqlplmlk
lhlglfleZDC
BAZ
TX γγγγγγγγ
(3.16)
Inspecting these two ABCD matrices it can be seen that g, h, k and m can be
obtained by solving a system of linear equations given by (3.17), (3.18),
(3.19) and (3.20), respectively; mathematically, these systems are:
)sinh()cosh( 1110 lhlgBZ γγ += (3.17)
)sinh()cosh( 2220 lhlgBZ γγ += (3.18)
)sinh()cosh( 1110 lmlkCZ γγ += (3.19)
)sinh()cosh( 2220 lmlkCZ γγ += (3.20)
55
As can be seen, nnnn CBZll ,,),sinh(),cosh( 0γγ are known so there are
four equations and four unknowns. The solutions for the systems expressed
in (3.17), (3.18), (3.19) and (3.20) are determined using basic linear algebra.
In consequence, g, h, k and m can be obtained from:
Δ−
=))sinh()sinh(( 12210 lBlBZg γγ (3.21)
Δ−
=))cosh()cosh(( 21120 lBlBZh γγ (3.22)
Δ−
=))sinh()sinh(( 12210 lClCZk γγ (3.23)
Δ−
=))cosh()cosh(( 21120 lClCZm γγ (3.24)
where )sinh()cosh()sinh()cosh( 1221 llll γγγγ −=Δ . Once g, h, k and m are known α,
β, δ and ε are determined by simultaneously solving equations (3.25)-(3.26)
and (3.27)-(3.28) respectively. In this case, the following equations are
obtained:
04
22
4 =−+ ββ hg (3.25)
02 Zgβ
α = (3.26)
04
22
4 =−+ εε mk (3.27)
02 Zkε
δ = (3.28)
Hence, β is obtained by solving (3.25); then, α is calculated by applying
(3.26). Notice that, in order to reduce computing time, equation (3.25) can be
56
firstly solved for β2 and then β can be obtained by calculating the
corresponding square root. Afterwards, δ and ε are obtained by
simultaneously solving (3.27) and (3.28), At this point; it has been shown that
the adapter network parameters can be analytically determined from
experimental ABCD-parameters of two transmission line-based test-
structures differing only in length. However, by inspecting the solutions for α,
β, δ and ε a problem is present: there are many solutions for it, and therefore
the selection of the correct values has to be done in order to obtain the
corresponding ABCD-parameters for the transition. In the next lines, a
criterion for the root selection is shown.
There are four values for β that satisfy (3.25), and the same applies for
ε and equation (3.27). This means that there are sixteen possible
combinations of values that β and ε can take to define the L and R matrices.
Fortunately, it is known that the adapters represented by these matrices are
passive devices that present reciprocity. Thus, the ABCD matrices associated
with the left and right adapters necessarily have to satisfy the passivity
condition which is verified by applying the following expressions:
1221
211 <+ SS (3.29)
1212
222 <+ SS (3.30)
In this notation, the subscripted S-parameters correspond to the two-port
scattering parameters of the adapter. In order to write (3.29) and (3.30) in
terms of the ABCD parameters of the adapter defined in (3.3) and (3.4), the
corresponding two-port S-to-ABCD parameter conversion can be applied.
Thus, the passivity conditions can be expressed as:
57
122
21
2
21
21 <+
++−
XXXXXX (3.31)
122
21
0
2
21
321 <+
++
++−XX
XXX
XXX (3.32)
where
βδαε −=0X (3.33)
βα +=1X (3.34)
εδ +=2X (3.35)
)(23 δβ −=X (3.36)
and a reference impedance of 1 Ω has been assumed for the S-parameters in
this conversion for simplicity. A second useful criterion can be used to
discriminate the roots of (3.25) and (3.27); this is reciprocity. In this case, the
roots have to be selected so that:
10 =X (3.37)
The correct roots of (3.25) and (3.27) satisfy simultaneously the passivity and
reciprocity conditions. In this case, the correct values for α, β, δ and ε satisfy
(3.37). However, in accordance to (3.33), equation (3.37) can also be
satisfied by the negative value of α, β, δ and ε, which introduces a sign
ambiguity for the adapter characterization solution. For this reason, one
useful criterion to resolve this ambiguity is explained hereafter.
A reciprocal device can be represented by means of a T-network as
the one shown in Figure 3.2. Notice in this figure that z1 and z2 are assumed
to be different since the adapter is not necessarily symmetrical. According to
this T-network, the ABCD matrix associated with L can be expressed as:
58
⎥⎦
⎤⎢⎣
⎡++++
=2
21211
11
zyyzzyzzzy
L (3.38)
where z1 and z2 are the series impedances and y is the shunt admittance. It is
important to point out that independently of the effects associated with z1, z2,
and y, these parameters present pure positive real numbers within the direct-
current (dc) regime (i.e. in dc the reactance is zero). Thus, comparing (3.3)
and (3.38) leads to the conclusion that α, β, δ and ε present a positive real
part at low frequencies. This suggests that, at relatively low frequencies the
sign ambiguity is resolved, and for higher frequencies it can be resolved by
considering that the real and imaginary parts of α, β, δ and ε are continuous
when plotted versus frequency.
Figure 3.2 T-network used to represent a reciprocal device.
A final remark on the sign ambiguity solution is that, when z1, z2, and y
present low resistive components, the real part of β and δ may be as low as
the measurement resolution at low frequencies, complicating to determine if
these parameters are negative or positive. Thus, the inspection of α and ε at
low frequencies is preferred when resolving the sign ambiguity.
z2z1
y
59
3.3 APPLICATION OF THE NEW CHARACTERIZATION METHOD TO A CPW-M TRANSITION
In the previous section, the analytical method to characterize electrical
transitions using transmission line measurements was developed and
described. In order to verify the applicability and validity of this new de-
embedding method, CPW-M transitions designed to probe microstrip lines
fabricated on PCB technology are characterized hereafter using the proposed
method. With this purpose, microstrip lines of several lengths and terminated
with CPW-M transitions were fabricated on PCB technology (copper over a
Rogers RT/Duroid 5880 substrate with nominal relative permittivity and loss
tangent of 2.2 and 0.0009 respectively).
Figure 3.3 Layout of a microstrip line terminated with CPW-M transitions.
In the Table 3.1, the geometrical parameters for microstrip line are
presented, as well as the description for each one. As it was mentioned
before, the characterization method requires two transmission lines with
different lengths in order to extract the experimental parameters that fully
characterize the CPW-M transition and the lengths employed for this purpose
are shown in the Table 3.1 also. The other geometrical features that conform
CPW-Microstrip transition such as via diameter, pad dimensions and shape
are described in detail in the Appendix A, Section A.1.
6
u
s
s
r
s
o
e
A
c
60
The
using a VN
system was
standard-su
reflect-matc
system is c
outer edge
experiment
ABCD-para
correspond
Figure 3.4
S-parame
Parameter
L
W
G
H
Table
S-paramet
NA and GS
s previously
ubstrate (IS
ch (LRM) p
calibrated t
e of the CP
tal S-param
ameters o
ding two-po
Simplified s
eters once
Value
282, 335 mil
7.2 mils
3 mils
40 mils
e 3.1 Spec
ters of thes
SG coplana
y calibrated
SS) provide
procedure [
the measur
PW adapter
meters is se
of the lin
rt network p
sketch show
the VNA ha
ls Physical
Width of a
Separatio
Substrate
ifications fo
se lines we
ar probes w
d up to the
ed by the
[56]. As ca
rement refe
rs, whereas
et to 50 Ω.
nes from
parameter
wing the re
as been ca
Descripti
length of micr
a microstrip li
on from groun
e height
or microstrip
ere measur
with a pitch
probe tips b
probe man
n be seen
erence plan
s the refere
This step i
the S-p
conversion
ference pla
librated wit
on
rostrip line
ine
nd to signal pa
p lines.
red from 0.
h of 250 μ
by using an
nufacturer a
in Figure 3
ne is estab
ence imped
s required
parameters
.
ane for the e
h the LRM
ad
.1 to 40 GH
m. The VN
n impedanc
and the lin
3.4, once th
blished at th
dance for th
to obtain th
using th
experiment
procedure.
Hz
NA
ce-
ne-
he
he
he
he
he
tal
.
61
Once the S-parameters for each microstrip line are measured, the
proposed characterization method can be implemented in a computer with
numeric data processing software. As can be seen, the characterization
process begins with the calculation of complex propagation constant γ and
the characteristic impedance Z0. The two parameters can be calculated
implementing the corresponding algorithms described in [98]-[99]. Afterwards,
the auxiliary variables g, h, k and m are determined from equations (3.21) to
(3.24). Notice that these quantities only depend on known variables such as
the propagation constant, characteristic impedance, and the physical length
of the used transmission lines. Thus, the variables α, β, δ and ε are easily
obtained from g, h, k and m as explained before.
Notice that the established root selection criterion has to be applied in
order to determine the correct values. If the root selection criterion is not
accomplished, then the next combination of values for α, β, δ and ε has to be
tested until selection criterion becomes fulfilled. Finally, when the correct
values for α, β, δ and ε are determined, the ABCD matrix corresponding to
the CPW-microstrip transition can be converted to S-parameter, impedance
or admittance matrix for analysis and modeling.
The algorithm for the characterization method was implemented in
MATrix LABoratory (MATLAB) software. Although the MATLAB code was
written for a particular case; with minor modifications it can be used to
characterize other electrical transitions such as coaxial-microstrip, CPW-
stripline, etc. The key idea is the same for all the cases previously mentioned
and only some variables will change.
In the next figures, the obtained results of the characterization method
for CPW-microstrip transition are shown. Figure 3.5 shows the complex
propagation constant for the microstrip (MS) line described in Figure 3.3 and
Table 3.1 and in the next figure the corresponding characteristic impedance
6
(
i
G
c
a
T
t
t
s
62
(real and
imaginary
Given that
characteris
accuracy o
Therefore,
the best op
Figure 3.5
Figure 3.6
In F
that the cor
same for th
imaginary
parts of th
the formu
stic impeda
of α, β, δ a
in this cas
ption.
Complex p
Characteris
igures 3.7
rresponding
he L and R
part). As
he characte
ulation of th
ance Z0 a
nd ε will de
se, a freque
propagation
stic impeda
and 3.8, th
g extracted
adapters b
can be se
eristic impe
he characte
and compl
epend on t
ency-depen
n constant odelay.
ance of MS:
he results fo
parameter
but rotated
een in Fig
edance are
erization m
ex propag
the accurac
ndent impe
of MS: a) at
: a) real par
or α, β, δ a
rs for the C
180° from
gure 3.6, t
e frequency
method dep
gation con
cy of these
edance det
ttenuation a
rt and b) im
and ε are s
PW-M tran
each other
the real an
y dependen
pends on th
stant γ, th
e parameter
ermination
and b) phas
maginary pa
hown. Noti
sition are th
. Currently,
nd
nt.
he
he
rs.
is
se
art.
ce
he
, a
c
a
s
Z
a
f
complete s
adapters is
sensitivity o
Z0 and γ is
affected if
frequency-d
Figu
Fig
study abou
s under inv
of this char
s being carr
the charac
dependent?
ure 3.7 Rea
gure 3.8 Re
ut the imp
estigation.
racterizatio
ried out. Fo
cteristic im
?
al and imag
eal and ima
lications o
Additionall
n method t
r example:
mpedance is
ginary parts
ginary part
f the assu
y, research
to the accu
Will the res
s considere
s obtained f
obtained fo
umed symm
h on the an
uracy of the
sults for α,
ed purely
for a) α and
or a) δ and
metry of th
nalysis of th
e determine
β, δ and ε b
real and n
d b) β.
b) ε.
63
he
he
ed
be
not
64
At this point, the experimental ABCD-parameters of the CPW-M
transition have been obtained using the proposed characterization method
which uses measurements of two transmission lines of different length. Once
the ABCD-parameters are determined, an assessment of the performance of
the CPW-M transition from the return and insertion losses is possible. In
addition, from these data an equivalent circuit can be associated to the
transition to model the structure in circuit simulators. All this information can
be extracted from the experimental parameters associated to the
corresponding transition and it could be used to improve the transition
performance. However, the results of the assessment of the performance and
the rest of the analysis of the parameters associated to the transition will
depend on the accuracy of the characterization method from which the
ABCD-parameters were determined. In the following section, the accuracy of
the corresponding extracted values will be verified and thus the validity of the
proposed characterization method. 3.4 VALIDATION OF THE NEW CHARACTERIZATION
METHOD: FREQUENCY AND TIME -DOMAIN CORRELATIONS TO MEASUREMENTS
As can be seen in Figure 3.1, an actual transmission line-based test structure
is composed of two CPW-M transitions and one UTL (a uniform microstrip line
without electrical transitions). Thus, a transmission line-based test structure
can be represented by means of the block model of Figure 3.1. One way to
verify the validity of the characterization process is by reproducing the
measurements of a transmission line using the model of Figure 3.1. In order
to carry out a correlation of the model with experimental data, the
determination of the ABCD matrix for each component of the block model is
necessary.
t
a
a
t
t
p
c
S
w
e
a
Fort
the determ
and the on
associated
the charact
the comple
process, w
At th
channel wit
System (AD
with experi
Fig
Freq
experiment
and 3.11,
Fourier Tra
unately, the
ination of th
nly remaini
with the U
terization p
ex propaga
hich are the
his point, th
th a micros
DS), the blo
mental data
gure 3.9 Im
quency an
tal data are
respectivel
ansform (iFF
e characte
he experim
ng compon
UTL, which
process is a
ation consta
e only para
he block m
strip 650 mi
ock model
a.
mplementati
nd time-do
e carried o
ly. For the
FT) of the r
rization pro
mental S-pa
nent to be
can be mo
applied, the
ant γ are d
meters nee
odel of Fig
ls long. Us
is simulate
ion of the b
omain co
ut and the
case of t
reflection pa
ocess prev
rameters fo
determine
odeled usin
e character
determined
eded to rep
gure 3.1 ca
ing the Agi
ed (Figure 3
lock model
rrelations
results are
the time-do
arameter S
iously desc
or the CPW
ed is the p
ng equation
ristic imped
in the firs
resent the
n be imple
lent’s Adva
3.9) and lat
of Figure 3
of simula
e shown in
omain data
11 was carr
cribed allow
W-M transitio
arameter s
n (3.2). Whe
dance Z0 an
t step of th
UTL.
mented for
anced Desig
ter correlate
3.1 in ADS.
ated vers
n Figure 3.
a, an Inver
ried out.
65
ws
on
set
en
nd
he
r a
gn
ed
us
10
se
6
t
t
b
p
d
t
r
66
Figu
a) Magn
Figure 3.1
The
that the ch
transmissio
been corre
process. U
determined
the CPW-m
represents
re 3.10 Fre
itude of S11
1 Time-dom
excellent f
haracterizat
on line tes
ctly charac
p until this
d. In the nex
microstrip tra
the structu
equency-do
1, b) magnit
main correl
frequency
ion process
t structure
terized, wh
point, the
xt sections,
ansition, an
re, is propo
omain corre
tude of S21,
ation for th
and time-d
s is correct
(CPW-mic
hich verifies
ABCD-para
, based on
n equivalen
osed.
elation for th
c) phase o
e block dia
domain cor
t and that
crostrip tra
s the validity
ameters of
the experim
nt circuit top
he block dia
of S11, d) ph
gram of the
relation res
each comp
nsitions an
y of the cha
the CPW-M
mental data
pology, whic
agram.
hase of S21
e Figure 3.1
sults indica
ponent of th
nd UTL) h
aracterizatio
M have bee
a obtained f
ch accurate
.
1.
ate
he
as
on
en
for
ely
67
3.5 A NEW EQUIVALENT CIRCUIT TOPOLOGY TO MODELING CPW-M TRANSITION
There is previous work on CPW-to-microstrip transitions focused on analyzing
via-hole interconnects as discontinuities in the signal path of a microstrip line
[100] or as grounds [101]. In [102], a study of two parallel microstrip lines
coupled through interconnects vias and the development of a lumped-
element equivalent circuit was performed. In [94] an equivalent circuit
topology is proposed to model CPW-microstrip transitions which has a form of
a four-port circuit that includes via inductance and mutual coupling between
ground vias and signal pad. Thus, the CPW-M transition can be represented
as a four-port with three ports on the left input side and one microstrip port on
the output side. Since energy flow between these ports is caused by both
magnetic and electric coupling in the vicinity of the transition, the
development of an accurate equivalent circuit model requires those mutual
inductances, self inductances and the capacitances between the ground and
signal pads to be taken into account. In that case, model elements are
determined by means of full-wave simulations (FDTD algorithm).
Figure 3.12 Modified equivalent circuit topology based on [94].
68
A new equivalent circuit topology to model a CPW-M transition based
on [94] is proposed here. Figure 3.12 shows the modifications made to the
original topology which includes the addition of one inductor (Lm) and three
resistors (Rp and Rc). In Figure 3.13, the lumped elements of the proposed
topology associated with the 3D CPW-M transition are shown.
Figure 3.13 Lumped circuit elements associated with a 3D CPW-M structure
(the mutual inductance between the signal pad and the ground vias is not shown).
As it was mentioned before, the proposed equivalent circuit topology is
a modification of the topology presented in [94] and the physical phenomena
associated with each one of these elements is not presented. In order to
demonstrate the physical meaning of this equivalent circuit topology and the
corresponding modifications, an analysis of the behavior of the electric (E)
and magnetic (H) fields in the vicinity of the transition was performed. With
this purpose, full-wave simulations of the CPW-M transition were carried out,
whose validity was verified by means of a frequency and time-domain
correlations to measurements (Figures 3.14 and 3.15). For the time-domain
correlation, an Inverse Fourier Transform (iFFT) of the reflection parameter
S11 was carried out to obtain the corresponding TDR waveform.
l
f
b
g
Figure measurem
Figu
In th
lumped ele
figures 3.1
between th
ground plan
3.14 Frequent: a) Ma
ure 3.15 Tim
he followin
ements of
6 and 3.1
he signal an
ne at 40 GH
uency-domagnitude of
d)
me-domainm
g lines, th
the propos
17, the 3D
nd the grou
Hz, respect
ain correlatS11, b) pha) phase of S
n correlationmeasureme
e physical
sed topolog
D plot show
nd pads an
tively.
ions of full-se of S11, cS21.
n of full-wavent.
phenomen
gy are exp
ws the dis
nd between
wave simuc) magnitud
ve simulatio
na associa
plained in d
stribution o
n the signal
lations to de of S21, an
ons to
ated with th
detail. In th
of the E-fie
l pad and th
69
nd
he
he
eld
he
70
Figure 3.16 3-D plot of the E-Field showing the electric coupling between the signal and ground pads at 40 GHz.
Figure 3.17 2-D plot of the E-Field showing the electric coupling between signal pad and ground plane at 40 GHz.
As can be seen in Figure 3.16, there are E-field lines that begin at the
signal pad and finish at the ground pads (the direction of the lines depend on
the E-field phase and the terms “begin” and “finish” are relative). This effect is
associated with the capacitors Cg. In Figure 3.17, E-field lines begin at the
signal pad and finish at the ground plane yielding a capacitance Cs. However,
there are more E-field lines that begin at the signal pad and finish at the
ground vias, which is an effect that is also associated with the capacitance Cs
(see Figure 3.18). It is important to mention that the real distribution of the E-
field is 3D and the plots were made in transversal planes only to show the
71
physical effect. Thus, for example, the distribution of the E-field which
originates the capacitance Cg is similar along the signal pad (normal direction
to the transversal plane in Figure 3.16) until the CPW-M transitions to the
microstrip line section.
Figure 3.18 3-D plot of the E-Field showing the electric coupling between signal pad and ground vias at 40 GHz.
On the other hand, the resistor Rc is associated with the losses in the
capacitor Cs formed by the signal pad and the ground vias-plane structure. An
ideal vacuum-filled capacitor presents a value C0. However, when the
capacitor is filled with a dielectric material, the admittance is scaled by the
relative permittivity of the material ( )(ωε r ), which is in general a complex
function of frequency; mathematically:
)()( 0 ωεωω rC CjY = (3.39)
)()()]()([)( ''''0 ωωωεωεωω CCC GjSjCjY +=−= (3.40)
So, )(ωCY has the form of a frequency-dependent capacitance, ωω /)(CS , in
parallel with a frequency-dependent conductance, )(ωCG . The corresponding
impedance can be written as:
72
⎥⎥⎦
⎤
⎢⎢⎣
⎡+== 2
''
2
'
0 )()(
)()(1
)(1)(
ωεωε
ωεωε
ωωω
rrCC j
CjYZ (3.41)
In this case, the effect is represented by means of a frequency-dependent
capacitance in series with a frequency-dependent equivalent series
resistance (ESR) [103].
The impedance for a lossy capacitor expressed by equation (3.41)
presents the same form than the capacitor Cs in series with the resistor Rc in
the model shown in Figure 3.13. Thus, equation (3.41) suggests that the
resistor in the equivalent circuit topology is a frequency-dependent resistor
that has been reported to present a linear-dependence with frequency [103].
Although, as a first approach, the resistor in the equivalent circuit could be
modeled by a linear frequency-dependent resistor, there are other effects in
the E-field distribution associated to the capacitor Cs such as radiation (open-
end effect in a transmission line) which could be considered as loss
mechanism additional to the dielectric losses. The full physical justification of
the origin of this resistor in the proposed equivalent circuit topology is not
available at this moment, but research in this direction is currently ongoing.
The figures 3.19, 3.20 and 3.21 show the H-field distribution in different
points of the CPW-M transition. In Figure 3.19, the H-field is plotted in the
region close to the ground vias aside the signal pad, whereas the same
distribution is shown in Fig. 3.20 but for the ground vias behind the signal
pad. As it is well known, if there is a time-varying current flow then a magnetic
field is originated and hence an inductor. Therefore, the current that flows in
the signal pad causes a self inductance Ls. Due to the proximity of the ground
vias and the signal pad, the corresponding magnetic field interacts with the
magnetic field originated by the current flow in the ground vias (this current
flow is associated with the return path for a quasi-TEM transmission line and
yields the self-inductance Lg).
73
Figure 3.19 3-D plot of the E-Field showing the magnetic coupling between signal pad and the lateral ground vias at 40 GHz.
Figure 3.20 3-D plot of the E-Field showing the magnetic coupling between the signal pad and the ground vias behind at 40 GHz.
The previously described effect originates the mutual inductance M
between the signal pad and the ground vias. The inductance Lm is associated
with a similar effect, but in this case the magnetic field (Figure 3.21) is
originated by a concentration of current flow in the width-step occurring at the
signal pad-to-microstrip transition. Additionally, due to the finite diameter of
the ground vias there will be resistive losses (Joule Effect) occurring in this
part of the structure, and this effect is represented by the resistors Rp.
74
Figure 3.21 3-D plot of the H-field in the width-step from de signal pad to the microstrip line at 40 GHz.
At this point the lumped elements of the proposed equivalent circuit
topology have been related to electromagnetic phenomena, and a physical
meaning of this topology was explained. Subsequently, an extraction method
to determine the values of the lumped elements is developed and explained
in the next section. The formulation of this method will be based on the
experimental ABCD matrices obtained in Section 3.3, the T-network model of
Fig. 3.2, and some simplifications made to the four-port equivalent circuit
topology reported in [94].
3.6 ANALYTICAL EXTRACTION OF THE LUMPED ELEMENTS VALUES FOR THE CPW-M EQUIVALENT CIRCUIT TOPOLOGY
In Figure 3.12 a four-port equivalent circuit topology to represent CPW-M
transition based in [94] was shown. In order to determine all the parameters
associated with this model, four-port network parameters are required. This is
the reason why electromagnetic simulations and optimization procedures are
used to obtain the model parameters. As can be seen, an analytical
extraction procedure for determining the model parameters is hard to develop
due to the complexity of the model. Additionally, the most commonly available
75
RF measurements are two-port measurements. Thus, the definition of an
equivalent circuit topology to represent the transition as a two port structure is
necessary to allow the determination of the parameters in a simple and
straightforward way from two-port measurements.
The derivation of a two-port equivalent circuit to represent CPW-M
transition from four-port equivalent circuit topology proposed in Figure 3.12
can be made making several assumptions and simplifications [76]. In
accordance with the model of Figure 3.12, the current flows at the pads are
related by:
21 ggs iii += (3.42)
where the sum ig1+ig2 represents the total current associated with the return
path.
The equation (3.42) is the Kirchhoff Current Law which indicates that
the current flow at the signal pad is equal to the flow current associated with
the return path. This suggests that the resistors in serie Rp which represent
the losses at the ground vias can be replaced by only one resistor in serie
with the inductor Ls. Because the CPW-M is a symmetric structure (i.e., the
resistance Rp associated with one ground via is approximately the same as
the other ground via), the resultant Rp is the parallel combination of the two
resistors associated with the ground vias. In Figure 3.22, the resultant
equivalent circuit topology is shown. Notice that the new resistor Rp is in the
signal loop pad.
Additional assumptions can be made to the resultant equivalent circuit
topology shown in Figure 3.20 in order to carry out a simplification. The next
lines describe these assumptions.
76
Figure 3.22 Equivalent circuit topology including Rp in the signal pad loop.
Since the pad capacitance is usually much bigger than the capacitance
associated with the fringing effects (i.e. Cs >>Cg), the voltage at the probe-to-
signal pad interface can be approximated by:
Bpggs
sA vvdt
diM
dtdi
MdtdiLv ++−−= 21 (3.43)
where M is the mutual inductance between the signal pad and the ground
pads. Thus, assuming ig1= ig2= is/2, which is in accordance with the fact that
the CPW-M is a symmetrical structure and that the current flow associated
with the return path is divided in two equal parts, the equation (3.43) can be
rewritten as
Bpsss
sA vvdtidM
dtidM
dtdiLv ++−−=
)2/()2/( (3.44)
After grouping terms, equation (3.44) can be expressed as:
77
Bps
eqA vvdtdiLv ++≈ (3.45)
where
MLL seq −= (3.46)
In accordance with the equation (3.45), the CPW-M transition can be
represented approximately by means of the equivalent circuit shown in Figure
3.23. Notice that equivalent inductance, Leq, is an effective inductance
resulting from the self inductances of signal pad and the mutual inductances
between the signal and the ground pads.
Figure 3.23 Two-port equivalent circuit topology derived from the topology
shown in Fig. 3.22.
After obtaining a two port equivalent circuit topology from the original
four-port equivalent circuit model, an analytical parameter extraction
procedure can be developed based on two-port network matrices. In Figure
3.24, a T-model for a two port network is shown. The corresponding ABCD
matrix for this network is given by equation (3.47).
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
+
+++=⎥
⎦
⎤⎢⎣
⎡
3
2
3
3
2121
3
1
11
1
ZZ
Z
ZZZZZ
ZZ
εδβα
(3.47)
7
3
i
e
(
78
As c
3.23 can b
impedance
F
The
equivalent
(3.50).
can be see
e associate
s as shown
Figure 3
Figure 3.25
expression
circuit top
n, the two-
ed to the T
n in Figure
.24 T netwo
Equivalent
ns that rela
pology are
Z
Z
Z
-port equiva
-model of t
3.25.
ork model f
circuit topo
ate the T-m
given by
eqLjZ += ω1
mLjZ ω=2
sCjZ +=
ω1
3
alent circuit
the Figure
for CPW-M
ology seen
model param
the equati
pR
cR
t topology
3.24 by co
transition.
as a T-mod
meters with
ons (3.48)
of the Figu
nsidering th
del.
the two-po
), (3.49) an
(3.4
(3.4
(3.5
ure
he
ort
nd
48)
49)
50)
79
By using equations (3.48), (3.49) and (3.50) and substituting these
equations in (3.47) the expressions for the ABCD parameters for the T-model
can be derived in function of the lumped elements of the proposed equivalent
circuit. In the equations (3.51) to (3.59) the ABCD-parameters for the T-model
in function of the inductors, capacitors and resistors are shown. The full
derivation of each one of the elements of the ABCD matrix is presented in the
Appendix A, Section A.2. For the case of the parameterα , the real and
imaginary part are given by (3.52) as
( )cs
pseqs
cs
peq
RCjRCjLC
RCj
RLjω
ωω
ω
ωα
++−
+=
⎟⎟⎠
⎞⎜⎜⎝
⎛+
++=
11
11
2
(3.51)
{ } 222
22
11Re
cs
eqscps
RCLCRRC
ωωω
α+
−+= { } 222
23
1Im
cs
psceqs
RCRCRLC
ωωω
α+
+=
…(3.52)
The parameter β is given by the equation (3.53) and the
corresponding real and imaginary parts by the equations (3.55). Notice that
an effective inductor Lx is introduced and defined by equation (3.54) and
represents the sum of the equivalent inductance Leq and the inductance Lm.
( )( )
⎟⎟⎠
⎞⎜⎜⎝
⎛+
++++=
cs
mpeqmpeq
RCj
LjRLjLjRLj
ω
ωωωωβ
1 (3.53)
meqX LLL += (3.54)
{ } 222
224
1Re
cs
pmscmeqsp RC
RLCRLLCR
ωωω
β+
−−+=
{ } 222
323
1Im
cs
meqscpmsX RC
LLCRRLCL
ωωω
ωβ+
−+= (3.55)
80
For the case of the parameter δ, the expressions that relate the
lumped elements of the two-port equivalent circuit topology with this
parameter are shown in the equations (3.56) and (3.57). Again, the real and
imaginary part equations for parameter δ are shown in the equation (3.57).
⎟⎟⎠
⎞⎜⎜⎝
⎛+
=
cs
RCjω
δ1
1 (3.56)
{ } 222
22
1Re
cs
cs
RCRC
ωωδ+
= { } 2221Im
cs
s
RCC
ωωδ
+= (3.57)
Finally, the parameter ε is derived and the corresponding equations
are presented. Here, the real and imaginary parts for this parameter are
expressed by equation (3.59)
cs
ms
cs
m
RCjLC
RCj
Ljω
ω
ω
ωε+−
+=
⎟⎟⎠
⎞⎜⎜⎝
⎛+
+=1
11
12
(3.58)
{ } 222
2
11Re
cs
ms
RCLC
ωωε+
−= { } 222
23
1Im
cs
cms
RCRLC
ωωε+
= (3.59)
Once each of the parameters of the ABCD matrix for the T-model are
derived, the equations (3.52), (3.55), (3.57) and (3.59) can be used to find de
values for the inductors, capacitors and resistors from the experimental ABCD
matrix associated with the CPW-M transition. However, after inspecting
(3.52), (3.55), (3.57) and (3.59), the extraction of the lumped element values
from these equations is not straightforward and easy. In fact, the equations in
this form do not allow the determination of the corresponding values from
experimental ABCD parameters. Nevertheless, simplifications to these
equations can be made in order to allow the easy determination of the
81
element values of the equivalent circuit. To make simplifications, equation
(3.57) gives the expression for the real and imaginary part for the parameters
δ and if this equation is rewritten, the product csRC can be calculated in
accordance with (3.60).
ωδδ )Im(/)Re(
=csRC (3.60)
In Figure 3.26 a plot of the product CsRc is shown. As can be seen in
this figure, the above mentioned product is very small (in the 10-12 range)
within the frequency range of interest. In accordance with the result shown in
Figure 3.24, the assumption that 1 >> ω2Cs2Rc
2 can be made from low
frequencies to 40 GHz. Bearing this consideration in mind and making
additional assumptions about values for inductors and capacitor in CPW-M
transition (typical values for the these elements are within the nH and pF
range, respectively), the equation for the ABCD parameters for the T-model
can be simplified.
Figure 3.26 csRC product up to 40 GHz.
The respective equations for the real and imaginary parts for each element of
the ABCD matrix are given as
82
{ } eqsLC21Re ωα −= (3.61)
{ } ps RCωα =Im (3.62)
{ } pR=βRe (3.63)
{ } XLωβ =Im (3.64)
{ } cs RC 22Re ωδ = (3.65)
{ } sCωδ =Im (3.66)
{ } msLC21Re ωε −= (3.67)
{ } cms RLC 23Im ωε = (3.68)
Notice that the simplified equations allow the straightforward and easy
determination of the lumped element values from the experimental α, β, δ and
ε values determined in Section 3.3 (these values are elements of the ABCD
matrix associated to the CPW-M transition). Thus, Cs and Lx can be
determined from the slope of the linear regression of the Im (δ) and Im (β)
versus frequency curves respectively as shown in Figure 3.27. Once the
capacitance CS is extracted, the inductance Lm can be extracted by the
equation (3.69)
{ }s
m CL 2
Re1ω
ε−= 3.69)
And the inductance Leq can be determined using the equation (3.54). The
results for Leq and Lm are also shown in Figure 3.27. Notice that the
equivalent inductance seen at the edge of the CPW-M adapter is negative.
According to equation (3.46), this indicates that the mutual inductance
between the ground pads and the signal pad is bigger than the self-
inductance of the signal pad.
t
r
e
d
Figure
The
the linear
respectively
equivalent
Figure dep
An
determinati
3.27 Regreelem
frequency-
regression
y. Figure 3
circuit topo
3.28 Regrependent res
interesting
ion of the e
ession of thments of the
-dependent
of the Re
3.28 shows
ology.
ession of exsistive elem
g result is
effective ind
e experimee equivalen
t resistors R
e(β) and th
s the resul
xperimentaents of the
s the fac
ductance o
ental data tot circuit top
Rp and RC c
he quadrat
lts for thes
al data to obequivalent
ct that the
of the adap
o obtain thepology.
can be dete
ic regressi
se two elem
btain the fret circuit topo
e method
pter (CPW-M
e reactive
ermined fro
on of Re(δ
ments of th
equency-ology.
allows th
M transition
83
om
δ),
he
he
n),
84
which includes the self-inductance of the signal pad and the mutual
inductance between signal pad and ground pads.
Element Values
Lx 0.35 nH
Lm 0.4 nH
Leq -0.1 nH
Cs 10 fF
Rp freq1054.2 10−×
Rc freq105.4 9−×
Table 3.2 Extracted values for the equivalent circuit model for CPW-M
transition.
Thus, as predicted by equation (3.46), when the mutual inductance is
bigger than the self-inductance of the signal pad, Leq presents a negative
effective value as shown in Figure 3.27. This effect of the negative equivalent
inductance has been studied in the literature for other type of microwave
structures [104]. At this point, values of the lumped elements that form the
equivalent circuit topology have been determined, but their validity and
correctness of both extracted values and for the equivalent circuit topology
have to be demonstrated as shown afterwards.
3.7 VALIDATION OF EQUIVALENT CIRCUIT TOPOLOGY AND EXTRACTED VALUES: FREQUENCY AND TIME-DOMAIN CORRELATIONS TO MEASUREMENTS
The equivalent circuit topology used to represent the CPW-M transition has to
be verified in order to demonstrate the corresponding accuracy and
c
p
r
i
r
c
o
c
e
f
t
correctness
proposed e
reproducing
With
implemente
represented
cascade m
obtained fro
correspond
equivalent
Figure 3.2
As c
frequency
that the circ
s within th
equivalent
g measurem
h this purp
ed in ADS
d by means
odel was s
om a micro
ding to the
circuit topo
29 Block cas
can be see
and time-d
cuit topolog
e frequenc
circuit can
ments start
pose, the
S. In this c
s of the pro
simulated in
ostrip line w
e L and Rology.
scade mod
model s
n in Figure
domain agr
gy is adequ
cy range o
n be done
ting from a
block casc
case, howe
oposed two
n ADS and
with a length
R adapters
el impleme
shown in Fi
e 3.30 and
ree well wi
ate up to 40
o interest. T
in a simila
block casca
cade mode
ever, the
-port equiv
compared
h of 352 mi
were repl
ented in AD
igure 3.1.
Figure 3.3
ith measur
0 GHz.
The verific
ar way to
ade model.
el of Figur
CPW-M tra
alent circui
with exper
il. Notice th
aced by th
S correspo
1 the simu
rements, w
cation for th
Section 3
re 3.29 w
ansition w
t model. Th
rimental da
hat the bloc
he propose
onding to th
lations in th
which indica
85
he
.4:
as
as
his
ata
cks
ed
e
he
ate
8
d
a
t
o
86
Figure 3.3.27: a) M
Figure 3
As c
domain co
and accura
the informa
order to ca
.30 Frequenagnitude of
3.31 Time-d
can be not
rrelations s
acy of the
ation extrac
rry out a po
ncy-domainf S11, b) ma
domain corr
ticed, the e
shown in th
proposed
cted from th
ossible optim
n correlatioagnitude of
of S21.
relation for
excellent re
he previou
equivalent
he proposed
mization of
n for the bloS21, c) pha
the block d
esults of th
s figures s
circuit topo
d equivalen
f the CPW-M
ock diagramase of S11, a
diagram in F
he frequenc
support the
ology. In c
nt circuit ca
M transition
m in Figure and d) phas
Figure 3.1.
cy and tim
e correctne
consequenc
an be used
n.
se
me-
ss
ce,
in
87
3.8 CONCLUSIONS
A simple and analytical measurement-based method to characterize CPW-M
transitions used to probe microstrip lines has been demonstrated. This
method allows the direct determination of the experimental ABCD matrix
associated with the transitions from measurements performed to transmission
lines with different lengths in an easy and straightforward way. The accuracy
of this method was verified up to 40 GHz by means of frequency and time-
domain correlation of a block cascade model to measurements. The excellent
frequency and time-domain correlations indicate that the characterization
process is correct and accurate at least up to 40 GHz. Furthermore, the
proposed method can be used to characterize the most common adapters
used for microwave measurements on PCB because it has a simple but
rigorous formulation.
Once the ABCD matrix corresponding to CPW-M was determined, a
two-port equivalent circuit topology was developed from a four-port circuit
reported in [94] to modeling CPW-M transition. The physical meaning of this
four-port circuit was supported by full-wave simulations and the reduction of
this to two-port circuit was done. Later on, an analytical extraction method
was developed in order to determine the element values of the circuit. The
correlation results in frequency and time-domain of a block cascade model (in
which the ABCD matrix associated to a CPW-M was changed for two-port
equivalent circuit) to measurements shown that the reduction of the four-port
circuit to two-port and the analytical extraction method are accurate and
correct. The information provided by the characterization and modeling
methodology described in this chapter can be used for future research and
optimal design of CPW-M transitions to improve their performance and to get
better S-parameter measurements for DUTs fed by microstrip lines (which
could be measured with CPW probe-tips).
89
CHAPTER IV
Electrical Characterization and Equivalent Circuit Modeling of Prototype Chip-to-Chip Interconnection Channels
4.1 INTRODUCTION
As it was previously mentioned in Chapter I, the aim of this thesis is to
investigate the electrical behavior of chip-to-chip interconnection channels
(Level 1.0 and 2.0 in the EMP) to allow the assessment of their performance
at high-frequencies. In order to achieve this goal, the electrical
characterization of the sections that form the channel is necessary because
they have an impact on the overall performance of the channel. Among the
sections that form the channel are IC packages, transmission lines and other
electrical transitions such as vias and solder bumps.
In this chapter, the electrical characterization of a complete chip-to-
chip interconnection channel is carried out by using several techniques
described in Chapter II such as de-embedding, calibration, TDR, etc. With the
information obtained from the electrical characterization, the identification of
the critical sections in the channel will be carried out analyzing the
corresponding experimental data. Finally, equivalent circuits are proposed for
each section of the channel and the extraction of the corresponding values is
determined.
4.2 DESCRIPTION OF PROTOPYPE CHIP-TO-CHIP INTERCONNECTION CHANNELS
Typical chip-to-chip interconnection channels (and the corresponding
components) were described in Chapter I. Accordingly, a typical chip-to-chip
90
interconnection channel uses packages, transmission lines and other
components such as solder bumps, sockets, etc. Therefore, the implemented
prototypes are chip-to-chip interconnection channels composed by packages
and transmission lines designed to operate under a single-ended signaling
scheme (i.e. one wire per logic signal). Additionally, solder bumps are
employed to achieve the interconnection between the package and the
transmission line (microstrip) in the PCB.
In Figure 4.1 a), the top view of the fabricated prototype
interconnection channel is shown, whereas Figure 4.1 b) shows the
corresponding simplified cross-sectional view. In order to illustrate the
physical configuration of these chip-to-chip interconnection channels and the
corresponding transitions, the main components are described hereafter.
Figure 4.1 a) Top-view and b) simplified cross-sectional view of the prototype
channel.
As can been seen in Figure 4.1 b), there are vertical transitions inside
the packages, which allow the interconnection of the chip I/O pads to
transmission lines on the PCB. These vertical transitions are composed of
a)
b)
91
vias, microvias and pads, whereas the core of the package is a plated-
through-hole (PTH) which interconnects the superior vertical transitions with
the bottom vertical transitions. Thus, in this channel a signal is propagated
from the IC pad, throughout the vertical transition, to the transmission line
(microstrip) on the PCB. However, the previous description is very simplified,
because the package has a complex structure that includes additional vertical
transitions. A more detailed view of the internal structure of the package is
shown in the Figure 4.2. As can be noticed, due to the fact that the package
is a multilayered device (i.e., inside the package there are several metal and
dielectric layers), additional vertical transitions (ground vias array) are
necessary to provide the electrical interconnection between the PCB’s ground
plane and the IC’s ground plane in order to establish a common return path in
the channel. In consequence, when the electrical characterization of the
package is carried out, the obtained data will be associated to the complete
internal structure of the package plus the solder bumps (notice that the solder
bumps are not part of the package, but serve as electrical interfaces between
the package and the PCB).
Figure 4.2 Internal structure of the prototype package (metal and dielectric
layers are not shown).
92
On the other hand, in the implementation of the prototype chip-to-chip
interconnection channels, two package technologies were used. The
difference between these technologies is the thickness of the package,
determined by the height of the core of the package. Thus, the packages
fabricated with these technologies are referred to as “thick package” and “thin
package”. Both technologies have the same ground distribution, i.e., the
distance between the vertical transition of the signal and the ground vias
array is the same. Additionally, the geometrical features of microvias, pads
and antipads are the same in both packages. The PTH that forms the core for
the thick package has a height of 800 µm, and for thin package this
dimension is 60 µm. In the Figures 4.3 and 4.4, a detailed view of the vertical
transition is shown for the thick and thin packages, respectively.
The use of thick and thin packages in the implementation of the
prototypes yields two types of chip-to-chip interconnection channels. From
now on, a channel using thick will be denominated as “thick-channel”
whereas a channel using thin packages will be referred to as “thin-channel”.
Figure 4.3 Vertical transitions inside the thick package.
93
To implement the prototypes, the packages in the thick and thin
channels are mounted on a PCB and interconnected in each case with a
microstrip transmission line. Similarly to the packages, in the fabrication of the
prototypes channels, microstrips with different lengths were used to
implement channels with different lengths. Thus, the channel which uses a
microstrip with a length of X inches and thick/thin packages will be referred to
as “X in-thick/thin channel”.
Figure 4.4 Vertical transitions inside the thin package.
Finally, both types of packages (thick and thin) include a coplanar
waveguide at the top level in order to feed the channel (package and
microstrip line) with a quasi-TEM propagation mode signal. Additionally, the
CPW lines allow the measurement of the S-parameters or the impedance
profile (TDR) using ground-signal-ground (GSG) probes. Bear in mind that
these lines introduce undesirable effects, their contribution to the
measurements have to be removed.
9
4
T
f
c
s
fc
94
4.3 ELECHIP-T
The electri
frequency
characteriz
by means
mentioned
spaced dis
limited. In
prototypes
parameters
performed
Fi
As can for the thicclose to 0 d
ECTRICATO-CHIP
ical charac
or tim
zation of the
of S-para
in Section
scontinuitie
conseque
interconne
s measurem
to the thick
igure 4.5 Ma) Magnit
b) ph
be seen inck and thindB).
AL CHARINTERCO
cterization
e-domain
e prototype
ameters or
2.4 of Cha
s such as
ence, the
ection chann
ments. The
k and thin c
Measured S-tude of S11
hase of S11
n these figu channels
RACTERIONNECT
of any DU
measure
e interconne
TDR mea
apter II, the
s the vertic
appropriat
nels depicte
correspon
hannels are
-parameterand S22, b)and S22, d)
ures, the reshow that
ZATION ION CHA
UT can be
ments. T
ection chan
asurements
e ability of
cal transitio
e approac
ed in the Fi
ding S-par
e shown in
rs for a 1 in) magnitude) phase of S
eflection pathe return
OF PRANNELS
performed
Thus, the
nnels can b
s. Howeve
TDR to re
on of the
ch to char
igure 4.1 is
ameters m
the Figure
-thick chane of S12 andS12 and S21
arameters (loss is ve
ROTOPYP
d with eith
e electric
be performe
r, as it w
solve close
packages
racterize th
s based on
easuremen
4.5 and 4.6
nel. d S21, .
(S11 and S2
ry high (ve
PE
her
cal
ed
as
ely
is
he
S-
nts
6.
22) ery
d
t
F
On t
loss when
discussion,
this reason
must be de
Figure 4.7th
Figure 4.6 Ma) Magnit
c) p
the other h
n the frequ
, the perfor
n, the electr
etermined in
7 Time-dome compone
Measured Stude of S11
phase of S11
hand, the in
uency is
rmance of
rical behavi
n order to id
main impedaents associa
S-Parameteand S22, b)1 and S22, d
nsertion pa
increased.
the prototy
or for each
dentify the c
ance profileated with ea
ers for a 1in) magnituded) phase of
rameters (
In accord
ype channe
section tha
critical com
e for a 3 in-ach variatio
n-thin channe of S12 and
S12 and S2
S12 and S2
dance with
els is very
at conforms
mponents.
-thick channon in the cu
nel. d S21, 21.
21) show hig
h the abov
poor and f
s the chann
nel showingurve.
95
gh
ve
for
nel
g
9
c
d
a
f
T
w
a
c
s
e
96
Due
complex ch
be carried a
discontinuit
measureme
and 4.8, th
for a 3 in-t
TDR wavef
waveform,
identified in
Figure 4.8
Afte
and the cor
can be de
identificatio
sections, a
each block
to the diff
hannel from
as a first ap
ties presen
ents have a
he impedan
thick chann
forms are a
and the e
n figures 4.7
Time-domacomponent
r this analy
rresponding
etermined
on of the cr
a cascade
will be pre
iculty of dir
m the meas
pproach to
nt in the c
a limited re
nce profile
nel and for
available, a
electrical d
7 and 4.8.
ain impedants associate
ysis, a casc
g experime
using de-e
ritical comp
model for
sented.
rectly ident
sured S-par
get an insig
channel. Be
esolution m
obtained fr
r a 3 in-thin
a time-dom
discontinuit
nce profile ed with eac
cade mode
ental data (S
embedding
onents in t
an entire c
tifying the c
rameters, T
ght of the m
ear in mind
ost of the t
rom TDR m
n channel,
ain analysi
ies presen
for a 3 in-thch variation
l for the ch
S-paramete
technique
he channel
channel an
critical com
TDR measu
most import
d, howeve
times. In th
measureme
respective
s is perform
nt in the c
hin channel in the curv
hannel can
er model) fo
s. In this
l is possible
d the dete
mponents of
urements ca
tant electric
r, that the
he figures 4
ents is show
ely. Once th
med for ea
channels a
l showing thve.
be propose
or each blo
fashion, th
e. In the ne
ermination f
f a
an
cal
se
4.7
wn
he
ch
are
he
ed
ck
he
ext
for
97
4.3.1 Cascade Model for a Prototype Chip-to-Chip Interconnection Channel
In accordance with the time-domain analysis presented in figures 4.7 and 4.8,
the entire channels can be seen as a cascade of the elementary blocks.
Although a cascade model for the entire channel can be proposed by simply
inspecting the layout shown in Figure 4.1; the time-domain analysis yields an
extra insight. In Figure 4.9, a cascade model is proposed for the entire
channel. This model is composed of several S-parameter blocks which
represent each section (main discontinuities) in the channel.
Figure 4.9 Proposed cascade model for the entire channel.
As can be seen in Figure 4.9, the test fixtures A and B represent the
CPW transmission lines on the top of the packages. In A and B, the
discontinuities caused by the CPW pads used to probe the channel are
included. The model that represents the package includes the vertical
transitions (signal and ground vertical transitions) plus the solder bumps used
to interconnect the package with the microstrip line.
4.3.2 Determination of S-parameter Model for the Cascade Model Using Thru-Reflect-Line (TRL) Calibration Technique
When the S-parameter measurements were performed to the
prototype chip-to-chip interconnection channels, the resulting measurements
include the effects of the packages, microstrip and CPW structures. In order
98
to determine the S-parameter model associated to each component of the
cascade model depicted in the Figure 4.9, additional test structures were
designed so that the S-parameters of the packages, test fixtures, and
microstrip can be accurately determined. Figure 4.10 depicts a single
package-to-microstrip (PTM) test structure that can be used for the
determination of the S-parameter model of the package. This structure is
implemented with one package (thick or thin) having a CPW on top and is
connected to a PCB microstrip line at the bottom. Hence, the PTM structure
can be seen as a DUT (i.e. the package) embedded between two
asymmetrical transmission lines (the CPW and microstrip transmission lines)
which can be regarded as part of the test fixture (see Figure 4.11). Thus, the
de-embedding process consists of removing the effect of the test fixture from
the S-parameters measured to the PTM structure for isolating those
corresponding to the package’s vertical transition.
Figure 4.10 PTM interconnection structure.
The microstrip and CPW transmission lines can be seen as part of the
test fixture structures. Thus, their effects need to be characterized and
removed from the measured results in order to obtain the S-parameters of the
DUT. As it was mentioned in Chapter II, there are primarily two methods to
remove the undesirable effects of the test fixtures: using measurement-based
models and simulation-based models. In the case for the first approach,
calibration methodologies such as TRL are used to obtain the model
99
associated with the test fixture. In contrast, the second method uses
electromagnetic simulation to characterize the test fixture. In both methods,
the model for the test fixture can be obtained.
Figure 4.11 Cascade model for the PTM structure.
Once the S-parameters model associated with the test fixtures have been
obtained, their corresponding effect can be removed from the experimental
measurements by converting the S-parameter matrix to an ABCD matrix and
using simple matricial operations [17].
To determine the S-parameter model of the test fixtures of Figure 4.11
and thus determining the corresponding S-parameters model of the package,
the TRL calibration technique is used. Unfortunately, the straightforward
application of TRL is not suitable to the cases where the DUT is embedded
between two lines with different characteristic impedance (Z0) and
propagation constant (γ) such as the case of the PTM interconnection
structure. Consequently, additional analysis and processing is required to de-
embed the S-parameters of the package. The conventional TRL calibration
technique allows determining the S-parameters of a transmission line-based
test fixture. As a result, a set of dummy structures (see Figure 4.12) was
designed to obtain the S-parameters associated with each test fixture, i.e., a
set of CPW and microstrip transmission lines were designed to obtain the
corresponding S-parameter model of the test fixture A and B shown in figure
4.11.
t
d
g
w
a
s
c
o
t
o
100
Figure 4
Onc
their effect
manipulatio
direct conv
given by:
where TM is
and TB ar
respectively
straightforw
consequen
obtained by
Afte
the resultin
of the tran
however, th
.12 Set of d
ce the S-pa
can be re
on. Thus, a
version of
s the exper
re ABCD
y. Notice
ward conv
nce, the ex
y solving (4
r removing
ng S-param
nsmission l
hat the refe
dummy stru
rameters a
moved from
according t
the meas
rimental AB
matrices a
that the m
version o
xperimental
4.1) for TPKG
the effect
meters of th
ine used to
erence impe
uctures for cfixture.
associated w
m the mea
to Figure 4
ured S-par
PKAM TTT ⋅=
BCD matrix
associated
matrices TA
of the co
data asso
G, which yie
1− ⋅= APKG TT
of the test
he package
o feed the
edance in th
characteriz
with A and
sured data
4.11, the m
rameters to
BKG T⋅
x of the PTM
with the
A and TB
orrespondin
ociated wit
elds:
1−⋅ BM TT
t fixtures fro
e are refere
e structure.
his case is
ing the mic
B have be
a by using A
matrix obtain
o ABCD-p
M structure
test fixture
are obtain
ng S-para
th the pack
om the me
enced at the
Notice in
expected to
crostrip test
een obtaine
ABCD mat
ned from th
arameters
(4.
, whereas
es A and
ed from th
ameters.
kage can b
(4.
easured dat
e impedan
Figure 4.1
o be differe
ed,
rix
he
is
.1)
TA
B
he
In
be
.2)
ta,
ce
11,
ent
101
at each port since the A and B fixtures are associated with different type of
transmission lines (CPW and microstrip respectively). For this reason, an
impedance renormalization of the obtained S-parameters of the package has
to be performed:
ARSIRSAS 11* ))(( −− −−= (4.3)
where S is the S-parameter matrix without renormalization, *S is the resulting
S-parameter matrix after renormalization and I is the identity matrix. The
matrices A and R are given by the equations (4.4) and (4.5):
⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜
⎝
⎛
=
)(....00..........0..)(00....0)(
2
1
nZr
ZrZr
R
beforenn
beforennn ZZ
ZZZr
,
,)(+−
= (4.4)
⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜
⎝
⎛
=
nA
AA
A
....00..........0..00....0
2
1
beforennbeforen
nn ZZZ
ZA,,
1+
= (4.5)
In these equations, nZ is the impedance reference at the n-port after
renormalization, beforenZ , the impedance reference at the n-th port before
renormalization. In the case of singled-ended devices, the resulting matrices
have 2x2 dimensions.
The de-embedding process mentioned above which uses TRL
calibration technique was applied to the thick-PTM and thin-PTM structures in
order to obtain the S-parameter model of the corresponding packages. The
figures 4.13 and 4.14 show how the effects of the test fixtures A and B were
removed from the measurements corresponding to each PTM structure. On
t
t
a
102
the other h
the thick an
Figure 4
Figure 4
As c
and port 2
and, the Fi
nd thin pack
.13 S-paramembedd
4.14 S-paraembedd
can be seen
(|S11| and |
gures 4.15
kage, respe
meters of thding the eff
ameters of tding the eff
n in the figu
|S22| respec
and 4.16 s
ectively.
he thick-PTfect of the t
the thin-PTMfect of the t
ures 4.15 a
ctively) con
show the re
TM structureest fixtures
M structureest fixtures
nd 4.16, th
nsiderably in
esulting S-p
e before an A and B.
e before and A and B.
e return los
ncrease wit
parameters
nd after de-
d after de-
sses at port
th frequenc
of
t 1
cy.
T
t
This clearl
packages d
that this is t
Figure 4.1of S11 and
Figure 4.1of S11 and
y indicates
degrade th
the critical
5 De-embeS22 b) mag
6 De-embeS22 b) mag
s that the
e channel
component
edded S-pagnitude of S
o
edded S-pagnitude of S
o
electrical
performanc
t in the cha
rameters foS12 and S21,of S12 and S
arameters foS12 and S21,of S12 and S
discontinui
ce at high
nnel.
or the thick , c) phase oS21.
or the thin p, c) phase oS21.
ities introd
frequencie
package: aof S11 and S
package: aof S11 and S
1
uced by th
es suggestin
a) magnitudS22, d) phas
) magnitudS22, d) phas
103
he
ng
de se
e se
104
Additionally, in Figure 4.16 it can be noticed that the thin package
presents a resonance effect in the transmission parameter at approximately
25 GHz, which yields an undesirable notch filter characteristic in the
propagation of the signal throughout this package.
Up until this point, the S-parameter models for the thick and thin
packages have been determined using TRL calibration technique.
Nevertheless, there are remaining components in the cascade model that
must be determined in order to achieve a complete electrical characterization
of the entire prototype chip-to-chip interconnection channels. Fortunately, the
de-embedding process previously described allowed the determination of the
S-parameter models for the package and additionally for the CPW test
fixtures. Thus, the only remaining component is the microstrip line, which can
be modeled using the following equation:
⎥⎦
⎤⎢⎣
⎡=⎥
⎦
⎤⎢⎣
⎡− )cosh()sinh(
)sinh()cosh(1
0
0
llZlZl
DCBA
γγγγ
(4.6)
where the complex propagation constant γ was obtained from the TRL
calibration process and the characteristic impedance Z0 can be determined
using the method reported in [99]. Thus, the ABCD matrix corresponding to
the microstrip line can be determined. Furthermore, the S-parameter model
for the microstrip line can be obtained by means of an ABCD-to-S conversion.
4.3.3 Validation of the Characterization Process Using Frequency and Time-Domain Correlations to Measurements
At this point, the S-parameters models that compose the cascaded model of
Figure 4.9 have been obtained using the TRL calibration technique. This
a
t
a
t
t
f
c
e
c
c
S
s
allowed the
the transm
accuracy o
the correct
the channe
A co
fixtures and
complete p
using this
electrical c
calibration
measureme
carry out a
S-paramete
simulator w
Figuremagnitu
e assessme
mitted signa
of the S-par
tness of the
el.
omplete ch
d a microst
prototype ch
cascade m
characteriza
technique
ents of an e
correlation
er block s
was used to
4.17 Frequude of S11 b
ent of the i
als from the
rameter mo
e electrical
hannel is c
trip line tha
hip-to-chip
model. Thu
ation proc
as de-em
entire chan
n of the cas
simulator is
o correlate t
uency-domb) magnitud
mpact cau
e insertion
odels has to
characteri
composed
at interconn
interconne
s, one way
ess (which
mbedding t
nnel using t
scade mode
s necessa
the cascade
ain correlatde of S21, c
sed by the
and return
o be verifie
ization proc
of two pa
nects the tw
ection chan
y to verify
h includes
echnique)
he model o
el with expe
ary. In this
e model to
tion for a 3 ) phase of S
package t
n losses. H
ed in order
cess of eac
ckages, tw
wo package
nel can be
the correc
the use
is by rep
of Figure 4.
erimental d
s case, Ag
experiment
in-thick chaS11, d) phas
1
transitions o
However, th
to guarante
ch section
wo CPW te
es so that th
e represente
ctness of th
of the TR
roducing th
9. In order
ata, using a
gilent’s AD
tal data.
annel: a) se of S21.
105
on
he
ee
in
est
he
ed
he
RL
he
to
an
DS
e
c
s
c
c
c
a
T
106
Freq
experiment
channels a
seen, the
parameters
presented o
range (0-30
correlations
chip-to-chip
independen
correlation
renormaliza
a correct w
Figuremagnitu
In t
Transform
quency-dom
tal data we
are shown
magnitude
s are sho
only up to
0 GHz) pre
s for both ty
p measure
nt from the
was perfo
ation of the
way.
e 4.18 Frequde of S11 b
his case,
(iFFT) of th
main correl
ere carried
in the figu
and phase
wn. The
10 GHz in
esent many
ypes of cha
ements us
e character
ormed in o
e S-parame
uency-domb) magnitud
for the tim
he reflection
lations of
out. The re
ures 4.17 a
e of the fo
phase of
both cases
y periods. N
annels were
sed in th
rization pro
order to m
ters related
main correlade of S21, c
me-domain
n paramete
the simula
esults for a
and 4.18, r
orward refle
the transm
s, because
Notice that
e obtained
e compar
ocess. Add
make certa
d to the pac
ation for a 3) phase of S
n correlatio
er S11 was c
ated cascad
3 in-thick
respectively
ection and
mission pa
the curves
good frequ
despite the
rison were
itionally, a
in that the
ckage was
3 in-thin chaS11, d) phas
on, an Inv
carried out
de model
and 3 in-th
y. As can b
transmissio
arameters
in the who
uency-doma
e fact that th
e complete
time-doma
e impedan
carried out
annel: a) se of S21.
erse Fouri
to obtain th
to
hin
be
on
is
ole
ain
he
ely
ain
ce
in
ier
he
c
w
a
t
c
c
4
e
a
t
correspond
waveforms
are present
Figure 4.19
The
that the d
channel (p
characteriz
process.
4.4 EQUCHIP-T
Once the S
been deter
each one
(lumped, d
analyze an
package o
used in SP
to obtain
ding TDR
for the sim
ted.
9 Time-dom
excellent f
e-embeddi
ackages, t
zed. This v
UIVALENTO-CHIP
S-paramete
rmined, equ
of these se
istributed o
d do not gi
r any elec
PICE-like sim
accurate p
waveform.
mulated ca
main correla
frequency
ng proces
est fixtures
verifies the
NT CIRCINTERCO
er models
uivalent circ
ections. Th
or hybrids) i
ve an insig
trical trans
mulators wh
prediction
. In Figure
scade mod
ation for: a)channel.
and time-d
s is correc
s and trans
e validity
UIT MOONNECT
for every s
cuit topolog
he main re
is that the S
ght about th
sition. In ad
hich do not
of the per
e 4.19, th
del for the
) 3 in-thick c
domain cor
ct and tha
smission lin
of the ele
DELING ION CHA
section of t
gies can be
eason for u
S-paramete
he physical
ddition, equ
t require mu
rformance
he corresp
thick and t
channel an
rrelation res
at each se
nes) has be
ectrical cha
OF PRANNELS
the each c
e proposed
using equiv
er models a
phenomen
uivalent cir
uch compu
associated
1
onding TD
thin channe
d b) 3 in-th
sults indica
ection of th
een correc
aracterizatio
ROTOPYP
channel hav
d to modelin
valent circu
are difficult
on inside th
rcuits can b
tational effo
d with the
107
DR
els
in
ate
he
ctly
on
PE
ve
ng
its
to
he
be
ort
se
108
electrical transitions. However, in order to obtain accurate predictions in
SPICE-like simulators, the equivalent circuit which is used to represent the
electrical transitions must be accurate in the frequency range of interest. In
consequence, many extraction techniques to determine the equivalent circuit
model have been developed, such as it was presented in Chapter II.
The equivalent circuit modeling of each section can be performed in
order to obtain an equivalent circuit that represents the entire channel.
Therefore, a circuit topology must be associated with the test fixtures,
packages and microstrip line. In order to model the microstrip line, the RLCG
equivalent circuit can be utilized, and for the case of the test fixtures (CPW
lines), the same model in conjunction with an equivalent circuit that
represents the electrical transitions caused by the pads can be used. The
RLCG equivalent circuit can be extracted from experimental S-parameters
[105] associated with a homogeneous section of transmission line, and the
extraction method of the values corresponding to the equivalent circuit
topology (related to the pads) can be found in [76]. Nonetheless, the current
SPICE-like simulators such as ADS have libraries to model several types of
transmission lines (among them, CPWs and microstrips). These ADS models
require as input data the physical dimensions and material specifications
(width, length, height, conductivity, loss tangent, permittivity, permeability,
etc.) which the transmission lines are made of. As can be seen, the above-
mentioned quantities are known. Hence, instead of using RLCG models, the
modeling of the transmission lines is carried out by means of ADS models. In
Section 4.4.2, the accurateness of the model for the CPW test fixtures and
the microstrip on the PCB will be verified.
In contrast, the modeling of the electrical transitions caused by the
packages is more difficult than modeling transmission lines terminated with
pads. In fact, developing the equivalent circuit topologies for complex
electrical transitions such as packages is currently a hot topic. In the next
s
e
d
4
A
t
v
t
t
o
d
section, an
experiment
determined
4.4.1 Equ
As it was m
thick packa
not shown.
planes are
vertical tra
topologies
these are
optimizatio
in Chapter
determine e
Unfo
packages.
parameters
not approp
n equivalent
tal data. I
d by using t
uivalent C
mentioned
age (see Fig
. Figure 4.2
depicted. A
ansition are
for modeli
obtained
n tools and
r II), and
each eleme
Figure 4.20
ortunately,
Additionally
s with physi
priate for o
t circuit top
n addition
he ADS op
Circuit Mo
before, the
gure 4.3). I
20 shows a
As can be
e surround
ng a via li
using m
d analytical
these tech
ent in the m
0 Via packa
the model
y, there are
ical phenom
optimizing
pology for t
, the valu
ptimization t
odeling o
ere exist se
In this figur
a section of
observed, t
ded by gro
ke the one
mathematica
l methods
hniques ar
model.
age surroun
of a simple
e severe d
mena. In co
a complex
he package
ues for the
tool.
of the Thi
veral vertic
re, however
f the packa
the vias as
ound plane
e shown in
al techniqu
(these tech
re applied
nded by gro
e via is not
ifficulties in
onsequence
x DUT like
e is propos
e circuit e
ck Chann
cal transitio
r, the groun
age in whic
ssociated w
es. There e
n Figure 4.
ues such
hniques we
to measu
ound plane
t enough in
n associatin
e, these ap
e a packag
1
sed based o
elements a
nel
ns inside th
nd planes a
ch the groun
with the sign
exist sever
20. Some
as VF-lik
ere describe
ured data
s.
n the case
ng the mod
proaches a
ge. In [106
109
on
are
he
are
nd
nal
ral
of
ke,
ed
to
of
del
are
6],
t
s
q
e
f
v
g
w
t
v
110
modeling te
topologies
structures h
In [
quasi-static
elements v
10 GHz). O
from exper
validated w
F
In c
based struc
model a v
geometrica
with the pa
inductance
is related to
Altho
networks g
the via. Th
vertical tran
echniques
studied. Ho
have not be
107], a sim
c behavior
values is pr
Other publi
rimental da
within relativ
Figure 4.21
consequenc
cture. A sim
via. This
al features
arallel plate
is associa
o metal loss
ough there
ive an intui
en, an equ
nsition base
for via stru
owever, ge
een reporte
mple meth
r and usin
oposed, bu
ications de
ata; but ag
vely low-fre
Simple П-t
ce, a topolo
mple equiva
simple Π-
of the via.
capacitor
ated with th
ses.
are more
tive insight
uivalent circ
ed on the Π
uctures are
eneral techn
ed.
hod for mo
ng analytic
ut with a lim
escribe met
gain, most
quency ran
ype RLC e
ogy must
alent circui
-type RLC
For instan
composed
e cylindrica
sophisticat
on the phy
cuit topolog
Π-type RLC
described
niques to re
odeling diff
cal formul
mited freque
thods to ob
t of these
nges.
quivalent c
be develop
t, shown in
topology
nce, the ca
by the pad
al body of t
ted topolog
ysical pheno
gy can be d
network.
and the co
epresent m
ferential via
as to ext
ency range
btain equiv
equivalent
ircuit mode
ped for a c
n Figure 4.2
is associa
pacitance i
d and groun
the via, and
ies, simple
omena that
developed
orrespondin
more compl
as assumin
tract lumpe
(up to abo
valent circu
t circuits a
el for a via.
complex vi
21 is used
ted with th
is associate
nd plane, th
d the resist
e Π-type RL
t occur insid
to model th
ng
ex
ng
ed
out
its
are
ia-
to
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tor
LC
de
he
t
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d
d
Figu
The
transition i
elements w
Optimizatio
Figure 4.
Figu
data using
demonstrat
ure 4.22 Pro
equivalen
s shown i
were determ
on Controlle
23 Model o
ure 4.23 sh
this model
te that the
oposed equ
nt circuit t
n Figure 4
mined by m
er).
optimization
hows the e
and the ex
thick pack
uivalent circ
topology p
4.22, and t
means of th
n using ADS
excellent a
xperimental
kage can b
cuit topolog
proposed
the corresp
e ADS opt
S Test Lab
agreement
l data up to
be represen
gy for the th
to model
ponding va
imization to
Simulation
between th
o 30 GHz. T
nted with t
1
hick packag
the vertic
alues for th
ool (Test La
Controller.
he simulate
These resu
the propose
111
ge.
cal
he
ab
.
ed
lts
ed
e
e
c
t
e
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t
c
a
4
T
t
t
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4
112
equivalent
extraction
currently un
to determin
equivalent
equivalent
this packag
captured by
about the r
4.4.2 ValCha
The equiva
the thick p
Neverthele
the micros
accuratene
correlations
4.9 was im
Figure 4.24
circuit at le
techniques
nder invest
ne the valu
circuit mod
circuit topo
ge (the not
y the propo
esearch of
idation oannel
alent circuit
package w
ss, the equ
strip lines
ess of the e
s are carrie
plemented
4 Equivalen
east up to t
s to determ
igation (for
ues of the
deling of th
ology for the
tch charac
osed equiva
the thin pa
of Equiva
t topology
was verified
uivalent circ
still have
extracted eq
ed out. For
again
nt circuit of t
his frequen
mine the v
r this reason
equivalent
e thin pack
e thick pac
teristic in t
alent circuit
ackage are
alent Circ
used to re
d up to 30
cuit associ
e to be v
quivalent ci
r this purpo
the entire c
ncy. The de
values for t
n, optimizat
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kage is cur
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the transm
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presented.
cuit Mode
present the
0 GHz us
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On the oth
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o verify th
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in ADS.
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ta.
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he
ain
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e
t
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e
f
In th
equivalent
the CPW te
for a CPW
microstrip (
This
experiment
Figuremagn
As c
frequency
his case, ho
circuit mod
est fixtures
W and the
(see Figure
Figure 4
s cascade
tal data obt
4.26 Frequitude of S11
can be see
and time-d
owever, the
del explaine
by means
microstrip
e 4.24).
.25 Equival
model wa
tained from
uency-dom1 magnitude
n in Figure
domain agr
e package
ed in the p
of the equ
line on th
lent circuit f
as simulat
a 3-in long
ain correlate of S21, c)
e 4.26 and
ree well wi
was repres
previous se
uivalent circ
he PCB w
for the thick
ed in ADS
g channel.
tion for a 3 phase of S
Figure 4.2
ith measur
sented by m
ction (see
cuit and the
ith the AD
k package.
S and com
in-thick chaS11, d) phase
7 the simu
rements, w
1
means of th
Figure 4.25
e ADS mod
DS model f
mpared w
annel: a) e of S21.
lations in th
which indica
113
he
5),
del
for
ith
he
ate
t
3
4
t
c
c
s
c
t
e
w
t
a
c
114
that the circ
30 GHz.
Fig
4.5 Con
In this cha
interconnec
parameters
the propos
characteriz
characteriz
structures.
characteriz
that the c
package du
equivalent
with the th
transition.
accurately
characteriz
used for
interconnec
high-speed
cuit topolog
gure 4.27 T
nclusions
apter, it h
ction chann
s and the
sed charact
ze chip-to-c
zation proc
Using th
zation meth
ritical com
ue to the el
circuit topo
hick packag
It was fo
the packa
zation and m
future re
ctions and
d computer
gy which re
ime-domain
s
has been d
nel can be
well-establ
terization te
chip interco
cess desc
he informa
hodology, a
ponent in
lectrical dis
ology base
ge and us
ound that
age up to
modeling m
search an
to improve
application
presents th
n correlatio
demonstrat
e character
ished TRL
echnique is
onnection c
cribed in t
ation obtai
an assessm
high-speed
scontinuities
d on a П-t
sed for mo
the propo
30 GHz.
methodology
nd design
e the perfor
ns.
he entire ch
n for the 3
ted that a
ized at hig
calibration
s accurate
channels. O
this chapt
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odeling the
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ter require
applying th
arried out w
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-speed pa
chip-to-chip
dequate up
annel
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e. Therefor
be applied
the electric
es addition
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annel is th
n addition, a
as associate
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115
CHAPTER V
Future Developments
5.1 INTRODUCTION
In the previous chapter, an equivalent circuit to model packages with several
transitions was proposed. This model was adequate to represent the
electrical behavior of a package with relatively long core via that is referred to
in this thesis as thick package. In contrast, the behavior of a package with a
much shorter core via (the one called thin package) was not properly
reproduced using a simple equivalent circuit. Furthermore, the de-embedded
S-parameters associated with the thin package showed that there exists a
resonance effect (i.e., a notch response characteristic) in the transmission
parameters (S12 and S21). For this reason, an analysis for the identification of
the origin of the resonance effect in the thin package is necessary in order to
develop an adequate equivalent circuit topology and eventually an
optimization of the structure.
In this chapter, preliminary results on the analysis of the origin of the
resonance effects that causes the notch response in the transmission
parameters of the thin package are presented. When using full-wave
simulations, the possible origin of the resonance is identified and a parametric
simulation of a simple via transition in a parallel plate environment is carried
out in order to show the impact of the location of the ground array vias on the
overall performance of the package. Finally, some ideas for future research
are proposed to overcome the drawbacks presented in the equivalent circuit
modeling and in the optimization of electronic packages.
116
5.2 ISSUES UNDER INVESTIGATION
As it was previously mentioned, the transmission parameters associated with
the thin package show notch responses. In a chip-to-chip interconnection
channel this type of responses in the transmission is undesirable due to the
negative impact introduced by the degradation of the signal integrity. In order
to understand how a notch response affects the propagated signal in a
channel with this type of transmission response, a brief discussion of this
situation is presented hereafter.
In the left side of Figure 5.1, the spectrum of a high-speed signal is
shown. When this high-speed signal is propagated throughout a chip-to-chip
interconnection channel which has a notch response, the spectrum of the
received signal will be affected (see right side of Figure 5.1). The spectrum of
the received signal is affected in magnitude in several regions, depending on
the transmission characteristics of the channel. These results in the
degradation of the signal integrity because the obtained time-domain signal
has undesirable effects such as ringing, overshoot, distortion, etc. In fact, the
effect of a notch response in the channel is similar to a filter, but in this case
the phenomenon is undesirable.
Figure 5.1 Effect in a propagated signal throughout notch response channel.
w
a
s
A
d
a
W T
t
o
e
As c
with the t
accordance
signals in
Additionally
degradation
are identifie
Figure 5.2
5.2.1 SimWave So
The detaile
the extrac
identificatio
out in this
propagate
move throu
package c
electric an
propagation
modes).
can be seen
hin packag
e with the
the chann
y, the high-
n to the sig
ed by mean
2 Notch res
mulation oolvers
ed investiga
ction of p
on of the or
way. Thus
along the
ugh the dis
can help to
nd magneti
n, transve
n in Figure
ge present
previous d
nel will be
-reflection c
nal. In the
ns of full-wa
ponse chart
of the Re
ation of the
physically
rigin of the
s, the obse
structure a
scontinuity
o identify
ic energy
rse magne
5.2, the tra
t a notch
discussion,
e severally
caused by
next sectio
ave simulat
racteristic inthin packag
esonance
e field patte
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and how t
caused by
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ansmission
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n, the poss
ions.
n transmissge.
e in the T
erns can b
ackage m
in the thin
on how the
he field pa
y the vertic
lectromagn
transverse
gation or
n parameter
at about
trum of the
by the th
package w
sible origins
sion parame
Thin Pack
e the first
models. Mo
package ca
e electroma
atterns cha
cal transitio
netic pheno
electric a
excitation
1
rs associate
25 GHz.
e propagate
hin packag
will add mo
s of this effe
eters for the
kage: Fu
step towar
oreover, th
an be carrie
agnetic fiel
ange as th
on inside th
omena (e.g
nd magne
of parasi
117
ed
In
ed
ge.
ore
ect
e
ll-
ds
he
ed
ds
ey
he
g.,
tic
tic
118
Figure 5.3 Boundaries in the HFSS model for the thin package.
In order to carry out a detailed investigation about the field patterns,
using a full-wave solver is necessary. For this purpose, Ansoft’s HFSS is
used. However, to obtain reliable full-wave simulations, several aspects have
to be taken in to account in order to avoid mistakes. The most important is
related to the boundary conditions imposed to the model. In Figure 5.3, the
simulated model corresponding to the thin package is shown.
In this case, in order to avoid mistakes in the simulated response, the
boundary condition selected for the walls of the package is RADIATION,
which allows the absorption of the incident waves. Additionally, the calibration
of the ports must be carried out in order to guarantee reliable simulations. In
Figure 5.4, the geometry used for the full-wave simulation is depicted.
Figure 5.4 Geometry used for full-wave simulations of the thin package.
t
t
s
5
e
e
c
As it
transmissio
is a microst
that feed th
model has
specificatio
5.5, the res
Figure 5.5
As c
effect in the
experiment
correspond
possible or
t was ment
on line, whe
trip line. Alt
he package
been con
ons have be
sulting S-pa
Frequency
can be notic
e transmiss
tal data ass
ding electro
rigin of the r
tioned befo
ereas at the
though in F
e are define
structed an
een determ
arameters o
y-domain co3D mode
ced, the full
sion param
sociated wit
omagnetic
resonance.
ore, at the t
e PCB in w
Figure 5.4 th
ed at the te
nd all ports
mined, the m
of the full-w
orrelations el shown in
l-wave simu
eters. The
th the thin p
fields dist
op of the p
hich the pa
hese lines a
ermination o
s, boundar
model can
wave simula
to measureFigure 5.4.
ulation also
good corre
package, a
tribution in
package the
ackage is m
are not sho
of these lin
ry condition
be simulat
tions are sh
ements of th.
o predicts th
elation obta
llows the a
n order to
1
ere is a CP
mounted the
own, the por
es. Once th
ns and oth
ed. In Figu
hown.
he simulate
he resonan
ained with th
nalysis of th
identify th
119
PW
ere
rts
he
her
ure
ed
ce
he
he
he
120
5.2.2 Parallel Plate Propagation Modes (PPM) in Thin Package
In accordance with Figure 5.5, the resonance effect occurs approximately at
25.5 GHz. Thus, in Figure 5.6, the electric field distribution at 25.5 GHz
between two layers in the thin package structure is shown. As can be seen,
there is propagation of electric field in spite of the fact that these layers are
ground planes. This phenomenon is associated with the discontinuity caused
by a via transition that excites parasitic modes which cannot be recovered as
signal.
Figure 5.6 Electric field distributions at 25.5 GHz: a) 0°, b) 15°, c) 25°, d) 45°, e) 65°, and f) 85° degrees.
The excitation of parasitic modes caused by electrical discontinuities in
PCB structures have been reported and studied [108]. Moreover, the
excitation and propagation of PPM have been studied in electronic packages
121
[109]-[110] and high-speed via-based interconnections [111]. Although the
electric field distribution at the resonant frequency shows the presence of
PPM, a plot of the same field distribution at other frequencies shows that
PPM is also present. In accordance with the previous lines, the analysis of
the field patterns is not enough to identify the actual origin of the resonance.
In consequence, a more detailed study about PPM excitation caused by via
transitions must be carried out. In Figure 5.7, a simplified sketch about the
PPM generation caused by a via transition in a two-layer environment is
shown. In order to understand the physics behind the PPM generation, a brief
compilation about this topic based on the reported literature is presented
hereafter.
Figure 5.7 Excitation of PPM in a via transition between two layers.
In [112], a formulation for modeling PPM is presented. In accordance
with this paper, PPM can be modeled using radial transmission line theory. In
this analysis, a transmission-line-type formalism is introduced for the
dominant propagating mode by means of solving the Helmholtz’s equation
which is in spherical coordinates. Thus, when the mentioned equation is
resolved, a set of telegrapher’s equations with characteristic impedance Zpp,
which varies with the radial distance ρ, can be written. The corresponding
characteristic impedance for a PPM is given as:
πρη2
hZ pp = (5.1)
122
where η is the intrinsic impedance of the medium between the parallel planes,
h is the height of the parallel planes and ρ is the radial distance from the
origin to the observation point. As can be noticed, the characteristic
impedance for PPM has a similar definition for the other type of propagation
modes such as TEM, TE, and TM. Additionally, in [112] a discussion about
the behavior of the input impedance for radial transmission lines is
elaborated: an interesting feature of radial transmission lines is that the
characteristic impedance for an infinite line is not the same as its input
impedance. In consequence, the input impedance for PPM (also known as
driving point/input impedance) yields a complex behavior in frequency. In
[106], a compilation of closed formulas for the analytical calculation of the
characteristic impedance for PPM are shown. In compliance with this paper,
there are three fundamental configurations of parallel planes in which PPM
can be determined analytically:
1. Parallel planes of finite, rectangular size with open boundaries,
2. Parallel planes of finite, rectangular size with shorted
boundaries, and
3. Parallel planes of infinite size.
The first type of configuration of the parallel planes is known as Perfect
Magnetic Conductor (PMC) configuration. The second is referred to as
Perfect Electric Conductor (PEC) configuration and the last one as Perfect
Matched Layer (PML) configuration. For the first two configurations, the
parallel plane impedance Zpp is given by the equation (5.2)
∑∑∞
=
∞
= −⎟⎠⎞
⎜⎝⎛+⎟
⎠⎞
⎜⎝⎛
⋅⋅⋅=
0 0 222
22 ),(),(
m n
YXportYXboundarynmpp
kb
na
m
LLffCCab
hjZππ
ρρωμ (5.2)
123
Where j is the imaginary unit, ω the angular frequency, µ the permeability, h
the height of the parallel planes, a and b the plane dimensions, ρX and ρY the
ports locations, LX and LY the ports dimensions and K is the wave vector. The
other parameters are given as:
⎩⎨⎧ =
=otherwise2
0,1,
nmCC nm (5.3)
⎪⎪⎩
⎪⎪⎨
⎧
⎟⎠⎞
⎜⎝⎛⋅⎟
⎠⎞
⎜⎝⎛
⎟⎠⎞
⎜⎝⎛⋅⎟
⎠⎞
⎜⎝⎛
=PECFor sinsin
PMCFor coscos),(
22
22
bn
am
bn
am
fYX
YX
YXboundary πρπρ
πρπρ
ρρ (5.4)
⎟⎟⎠
⎞⎜⎜⎝
⎛⋅⎟⎠⎞
⎜⎝⎛=
bLm
aLmLLf yX
YXport 2sinc
2sinc),( 22 ππ (5.5)
Figure 5.8 shows the coordinate system and the dimensions for PEC
and PMC configurations. As can be noticed, due to the finite size of the
planes, there are reflective planes edges for incident electric and magnetic
fields (for this reason the name of PEC and PMC). The equation for the
parallel plane impedance shows a complex behavior in frequency. This is due
to the fact that the pair of planes forms a resonator and in combination with
the defined PEC, PMC or PML boundary conditions, the resulting parallel
plane impedance shows the above mentioned complex behavior.
On the other hand, the parallel plane impedance for the third
configuration (PML) is given as:
)()(
2 0)2(
1
0)2(
0
0 ρρ
πρη
kHkHhjZ pp ⋅= (5.6)
124
Figure 5.8 Coordinate system and geometric features in PEC and PMC
configuration [106].
where η is the intrinsic impedance of the medium between the planes, ρ0 is
the radius of the via, H0(2) and H1
(2) are Hankel functions of second kind with
orders 0 and 1, respectively. In Figure 5.9, the coordinate system and the
dimensions for this configuration are depicted.
Figure 5.9 Coordinate system and geometric features in PML configuration
[106].
The previous discussion is applied to study the performance of a via in
three configurations. In [106], a discussion about the relationship between S-
parameters and Zpp is elaborated for the three types of parallel planes
configurations and it is important to remark the conclusion: the higher the
magnitude of Zpp the lower the transmission. In the next section a similar
study to that presented in [106] is carried out.
125
5.2.3 Performance of a Simple Via Transition with PPM Effects
In the previous section, an overview about the generation PPM was
presented. In addition, the analytical expression of the parallel plane
impedance for three configurations was given. In accordance with [106], the
performance of a via is affected by the return current loop. The return current
loop is closed by both the parallel planes and the ground vias. In the thin
package, the return current loop can be very complex because there are
ground via arrays surrounding the signal via. In consequence, the boundary
conditions are not ideal (i.e., the boundary conditions for the package are not
PEC, PMC or PML). Additionally, there are many layers in the thin package in
which PPM propagation is present. Thus, the detailed calculation and
analysis of the input impedance (which affects the S-parameters of the
package) for this complex structure is very hard. As it was mentioned before,
the input impedance for a device in which there exists PPM propagation is
dependent of the Zpp.
In order to begin a systematic analysis, one layer with geometrical
features similar to those of the thin package core is simulated. In Figure 5.10,
the via geometry under investigation is shown. The ground vias are placed at
several distances from the signal via. This distribution has the purpose of
observing the effect of the ground vias location in the S-parameters
associated with the via.
126
Figure 5.10 Via geometry under investigation.
The structure depicted in Figure 5.10 was simulated in HFSS varying
the distance of the ground vias. In Figure 5.11, the resulting S-parameters are
shown for the different distances. In this figure, the impact of the placement of
the ground vias with respect to the signal via is visible. In fact, the full-wave
simulation for the structure when the distance between the signal and the
ground vias is 1.77 mm corresponds to the same distance of the ground vias
in the thin package. Approximately at 25 GHz, the transmission parameter S21
corresponding to the via geometry of Figure 5.10 presents the same notch
response than the thin package. This suggests that the ground vias
distribution in the thin package in addition to the dimensions of the parallel
planes is responsible for the resonance.
Also, the effect in the phase of the transmission parameter is
important; notice that the phase is not linear in the frequency range where the
notch effect is present. This is a problem because the non-linearity of any
microwave device yields distortion of the signals. In Figure 5.11, the
magnitude of the electric field distribution is shown for several configurations
of ground vias. As can be seen, when the ground vias are closer to each
127
other, the electric field has as boundary condition a quasi-PEC yielding better
transmission characteristics.
Figure 5.11 Effect of varying the location of the ground vias in the S-
parameters of the via: a) magnitude of S11, b) magnitude of S21, c) phase of S11, and d) phase of S21
Figure 5.12 Magnitude of the electric field at 20 GHz for several distances: 1.97 mm, b) 1.77 mm, c) 1.37 mm, and d) 0.47 mm.
128
In accordance with the previous section, the origin of the notch effect
in the transmission parameters of the via is the high value of the driving point
impedance which includes the effect of the parallel plane impedance Zpp. As
can be noticed, the placement of the ground vias influences the frequency
point where the Zpp has a high-value. Thus, in order to confirm that the
parallel plane impedance has a high-value in the frequency point where exists
the notch response, this impedance needs to be determined. Unfortunately,
the determination of the parallel plane impedance for this case with closed
analytical formulas is not available in the literature.
5.3 Future Research Due to the fact that the calculation of the driving point impedance for a via is
not available in closed form equations when the ground vias distribution is
complex (e.g., that in the thin package), as a first approach, an experimental
characterization method to determine Zpp is necessary. Although the
verification of the influence of the Zpp in the transmission characteristics
presented in [106] has been carried out with correlations to measurements,
an experimental characterization methodology has not been developed yet.
In the next section a brief description about the challenges in the
development of an experimental characterization method is presented.
5.3.1 Challenges in the Development of a PPM Experimental
Characterization Methodology.
In actual microwave experimental characterization processes, the use of test
fixtures to feed the DUT are indispensable in order to allow the
measurements. As it was presented in Chapter II, there are de-embedding
techniques to remove the undesirable effects. In the case of the
129
measurements performed to a via structure, the use of transmission line-
based test fixtures is required to feed the structure, and the de-embedding
process may become difficult. Additionally, the use of a model for developing
an analytical process to determine Zpp from measurements is required. A brief
overview of all these problems is elaborated hereafter.
A typical via discontinuity is usually characterized by two important
types of propagation: a horizontal propagation over transmission lines which
feed the via and a vertical propagation over the via barrel (exciting parallel
plane modes between two solid metal layers). In Figure 5.13, a via structure
fed by striplines is shown. As can be seen, the horizontal propagation is
supported by striplines and the horizontal ones by the via.
Figure 5.13 Via fed by striplines.
Hence, to develop an analytical characterization process, a model is
required in order to associate measurements to elements of a circuit such as
capacitors, inductors, transmission lines, etc. With this purpose, the
equivalent circuit topology reported in [114] can be used. This equivalent
circuit is based on the RLC π topology in which the effect of the parallel
planes is included by means of a current-dependent voltage source (see
Figure 5.14). In consequence, this circuit topology combines the first type of
propagation (TEM or quasi-TEM) with the PPM propagation in order to obtain
a physically based model.
f
v
d
a
e
130
Figure 5
Then
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.14 Equival
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uivalent cir
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used by th
5.14.
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valent circuure 5.12
med to the
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mployed to a
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ysical geom
sion line mo
ivalent circ
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associate t
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roposed. F
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13
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For
ed
131
data to the circuit elements and thus determine the experimental data
corresponding to Zpp. Unfortunately, the inclusion of the test fixtures in the
model results in complex equations which do not allow the easy
determination of Zpp. Therefore, in order to develop a straightforward and
simple analytical method, removing these test fixture effects is necessary. A
more detailed analysis of the proposed equivalent circuit for the structure of
the Figure 5.13 shows that PPM must also be included in the models for the
striplines because part of the via barrel is inside the two layers which support
the horizontal propagation. This situation is depicted in the Figure 5.16.
Figure 5.16 Inclusion of PPM to the transmission lines models for the
structure of the Fig. 5.13.
Striplines support horizontal propagation in a TEM fashion; in
consequence, the inclusion of the PPM propagation will affect the
characteristic of these transmission lines. As can be seen, this is a major
problem because the de-embedding of the effects caused by the striplines
cannot be carried out in a traditional way. If the traditional de-embedding
process is to be applied, the characterization of the striplines (and in general
132
any test fixtures used to feed the via transition) must be carried out including
the PPM component. Thus, future research about the solution of this problem
will be performed in order to achieve a straightforward and simple analytical
characterization method. Although there are many problems associated with
the development of the analytical method for extracting the parallel plane
impedance, fortunately there are some advances that can be useful. For
example, in [115] the authors present a semi-analytical approach for
modeling the electrical performance of complex electronic packages with
multiple power/ground planes and large number of vias. This method is based
on the modal expansion technique and the method of moments. Inside the
package there are multiple power/ ground planes and many vias. Thus, the
modal expansion method is employed to compute the electromagnetic fields,
which allow the determination of the multiport network parameters, e.g., the
admittance matrix. Additionally, in [116] the simulation of via interconnects in
multilayered printed circuit boards and packages, combining physically based
via models and microwave network theory is discussed. In this paper, the
description of the via in terms of network parameters, partitioning the complex
interconnection, and using a combination of partial results is addressed in
order to obtain accurate simulations. Of course, the model associated with
the vertical transition includes PPM effects. All mentioned works could be
helpful to develop a PPM experimental characterization methodology. When
this aim is reached, the information about the impact of PPM in the
performance of electronic packages will play a major role in the package’s
optimization.
5.4 CONCLUSIONS In this chapter, preliminary results about the root causes of a resonance in
the thin package have been presented. Also, the PPM propagation in the
inner layer of the thin package was investigated. It was pointed out that the
133
complex structures associated with the internal distribution of ground vias in
the package, do not allow for a straightforward analysis. In consequence, a
parametric study about the impact of the distribution of the ground vias on the
performance of the thin package was carried out. In accordance with this
study, the placement of the ground vias affects the performance of the
vertical transition.
Additionally, the challenges in the development of an experimental
characterization technique to determine the PPM impedance were discussed.
Thus, in order to overcome several problems about characterization,
modeling, and optimization of complex electronic packages the availability of
the previous mentioned characterization technique in a near future is
necessary.
135
CHAPTER VI
General Conclusions
A detailed study about current chip-to-chip interconnection channels on PCB,
and the most important limiting factors at high-frequencies has been
presented in this thesis. Within this study, novel electrical characterization
and modeling techniques for IC packages and interconnects have been
presented in order to perform an accurate electrical characterization of
interconnects and IC packages. As it was mentioned throughout this thesis,
the accurate characterization and modeling of a package plays an essential
role in the design and development of high-frequency and miniaturized
electronic systems. Therefore, in Chapter III a new de-embedding technique
to characterize electrical transition was developed and a modified equivalent
circuit to model CPW-M transition was proposed. This method is simple,
analytical, based on measurements and allows the direct determination of the
experimental ABCD matrix associated with the transitions used to excite
transmission lines. In Chapter IV, a characterization process to extract the S-
parameter models of the sections composing a complete channel was
described, whereas in Chapter V, a discussion about the challenges for
characterizing a thin package was presented. Thus, the contributions of this
thesis can be summarized in the next points:
1. A methodology based on S-parameter measurements and TRL
calibration technique has been described to characterize a complete
channel in a sectional way, i.e., the electrical model of a complete
channel was partitioned in elemental blocks which are related to
electrical transitions. The determination of the S-parameter model
associated with the main blocks (packages, transmission lines and
other transitions) was performed using TRL calibration technique and
136
the accuracy of this process was verified with frequency and time-
domain correlations to measurements. Although the methodology uses
frequency-domain measurements, TDR was useful in the development
of the cascade model and also in the verification of the accuracy of the
methodology.
2. By application of the previous mentioned characterization
methodology, the S-parameter model associated with a prototype
package was determined, which allows the corresponding assessment
of the package’s performance. Thus, the identification of the packages
as the critical components in a chip-to-chip interconnection channel
was carried out. Additionally, it was shown that the thin package
technology is not necessarily better that thick technology despite thin
technology uses shorter core vias. Moreover, the thin package
presents adverse effects in the transmission parameters (notch
response), suggesting that there is not a simple trade-off between
performance and size in the design of packages (the original idea
about the thin package is that it should be better that thick package
because it has less losses).
3. It was shown that equivalent circuit modeling of a complete channel is
possible and accurate. In Chapter IV, an equivalent circuit topology for
a thick package was proposed based on π-RLC network topology. The
proposed topology represents accurately the thick package up to 30
GHz.
4. Although an equivalent circuit topology was proposed for the thick
package, this topology is not adequate for the thin package because
there are parasitic propagation modes. In consequence, research
about the origin of excitation of parasitic modes was carried out using
137
full-wave simulations. The results indicate that the parallel plane
environment of the package structures influences their performance,
(i.e., it was found that these parallel plane modes are scattered from
surrounding signal/ground vias and board edges which greatly
influence the package performance). It is pointed out that the adverse
effects in the packages are the excitation of parasitic modes such as
PPM. Thus, optimizing the structure by inspecting some figures-of-
merit associated with the package (for example the return losses) may
not be enough to guarantee that the overall performance of the
package will be better.
5. As a result of the previous point, future research is proposed to
overcome the problems in the packages. Thus, in the near future new
guidelines to reduce or suppress the effects of PPMs will be
developed.
List of Publications
• Gaudencio Hernández-Sosa, Reydezel Torres-Torres, Gerardo Romo,
“Characterization and Modeling of Electronic Packages Using S-Parameters,”
IEEE 8th International Caribbean Conference on Devices, Circuits and Systems
(ICCDCS), Cancun, Mexico, April 2008.
• Reydezel Torres-Torres, Gaudencio Hernández-Sosa, Gerardo Romo and Adán
Sánchez, “Characterization of Electrical Transitions Using Transmission Line Measurements,” Article accepted for publication in Transactions on Advanced
Packaging.
• Gaudencio Hernández-Sosa, Reydezel Torres-Torres, Gerardo Romo, “CPW-Microstrip Transition Optimization Using Equivalent Circuit Approach” Article
under writing, to be submitted to Transactions on Advanced Packaging.
139
Appendix A A.1 LAYOUT OF THE MICROSTRIP LINE The detailed layout of the microstrip lines used in the characterization
process described in Chapter III, Section 3.3 is shown in Figure A.1. The
corresponding parameters are shown in the Table A.1.
Figure A.1 Detailed view of the layout associated with the CPW-M transition.
Parameter Value Description
L 282, 335 mils Physical length of microstrip line
W1 7.2 mils Width of a microstrip line
W2 3 mils Width of the signal pad
G 6 mils Separation from ground pads
LG1 26 mils Ground pad length in Y
LG2 13 mils Ground pad length in X
RG 2 mils Ground via radius
H 40 mils Substrate height
Table A.1 Values for the parameters shown in Figure A.1.
X
y
140
A.2 DERIVATION OF ABCD-PARAMETER OF THE EQUIVALENT CIRCUIT TOPOLOGY ASSOCIATED WITH THE CPW-M TRANSITION
The ABCD matrix associated with the two-port equivalent circuit topology of
the Fig. 3.23 is given as:
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
+
+++=⎥
⎦
⎤⎢⎣
⎡
3
2
3
3
2121
3
1
11
1
ZZ
Z
ZZZZZ
ZZ
εδβα
(A.1)
where
peq RLjZ += ω1 (A.2)
mLjZ ω=2 (A.3)
cs
RCj
Z +=ω1
3 (A.4)
The parameters in the left side of the equation (A.1) can be written in terms of
the elements of the equivalent circuit (right side). Thus, substituting equations
(A.2), (A.3) and (A.4), the parameter α can be written as:
( )cs
pseqs
cs
peq
RCjRCjLC
RCj
RLjω
ωω
ω
ωα
++−
+=
⎟⎟⎠
⎞⎜⎜⎝
⎛+
++=
11
11
2
(A.5)
In order to separate the real and imaginary parts of the equation (A.5), this
equation can be multiplied by the corresponding complex conjugate
denominator term (equation A.6). Thus in the equation (A.7) the real and
imaginary parts are obtained.
cs
cs
cs
pseqs
RCjRCj
RCjRCjLC
Aωω
ωωω
−−
⋅+
+−+=
11
11
2
(A.6)
141
222
23
222
22
111
cs
psceqs
cs
eqscps
RCRCjRLCj
RCLCRRC
Aω
ωωω
ωω+
++
+−
+= (A.7)
Separating the terms of the equation (A.7) in the real and imaginary parts, the
corresponding expressions by these parts are:
{ } 222
22
11Re
cs
eqscps
RCLCRRC
ωωω
α+
−+= { } 222
23
1Im
cs
psceqs
RCRCRLC
ωωω
α+
+= (A.8)
In a similar fashion, the parameter β is obtained. Thus, the parameters β is
given by the equation (A.9) in terms of the Leq, Rp and Lm as:
( )( )
⎟⎟⎠
⎞⎜⎜⎝
⎛+
++++=
cs
mpeqmpeq
RCj
LjRLjLjRLj
ω
ωωωωβ
1 (A.9)
In this case an equivalent inductance is defined in order to simplify the
equations. The equivalent inductance is defined by the following equation:
meqX LLL += (A.10)
Making several operations, the result is shown in the next equation:
cs
meqspmspX RCj
LLCjRLCRLj
ωωω
ωβ+
−−++=
1
32
(A.11)
Similarly to the parameter α, separation process of the real and imaginary
parts are depicted in the equations (A.12) and (A.13) and finally the results
are shown in the equation (A.15).
142
cs
ps
cs
meqspmspX RCj
RCjRCj
LLCjRLCRLj
ωω
ωωω
ωβ−−
⋅+
−−++=
11
1
32
(A.12)
222
323
222
224
11 cs
meqscpmsX
cs
pmscmeqsp RC
LLCjRRLCjLj
RCRLCRLLC
Rω
ωωω
ωωω
β+
−++
+−−
+= (A.13)
{ } 222
224
1Re
cs
pmscmeqsp RC
RLCRLLCR
ωωω
β+
−−+=
{ } 222
323
1Im
cs
meqscpmsX RC
LLCRRLCL
ωωω
ωβ+
−+=
.14)
The next parameter derivation is shown in the equations (A.15) – (A.18). As
can be seen the same process is applied: the equation (A.16) is multiplied by
the corresponding complex conjugate denominator term in order to determine
the corresponding real and imaginary part (A.18)
⎟⎟⎠
⎞⎜⎜⎝
⎛+
=
cs
RCjω
δ1
1 (A.15)
cs
cs
cs
s
RCjRCj
RCjCj
ωω
ωωδ
−−
⋅+
=11
1 (A.16)
222
22
1 cs
scs
RCCjRC
ωωωδ
++
= (A.17)
{ } 222
22
1Re
cs
cs
RCRC
ωωδ+
= { } 2221Im
cs
s
RCC
ωωδ
+= (A.18)
Finally, the derivation of the real and imaginary part corresponding to the
parameter ε is shown is the next set of equations. As can be noticed, the last
equations relate the imaginary and real parts with the lumped elements of the
equivalent circuit topology.
143
cs
ms
cs
m
RCjLC
RCj
Ljω
ω
ω
ωε+−
+=
⎟⎟⎠
⎞⎜⎜⎝
⎛+
+=1
11
12
(A.19)
cs
cs
cs
ms
RCjRCj
RCjLC
ωω
ωωε
−−
⋅+−
+=11
11 1
2
(A.20)
222
23
222
2
111
cs
cms
cs
ms
RCRLCj
RCLC
ωω
ωωε
++
+−
+= (A.21)
{ } 222
2
11Re
cs
ms
RCLC
ωωε+
−= { } 222
23
1Im
cs
cms
RCRLC
ωωε+
= (A.22)
145
List of Figures 1.1 Interconnection levels in a generic electronic product…………………1
1.2 IC package history and trends…………………………………………….6
1.3 Microstrip and CPW lines with their corresponding electromagnetic
field pattern………………………………………………………………….8
1.4 Through-hole, blind and buried via………………………………………9
1.5 Solder bump serving as an electrical interface between an IC and the
package…………………………………………………………………….11
1.6 Simplified cross-sectional view of a typical chip-to-chip interconnection
channel……………………………………………………………………..12
1.7 Expected CPU interface and memory bandwidth……………………..13
1.8 High-speed interconnection effects……………………………………..15
2.1 An arbitrary N-port network……………………………………………….21
2.2 Common terms for high-frequency characterization...………………..25
2.3 Forward and reverse S-parameters for a two-port DUT………………26
2.4 Voltage waveform after traveling from the input to point X in an
infinitely transmission line..……………………………………………….28
2.5 Transmission line terminated with different impedance to Z0…………29
2.6 Functional block diagram for a TDR………………………………….....30
2.7 Capacitive and inductive discontinuities calculated from TDR
waveforms………………………………………………………………….31
2.8 Setup for performing high-frequency/high-speed measurements….32
2.9 Shifting of the measurement reference plane through a calibration
process……………………………………………………………………..33
2.10 Shifting of the reference plane after the de-embedding process…...35
2.11 Model for the CPW – M transition in [76]……………………………….42
2.12 Capacitance and inductance determination…………………………..43
146
3.1 Cascade model for a transmission line embedded between two
electrical discontinuities….……………………………………………….52
3.2 T-network used to represent a reciprocal device………………………58
3.3 Layout of a microstrip line terminated with CPW-M transitions……...59
3.4 Simplified sketch showing the reference plane for the experimental S-
parameters once the VNA has been calibrated with the LRM
procedure…………………………………………………………………..60
3.5 Complex propagation of MS: a) attenuation and b) phase delay…....62
3.6 Characteristic impedance of MS: a) real part and b) imaginary part...62
3.7 Real and imaginary parts obtained for a) α and b) β…………………..63
3.8 Real and imaginary parts obtained for a) δ and b) ε…………………..63
3.9 Implementation of the block model of Figure 3.1 in ADS…………….65
3.10 Frequency-domain correlation for the block diagram a) Magnitude of
S11, b) magnitude of S21, c) phase of S11, d) phase of S21…………….66
3.11 Time-domain correlation for the block diagram of the Figure 3.1…….66
3.12 Modified equivalent circuit topology based on [94]…………………….67
3.13 Lumped circuit elements associated with a 3D CPW-M structure (the
mutual inductance between the signal pad and the ground vias is not
shown)……………………………………………………………………...68
3.14 Frequency-domain correlations of full-wave simulations to
measurement: a) Magnitude of S11, b) phase of S11, c) magnitude of
S21, and d) phase of S21…………………………………………………..69
3.15 Time-domain correlation of full-wave simulations to measurement….69
3.16 3-D plot of the E-Field showing the electric coupling between the signal and ground pads at 40 GHz………………………………………………70
3.17 2-D plot of the E-Field showing the electric coupling between signal pad and ground plane at 40 GHz………………………………………..70
3.18 3-D plot of the E-Field showing the electric coupling between signal pad and ground vias at 40 GHz………………………………………….71
3.19 3-D plot of the E-Field showing the magnetic coupling between signal pad and the lateral ground vias at 40 GHz……………………………..73
147
3.20 3-D plot of the E-Field showing the magnetic coupling between the signal pad and the ground vias behind at 40 GHz……………………..73
3.21 3-D plot of the H-field in the width-step from de signal pad to the microstrip line at 40 GHz………………………………………………….74
3.22 Equivalent circuit topology including Rp in the signal pad loop……….76
3.23 Two-port equivalent circuit topology derived from the topology shown
in Fig. 3.22………………………………………………………………….77
3.24 T network model for CPW-M transition………………………………….78
3.25 Equivalent circuit topology seen as a T-model…………………………78
3.26 csRC product up to 40 GHz………………………………………………..81
3.27 Regression of the experimental data to obtain the reactive elements of
the equivalent circuit topology.............................................................83
3.28 Regression of experimental data to obtain the frequency-dependent
resistive elements of the equivalent circuit topology...........................83
3.29 Block cascade model implemented in ADS corresponding to the model
shown in Figure 3.1……………………………………………………....85
3.30 Frequency-domain correlation for the block diagram in Figure 3.27: a) Magnitude of S11, b) magnitude of S21, c) phase of S11, and d) phase of S21…………………………………………………………………………...86
3.31 Time-domain correlation for the block diagram in Figure 3.1…………86
4.1 a) Top-view and b) simplified cross-sectional view of the prototype
channel……………………………………………………………………..90
4.2 Internal structure of the prototype package (metal and dielectric layers
are not shown)……………………………………………………………..91
4.3 Vertical transitions inside the thick package…………………………....92
4.4 Vertical transitions inside the thin package…………………………….93
4.5 Measured S-parameters for a 1 in-thick channel: a) Magnitude of S11
and S22, b) magnitude of S12 and S21, c)phase of S11 and S22, d) phase
of S12 and S21………………………………………………………………94
148
4.6 Measured S-Parameters for a 1in-thin channel: a) Magnitude of S11
and S22, b) magnitude of S12 and S21, c) phase of S11 and S22, d)
phase of S12 and S21………………………………………………………95
4.7 Time-domain impedance profile for a 3 in-thick channel showing the
components associated with each variation in the curve……………..95
4.8 Time-domain impedance profile for a 3 in-thin channel showing the
components associated with each variation in the curve………….…96
4.9 Proposed cascade model for the entire channel………………………97
4.10 PTM interconnection structure…………………………………………...98
4.11 Cascade model for the PTM structure………………………………..…99
4.12 Set of dummy structures for characterizing the microstrip test
fixture………………………………………………………………………100
4.13 S-parameters of the thick-PTM structure before and after de-
embedding the effect of the test fixtures A and B…………………….102
4.14 S-parameters of the thin-PTM structure before and after de-embedding
the effect of the test fixtures A and B…………………………………..102
4.15 De-embedded S-parameters for the thick package: a) magnitude of S11
and S22 b) magnitude of S12 and S21, c) phase of S11 and S22, d) phase
of S12 and S21……………………………………………………………..103
4.16 De-embedded S-parameters for the thin package: a) magnitude of S11
and S22 b) magnitude of S12 and S21, c) phase of S11 and S22, d) phase
of S12 and S21……………………………………………………………..103
4.17 Frequency-domain correlation for a 3 in-thick channel: a) magnitude of
S11 b) magnitude of S21, c) phase of S11, d) phase of S21……………105
4.18 Frequency-domain correlation for a 3 in-thin channel: a) magnitude of
S11 b) magnitude of S21, c) phase of S11, d) phase of S21……………106
4.19 Time-domain correlation for: a) 3 in-thick channel and b) 3 in-thin
channel……………………………………………………………………107
4.20 Via package surrounded by ground planes…………………………..109
4.21 Simple П-type RLC equivalent circuit model for a via………………..110
149
4.22 Proposed equivalent circuit topology for the thick package…………111
4.23 Model optimization using ADS Test Lab Simulation Controller…….111
4.24 Equivalent circuit of the entire channel implemented in ADS………112
4.25 Equivalent circuit for the thick package………………………………..113
4.26 Frequency-domain correlation for a 3 in-thick channel: a) magnitude of
S11 magnitude of S21, c) phase of S11, d) phase of S21………………113
4.27 Time-domain correlation for the 3 in-thick channel………………….114
5.1 Effect in a propagated signal throughout notch response channel…116
5.2 Notch response characteristic in transmission parameters for the thin
package…………………………………………………………………...117
5.3 Boundaries in the HFSS model for the thin package……………….118
5.4 Geometry used for full-wave simulations of the thin package……..118
5.5 Frequency-domain correlations to measurements of the simulated 3D
model shown in Figure 5.4…………………………………………..….119
5.6 Electric field distributions at 25.5 GHz: a) 0°, b) 15°, c) 25°, d) 45°, e)
65°, and f) 85° degrees………………………………………………….120
5.7 Excitation of PPM in a via transition between two layers……………121
5.8 Coordinate system and geometric features in PEC and PMC
configuration [106]……………………………………………………….124
5.9 Coordinate system and geometric features in PML configuration
[106]……………………………………………………………………….124
5.10 Via geometry under investigation……………………………………...126
5.11 Effect of varying the location of the ground vias in the S-parameters of
the via: a) magnitude of S11, b) magnitude of S21, c) phase of S11, and
d) phase of S21……………………………………………………………127
5.12 Magnitude of the electric field at 20 GHz for several distances: 1.97
mm, b) 1.77 mm, c) 1.37 mm, and d) 0.47 mm……………………….127
5.13 Via fed by striplines………………………………………………………129
5.14 Equivalent circuit topology of a via including the PPM effects……..130
150
5.15 Distribution of the equivalent circuit elements within the structure of
Figure 5.12………………………………………………………………..130
5.16 Inclusion of PPM to the transmission lines models for the structure of
the Fig. 5.13………………………………………………………………131
List of Tables 1.1 Description of EMP’s interconnection levels……………………………..3
2.1 Summary of typical S-parameter measurement-based model extraction
methods…………………………………………………………………….44
3.1 Specifications for the microstrip lines……………………………………60
3.2 Extracted values for the equivalent circuit model for CPW-M
transition……………………………………………………………………84
151
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