Chapter5: Synchronous Sequential Logic – Part 3

Originally Wafa Alrajhi

Imam Muhammad Bin Saud University

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Outline

State reduction.

State assignment.

Design procedure Design with D FF. Design with JK FF. Design with T FF.

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State Reduction

This section discusses certain properties of sequential circuits

that may be used to reduce the number of gates and flip-flops

during the design

State reduction: The reduction of the number of flip-flops in a

sequential circuit is referred to as the state-reduction problem

State-reduction algorithms are concerned with procedures for

reducing the number of states in a state table, while keeping

the external input-output requirements unchanged

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State Reduction (Cont.)

We explain with a sequential circuit whose state diagram is

given in the next slide

Here, only input-output sequence is important, not the internal

states

The states are denoted by letters

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State Reduction (Cont.)

Consider the input sequence 01010110100 starting from the initial state a

With the circuit in initial state a, an

input of 0 produces an output of 0

and the circuit remains in state a In state a with input of 1, the output

is 0 and the next state is b. With present state b with input of 0,

the output is 0 and the next state is c, Continue…

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State Reduction (Cont.)

Consider the input sequence 01010110100

starting from the initial state a.

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State Reduction (Cont.)

State reduction means to reduce the

number of states in a sequential circuit

with an identical input-output

relationship

The easiest way of state reduction is

through state table as follows:

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State Reduction (Cont.)

Algorithm: Two states are equivalent if for identical inputs

they give exactly the same output and result in a transition to

the same state (or an equivalent state).

If two states are equivalent, one of them can be removed

without changing the input-output operation of the circuit.

We have to find a pair of equivalent states and delete one.

States g and e are equivalent and we can delete g and replace it

with e.

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State Reduction (Cont.)

Reducing the state table is shown below:

Now we can see that d and f also have similar rows associated

with them.

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State Reduction (Cont.)

State f can be removed and replaced by d

Reduced state table is shown below:

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State Reduction (Cont.)

Reducing the number of states does not necessarily mean a

circuit with fewer gates and/or flip-flops.

Note that state reduction in general may lead to a circuit with

more gates than the original system (for the combinational

circuit which provides inputs to the flip-flops)

For the above reduced diagram and the input sequence that

was given before, we have:

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State Reduction (Cont.)

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State Reduction (Cont.)

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State Assignment

In order to design a sequential circuit with physical components, it

is necessary to assign coded binary values to the states

For a circuit with m states, the codes must contain n bits where 2n

>=m.

For example, with three bits it is possible to assign codes to eight

states denoted by binary numbers 000 to 111

Whatever state table is used, first states are assigned sequentially,

remaining states are kept unused (don’t care conditions)

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State Assignment

Three possible binary state assignments

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State Assignment

Using binary assignment 1, the previous simplified state table

will be:

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Design Procedure

It specifies the hardware that will implement a desired behavior.

Given: Set of specifications.

Goal: Find logic diagram.

Input and output equations provide the necessary information to draw the logic diagram of

SC.

Steps: 1. Derive a state diagram from the word description.

2. Obtain the binary-coded state table.

3. Choose the type of FF to be used.

4. Derive the simplified FF input equations and output equations.

5. Draw the logic diagram.

Example

Design a sequential circuit that detect a sequence of three or more consecutive ones in a string of bits coming through an input line. Use D FF. 1. Derive state diagram from specification

00/0

10/011/1

01/0

0

0

0

0

1

1

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Design with D FF

2. Obtain the binary coded state table.

3. Choose type of FF

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Design with D FF

4. Derive the simplified FF input equations.

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Design with D FF

5. Draw logic diagram.

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Excitation Table

Design with other types of flip-flops is not straightforward as

the next state cannot directly be related to the input equations

In such cases we should use excitation tables, which list the

required input for a given change of state

Next slide shows excitation tables for JK & T Flip-Flops

The symbol X represents a don’t care condition

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Excitation Table (Cont.)

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Excitation Table (Cont.)

Consider the sequential circuit given by the following table:

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Design with JK FF

Assume that it is desired to design this sequential circuit using

JK flip-flops

Using excitation table of JK FF, we have:

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Design with JK FF (Cont.)

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Design with JK FF (Cont.)

The logic diagram can be obtained from the input equations

given above

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Design with T FF

Example: Consider a 3-bit

binary counter shown in the

diagram:

In fact the only input to the

circuit is the clock and the

output is the present state of

the flip-flops.

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Design with T FF

The state

table for this

example is as

follows:

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Design with T FF

The most efficient way to construct a binary counter is by

using T flip-flops, because of their complement property.

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Design with T FF

Logic diagram of the counter:

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Reading

5.1

5.2

5.3

5.4

5.5

5.8