chapter 9 optimizing power @ standby – memoryee.sut.ac.ir/people/courses/167/09.pdf · fly curves...

Chapter 9

Optimizing Power @ Standby – Memory

Benton H. CalhounJan M. Rabaey

Optimizing Power @ Standby

Memory

Slide 9.1This chapter describesapproaches for optimizingthe power consumption ofan embedded memory,when in standby mode. Asmentioned in Chapter 7,the power dissipation ofmemories is, in general,only a fraction of the over-all power budget of adesign in active mode. Thereverse is true when the cir-

cuit is in standby. Owing to the large (and growing) number of memory cells on a typical IC, theircontribution to the leakage power is substantial, if not dominant. Reducing the standby powerdissipation of memories is hence essential.

Chapter Outline

Memory in StandbyVoltage ScalingBody BiasingPeriphery

Slide 9.2In this Chapter, we firstdiscuss why the standbyleakage current of largeembedded SRAM mem-ories is becoming a growingconcern. When looking atthe possible solutionspace, it becomes clearthat static power in thememory core is best con-tained by manipulating thevarious voltages in andaround the cell. One option

is to reduce the supply voltage(s); another is to change the transistor bias voltages. Variouscombinations of these two can be considered as well. Bear in mind however that any realisticleakage power reduction techniquemust ensure that the data is reliably retained during the standby

J. Rabaey, Low Power Design Essentials, Series on Integrated Circuits and Systems,DOI 10.1007/978-0-387-71713-5_9, � Springer ScienceþBusiness Media, LLC 2009

233

period. Though the periphery presents somewhat of a lesser challenge, it has some special char-acteristics that are worth-examining. The Chapter is concluded with some global observations.

Memory Dominates Processor Area

SRAM is a major source of static power in ICs, especially for low-power applicationsSpecial memory requirement: need to retain state in standbyMetrics for standby: – 1. Leakage power – 2. Energy overhead for entering/leaving standby– 3. Timing/area overhead

BL BLWL

M1M2

M3

M4M5

M6Q

QB

Slide 9.3During standby mode, anembedded memory is notaccessed, so its inputs andoutputs are not changing.The main function of thememory during standby istherefore to retain its datauntil the next transition toactive operation. Theretention requirement com-plicates the reduction of theleakage power. Althoughcombinational logic mod-ules can be disconnectedfrom the supply rails usingpower gating, or their sup-ply voltages reduced to

zero, this is not an option for the embedded SRAM (unless it is a scratch-pad memory). Hence,minimizing the leakage, while reliably maintaining state, is the predominant requirement. Some ofthe techniques that are introduced in this chapter carry some overhead in terms of power and/ortime to bring a memory in to and/or out of standby. A secondary metric is hence the energyoverhead consumed during the transition, which is important because it determines the minimumtime that should be spent in standby mode for the transition to be worthwhile. If the power savingsfrom being in standby for some time do not offset the overhead of entering/leaving that mode, thenstandby should not be used. In addition, rapid transitions between standby and active modes arehelpful in many applications. Finally, we also observe that reducing standby power often comeswith an area overhead.

We begin this chapter by taking a brief top-level look at the operation of an embedded SRAMcell during standby. Next, we examine a number of standby power reduction techniques. The mosteffective techniques to date are based on voltage manipulation – either lowering the supply voltage,or increasing the bias voltages of the transistors inside the cell. The standby power of the peripheralcircuits is briefly discussed before the chapter is summarized.

234 Chapter #9

Reminder of “Design-Time” Leakage Reduction

Design-time techniques (Chapter 7) also impact leakage – High- VTH transistors– Different precharge voltages– Floating BLs

This chapter: adaptive methods that uniquely address memory standby power

Slide 9.4Some of the approachesdescribed in Chapter 7 forlowering power at designtime reduce leakage powerin both active and standbymodes. These approachesinclude using high-thresh-old-voltage transistors,lowering the precharge vol-tage, or allowing bitlines tofloat (they float to a voltagethat minimizes leakage intothe bitcells. Though theseapproaches do affect the

leakage power during standby, this chapter focuses on approaches that uniquely address thestandby leakage.

The Voltage Knobs

Changing internal voltages has different impact on leakage of various transistors in cellVoltage changes accomplished by playing tricks with peripheral circuits

Offset voltage, δ (V)

Leak

age

redu

ctio

n (r

atio

)

1

10

10

10

10

0 0.2 0.4 0.6 0.8

DD

DD

TH

TH

1.010

L = 90 nm, T = 2 nmVDD = 1 VS = 100 mV/decadeK = 0.2 V1/2, 2 = 0.6 V

= 0.05

V

0

0

-

V

0

0

- δ

V

+

0

V δ

δ ψψ

ψ

δ

λ

δ

δ

-

0

0

0(DIBL)

NMOS

V

00

+

C

B1

B2

A1

A2

− δ≅ΔV

)22( −+≅Δ kV

DD

DDDD

[Ref: Y. Nakagome, IBM’03]

Slide 9.5Though there are manycircuit-level knobs avail-able for addressing leakagepower, the various voltagelevels in and around the bit-cell are the most effective.In Chapter 7, we discussedhow these voltages can beassigned at design time toreduce power. Altering thevoltages by manipulatingthe peripheral circuits dur-ing standby mode candecrease leakage powerduring standby mode.There is more flexibility to

alter the voltages in standbymode because many of the functionality-limiting metrics are no longerrelevant, such as read static noise margin and write margin. In standby mode, the primaryfunctionality metric of concern is the hold static noise margin, as the bit-cells are only holdingtheir data.

Slide 9.6The most straightforward voltage scaling approach to lowering standby leakage power in amemory is reducing the supply voltage, VDD. This approach lowers power in two ways: (1) voltagereduction (P= VI) and (2) leakage current reduction. The dominant mechanism behind the latteris the drain-induced barrier lowering (DIBL) effect. In addition, other contributors to leakagecurrent drop off as well. Gate-induced drain leakage (GIDL) quickly decreases with VDD, and

Optimizing Power @ Standby – Memory 235

gate-tunneling currentdecreases roughly as VDD.Junction leakage currentsat the source and drain ofthe transistors also decreaserapidly with VDD.One approach to imple-

menting standby voltagescaling is to switch to alower supply voltage usingPMOS header switches, asshown in the slide. Thestandby, or drowsy, supplyprovides a lower voltage toreduce leakage only forSRAM blocks that are instandby mode. During

active mode, the power supply returns to the nominal operating voltage. As we have describedbefore, the key limitation to the extent by whichVDD is lowered is that the data inside the cells mustbe protected. If the data are no longer required, then the power supply can simply be disconnectedusing power gating approaches like those that were described earlier for combinational logic, or byramping the supply down to GND.

Limits to VDD Scaling: DRV

Data Retention Voltage (DRV): Voltage below which a bit-cell loses its data

That is, the supply voltage at which the Static Noise Margin (SNM) of the SRAM cell in standby mode reduces to zero.

0 0.1 0.2 0.3 0.40

0.1

0.2

0.3

0.4

V1 ( V)

V2

( V

)

VTC1

VTC2

VDD = 0.18 V

VDD = 0.4 V

130 nm CMOS

[Ref: H. Qin, ISQED’04]

Slide 9.7Given the effectiveness ofvoltage reduction in lower-ing the standby power ofan SRAM memory, theultimate question now ishow much the supply vol-tage can safely be reduced.We define the minimumsupply voltage for whichan SRAM bit-cell (or anSRAM array) retains itsdata as the Data RetentionVoltage (DRV).

The butterfly plots shownon this slide illustrate howthe noise margins of a 6Tcell (with its access transis-

tors turned off) collapse as the supply voltage is reduced. Due to the asymmetrical nature of a typicalcell (caused by the dimensioning of the cell transistors as well as by variations), the SNM of the cell isdetermined by the upper lobe of the butterfly plot. Once the supply voltage reaches 180mV, the SNMdrops to zero and the stored value is lost. The cell becomes monostable at that point. In a purelysymmetrical cell, the supply voltage could be lowered substantially more before the data is lost.

Lower VDD in Standby

Basic Idea: Lower VDD lowers leakage– sub-threshold leakage– GIDL– gate tunneling

Question: What sets the lower limit?

VDD VDDlow

VDD_SRAM

drowsy drowsy

SRAMSRAM

VDD

VDDH

VDDL

Active mode

Standby mode

Example

[Ref: K. Flautner, ISCA’02]

236 Chapter #9

We can therefore also specify the DRV as the voltage at which the SNM of a non-addressed cell(or cell array) drops to zero.

Power savings of DRV

0 0.2 0.4 0.6 0.8 10

10

20

30

40

50

60

Supply Voltage (V)

Leak

age

Cur

rent

(A

)

MeasuredDRV range

• More than 90% reduction in leakage power with 350 mV standby VDD (100 mV guard band).

Test chip in 130 nm CMOS technology with built-in voltage regulator

1.4 mm

1.4 mm

IP Module of 4 kB SRAM


Slide 9.8The advantages of scalingthe VDD during standbycan be quite significant. A0.13�m test chip showsover 90% reduction instandby leakage by loweringthe power supply to within100mV of the DRV. Thereduction in the DIBL effectis one of the most importantreasons behind this largedrop in leakage current.

Hence, it seems thatmini-mizing the DRV voltage ofa memory is an effectivemeans to further reductionsin standby leakage power.

DRV and Transistor Sizes

0 1 2 3140

150

160

170

180

190

Width Scaling Factor

DR

V(m

V)

MaMpMnModel

Where Ma, , Mp and Mn are the access transistor, PMOS pull-up, and NMOS pull-down, respectively [Ref: H. Qin, Jolpe’06]

Slide 9.9The DRV of a bit-celldepends upon a range ofparameters. Intuitively wecan see that the DRVwould be minimized if itsbutterfly curve would besymmetrical – that is, thatthe upper and lower lobesshould be of equal size.This is accomplished if thepull-up and pull-downnetworks (including theturned-off NMOS accesstransistors) are of equalstrength.

From this, it becomesclear that the DRV must

be a function of the sizes of transistors in the bit-cell. As the DRV voltage typically lies belowthe threshold voltage of the process, it means that all transistors operate in the sub-thresholdmode.Under these operational conditions, the standard (strong-inversion) rationing rules betweenNMOS and PMOS transistors do not apply. In strong inversion, NMOS transistors are typically2–3 times stronger than equal-sized PMOS devices owing to the higher electron mobility. In thesub-threshold region, the relative strength is determined by the leakage current parameter IS, thethreshold voltage VTH, and the sub-threshold slope factor n of the respective devices. In fact, sub-threshold PMOS transistors may be substantially stronger than their NMOS counterparts.


The influence of changing the respective transistor sizes on a generic 6T cell is shown in the slide.For this cell, increasing the size of the PMOS transistors has the largest impact on DRV. Given thestrong pull-down/weak pull-up approach in most of the generic cells, this is not unexpected.

Note: Though a symmetrical butterfly curve minimizes the DRV voltage, it is most likely not thebest choice from an active read/write perspective. SRAM memories provide fast read accessthrough precharged bitlines and strong NMOS discharge transistors. This leads automatically toan asymmetrical cell.

Impact of Process “Balance”

Stronger PMOS or NMOS (SP, SN) in sub-threshold lowers SNM even for typical cell

[Ref: J. Ryan, GLSVLSI’07]

Slide 9.10Any variation from thesymmetrical bit-cell causesa deterioration of theDRV. This is illustrated inthis slide where the impactof changing the relativestrengths of the sub-thresh-old transistors is shown.Both strong NMOS (SN)and strong PMOS (SP)transistors warp the butter-fly curves and reduce theSNM.

Impact of Process Variations on DRV

DRV Spatial Distribution

DRV histogram for 32 Kb SRAM

� DRV varies widely from cell tocell

� Most variations random withsome systematic effects (e.g.,module boundaries)

�DRV histogram has long tail

130 nm CMOS


100 200 300 4000

1000

2000

3000

4000

5000

6000

DRV (mV)

Slide 9.11Given the high sensitivityof the DRV to the relativestrengths of transistors, itshould be no surprise thatprocess variations have amajor impact on the mini-mal operational voltage ofan SRAM cell. Local varia-tions in channel length andthreshold voltages are themost important cause ofDRV degradation. This isbest demonstrated withsome experimental results.This plot shows a 3-D ren-dition of the DRV of a130 nm 32Kb SRAM

memory, with the x- and y-axis indicating the position of the cell in the array, and the z-axisdenoting the value of the DRV. Local transistor variations seem to cause the largest DRV changes.Especially threshold variations play a major role.

238 Chapter #9

The histogram of theDRVs shows a long tail, which means that only a few cells exhibit very highvalues of the DRV. This is bad news: the minimum operation voltage of a complete memory (thatis, the DRV of the complete memory) is determined by theDRV of the worst-case cell, padded withsome extra safety margin. This means that the DRV of this particular memory should be approxi-mately 450mV (with a 100mV safetymargin added), thoughmost of the cells operate perfectly welleven at 200mV.

Impact of Process Variations on DRV

DRV (mV)

Fre

qu

ency

50 100 150 200 250 300 350

45 nm tail90 nm tail

0

0.02

0.04

0.06

0.08

0.10

Other sources of variation:Global variations, data values, temperature (weak), bitline voltage (weak )

DRV distribution for 90 nm and 45 nm CMOS

©IEEE 2007

[Ref: J. Wang, CICC’07]

Slide 9.12A similar picture emergesfor memories implementedin the 90 nm and 45 nm (inthis particular case, a 5Kbmemory). Clearly, localvariations cause a DRVdistribution with a longtail toward higher DRVs,and the influence of localvariations increases withprocess technology scaling.

The DRV also dependson other factors (but lessstrongly so) such as globalvariations, the stored datavalues, temperature, andthe bitline voltage.

DRV Statistics for an Entire Memory

DRV distribution is neither normal nor log-normalCDF model of DRV distribution (FDRV(x ) = 1 – P(SNM < 0, VDD = x ))

Wor

st D

RV

(m

V)

Memory size σ

ModelNormalLog-normalMonte-Carlo

3 4 5 6 7 8100

350

300

250

200

150

© IEEE 2007

[Ref: J. Wang, ESSCIRC’07]

Slide 9.13Understanding the statisti-cal distribution of the DRVis a first and essential steptoward identifying whichcircuit techniques wouldbe most effective in lower-ing operational voltage andhence leakage. (This will bepainstakingly made clear inChapter 10, where we dis-cuss runtime power reduc-tion techniques).

Inspection of the DRVdistribution shows that itfollows neither a normalnor a log-normal model. Abetter match is presented

by the equation shown in the slide. The resulting model matches true Monte-Carlo simulationalong the DRV tail to 6� – which means that outliers can be predicted quite effectively. The


independent parameters of the model (�0 and �0 – the mean and variance of the SNM at a supplyvoltage V0) can be obtained from a small Monte-Carlo simulation (at VDD = V0) of the SNM inthe one lobe of the butterfly plot that is the most critical.

100 200 300 4000

1000

2000

3000

4000

5000

6000

DRV (mV)

Reducing the DRV

Chip DRV

1. Cell optimization2. ECC (Error-Correcting Codes)3. Cell optimization + ECC

Slide 9.14Building on the presentedanalysis of the DRV, itsparameters and its statis-tics, we can devise a num-ber of strategies to lower itsvalue. The first approach isto use optimization. Theavailable options areappropriate sizing of thetransistors to either bal-ance the cell or reduce theimpact of variations, care-ful selection of the body-biasing voltages (for thesame reasons), and/or play-ing with the peripheral vol-tages to compensate for

unbalancing leakage currents. The net effect is to shift the DRV histogram to the left. Mostimportantly, the worst-case value is also lowered as is indicated in green on the chart. Nothingever comes for free though – manipulating the DRV distribution means trading off some othermetric such as area or access time. The designer must therefore weigh the importance of DRV forlow-power standby mode with other design considerations.

A second approach is to lower the voltage below the worst-case value. This approach, which wewill call ‘‘better-than-worst-case’’ design in the next chapter, may potentially lead to errors. As thetail of the distribution is long, the number of failing cells will be relatively small. The addition ofsome redundancy in the form of error detection can help to capture and correct these rare errors.Error-correcting (ECC) strategies have been exploited for a long time in DRAM as well as in non-volatile memories, but are not a common practice in embedded SRAMs. The potential benefits inleakage reduction and overall robustness are worth the extra overhead. From a DRV perspective,the impact of ECC is to lob off the tail of DRV distribution (as indicated in red).

Naturally, both cell optimization and ECC can be applied in concert resulting in a DRV with alower mean and narrower distribution (indicated in blue).

240 Chapter #9

Lowering the DRV Using ECC

Error Correction Challenges

Maximize correction rateMinimize timing overhead Minimize area overhead

Hamming [31, 26, 3] achieves 33% power saving

Reed-Muller [256, 219, 8] achieves 35% power saving

Hamming [31, 26, 3] achieves 33% power saving

Reed–Muller [256, 219, 8] achieves 35% power saving

Write

Read

ECCEncoder

ECCEncoder

ECCDecoder

ECCDecoder

Data In

Data Out

D P

Dat

a C

orre

ctio

n[Ref: A. Kumar, ISCAS’07]

Slide 9.15ECCs have been used inmemories for a long time.Already in the 1970s, ECChad been proposed as ameans to improve the yieldof DRAMs. Similarly,error correction is exten-sively used in Flash mem-ories to extend the numberof write cycles. As indi-cated in the previous slides,another use of ECC is toenable ‘‘better-than-worstcase’’, and lower the supplyvoltage during standbymore aggressively.

The basic conceptbehind error detection and correction is to add some redundancy to the information stored. Forinstance, in a Hamming (31, 26) code, five extra parity bits are added to the original 26 data bits,which allows for the correction of one erroneous bit (or the detection of two simultaneous errors).The incurred overhead in terms of extra storage is approximately 20%. Encoder and decoder unitsare needed as well, further adding to the area overhead. The leakage current reduction resultingfrom the ECC should be carefully weighed against the active and static power of the extra cells andcomponents.

Yet, when all is considered, ECC yields substantial savings in standby power. Up to 33% inleakage power reduction can be obtainedwithHamming codes. Reed–Muller codes perform even abit better, but this comes at the cost of a more complex encoder/decoder and increased latency.

Slide 9.16The impact of combiningcell optimization and errorcorrection is illustrated fora 26Kb SRAM memory(implemented in a 90nmCMOS technology). Theuse of a (31, 26, 3)Hammingcode actually increases thetotal size of the memory to31Kb.

The optimized memoryis compared with a genericimplementation of the mem-ory, integrated on the samedie. In all scenarios, a guardband of 100mV above theminimum allowed DRV is

Combining Cell Optimization and ECC

100 150 200 250 300 350 400 450 500 5500

100

200

300

Original DRV (mV)

1K w

ords

DR

V h

isto

gram

100 150 200 250 300 350 400 450 500 5500

100

200

300

Optimized DRV (mV)

1K w

ords

DR

V h

isto

gram

100 150 200 250 300 350 400 450 500 5500

100

200

300

Optimized DRV with Error Correction (mV)

1K w

ords

DR

V h

isto

gram

A

B

C

D

650mV

320mV

255mV

50X

Standard

Optimized

Optimized+ECC

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

VDD (V)

Nor

mal

ized

SR

AM

leak

age

curr

ent

Original SRAMOptimized SRAM w/ ECC

[Ref: A. Kumar, ISCAS’07]

SRAM

A Standard 1V

DRVMAX +100 mV

DRVMAX+100 mV

DRVECC_MAX+100 mV

Standard

Optimized

Optimizedwtih ECC

B

C

D

Standby VDD


maintained.TheDRVhistograms illustrate how the combinationof optimizationandECCboth shifts themean DRV to lower values and narrows the distribution substantially. The leakage current in standby isreduced by a factor of 50. This can be broken down as follows:

� Just lowering the supply voltage of the generic memory to its DRV+100mV reduces theleakage power by 75%.

� Optimizing the cell to lower the DRV yields another 90% reduction.� Finally, the addition of ECC translates into an extra 35% savings.

For this small memory, the area penalty to accomplish this large leakage savings is quitesubstantial. The combination of larger cell area, additional parity bits, and encoders and decodersapproximately doubles the size of the memory. Though this penalty may not be acceptable for top-of-the-line microprocessor chips with huge amounts of cache memory, the reduction in staticpower makes this very reasonable in ultra low-power devices with low duty cycles (such as thoseencountered in wireless sensor networks or implanted medical devices).

How to Approach the DRV Safely?

Core CellsFailure DetectorsSub-VTH

Controller

VDD

VCTRL voltages

“1” “0”“1” “0”

Adjustable Power Supply

Reset

Using “canary cells” to set the standby voltage in closed loop [Ref: J. Wang, CICC’07]

Slide 9.17The standby voltage reduc-tion techniques discussedso far lower the supply vol-tage to a value that is set ata guard band above theworst-case DRV. The latteris obtained by careful mod-eling, simulation, andexperimental observationof the process variability.This open-loop approachmeans that all chips thatdo not suffer the worst-case DRV cannot take fulladvantage of the potentialleakage savings. It has been

widely reported that the difference in leakage current between the best- and worst-case instances ofthe same design can vary by as much as a factor of 30.

One way to get around this is to use a closed-loop feedback approach, which promises to increase theleakage savings for every chip. The idea is tomeasure the distributions on-line, and set the standby voltageaccordingly. Themeasurements are provided by a set of ‘‘canary replica cells’’ added to thememory (as in‘‘the canary in the coalmine’’ strategyused to detect the presence of noxious fumes inmines in older times).

The canary cells are intentionally designed to fail across a range of voltages above the DRVdistribution of the core SRAMcells. Based on the knowledge of the shape underlying the SRAM-cellDRV distribution (using models such as the one presented in Slide 9.13), the feedback loop uses themeasured data to dynamically set the supply voltage.

The diagram shows a prototype architecture that organizes the canary cells in banks. Each canarycell is structured and sized like the bit-cells in the core array, except that an additional PMOS headerswitch presents a lower effective VDD to the cell. Controlling the gate voltage of the PMOS headers(VCTRL) allows us to set the DRV of the canary cells across a wide range of voltages.

Note: The ‘‘canary’’ approach is a first example of a runtime power reduction technique, which isthe topic of Chapter 10.

242 Chapter #9

How to Approach the DRV Safely?

Multiple sets of canary cells

128KbSRAMARRAY

Canary Replica & test circuit

0.6% area overheadin 90 nm test chipM

ean

DR

V o

f Can

ary

Cel

ls (

V)

More reliable

Less power

Failure Threshold

SRAM cell

DRV

His

togr

am

0 0.2 0.4 0.6 0.8

VCTRL (V)

0

0.2

0.4

0.6

0.8

©IEEE 2007

[Ref: J. Wang, CICC’07]

Slide 9.18The concept of how canarycells can be used to estimatethe ‘‘safe’’ operational vol-tage is illustrated in the topleft drawing. The cells aredivided into clusters, tunedto fail at regular intervalsabove the average DRV ofthe core cells. To reduce thespread of DRV distribu-tion of the canary cells rela-tive to the core, larger sizesare used for canary transis-tors. Of course, the smallset of canary cells cannottrack the local variationsin the main array, but it is

sufficient to estimate the global ones (such as systematic variations or the impact of temperaturechanges), and hence remove a large fraction of the guard band.

By varying VCTRL (e.g., by providing different values of VCTRL to different banks) and measur-ing the failure point, an estimate of the safe value of the minimum operational voltage is obtained.The measured relationship between the DRV of the canary cells and VCTRL is shown in the lower-left plot, demonstrating clearly that VCTRL is a good measure for the DRV value.

A 90 nm test chip implements the canary-based feedback mechanism at a cost of 0.6% areaoverhead. Measurements confirm that the canary cells reliably fail at voltages higher thanthe average core cell voltage and that this relationship holds across environmental changes. Thisapproach helps to reduce leakage power by factors of up to 30 compared to a guard bandapproach.

Slide 9.19All standby power reduc-tion techniques discussedso far are based on lower-ing theVDD. An alternativeapproach is to raise theground node of the bit-cells, VSS. This approachdecreases VDS across anumber of transistors,which lowers sub-thresh-old conduction (due toDIBL) as well as theGIDL effect. Furthermore,for bulk NMOS devices,the higher VSS causes anegative VBS that increases

Raise bit-cellVSS in standby (e.g., 0 to 0.5 V) Lower BL voltage in standby (e.g., 1.5 to 1 V)

Raising VSS

Lower voltage less gate leakage and GIDL

‘0’ is 0.5 V

Lower VDS less sub-VTH leakage (DIBL)

Negative VBS reduces sub-VTH leakage

1.0 V 1.0 VWL = 0 V

1.5 V

0.5 V

‘0’ ‘1’

[Ref: K. Osada, JSSC’03]


the threshold voltage of the transistors, and lowers the sub-threshold current exponentially. Thecell presented in this slide exploits all of these effects. The choice between raising VSS and loweringVDD depends primarily on the dominant sources of leakage in a given technology and on therelative overhead of the different schemes.

Body Biasing

Reverse Body Bias (RBB) for leakage reduction– Move FET source (as in raised VSS )– Move FET body

Example: Whenever WL is low, apply RBB

0 V

V DD

0 V

V DD

0 V

V DD

2V DD

-V DD

Active Standby

WL

VDD,VSS

VPB,VNB

BL BLBWL

VDD

VSS

VPB

VNB

[Ref: H. Kawaguchi, VLSI Symp. 98]

Slide 9.20Another option is to inten-tionally apply reverse bodybiasing (RBB) to the transis-tors in the cell duringstandby mode. Again, anincrease in threshold voltagetranslates into an exponen-tial decrease in sub-thresh-old drain–source leakagecurrent, which makes it apowerful tool for loweringstandby currents.

To induce RBB, you caneither raise the source vol-tage (as in raised-VSSapproach of Slide 9.19) orlower the body voltage for

an NMOS. In traditional bulk CMOS, modulating the NMOS body node means driving the fullcapacitance of the P-type substrate. Transitioning in and out of standby mode hence comes with asubstantial power overhead. Changing the body voltage of the PMOS is relatively easier because ofthe smaller-granularity control offered by the N-well. Many bulk technologies now offer a triple-well option that allows for the placement of NMOS transistors in a P-well nested inside an N-well.This option makes adjustable RBB for standby mode more attractive, but the energy involved inchanging the voltage of the wells must still be considered.

This slide shows an RBB scheme that raises and lowers the PMOS and NMOS bulk voltages,respectively, whenever a row is not accessed. The advantage of this approach is that it operates at alow level of granularity (row-level), in contrast to all techniques discussed previously, which workon a per-block level. In general, at most a single row of a memory module is accessed at any giventime. The penalty is an increase in read and write access times.

244 Chapter #9

Combining Body Biasing and Voltage Scaling

0 V

VDD

0 V

VDD

0 V

VDD

2VDD

-VDD

Active Standby

WL

VDD,VSS

VPB,VNB

BL BLBWL

VDD

VSS

VPB

VNB

[Ref: A. Bhavnagarwala, SOC’00]

Slide 9.21Body biasing is a techniquethat can easily be deployedin conjunction with otherstandby power reductionmethods. This slide, forexample, shows an SRAMthat combines body biasingand supply voltage scaling.During active mode, theVDD and VSS rails for theaccessed cells are set atslightly more positive andnegative, respectively, thanduring standby. At thesame time, the body term-

inals of the transistors are driven to 0 and VDD such that the cell transistors have a slight forwardbody bias (FBB). The reducedVTH improves the read/write access times. In standbymode, the powerrails are pinched inward and RBB is applied. The combination of voltage scaling and body biaspotentially provides for a dramatic reduction in standby power. However, one has to ensure that thedouble overhead of supply and body voltage scaling does not offset the gains. Also, one has to makesure that the source/drain diodes are not forward biased in FBB mode.

Combining Raised VSS and RBB

28X savings in standby power reported

BL BLBWL

VDD

VSS

[Ref: L. Clark, TVLSI’04]

VPB

VNB

Slide 9.22Similarly we can combinethe raised-VSS approachwith RBB. During standby,the raised-VSS nodereduces the effective supplyvoltage of the cell, whileproviding RBB for theNMOS transistors. Araised N-well voltage pro-vides RBB to the PMOSdevices. The advantage ofthis approach is that a tri-ple-well technology is notrequired.

Slide 9.23From Chapters 7 and 9 emerges a wide spectrum of choices in setting the voltages in SRAMsduring active and standby modes. The design parameters include the choice of not only the supplyand well voltages, but also the peripheral voltages such as wordline and bitline voltages. Aliterature survey illustrates the broad range of options available.


In essence, each of theseapproaches follows thesame principles:

� For each operationalmode, voltage valuesare selected to minimizepower while ensuringfunctionality and relia-bility. The latter meansthat noise margin andDRV constraints mustbe met in active andstandby mode, respec-tively. In addition, theimpact on read andwrite access times as

well as on memory area must be kept within bounds.� Transition betweenmodes oftenmeans that multiple voltagesmust be adopted. The overhead in

time and power of these transitions should be carefully weighed against the gains.

Anyone who has ever designed SRAMs knows that the impact of a change in the cell or theperiphery can be quite subtle. Although the different techniques presented here may seem to yieldhuge benefits, a careful analysis including intensive simulation and actual prototyping is absolutelyessential in defining the ultimate benefits and pitfalls.

Periphery Breakdown

Periphery leakage often not ignorable– Wide transistors to drive large load capacitors– Low- VTH transistors to meet performance specs

Chapter 8 techniques for logic leakage reduction equally applicable, but …Task made easier than for generic logic because of well-defined structure and signal patterns of periphery – e.g., decoders output 0 in standby

Lower peripheral VDD can be used, but needs fast level-conversion to interface with array

Slide 9.24As we had mentioned inChapter 7, the peripheralcircuits that go around theSRAM array primarilyconsist of combinationallogic (examples are thewrite drivers, row and col-umn decoders, I/O drivers).Most of these circuits can bedisabled during standbymode, and their leakagecan be reduced using thetechniques from Chapter 8.However, there are somecharacteristics of theSRAM periphery circuits

that differentiate them from generic logic and thus deserve mentioning.

� Although the majority of transistors in an SRAM are situated in the memory array, the SRAMperiphery can still contribute a sizable amount of leakage. This can be attributed to the fact thatmost components of the periphery must be sized fairly large to drive the large capacitances insidethe array (e.g., wordline and bitlines). These wide transistors come with large leakage currents.

Voltage Scaling in and Around the Bitcell

Large number of reported techniques

[1] K. Osada et al. JSSC 2001[2] N. Kim et al. TVLSI 2004[3] H. Qin et al. ISQED 2004[4] K. Kanda et al. ASIC/SOC 2002[5] A. Bhavnagarwala et al. SymVLSIC 2004[6] T. Enomoto et al. JSSC 2003[7] M. Yamaoka et al. SymVLSIC 2002[8] M. Yamaoka et al. ISSC 2004[9] A. Bhavnagarwala et al. ASIC/SOC 2000[10] K. Itoh et al. SymVLSIC 1996[11] H. Yamauchi et al. SymVLSIC 1996[12] K. Osada et al. JSSC 2003[13] K. Zhang et al. SymVLSIC 2004[14] K. Nii et al. ISSCC 2004[15] A. Agarwal et al. JSSC 2003[16] K. Kanda et al. JSSC 2004

246 Chapter #9

� Whereas the SRAM bit-cells typically use high-threshold transistors, performance considera-tions dictate the use of low-threshold devices in the periphery.

� From our discussion, it had become clear that memory cells and logic are on somewhat differentvoltage-scaling trajectories. Logic supply voltages are expected to keep on scaling downward, whereasreliability concerns in the presence of increasing process variations force the voltages in memory tostay constant (if not increasing). Interfacing between periphery and memory core hence increasinglyrequires the presence of voltage-up and -down converters, which translates into a timing and poweroverhead. Moreover, this interface must be properly conditioned in standby mode. For example,floating wordlines caused by power gating of the periphery, could cause data loss in the bit-cells.

On the other hand, a sizable number of the generic standby power management techniquesintroduced in Chapter 8 perform even better when applied tomemory periphery. This is largely dueto the well-behaved repetitive structure of the peripheral circuits. In addition, many of the signalvoltages during standby are known very well. For instance, we know that all of the wordlines mustbe 0 in standby. This knowledge makes it easier to apply power gating or forced stacking tomaximally reduce the leakage power.

Summary and Perspectives

SRAM standby power is leakage-dominatedVoltage knobs are effective to lower powerAdaptive schemes must account for variation to allow outlying cells to functionCombined schemes are most promising– e.g., Voltage scaling and ECC

Important to assess overhead!– Need for exploration and optimization framework, in

the style we have defined for logic

Slide 9.25In summary, SRAM leak-age power is a dominantcomponent of the overallstandby power consumptionin many SoCs and general-purpose processing devices.For components that oper-ate at low duty cycles, it isoften THE most importantsource of power consump-tion. In this chapter, wehave established that themost effective knobs in low-ering leakage power are the

various voltages that drive the bit-cells. However, these voltages must be manipulated carefully so thatdata preservation is not endangered.

Aswith active operation, the large number of small transistors in an embeddedSRAMmeans that thefar tails of power and functionality distributions drive the design. This means that any worst-case oradaptive schemesmust account for the outliers on the distributions to preserve proper SRAM function-ality. The most promising schemes for leakage reduction combine several different voltage-scalingapproaches (selected from the set of VTH, VDD, VSS, and well and periphery voltages) along witharchitectural changes (e.g., ECC). In all of these approaches, the overhead requires careful attention toensure that the overall leakage savings areworth the extra cost in area, performance, or overheadpower.

All this having been said, one cannot escape the notion that some more dramatic steps may beneeded to improve the long-term perspectives of on-chip memory. Non-volatile memory structuresthat are compatible with logic processes and that do not require high voltages present a promisingvenue. Their non-volatile nature effectively eliminates the standby power concern. However, theirwrite and (sometimes) read access times are substantially longer than what can be obtained withSRAMs. It is worth keeping an eye on the multitude of cell structures that are currently trying tomake their way out of the research labs.


References

Books and Book Chapters:K. Itoh, M. Horiguchi and H. Tanaka, Ultra-Low Voltage Nano-Scale Memories, Springer 2007.T. Takahawara and K. Itoh, “Memory Leakage Reduction,” in Leakage in Nanometer CMOS Technologies, S. Narendra, Ed, Chapter 7, Springer 2006.

Articles:A. Agarwal, L. Hai and K. Roy, “A single-V/sub t/low-leakage gated-ground cache for deep submicron,” IEEE Journal of Solid-State Circuits, pp. 319–328, Feb. 2003.A. Bhavnagarwala, A. Kapoor, J. Meindl, “Dynamic-threshold CMOS SRAM cells for fast, portable applications,” Proceedings of IEEE ASIC/SOC Conference, pp. 359–363, Sep. 2000.A. Bhavnagarwala et al., “A transregional CMOS SRAM with single, logic V/sub DD/and dynamic power rails,” Proceedings of IEEE VLSI Circuits Symposium, pp. 292–293, June 2004.L. Clark, M. Morrow and W. Brown, “Reverse-body bias and supply collapse for low effective standby power,” IEEE Transactions on VLSI, pp. 947–956, Sep. 2004. T. Enomoto, Y. Ota and H. Shikano, “A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications, “ IEEE Journal of Solid-State Circuits,” 38(7), pp. 1220–1226, July 2003.K. Flautner et al., “Drowsy caches: Simple techniques for reducing leakage power”., Proceedings of ISCA 2002, pp. 148–157, Anchorage, May 2002.K. Itoh et al., “A deep sub-V, single power-supply SRAM cell with multi-VT, boosted storage node and dynamic load, ”Proceedings of VLSI Circuits Symposium, pp. 132–133, June, 1996. K. Kanda, T. Miyazaki, S. Min, H. Kawaguchi and T. Sakurai, “Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic Vdd control (RRDV) scheme,”Proceedings of IEEE ASIC/SOC Conference, pp. 381–385, Sep. 2002.

Slides 9.26–9.28Some references . . .

References (cont.)

K. Kanda, et al., “90% write power-saving SRAM using sense-amplifying memory cell,”IEEE Journal of Solid-State Circuits, pp. 927–933, June 2004H. Kawaguchi, Y. Itaka and T. Sakurai, “Dynamic leakage cut-off scheme for low-voltage SRAMs,”Proceedings of VLSI Symposium, pp. 140–141, June 1998.A. Kumar et al., “Fundamental bounds on power reduction during data-retention in standby SRAM,”Proceedings ISCAS 2007, pp. 1867–1870, May 2007.N.Kim, K. Flautner, D. Blaauw and T. Mudge, “Circuit and microarchitectural techniques for reducing cache leakage power,”IEEE Transactions on VLSI, pp. 167–184, Feb. 2004 167–184Y. Nakagome et al., “Review and prospects of low-voltage RAM circuits,”IBM J. R & D, 47(516),pp. 525–552, Sep./Nov. 2003.K. Osada, “Universal-Vdd 0.65–2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell,” IEEE Journal of Solid-State Circuits,

K. Osada et al., “16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors,”IEEE Journal of Solid-State Circuits, pp. 1952–1957, Nov. 2003.H. Qin, et al., “SRAM leakage suppression by minimizing standby supply voltage,”Proceedings ofISQED, pp. 55–60, 2004.H. Qin, R. Vattikonda, T. Trinh, Y. Cao and J. Rabaey, “SRAM cell optimization for ultra-low power standby,”Journal of Low Power Electronics, 2(3), pp. 401–411, Dec. 2006.J. Ryan, J. Wang and B. Calhoun, "Analyzing and modeling process balance for sub-threshold circuit design” Proceedings GLSVLSI, pp. 275–280, Mar. 2007. J. Wang and B. Calhoun, “Canary replica feedback for Near-DRV standby VDD scaling in a 90 nm SRAM,” Proceedings of Custom Integrated Circuits Conference (CICC ), pp. 29–32, Sep. 2007.

pp. 1738–1744, Nov. 2001.

References (cont.)

J. Wang, A . Singhee, R. Rutenbar and B. Calhoun, “Statistical modeling for the minimum standby supply voltage of a full SRAM array ”, Proceedings of European Solid-State Circuits Conference (ESSCIRC ), pp. 400–403, Sep. 2007.M. Yamaoka et al., “0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage scheme, Proceedings of VLSI Circuits Symposium, pp. 13–15,June 2002.M. Yamaoka, et al., “A 300 MHz 25 μA/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor,”Proceedings of IEEE Solid-State Circuits Conference, pp. 15–19, Feb. 2004.

K. Zhang et al., “SRAM design on 65 nm CMOS technology with integrated leakage reduction scheme,” Proceedings of VLSI Circuits Symposium, 2004, pp. 294–295, June 2004.

248 Chapter #9

Optimizing Power @ Standby - MemorySlide 9.1Slide 9.2Slide 9.3Slide 9.4Slide 9.5Slide 9.6Slide 9.7Slide 9.8Slide 9.9Slide 9.10Slide 9.11Slide 9.12Slide 9.13Slide 9.14Slide 9.15Slide 9.16Slide 9.17Slide 9.18Slide 9.19Slide 9.20Slide 9.21Slide 9.22Slide 9.23Slide 9.24Slide 9.25Slides 9.26–9.28

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