Intro Registers Shift Registers Accumulators

Chapter 8Registers

SKEE2263 Digital Systems

Mun’im/Ismahani/Izam

{munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my}

February 12, 2016

Intro Registers Shift Registers Accumulators

Table of Contents

1 Intro

2 Registers

3 Shift Registers

4 Accumulators

Intro Registers Shift Registers Accumulators

Basic Register

Clk

QD

D3

Q3

D2

Q2

D1

Q1

D0

Q0

QD QD QD

Clk

0010 0001 0010 1111 0110

0010 0001 1111 0110

D[3:0]

Q[3:0]

Ignored

Intro Registers Shift Registers Accumulators

Resettable Register

Clk

Clear

QD

CLR

D3

Q3

D2

Q2

D1

Q1

D0

Q0

QD

CLR

QD

CLR

QD

CLR

Clk

0010 0001D[3:0]

Clear

Cleared

0010 0001 0011 0000Q[3:0]

0010 0011 0100

00000011 0100xxxx

Intro Registers Shift Registers Accumulators

Register with Load Enable

ClkLoad

D0

1

0

QD

Q0

1

0

QD

1

0

QD

1

0

QD

Q1Q2Q2Q3

D1D2D3

Clk

D[3:0]

Load

Q[3:0]

1100 1000

0110xxxx 1110

1111 1110 0111 0110 0101

Intro Registers Shift Registers Accumulators

Basic Shift Register

Clk

QD

Q3 Q2 Q1 Q0

QD QD QDInput

Intro Registers Shift Registers Accumulators

Shift Register “Animation”

D Q D Q D Q D Q

CLK

D Q D Q D Q D Q

D Q D Q D Q D Q

D Q D Q D Q D Q

D Q D Q D Q D Q

D Q D Q D Q D Q

CLK

CLK

CLK

CLK

CLK

1 0 0 0 0

0 1 0 0 0

0 0 1 0 0

0 0 0 1 0

0 0 0 0 1

0 0 0 0 0

Initialcondition

Afterfirstclockpulse

Aftersecondclockpulse

Afterthirdclockpulse

Afterfourthclockpulse

Afterfifthclockpulse

Intro Registers Shift Registers Accumulators

Shift Register Timing Diagram

Clk

Input

Q3

Q2

Q1

Q0

Intro Registers Shift Registers Accumulators

Enabled Shift Register

Clk

Input

Shift

1

0

1

0

Q3

1

0

QD

1

0

Q2 Q1 Q0

QD

QD

QD

Clk

Input

Shift

Q[3:0] 101101110000 11101000 1100 1111

Intro Registers Shift Registers Accumulators

Universal Shift Register

1S

LSI

Q0Q1Q2Q3

0S Clk

D3 D1D2 D0

Clear

RSIS1 S0 Function

0 0 Hold0 1 Shift left1 0 Shift right1 1 Load new input

Can be used in either serial-to-serial, serial-to-parallel,parallel-to-serial, parallel-to-parallel, left shifting as well asright shifting.Useful in arithmetic operations to shift data left formultiplication or to shift data right for division.

Intro Registers Shift Registers Accumulators

Universal Shift Register Schematic

Clk

RSI

Clear

13

QD

02 13

QD

02 13

QD

02 13

QD

02

LSI

D0D1D2D3

1:0S 01:0S 0

1:0S 01:0S

Q0Q1Q2Q3

Intro Registers Shift Registers Accumulators

Universal Shift Register Timing Diagram

Clk

RSI

LSI

D[3:0]

S[1:0]

CA0 62 4 8

Q[3:0]

E 0

230 13 1 1 2 0

A00 40 2 8 5 2

2

3

2

Intro Registers Shift Registers Accumulators

Accumulators

AccumulatorClk

6 6

Acc

+1 Accumulator: register that keepsresults of arithmetic ops.Registers + Adders →Accumulator-based counter.Any adder architecture may be used.

Clk

Acc 00 01 02 03 04 05

Accumulatoroverflow

3E 3F 00 01

Intro Registers Shift Registers Accumulators

6-bit Accumulator-Based Counter

Clk

QD

HA

QD

HA

QD

HA

QD

HA

QD

HA

QD

HA 1

A0A5 A4 A3 A2 A1

A0A5 A4 A3 A2 A1

Intro Registers Shift Registers Accumulators

Multi-Function Counter No.1

Accumulator

Acc

Clk

+2 -1+1

1 2 30

0

S1 S0

S1 S0 Function

0 0 Clear0 1 Add 11 0 Add 21 1 Subtract 1

Intro Registers Shift Registers Accumulators

Multi-Function Counter No.2

Accumulator

Acc

Clk

S1 S0

Adder

1 2 30

1 2 -10

S1 S0 Function

0 0 Hold0 1 Add 11 0 Add 21 1 Subtract 1