chapter 7 the cpu and memoryrevised2 (1)

Chapter 7 The CPU and Memory

Copyright 2013 John Wiley & Sons, Inc.

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System Block Diagram


7-3

7-1. The Little Person Computer

ALU (arithmetic logic unit)◦ Performs calculations and comparisons

CU (control unit)◦ Performs fetch/execute cycle

Accesses program instructions and issues commands to the ALU

Moves data to and from CPU registers and other hardware components

◦ Subcomponents: Memory management unit: supervises fetching

instructions and data from memory I/O Interface: sometimes combined with memory

management unit as Bus Interface Unit


7-4

CPU: Major Components

Every instruction executed by the CPU requires memory access

Primary memory holds program instructions and data

Secondary storage is used for long term storage◦ Data is moved from secondary storage to primary

memory for CPU execution


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CPU and Memory

Small, permanent storage locations within the CPU used for a particular purpose

Manipulated directly by the Control Unit Wired for specific function Size in bits or bytes (not in MB like

memory) Can hold data, an address, or an

instruction How many registers does the LMC have? What are the registers in the LMC?


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7.2-Concept of Registers

Use of Registers◦ Scratchpad for currently executing program

Holds data needed quickly or frequently◦ Stores information about status of CPU and currently

executing program Address of next program instruction Signals from external devices

General Purpose Registers◦ User-visible registers◦ Hold intermediate results or data values, e.g., loop

counters◦ Equivalent to LMC’s calculator◦ Typically several dozen in current CPUs

Chapter 7 CPU and Memory7-7

Registers

Program Count Register (PC)◦ Also called instruction pointer

Instruction Register (IR)◦ Stores instruction fetched from memory

Memory Address Register (MAR) Memory Data Register (MDR) Status Registers

◦ Status of CPU and currently executing program◦ Flags (one bit Boolean variable) to track

condition like arithmetic carry and overflow, power failure, internal computer error


Special-Purpose Registers

Registers and the Control Unit•Single, permanent storage location within

the CPU used for a particular defined purpose.

•Each register in the CPU performs a specific role

•Unlike memory in which every address is like any other address, each register serves a specific purpose.

•Register size, the way its wired reflect its special function

•Register maybe as small as a single bit or as wide as several bytes-range 1-128 bits

•Size in bits or bytes (not MB like memory)

•Manipulated directly by the Control UnitCan hold data, an address or an instruction

Stores values from other locations (registers and memory)

Addition and subtraction Shift or rotate data Test contents for conditions such as zero or

positive


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Register Operations

PC IR MAR MDR 1 bit Registers- flags

status registers I/O interface (pair of

registers-one to hold one I/O address that addresses a particular I/O device- the other to the I/O data.

Reg can be loaded with values from another location

Data from another location can be added or subtracted from value previously stored in the register, leaving the sum or difference

Data in the register can be shifted.

Registers and the Control Unit

Each memory location has a unique address

Address from an instruction is copied to the MAR which finds the location in memory

MAR and MDR act as an Interface bween CPU and Memory.

CPU determines if it is a store or retrieval Transfer takes place between the MDR and

memory MDR is a two way register


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7.3 Memory Unit Operation of Memory

The Memory Unit

The relationship between the MDR, the MAR, and memory

MDR/MAR act as interface between CPU and memory


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Relationship between MAR, MDR and Memory

Address

Data


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MAR-MDR Example

Each cell in memory unit holds i bit of data.. In diagram above, each cellis organized in rows, Each row consists of one or more bytes.

MAR holds address in memory that needs to be opened or activared

In the diagram, what does 2n-1 represents?

There is a separate address line for each row of cells in the memory,If there are n bits of addressing, there will be 2n address lines

The MDR is connected to every memory cell in memory. Every bit of MDR is connected in a column to the corresponding bit of every location in memory. However, only a single row of cells are activated at any given time.

7.3 Memory Unit Operation of Memory

Memory Unit CPU copies an address to

MAR-Same time CPU sends message to memory unit whether it is a read/write

CPU turns on switch that connects MDR with MAR by using activation line.

Address decoder interprets address and activates address line in memory

Switch activated between memory and MDR and transfer takes place

MAR hold the address in the memory that is to be opened for data.

Each bit has an address line.


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Visual Analogy of Memory


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Individual Memory Cell

MEMORY CELL Address Line is turned on only if

the computer is addressing the data within the cell

The read/write determines whether the data will be transferred from the the cell to the MDR or from the MDR to the cell.

R switch if on connects output of the cell to MDR line.

W switch if on connect input of the cell to MDR which transfers the data bit on the MDR line to the cell for storage

Activation Line

Determined by two factors 1. Number of bits in the MAR

LMC = 100 (00 to 99) 2K where K = width of the register in bits

2. Size of the address portion of the instruction 4 bits allows 16 locations 8 bits allows 256 locations 32 bits allows 4,294,967,296 or 4 GB 64 bits allows 16 billion gigabytes


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Memory Capacity and Addressing Limitations

DRAM (Dynamic RAM)◦ Most common, cheap, less electrical power, less

heat, smaller space◦ Volatile: must be refreshed (recharged with

power) 1000’s of times each second SRAM (static RAM)

◦ Faster and more expensive than DRAM◦ Volatile◦ Small amounts are often used in cache memory

for high-speed memory access


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RAM: Random Access Memory

ROM◦ Read-only Memory◦ Holds software that is not expected to change

over the life of the system such as firmware used for the system BIOS

Flash Memory◦ Inexpensive nonvolatile secondary storage◦ Useful for nonvolatile portable computer

storage, digital cameras, tablets, smartphones◦ Slower rewrite time compared to RAM


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Nonvolatile Memory

Non-volatile memory to hold software that is not expected to change over the life of the system

Magnetic core memory EEPROM

◦ Electrically Erasable Programmable ROM◦ Slower and less flexible than Flash ROM

Flash ROM ◦ Faster than disks but more expensive◦ Uses

BIOS: initial boot instructions and diagnostics Digital cameras


ROM - Read Only Memory

Two-cycle process because both instructions and data are in memory

Fetch◦ Decode or find instruction, load from memory into

register and signal ALU Execute

◦ Performs operation that instruction requires◦ Move/transform data


7.4 Fetch-Execute Cycle


LMC vs. CPUFetch and Execute Cycle

Store Fetch/Execute Cycle1. PC -> MAR Transfer the address from the

PC to the MAR

2. MDR -> IR Transfer the instruction to the IR

3. IR(address) -> MAR Address portion of the instruction loaded in MAR

4. A -> MDR* Accumulator copies data into MDR

5. PC + 1 -> PC Program Counter incremented

*Notice how Step #4 differs for LOAD and STORE


ADD Fetch/Execute Cycle1. PC -> MAR Transfer the address from the

PC to the MAR

2. MDR -> IR Transfer the instruction to the IR

3. IR(address) -> MAR Address portion of the instruction loaded in MAR

4. A + MDR -> A Contents of MDR added to contents of accumulator

5. PC + 1 -> PC Program Counter incremented


LMC Fetch/Execute

SUBTRACT

PC MAR

MDR IR

IR[addr] MAR

A – MDR A

PC + 1 PC

IN

PC MAR

MDR IR

IOR A

PC + 1 PC

OUT

PC MAR

MDR IR

A IOR

PC + 1 PC

HALT

PC MAR

MDR IR

BRANCH

PC MAR

MDR IR

IR[addr] PC

BRANCH on Condition

PC MAR

MDR IR

If condition false: PC + 1 PC

If condition true: IR[addr] PC

The CPU, specifically the control unit of the CPU, carries out software instructions using the four-step sequence of the machine cycle. It records the location of the current instruction—called the instructions pointer—and fetches that instruction from primary storage (RAM) or its cache memory. The control unit decodes the instruction and then sends it to the arithmetic logic unit (ALU) to execute. The results of the instructions are then stored back in primary storage. The instruction pointer is then incremented to move to the next instruction and the cycle begins again.Each step of the machine cycle is carried out in time with the system clock. Today’s processors can overlap machine cycles and even execute multiple instructions simultaneously. Still, the machine cycle keeps processing orderly and the computer running smoothly.

Machine Cycle

Machine Cycle

1 a.(BL2-) Working from the F/E cycle for instruction 20,PC - MARMDR - IR ¬ final value of IR = 550IR [address] - MAR ¬ final value of MAR = 50MDR - A ¬ final value of MDR and A = 724PC + 1- PC ¬ final value of PC = 21

b. (BL2-) PC MAR MDR IR APC - MAR 21 21 724 550 724MDR - IR 21 21 151 151 724

IR [address] - MAR 21 51 151 151 724A + MDR – A 21 51 006 151 730PC + 1 - PC 22 51 006 151 730

Problems

2. 48-bit MAR can support 248 = 240 ´ 28 = 256 terabytes of addressable memory. 3.There are two different registers associated with memory because each memory location has an address that identifies it and the data that is stored there, just as each mailbox in the L PersonComputer has both an address and the slip of paper containing the data stuffed into the slot.

4. If a computer is to be used in outer space, it would be advantageous to use nonvolatile memory to hold power and data during momentary power outages. This suggests the use of magnetic core memory, particularly if an alternative method of nonvolatile storage, such as disk, is not available. Even a momentary power glitch would affect RAM, making stable power backup a necessity.

7.5 Buses7.5 BusesWhat is a bus?

Electrical channels that allow various devices inside the computer to communicate with each other

Bus width determines the number of bits transmitted at one time

Word size determines the number of bits the processor can interpret and execute at a given time

Bus interface bridges-interfaces between different buses to allow communication among them

Bus The physical connection that makes it

possible to transfer data from one location in the computer system to another

Group of electrical or optical conductors for carrying signals from one location to another◦Wires or conductors printed on a circuit board◦Line: each conductor in the bus

4 kinds of signals1.Data2.Addressing specify address of recipient of data3.Control signals control and timing signals for proper

synchronization and operation of the bus4.Power (sometimes)


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Bus Characteristics Number of separate wires or conductors Data width in bits carried simultaneously Addressing capacity Lines on the bus are for a single type of signal

or shared Throughput – data transfer rate in bits per

second Distance between two endpoints Number and type of attachments supported Type of control required Defined purpose Features and capabilities


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Bus Hierarchy Processor bus: on-chip Memory bus (northbridge)

◦ Connects the memory subsystem and processor

I/O bus (southbridge)◦ Connects I/O to the CPU and memory◦ Connects all peripheral cards and connectors◦ Examples: SATA, Thunderbolt, and USB

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North and South Bridge

North and South Bridge The southbridge is one of the two chips in the core logic

chipset on a personal computer (PC) motherboard, the other being the northbridge. The southbridge typically implements the slower capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. In Intel chipset systems, the southbridge is named Input/Output Controller Hub (ICH

The southbridge can usually be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU. Through the use of controller integrated channel circuitry, the northbridge can directly link signals from the I/O units to the CPU for data control and access.

Wikepedia

http://en.wikipedia.org/wiki/Chipset

http://en.wikipedia.org/wiki/Personal_computer

http://en.wikipedia.org/wiki/Motherboard

http://en.wikipedia.org/wiki/Northbridge_(computing)

http://en.wikipedia.org/wiki/Chipset

http://en.wikipedia.org/wiki/I/O_Controller_Hub

http://en.wikipedia.org/wiki/I/O_Controller_Hub

http://en.wikipedia.org/wiki/Central_processing_unit

Instructions and data flow back and forth between the CPU and RAM over the FSB controlled by a bridge in the chipset

Central Processing Unit (CPU) (continued)

FSB: Needs address lines to pass address stored in MAR to address decoder in memory and data lines to transfer data between CPU and MDR- Control lines provide timing signals for thedata transfer –definr transfer as R or W, specify # of bits

Backside BUS

BUS

Processor bus: on-chip Front Side Bus FSB Cache bus (backside bus) Memory bus (frontside bus)

◦ connects the memory subsystem and processor Local I/O bus

◦ high-speed bus used to connect performance critical peripherals to memory and processor

◦ Examples: PCI, VESA Local Bus Standard I/O bus

◦ connects slower peripherals (ISA) to Local I/O bus

Bus Hierarchy

Dedicated buses- internal to CPU serve a specific purpose

Buses-general purposemust have well-defined standard.

PCI Express, USB, IDE,SAA

Buses

Bus I/O Consists of an I/O device, I/O device

controller, system bus, and a device driver Device driver

◦ Software that controls the I/O devices Common interface buses-Protocols

◦ PCI-Express◦ USB – Universal Serial Bus◦ SCSI – Small Computer System Interface◦ SATA – Serial Advanced Technology Attachment◦ Thunderbolt◦ Display Port


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Bus Categorizations Parallel vs. serial buses (ground line) Direction of transmission

◦ Simplex – unidirectional◦ Half duplex – bidirectional, one direction at a time◦ Full duplex – bidirectional simultaneously

Method of interconnection◦ Point-to-point – single source to single destination

Cables – point-to-point buses that connect to an external device

◦ Multipoint bus – also broadcast bus or multidrop bus Connect multiple points to one another


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Parallel vs. Serial Buses Parallel

◦ High throughput because all bits of a word are transmitted simultaneously

◦ Expensive and require a lot of space◦ Subject to radio-generated electrical interference,

which limits their speed and length◦ Generally used for short distances such as CPU buses

and on computer motherboards-◦ Skew –difference in time delay on different lines◦ Fiber Optic

Serial◦ 1 bit transmitted at a time◦ Single data line pair and a few control lines◦ For many applications, throughput is higher than for

parallel because of the lack of electrical interferenceCopyright 2013 John Wiley & Sons, Inc.

7-49

Cable :Point to Point buses that connct an external device to a connector

Port The internal Connectors into which cables are plugged –durect connect

ex: network, Display Port Muluplexed w data and adress

BUS

Bus I/O Protocols-old Common

Bus8-bit ISA

16-bit ISAEISAMCAVLBPCI

64-bit PCI 2.1PCT eAGP

AGP (x2 mode)AGP (x4 mode)

AGP (x8 Mode)

Width (bits)8

16 32

32

3232

64variable

32323232

Bus Speed(MHz)8.3

8.3 8.3 33 33 33 33 2.5Ghz/lane 66 66X2 66 X4 533

Bus (MBytes/sec) 7.9 15.9 31.8 127.2 127.2 127.2 variable 254.3 508.6 1,017.3 2,133

Lane width Clock speed Throughput duplex

bits)Throughput (duplex

bytes)Initial expected uses

Lane widthClock speedThroughput (duplex

bits)Throughput (duplex

x1 2.5 GHz5 5 Gbps s 400 MBp Slots,Gigabit Ethernet

x2 2.5 GHz5 10 Gbps 800 MBpsx3 2.5 GHz5 20 Gbps 1.6 Gbps slots, 10 Gigabit

Ethernet, SCSI, SASx4 2.5 GHz5 40 Gbps 3.2 Gbpsx5 2.5 GHz5 80 Gbps 6.4 Gbps Graphic Adapters

PCI Express ImplementationEncoded Data Rate Unencoded Data Rate1

x1 5 Gbps 4 Gbps (500 MB/secx4 20 Gbps 16 Gbps (2 GB/sec)x8 40 Gbps 32 Gbps (4 GB/sec)x16 80 Gbps

Bus Interfaces or Bridges Throughput-bandwidth

Data Transfer Rate/8 X MHz Data Transfer Rate Bus Width Speed in MHz Type Single or Shared Physical topology Electrical voltages,

number of pins on connection

The Bus Protocols

Bus width X Mhz MHz= 1,000,000 MB/sec=1,048,576 EX PCI (32)=32/8*33*1,000,000/1,048,576 =127.2

MBytes/sec 32bit/8bits X 33Mhz = 132MB/sec

Parallel port Serial port

◦ RS-232C and RS-422 buses SCSI

◦ Small Computer System Interface USB, USB-2, USB 3.0 USB 3.1

◦ Universal Serial Bus IEEE 1394

◦ Firewire◦ i.link

Thunderbolt Lightning

External Interface Buses and Ports

USB1.1 12 mbps, 127 devices USB-2 -480 mbps, USB 3.0 4.8 gbps USB 3.1 10gbps

◦ Universal Serial Bus IEEE 1394 400mbps- 3.2 gbps eventually

6GBps 63 Devices

◦ Firewire◦ i.link

Thunderbolt-10 gbps and displayport 1.62Gbps, 2.7Gbps, or 5.4Gbps (DisplayPort 1.2

or later). If all four lanes were in use, you would be looking at a raw bandwidth of 6.48Gbps, 10.8Gbps, or 21.6Gb

BUS PROTOCALS

7.6 Classification of Instructions Data Movement (load, store)

◦ Most common, greatest flexibility◦ Involve memory and registers◦ What’s this size of a word ? 16? 32? 64 bits?

Arithmetic◦ Operators + - / * ^◦ Integers and floating point

Boolean Logic ◦ Often includes at least AND, XOR, and NOT

Single operand manipulation instructions◦ Negating, decrementing, incrementing, set to 0


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More Instruction Classifications

Bit manipulation instructions◦ Flags to test for conditions

Shift and rotate Program control Stack instructions Multiple data instructions I/O and machine control


7-58

Register Shifts and Rotates


7-59

Program Control Instructions

Program control◦ Jump and branch◦ Subroutine call

and return

Copyright 2013 John Wiley & Sons, Inc.7-60

Stack Instructions Stack instructions

◦ LIFO method for organizing information ◦ Items removed in the reverse order from how they

are added

Push Pop


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Fixed Location Subroutine Return Address Storage: Oops!


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Stack Subroutine Return Address Storage


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Block of Memory as a Stack


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Multiple Data Instructions Perform a single operation on multiple pieces

of data simultaneously◦ SIMD: Single Instruction, Multiple Data◦ Commonly used in multimedia, vector and array

processing applications


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Instruction Elements OPCODE: task Source OPERAND(s) Result OPERAND

◦ Location of data (register, memory) Explicit: included in instruction Implicit: default assumed

OPCODE SourceOPERAND

Result OPERAND

Addresses


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Instruction Format

Machine-specific template that specifies◦ Length of the op code ◦ Number of operands◦ Length of operands

Simple 32-bit Instruction Format


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Instructions Instruction

◦ Direction given to a computer◦ Causes electrical or optical signals to be sent through

specific circuits for processing Instruction set

◦ Design defines functions performed by the processor◦ Differentiates computer architecture by the

Number of instructions Complexity of operations performed by individual

instructions Data types supported Format (layout, fixed vs. variable length) Use of registers Addressing (size, modes)


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Instruction Word Size Fixed vs. variable size

◦ Pipelining has mostly eliminated variable instruction size architectures

Most current architectures use 32-bit or 64-bit words

Addressing Modes◦ Direct

Mode used by the LMC

◦ Register Deferred◦ Also immediate, indirect, indexed


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7. 6 Instruction Format Examples


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