chapter 7 input / output -...

Chapter 7Chapter 7

Input / Output Input / Output

YonseiYonsei UniversityUniversity

YonseiYonsei UniversityUniversity7-2

• External Devices• I/O Modules• Programmed I/O• Interrupt-Driven I/O• Direct Memory Access• I/O Channel and Processors• The External Interface:FireWire and Infiniband

Contents Contents


OverviewOverview External DevicesExternal Devices

• Input / Output modules are the third critical element of the computer system (others are the CPU and the memory)

• Why one does not connect peripherals directly to the system bus– Variety of peripherals with various methods of

operation– Data transfer rate of peripherals is slow– Different data format and word lengths

• I/O module major functions– Interface to the processor and memory via the

system bus or central switch– Interface to the one or more peripheral devices by

tailored data links


Generic Model of an I/O ModuleGeneric Model of an I/O Module External DevicesExternal Devices


Peripheral DevicePeripheral Device External DevicesExternal Devices

• External device is referred to as a peripheral device

• External Deveice– Human readable

• Screen, printer, keyboard– Machine readable

• Monitoring and control– Communication

• Modem• Network Interface Card (NIC)


External DeviceExternal Device External DevicesExternal Devices


Keyboard/MonitorKeyboard/Monitor External DevicesExternal Devices

• Most common means of computer/user interaction

• Basic unit of exchange is the character• ASCII is most commonly used


American Standard CodeAmerican Standard Code External DevicesExternal Devices

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

b7 b6 b5 b4 b3 b2 b1

0 0 0 0 NUL DLE SP 0 @ P ` p

0 0 0 1 SOH DC1 ! 1 A Q a q

0 0 1 0 STX DC2 “ 2 B R b r

0 0 1 1 ETX DC3 # 3 C S c s

0 1 0 0 EOT DC4 $ 4 D T d t

0 1 0 1 ENQ NAK % 5 E U e u

0 1 1 0 ACK SYN & 6 F V f v

0 1 1 1 BEL ETB ‘ 7 G W g w

1 0 0 0 BS CAN ( 8 H X h x

1 0 0 1 HT EM ) 9 I Y i y

1 0 1 0 LF SUB * : J Z j z

1 0 1 1 VT ESC + ; K [ k {

1 1 0 0 FF FS , < L ＼ l |

1 1 0 1 CR GS - = M ] m }

1 1 1 0 SO RS . > N ^ n ~

1 1 1 1 SI US / ? O _ o DEL


ASCII Control CharactersASCII Control Characters External DevicesExternal Devices

• Format Control

BS(Backspace)Indicates movement of the printing mechanism ordisplay cursor backward one position

HT(Horizontal tab)Indicates movement of the printing mechanism ordisplay cursor forward to the nex t preassigned"tab"or stopping position

LF(Line feed)Indicates movement of the printing mechanism ordisplay cursor to the start of the nex t line

VT(vertical tab)Indicates movement of the printing mechanism ordisplay cursor to the nex t of aseries preassignedprinting lines

FF(Form feed)Indicates movement of the printing mechanism ordisplay cursor to the starting position of the nextpage, form, or screen

CR(Carriage return)Indicates movement of the printing mechanism ordisplay cursor to the starting position of thesame line


ASCII Control Characters ASCII Control Characters External DevicesExternal Devices

• Transmission Control(1)

SOH

(start of heading)Used to indicate the start of a heading, which maycontain address or routing information.

STX

(Start of text)Used to indicate the start of the tex t and so alsoindicates the end of the heading.

ETX

(end of text)Used to terminate the tex t tha was started with STX

EOT

(End of

transmission)

indicates the end of a transmission which mayhave included one or more "tex ts"with theirheadings

ENQ

(Enquiry)

A request for a response from a remote station. Itmay be used as a "WHO ARE YOU" request for astation to identigy itself



• Transmission Control(2)

ACK

( Acknowledge )

A character transmitted by a receiv ing dev ice as anaffirmation response to a sender. It is used as apositive response to polling messages

NAK

( Negative

acknowledgment )

A character transmitted by a receiv ing dev ice as anegative response to a sender. It is used as anegative response to polling messages

SYN

(Synchronous/idle)

Used by a synchronous transmission system toachieve synchronization. When no data is beingsent a synchronous transmission system may sendSYN characters continuously

ETB

( End of

transmission block )

Indicates the end of a block of data forcommunication purposes. It is used for blockingdata where the block structure is not necessarilyrelated to the processing format.



• Information Separator

FS(File separator)

GS(Group separator)

RS(Record separator)

US(United separator)

Information separators to be used inan optional manner except that their

hierarchy shall be FS(the most inclus ive)to US(the least inclus ive)



• Miscellaneous(1)

NUL(Null)No character. Used for filling in time or filling space on tapewhen there are no data.

BEL(Bell)Used when there is need to call human attention. It may controlalarm or attention devices.

SO(Shift out)Indicates that the code combinations that follow shall beinterpreted as outside of the standard character set untila SI character is reached

SI(Shift in)Indicates that the code combinations that follow shall be interpretedaccording to the standard character set.

DEL(Delete) Used to obliterate unwanted characters; for example by overwriting

SP(Space)A nonprinting character used to separate words, or to move theprinting mechanism or display cursor forward by one position



• Miscellaneous(2)

DLE(Data link escape)

A character that shall change the meaning of one or morecontiguously following characters. It can provide supplementarycontrols or permits the sending of data characters having any bitcombination.

DC1, DC2, DC3, DC4(Dev ice controls)

Characters for the conntrol of ancillary devices or special terminalfeatures.

CAN(Cancel)Indicates that the data that precedes it in a message or blockshould be disregarded(usually because an error has beendetected).

EM(End of Medium)Indicates the physical end of a tape or other medium, or the end ofthe required or used portion of the medium

SUB(Substitute) Substituted for a character that is found to be erroneous or invalid

ESC(Escape)A character intended to provide code extension in that it gives aspecified number of continously following characters an alternatemeaning


Disk DriveDisk Drive External DevicesExternal Devices

• Disk driver exchanges data, control, status signal with an I/O module plus the electronics for controlling the disk read/write mechanism

• Fixed-head disk– Converts the magnetic patterns on the moving disk

surface to bits in the devices buffer• Moving-head disk

– Causes disk arm to move in and out across the disk’s surface


Module FunctionModule Function External DevicesExternal Devices

• Major function for an I/O module– Control and timing– Processor communication– Device communication– Data buffering– Error detection


Control and TimingControl and Timing External DevicesExternal Devices

• Control step of the transfer data– Processor interrogates the I/O module– I/O module returns the device status– Transfer data by means of a command to the I/O

module– I/O module obtains a unit of data– Data are transferred from the I/O module to the

processor


Processor CommunicationProcessor Communication External DevicesExternal Devices

• Processor communication – Command decoding

• I/O module accepts commands from processor

– Data• Exchange data between processor and I/O

– Status reporting• It is important to know status of I/O module• Common status signal : BUSY, READY

– Address recognition• Each I/O device has an address• An I/O module must recognize one unique address for each

peripheral it controls


I/O Device Data RatesI/O Device Data Rates External DevicesExternal Devices


Device CommunicationDevice Communication External DevicesExternal Devices

• Device communication involves commands, status information, and data


Data BufferingData Buffering External DevicesExternal Devices

• Data coming from main memory are sent to an I/O module in a rapid burst

• Data are buffered in the I/O module and then sent to the peripheral device at its data rate

• In opposite direction, data I/O module must be able to operate at both device and memory speeds.


Error DetectionError Detection External DevicesExternal Devices

• I/O module is responsible for error detection and for subsequently reporting errors to the processor


I/O Module StructureI/O Module Structure External DevicesExternal Devices

• Connect to the rest of the computer through a set of signal lines

• I/O module functions to allow the processor to view a wide range of devices in a simple-minded way

• I/O channel (I/O processor)– Takes most of the detailed processing burden – Used on mainframes

• I/O controller (Device controller) – Quite primitive and requires detailed control– Commonly seen on the microcomputer


Block Diagram of an I/O ModuleBlock Diagram of an I/O Module External DevicesExternal Devices


I/O Module DecisionsI/O Module Decisions Programmed I/O

• Hide or reveal device properties to CPU• Support multiple or single device• Control device functions or leave for CPU• Also O/S decisions

– e.g. Unix treats everything it can as a file


Techniques for I/O OperationsTechniques for I/O Operations Programmed I/O

• Programmed I/O • Interrupt driven I/O• DMA

No Interrupts Use of InterruptsI/O-to-memory transfer through processor

Programmed I/O Interrupt-driven I/O

Direct I/O-to-memory transfer

Direct memory access (DMA)


Programmed I/OProgrammed I/O Programmed I/O

• CPU requests I/O operation• I/O module performs operation• I/O module sets status bits• CPU checks status bits periodically• I/O module does not inform CPU directly• I/O module does not interrupt CPU• CPU may wait or come back later


I/O CommandsI/O Commands Programmed I/O

• Four type I/O commands– Control

• Activate a peripheral and tell it what to do

– Ex. Magnetic-tape rewind, forward…– Test

• Test a various status conditions associated with an I/O module and its peripherals

– Read• Obtain an item of data from the peripheral and place it in an

internal buffer(Fig6.4 data register)

– Write• Take an item of data(byte or word) from the data bus and

transmit that data item to the peripherals


Programmed I/O Programmed I/O Programmed I/O


I/O InstructionsI/O Instructions Programmed I/O

• Instructions are easily mapped into I/O commands

• The form of the instruction depends on the way in which external devices are addressed

• Each I/O device is given a unique identifier or address

• The command issued by processor contains the address of the desired device

• Each I/O module must interpret the address lines to determine if the command is for itself


Addressing I/O DevicesAddressing I/O Devices Programmed I/O

• Under programmed I/O data transfer is very like memory access (CPU viewpoint)

• Each device given unique identifier• CPU commands contain identifier

(address)


I/O InstructionsI/O Instructions Programmed I/O

• Two modes of addressing– Memory mapped I/O

• Single address space for memory locations and I/O devices• The processor treats the status and data registers of I/O

modules as memory locations• The processor uses same machine instruction to access both

memory and I/O devices– Isolated I/O

• Address space for I/O is isolated from memory• Need I/O or memory select lines• Special commands for I/O


MemoryMemory--Mapped and Isolated I/OMapped and Isolated I/O Programmed I/O

•• I/O ports are I/O ports are accessible only by accessible only by special I/O commandsspecial I/O commands

•• assume a 10bit addressassume a 10bit address-- 512 bit memory 512 bit memory (location 0(location 0--511)511)

-- 512 I/O addresses512 I/O addresses(location 512(location 512--1023)1023)


Memory Mapped and Isolated I/OMemory Mapped and Isolated I/O Programmed I/O

• If isolated I/O is used there are only a few I/O instructions

• Advantage of memory-mapped I/O– This large repertoire of instructions can be used,

allowing more efficient programming• Disadvantage of memory-mapped I/O

– Valuable address space is used up

• Both memory-mapped and isolated I/O are in common use


InterruptInterrupt--Driven I/ODriven I/O Interrupt-Driven I/O

• Problem of programmed I/O– The processor has to wait a long time for the I/O module

of concern to be ready for either reception or transmission of data

• Alternative– The processor issues an I/O command to a module and

go on to do some other useful work– Then the I/O module Interrupts the processor to request

service when it is ready to exchange data with the processor

– The processor then executes data transfer and resumes its former processing


InterruptInterrupt--Driven I/ODriven I/O Interrupt-Driven I/O

• Overcomes CPU waiting• No repeated CPU checking of device• I/O module interrupts when ready

• Interrupt I/O still consumes a lot of processor time because every word of data that goes from memory to I/O module or from I/O module must pass through the processor


InterruptInterrupt--Driven I/O Driven I/O Interrupt-Driven I/O


CPU ViewpointCPU Viewpoint Interrupt-Driven I/O

• Issue read command• Do other work• Check for interrupt at end of each

instruction cycle• If interrupted:-

– Save context (registers)– Process interrupt

• Fetch data & store

• See Operating Systems notes


Simple Interrupt ProcessingSimple Interrupt Processing Interrupt-Driven I/O


Interrupt ProcessingInterrupt Processing Interrupt-Driven I/O

• Sequence of hardware events1. Device issues an interrupt signal to processor 2. Processor finish execution of execution of current

instruction3. Processor signals acknowledgment of interrupt4. Processor push PSW and PC onto control stack5. Processor loads new PC value based on interrupt6. Save remainder of process state information7. Process interrupt restore process state

information8. Restore process state information9. Restore old PSW and PC


Changes in Memory & RegisterChanges in Memory & Register(a) Interrupt occurs after instruction at location N(a) Interrupt occurs after instruction at location N

Interrupt-Driven I/O


Changes in Memory & RegisterChanges in Memory & Register Interrupt-Driven I/O

(b) Return from interrupt(b) Return from interrupt


Design IssuesDesign Issues Interrupt-Driven I/O

• How does the processor determine which device issued the interrupt

• If multiple interrupts have occurred, how does the processor decide which one to process?



• How does the processor determine which device issued the interrupt

• Four device identification– Multiple interrupt lines– Software poll– Daisy chain(hardware poll, vectored)– Bus arbitration(vectored)


Multiple Interrupt LinesMultiple Interrupt Lines Interrupt-Driven I/O

• Most straightforward approach to the problem• Impractical to dedicate bus lines or processor

pins to interrupt lines• Each interrupt line has a priority• Higher priority lines can interrupt lower

priority lines• If bus mastering only current master can

interrupt


Software PollSoftware Poll Interrupt-Driven I/O

• On interrupt, the processor branches to an interrupt-service routine which it is to poll each I/O module to determine which module caused the interrupt

• The poll is in the form of a separate command line (TESTI/O)

• Each l/O module contains an addressable status register

• Read status register of each IO module to identify the interrupting module

• The disadvantage is time consuming


Daisy ChainDaisy Chain Interrupt-Driven I/O

• Called as a hardware poll• Vectored interrupt

– Vector • A word on the data lines• Address of the I/O module or unique identifier

– The processor uses vector as a pointer to the appropriate device routine

– Avoids the need to execute a general interrupt-service routine first


Bus ArbitrationBus Arbitration Interrupt-Driven I/O

• Another technique that makes use of vectored interrupts

• I/O module must first gain control of the bus before it can raise the interrupt request line

• One module can raise the line at a time• On interrupt, the processor responds on the

interrupt acknowledgement line• The requesting module places its vector on

the data lines



• If multiple interrupts have occurred, how does the processor decide which one to process?

• With multiple lines, the processor just picks the interrupt line with the highest priority

• With software polling, the order in which modules are polled determines their priority

• The order of modules on a daisy chain determines their priority

• The bus arbitration can employ a priority scheme


Example Example -- PC BusPC Bus Interrupt-Driven I/O

• 80x86 has one interrupt line• 8086 based systems use one 8259A

interrupt controller• 8259A has 8 interrupt lines


Sequence of EventsSequence of Events Interrupt-Driven I/O

• 8259A accepts interrupts• 8259A determines priority• 8259A signals 8086 (raises INTR line)• CPU Acknowledges• 8259A puts correct vector on data bus• CPU processes interrupt


ISA Bus Interrupt SystemISA Bus Interrupt System Interrupt-Driven I/O

• ISA bus chains two 8259As together• Link is via interrupt 2• Gives 15 lines

– 16 lines less one for link• IRQ 9 is used to re-route anything trying to

use IRQ 2– Backwards compatibility

• Incorporated in chip set


Intel 82C59A Interrupt ControllerIntel 82C59A Interrupt Controller Interrupt-Driven I/O

• Intel 80396 provides a single interrupt request (INTR) and a single acknowledge (INTA)

• Configured with an external interrupt arbiter, 82C59A which manages interrupt

• Interrupt modes– Fully nested

• Interrupt requests are ordered in priority from 0 (IR0) through 7 (IR7)

– Rotating• Receives the lowest priority in the group

– Special mask• The processor to allow inhibit interrupt from certain devices


82C59A Interrupt Controller82C59A Interrupt Controller Interrupt-Driven I/O


Intel 82C55A Intel 82C55A Interrupt-Driven I/O

• General-purpose I/O module designed for use with the Intel 80386 processor


Using 82C55A Using 82C55A Interrupt-Driven I/O

Control keyboard and display


DMADMA Direct memory access

• Drawbacks of Programmed and Interrupt-Driven I/O– The processor intervenes in data transfer between

memory and an I/O module• Inherent drawbacks

– I/O transfer rate is limited– The processor is tied up in managing an I/O transfer

• A more efficient technique is required:– Direct memory access(DMA)


DMA Block DiagramDMA Block Diagram Direct memory access


DMA FunctionDMA Function Direct memory access

• DMA involves an additional module on system bus

• DMA module take over control of the system from processor

• Cycle stealing – DMA module in effect steals a bus cycle



• Issue a command to the DMA module, by sending to the DMA module the following information– Whether a read or write is requested, using the

read or write control line between the processor and the DMA module

– Address of I/O device involved, communicated on the data lines

– Starting location in memory to read from or write to, communicated on the data lines and stored by the DMA module in its address register

– The number of words to be read or written, again communicated via the data lines and stored in the data count register



• The DMA module transfers the entire block of data– One word at a time – Directly to or from memory– Without going through the processor

• When the transfer is complete, the DMA module sends an interrupt signal to the processor

• The processor is involved only at the beginning and end of the transfer


DMA TransferDMA Transfer Cycle StealingCycle Stealing Direct memory access

• DMA controller takes over bus for a cycle• Transfer of one word of data• Not an interrupt

– CPU does not switch context• CPU suspended just before it accesses bus

– i.e. before an operand or data fetch or a data write• Slows down CPU but not as much as CPU

doing transfer


Direct Memory Access Direct Memory Access Direct memory access


DMA & Interrupt Break PointDMA & Interrupt Break Point Direct memory access


Alternative DMA ConfigurationAlternative DMA Configuration Direct memory access

• Single-Bus, Detached DMA• All modules share the same system bus

• Each transfer uses bus twice• I/O to DMA then DMA to memory

• CPU is suspended twice



• Single-Bus, Integrated DMA-I/O• There is a path between the DMA module and one

or more I/O modules• Controller may support >1 device• Each transfer uses bus once

• DMA to memory• CPU is suspended once



• I/O Bus• Connecting I/O modules to the DMA module using an I/O bus• This reduces the number of I/O interfaces in the DMA module to

one and provides for an easily expandable configuration• Each transfer uses bus once

• DMA to memory• CPU is suspended once


Evolution of I/O FunctionsEvolution of I/O Functions I/O Channels & Processors

• Evolutionary steps1. CPU directly controls a peripheral device2. Controller or I/O module is added3. Same configurations is used, but now interrupts

are employed4. I/O module is given direct access to memory via

DMA5. I/O module is enhanced to become a processor in

its own right, with a specialized instruction set tailored for I/O (I/O channel)

6. I/O module has a local memory of its own and is a computer in its own right (I/O processor)


Evolution of I/O FunctionsEvolution of I/O Functions I/O Channels & Processors

• More and more of the I/O function is performed without CPU involvement

• The CPU is increasingly relieved of I/O-related tasks, improving performance


Characteristics of I/O ChannelsCharacteristics of I/O Channels I/O Channels & Processors

• The I/O channel represents an extension of DMA concept

• The I/O channel has the ability to execute I/O instruction

• The CPU does not execute I/O instruction• Two types of I/O channels

– Selector channel– Multiplexor channel


Selector ChannelsSelector Channels I/O Channels & Processors

• Controls multiple high-speed devices• Is dedicated to the transfer of data with one of

those devices• Each device, or a small set of devices, is

handled by a controller, or I/O module, that is much like the I/O modules


MultiplexorMultiplexor ChannelChannel I/O Channels & Processors

• Handles I/O with multiple devices at the same time

• For low speed devices, a byte multiplexoraccepts or transmits characters as fast as possible to multiple devices

• For high speed devices, a block multiplexorinterleaves blocks of data from several devices


I/O Channel ArchitectureI/O Channel Architecture I/O Channels & Processors


Types of InterfacesTypes of Interfaces External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• Parallel interface– Multiple lines connecting the I/O module and the

peripheral– Multiple bits are transferred simultaneously– Used for higher speed peripherals (tape,disk)

• Serial interface– One line used to transmit data – Bits must be transmitted one at a time– Printer, terminals


Dialogue for a Write OperationDialogue for a Write Operation External Interface: External Interface: SCSI and FireWireSCSI and FireWire

1. The I/O module sends a control signal requesting permission to send data

2. The peripheral acknowledges the request3. The I/O module transfers data4. The peripheral acknowledges receipt of the

data

(read operation proceeds similarly)


Parallel and Serial I/OParallel and Serial I/O External Interface: External Interface: SCSI and FireWireSCSI and FireWire


PointPoint--toto--Point & MultipointPoint & Multipoint External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• Point-to-point– Provides a dedicated line between the I/O module

and the external device– On small systems (PC, WS), typical links include

keyboard, printer, and external modem• Multipoint

– Used to support external mass storage devices (disk, type) and multimedia devices (CD-ROM, video)

– These interfaces are in effect external buses


Fire Wire Serial BusFire Wire Serial Bus External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• FireWire– IEEE standard 1394, for a high-performance serial

bus• Advantages

– High speed– Low cost– Easy to implement

• Also being used in digital cameras, VCRs and TV


Fire Wire Serial BusFire Wire Serial Bus External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• Use serial transmission (bit at a time) rather than parallel

• Computers are getting physically smaller • Provides a single I/O interface with a simple

connector • User can reach behind the machine and plug

it in without looking


FireWire ConfigurationsFireWire Configurations External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• Use a daisy chain• Provides for what is known as hot plugging• Up to 63 devices on single port

– Really 64 of which one is the interface itself• Up to 1022 buses can be connected with

bridges• Automatic configuration• No bus terminators• May be tree structure


FireWire ConfigurationsFireWire Configurations External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• System automatically perform a configuration function to assign addresses

• Tree structured configuration is possible• Three layer of the stack

– Physical layer• Defines the transmission media

– Link layer• Describes the transmission of data in the packets

– Transaction layer• Defines a request-response protocol that hides the lower

layer details of FireWire from applications


FireWire ConfigurationFireWire Configuration External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• No terminations• The system automatically performs a

configuration function to assign addresses


FireWire 3 Layer StackFireWire 3 Layer Stack External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• Physical– Transmission medium, electrical and signaling

characteristics• Link

– Transmission of data in packets• Transaction

– Request-response protocol


FireWire Protocol StackFireWire Protocol Stack External Interface: External Interface: SCSI and FireWireSCSI and FireWire


Physical LayerPhysical Layer External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• Several alternative transmission media and their connectors

• Tree structured arrangement of the node• Data rates from 25 to 400Mbps • Two forms of arbitration

– Tree-structured arrangement• Linear daisy chain

– Supplemented by two additional functions• Fair arbitration• Urgent arbitration


Link LayerLink Layer External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• Two types of transmission– Asynchronous

• A variable amount of data and several bytes of transaction layer information are transferred as a packet to an explicit address and an acknowledgement is returned

– Isochronous• A variable amount of data is transferred in a sequence of

fixed size packets transmitted at regular intervals• This uses simplified addressing and no acknowledgement


Link LayerLink Layer External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• Subaction consists of five time periods– Arbitration sequence

• The exchange of signals required to give one device control of the bus

– Packet transmission• Every packet includes a header containing the source and

destination IDs.• A packet may also include a data block

– Acknowledgement gap• The time delay for the destination to receive and decode a

packet and generate an acknowledgment– Acknowledgment– Subaction gap

• An enforced idle period


FireWire FireWire SubactionsSubactions External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• Example Asynchronous Subactions



• Concatenated Asynchronous Subactions

• At the time that the acknowledgment is sent, the acknowledging node is in control of bus.

• If the exchange is a request/response interaction between two nodes then the responding node can immediately transmit the response packet without going through an arbitration sequence



• Example Isochronous Subactions

• A mixed traffic load of isochronous and asynchronous• One node is designated as cycle master• The cycle master issues a cycle_start packet• During this cycle, only isochronous packets may be sent• Each isochronous data source arbitrates for bus access. • The winning node transmits a packets• no acknowledgment• Other isochronous data sources immediately arbitrate for the bus

after the previous isochronous packet is transmitted• A small gap between the transmission of one packet and the

arbitration period for the next packet


InfiniBandInfiniBand External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• I/O specification aimed at high end servers– Merger of Future I/O (Cisco, HP, Compaq, IBM) and

Next Generation I/O (Intel)• Version 1 released early 2001• Architecture and spec. for data flow between

processor and intelligent I/O devices• Intended to replace PCI in servers• Increased capacity, expandability, flexibility


InfiniBandInfiniBand ArchitectureArchitecture External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• Remote storage, networking and connection between servers

• Attach servers, remote storage, network devices to central fabric of switches and links

• Greater server density• Scalable data centre• Independent nodes added as required• I/O distance from server up to

– 17m using copper– 300m multimode fibre optic– 10km single mode fibre

• Up to 30Gbps


InfiniBandInfiniBand Switch FabricSwitch Fabric External Interface: External Interface: SCSI and FireWireSCSI and FireWire


InfiniBandInfiniBand OperationOperation External Interface: External Interface: SCSI and FireWireSCSI and FireWire

• 16 logical channels (virtual lanes) per physical link

• One lane for management, rest for data• Data in stream of packets• Virtual lane dedicated temporarily to end t

o end transfer• Switch maps traffic from incoming to outg

oing lane


InfiniBandInfiniBand Protocol StackProtocol Stack External Interface: External Interface: SCSI and FireWireSCSI and FireWire

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