chapter 6 thermal design considerations - … · april 2000 6 - 3 philips semiconductors ic...
TRANSCRIPT
CHAPTER 6
THERMAL DESIGN CONSIDERATIONS
page
Introduction 6 - 2
Thermal resistance 6 - 2
Junction temperature 6 - 2
Factors affecting Rth(j-a) 6 - 2
Thermal resistance test methods 6 - 3
Test procedure 6 - 3
Forced air factors for thermal resistance 6 - 4
Thermal resistance data - assumptions and precautions 6 - 5
Thermal resistance (Rth(j-a)) data 6 - 6
Thermal resistance (Rth(j-c)) data tables - power packages 6 - 24
April 2000 6 - 2
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
INTRODUCTION
The ability to describe the thermal performancecharacteristics of a semiconductor IC package isbecoming increasingly crucial. With increased powerdensities, improved reliability and shrinking system sizes,the cooling of IC packages has become a challenging taskfor design engineers. The situation is further exacerbatedby the demand for ever decreasing sizes of electronicdevices because, in general, decreasing the size of anelectronic package decreases the thermal performance.The designer must carefully balance the benefits ofminiaturization and performance against the potentialreduction in reliability of electronic components resultingfrom high operating temperatures.
THERMAL RESISTANCE
The ability of a particular semiconductor package todissipate heat to its environment is expressed in terms ofthermal resistance (Rth(j-a)). This single entity describesthe heat path impedance from the active surface of thesemiconductor device (junction) to the ambient operatingenvironment. Rth(j-a) can be expressed by its constituentsas follows:
Rth(j-a) = Rth(j-c) + Rth(c-a)
Rth(j-c) is the impedance from junction to case (outsidesurface of package) and Rth(c-a) is the impedance fromcase to ambient. It is sometimes useful to use only theRth(c-a) to describe high performance packages wherecase temperatures are important and externally attachedheat radiators may need to be attached. In these cases theoverall Rth(j-a) will also include the contribution of the heatradiator.
JUNCTION TEMPERATURE
With the Rth(j-a) of a package known, the rise in junctiontemperature (Tj) with respect to the ambient temperature(Tamb) can be determined at a given power dissipation (Pd)of the semiconductor device:
Tj = (Rth(j-a) × Pd) + Tamb
Where:Tj = junction temperature (°C)Rth(j-a) = thermal resistance junction to ambient (K/W)Pd = power dissipated (W)Tamb = ambient temperature (°C)
It’s important to note that a lower Rth(j-a) indicates a higherthermal performance.
FACTORS AFFECTING Rth(j-a)
There are several factors which affect the characteristicthermal resistance of IC packages. Some of the moresignificant of these include the test board configuration,the lead frame material, the design of the lead frame andthe moulding compound.
Test board Configuration
An IC package’s thermal resistance highly depends on thePrinted Circuit Board (PCB) on which the package ismounted. The copper traces and thermal vias on the PCBprovide the major heat dissipation path of the package,therefore the configuration and the size of the coppertraces play a significant role in affecting Rth(j-a). For testpurpose, JEDEC standards (EIA/JEDEC51-3 and others)specify two categories of test boards: low effective thermalconductivity test board (low K board) and high effectivethermal conductivity test board (high K board). The low Kboard is a single sided board with only fine signal traces,the high K board is a board with two signal layers and twopower (or ground) layers. The real application board isalmost always different from the standard test boards,however, the thermal resistance measured from thestandard test board provides basic comparableinformation of the IC package thermal resistance.
Lead Frame Material
The lead frame material is one of the more importantfactors in IC package thermal resistance. In early dualin-line packages (DIPs), a Ni/Fe alloy (A42) was thematerial of choice for lead frames as it provided a goodcombination of strength and formability as well asassembly process compatibility. However, with thecontinued miniaturization of IC packages and the need forincreased electrical conductivity for advanced ICs, aswitch to sophisticated copper alloys was required.Copper alloy lead frames offer several advantages overA42:
• they have a high thermal conductivity which reducesthermal resistance, essential for packages such as theShrink Small Outline Package (SSOP) and Thin ShrinkSmall Outline Package (TSSOP)
• their improved electrical conductivity enhances theelectrical performance of a package
Most plastic encapsulated packages produced by PhilipsSemiconductors incorporate copper alloy lead frames intotheir design.
April 2000 6 - 3
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Lead Frame Design
The design of a lead frame is another significantcontributing factor to thermal resistance. The mostimportant design aspect is the IC attach-pad size and tiebar design. However, the lead frame designer is oftenfaced with fixed parameters such as die size and wirebonding limitations, which reduce lead frame designflexibility.
Moulding Compound
Moulding compounds also determine IC package thermalresistance. The mould compounds used by PhilipsSemiconductors are optimized for high purity and quality toprovide good thermal performance and reliability.
Heat Spreaders
The option of a heat spreader, or heat slug, within somepackages can improve thermal behaviour by spreading theheat over a larger area of the package, and so improveRth(j-a) or Rth(j-c).
Adhesive and Plating Type
Other package related factors include die attach adhesiveand lead frame plating type, but the actual influence onthermal resistance is small owing to the fine geometry ofthese factors.
THERMAL RESISTANCE TEST METHODS
Philip Semiconductors uses what is commonly called theTemperature Sensitive Parameter (TSP) method whichmeets EIA/JEDEC Standards EIA/JESD51-1,EIA/JESD51-2 and EIA/JESD51-3. A typical test fixture instill air is shown in Fig.1. The enclosure is a box with aninside dimension of 1 ft3 (0.0283 m3). The enclosure andfixtures are constructed from an insulating material with alow thermal conductance, and all seams thoroughly sealedto ensure there is no airflow through the enclosure. The ICpackage is then positioned in the geometric center of theenclosure.
The forward voltage drop of a calibrated diodeincorporated into a special IC is used to correlate ajunction temperature change in the IC package to betested. As the power dissipation is known, the thermalresistance can be calculated using the following equation:
Where:Rth(j-a) = thermal resistance junction to ambient (°C/W)Tj = junction temperature (°C)Pd = power dissipated (W)Tamb = ambient temperature (°C)
TEST PROCEDURE
The TSP diode on the semiconductor device is calibratedusing a constant temperature oil bath and a constantcurrent power supply (see Fig.2). Calibration temperaturesare typically 25 °C and 100 °C with a measured accuracyof ±0.1 °C. The calibration current must be kept low andconstant to avoid significant junction heating. Thetemperature coefficient (K-factor) shown in Fig.3 iscalculated using the following equation:
Where:K = temperature coefficient (°C/mV)T2 = high test temperature (°C)T1 = low test temperature (°C)VF2 = forward voltage at T2 (mV)VF1 = forward voltage at T1 (mV)
Fig.1 The test fixture in still air.
������
��������������������
Package
Cables
MSC599
Box
Substrate
Thermocouple
Rth j a–( )∆Tj
Pd---------
Tj Tamb–( )Pd
-----------------------------= =
KT2 T1–( )
VF2 VF1–( )------------------------------=
April 2000 6 - 4
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
With the K-factor determined, Rth(j-a) can be calculated bypowering up the device at ambient conditions andmeasuring the forward voltage drop across the TSP diodeafter temperature equilibrium. Manipulating the originalthermal resistance equation with the K-factor, the Rth(j-a) ofthe package can be determined:
Fig.2 Test procedure.
handbook, halfpage
MSB474
VF
IF
D = ON DIE TSPDIODE
D
OIL BATHMAINTAINEDAT CONSTANTTEMPERATURE
I = CONSTANT
Fig.3 VF as a function of Tj.
handbook, halfpage
MSB473
VF1
V (V)F
VF2
T1 T2 T ( C)jo
Rth j a–( )∆Tj
Pd---------
Tj Tamb–( )Pd
-----------------------------K VF amb( ) VF s( )–( )
VH IH×------------------------------------------------= = =
Where:VF(amb) = forward voltage of TSP at ambient
temperature (mV)VF(s) = forward voltage of TSP at steady-state
temperature (mV)VH = heating voltage (V)IH = heating current (A)
FORCED AIR FACTORS FOR THERMAL RESISTANCE
Many applications with ICs have the benefit of forced aircooling by fans or other means. The junction to moving-airthermal resistance can be measured by placing the testsetup inside a low velocity wind tunnel (see Fig.4). The testboard and device under test are supported with minimalobstruction to the air flow.
The average effect of airflow on thermal resistance forpackage types at a particular air flow rate can bedetermined using a “derating” curve (see Fig.5). Whenusing derating curves, it’s important to note that the varietyof sizes in a package type group has been averaged. Seethe following section on “Thermal resistance data -assumptions and precautions” concerning airflow.
Fig.4 Wind tunnel - dimensions in cm (inches).
MSB475
�FAN
TESTPART
ANEMOMETER
AIR FLOW
FLOWSTRAIGHTENER
43 (19)
35.5(14)
58.5 (23)132 (52)
183 (72)
DIAMETER = 15 (6)not to scale
April 2000 6 - 5
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
THERMAL RESISTANCE DATA -ASSUMPTIONS AND PRECAUTIONS
The graphical data presented in this section are based onmeasurements , modelling and estimations . As with alldata, some assumptions and contributing factors shouldbe noted:
1. The “measured” thermal resistance of an IC packageis highly dependent on the configuration and size ofthe test board. Data may not be comparable betweendifferent semiconductor manufacturers because thetest boards may not be the same. Also, the thermalperformance of packages for a specific applicationmay be different than presented here because theconfiguration of the application boards may bedifferent than the test boards. Philip Semiconductorsuses low effective thermal conductivity test boards formost of its packages.
2. Device standoff is a factor in determining thermalresistance especially for surface mounted packagessuch as SO and QFP packages. The same packagefrom two different manufacturers will often havedifferent standoff from the test boards. In general, highstandoff corresponds to a higher thermal resistance.
3. The operating environment temperature must be usedas the ambient temperature when calculating junctiontemperatures in an application. The temperaturesinside an electronic enclosure are generally higherthan the room temperature.
4. When using airflow derating curves (see Fig.5), pleasenote that in actual applications where airflow isavailable, the flow dynamics may be more complexand turbulent than in a wind tunnel. Also, the manydifferent sizes of packages in a package family suchas QFP have been averaged to give one curve forease-of-use. Lastly, the test boards used in the windtunnel contribute significantly to forced convectionheat transfer and may not be similar to an actualapplication PC board, especially its size.
5. Thermal resistance will vary slightly as a function ofinput power. Generally, as the power input increases,thermal resistance decreases. Thermal resistancechanges approximately 5% for a 100% power change.
6. Thermal resistance data for some packages were notavailable at the time of publication. Please contactPhilips Semiconductors for information on packagesnot listed in this handbook.
7. All data presented are accurate to approximately±15%. For more specific information regarding anapplication, please contact Philips Semiconductors.
8. Philips Semiconductors is evaluating a new technique,which was described in the ESPRIT project DELPHI,to thermally characterize IC packages. This results ina description of the package by means of a resistornetwork, the so-called compact model. This resistornetwork gives an accurate model of the package andis valid for all practical environments. It is expectedthat these models can be imported into system- andPCB-level analyses tools in the near future. If yourequire more information about compact models,please contact the ATO-Innovation office in Nijmegen,the Netherlands tel. +31-24-3533085 orfax +31-24-3533350.
Fig.5 Average effect of airflow on Rth(j-a).
handbook, halfpage
0 5
0
−50
−40
MSC554
−30
−20
−10
1 2 3 4air flow (m/s)
percent changein Rth(j-a) (%)
SOSOLSDIP
PLCC/QFP
DIPLQFP
April 2000 6 - 6
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
THERMAL RESISTANCE (R th(j-a) ) DATA
Fig.6 DIP8 (300 mil).
handbook, halfpage
0
120
110
100
9010 20 30
die size (mm2)
Rth(j-a)(K/W)
MBK303
Fig.7 DIP14/16 (300 mil).
handbook, halfpage
0
100
90
70
80
6010 20 30
die size (mm2)
Rth(j-a)(K/W)
MBK305
Fig.8 DIP18 (300 mil).
handbook, halfpage
0
90
80
70
6010 20 30
die size (mm2)
Rth(j-a)(K/W)
MBK307
Fig.9 DIP20 (300 mil).
handbook, halfpage
0
80
70
60
5010 20 30
die size (mm2)
Rth(j-a)(K/W)
MBK304
April 2000 6 - 7
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.10 DIP22 (400 mil).
handbook, halfpage
0
65
60
55
5010 20 30
die size (mm2)
Rth(j-a)(K/W)
MBK306
Fig.11 DIP24 (300 mil).
handbook, halfpage
0
70
65
55
60
5010 20 30
die size (mm2)
Rth(j-a)(K/W)
MBK308
Fig.12 DIP24 (400 mil).
handbook, halfpage
0
70
60
50
4010 20 30 40
die size (mm2)
Rth(j-a)(K/W)
MBK309
Fig.13 DIP24 (600 mil).
handbook, halfpage
0
60
55
50
40
45
10 20 30 40die size (mm2)
Rth(j-a)(K/W)
MBK311
April 2000 6 - 8
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.14 DIP28 (600 mil).
handbook, halfpage
0
55
50
45
4010 20 30 5040
die size (mm2)
Rth(j-a)(K/W)
MBK310
Fig.15 DIP40 (600 mil).
handbook, halfpage
0
50
45
40
3520 40 60 80
die size (mm2)
Rth(j-a)(K/W)
MBK312
Fig.16 DIP48 (600 mil).
handbook, halfpage
0
50
45
40
3520 40 60 80
die size (mm2)
Rth(j-a)(K/W)
MBK314
Fig.17 HSQFP240 (32 × 32 × 3.4 mm).
handbook, halfpage
0
22
20
18
16
14
12100 300200 400 500
die size (mm2)
Rth(j-a)(K/W)
MBK319
April 2000 6 - 9
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.18 LQFP32 (5 × 5 × 1.4 mm)
handbook, halfpage
0
100
95
85
90
805 10 15
die size (mm2)
Rth(j-a)(K/W)
MBK316
Fig.19 LQFP32 (7 × 7 × 1.4 mm).
handbook, halfpage
0
100
90
80
70
6010 20 30
die size (mm2)
Rth(j-a)(K/W)
MBK318
Fig.20 LQFP44 (10 × 10 × 1.4 mm)
handbook, halfpage
0
70
65
60
55
5020 40 60 80
die size (mm2)
Rth(j-a)(K/W)
MBK320
Fig.21 LQFP48 (7 × 7 × 1.4 mm).
handbook, halfpage
0
90
70
80
6010 20 30
die size (mm2)
Rth(j-a)(K/W)
MBK321
April 2000 6 - 10
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.22 LQFP64 (7 × 7 × 1.4 mm).
handbook, halfpage
0
80
75
70
6510 20 30
die size (mm2)
Rth(j-a)(K/W)
MBK323
Fig.23 LQFP64 (10 × 10 × 1.4 mm).
handbook, halfpage
0
70
65
60
55
5020 6040 80
die size (mm2)
Rth(j-a)(K/W)
MBK325
Fig.24 LQFP80 (12 × 12 × 1.4 mm).
handbook, halfpage
0
60
55
50
4520 40 8060
die size (mm2)
Rth(j-a)(K/W)
MBK322
Fig.25 LQFP100 (14 × 14 × 1.4 mm).
handbook, halfpage
0
60
55
50
45
4020 40 60 80 100
die size (mm2)
Rth(j-a)(K/W)
MBK324
April 2000 6 - 11
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.26 LQFP128 (14 × 14 × 1.4 mm).
handbook, halfpage
0
60
55
50
45
4020 40 8060 100
die size (mm2)
Rth(j-a)(K/W)
MBK326
Fig.27 PLCC20 (310 mil).
handbook, halfpage
0
82
70
74
78
6610 20 30
die size (mm2)
Rth(j-a)(K/W)
MBK327
Fig.28 PLCC28 (410 mil).
handbook, halfpage
0
80
70
60
5010 20 4030
die size (mm2)
Rth(j-a)(K/W)
MBK329
Fig.29 PLCC44 (610 mil).
handbook, halfpage
0
55
50
45
4020 40 80 10060
die size (mm2)
Rth(j-a)(K/W)
MBK328
April 2000 6 - 12
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.30 PLCC52 (710 mil).
handbook, halfpage
0
55
50
45
40
3520 40 60 80 100
die size (mm2)
Rth(j-a)(K/W)
MBK330
Fig.31 PLCC68 (910 mil).
handbook, halfpage
0
50
48
46
42
44
4040 12080 160
die size (mm2)
Rth(j-a)(K/W)
MBK332
Fig.32 PLCC84 (1110 mil).
handbook, halfpage
0
42
40
34
36
38
3220 40 60 80 100
die size (mm2)
Rth(j-a)(K/W)
MBK333
Fig.33 QFP44 (10 × 10 × 1.75 mm).
handbook, halfpage
0
75
70
65
60
55
5010 20 5030 40
die size (mm2)
Rth(j-a)(K/W)
MBK335
April 2000 6 - 13
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.34 QFP44 FeNi (14 × 14 × 2.2 mm).
handbook, halfpage
0
90
80
70
60
5020 6040 80
die size (mm2)
Rth(j-a)(K/W)
MBK337
Fig.35 QFP52 (10 × 10 × 2 mm).
handbook, halfpage
0
70
65
60
55
45
50
10 20 30 40 50die size (mm2)
Rth(j-a)(K/W)
MBK336
Fig.36 QFP64 (14 × 14 × 2.7 mm).
handbook, halfpage
0
60
55
50
45
4020 6040 80
die size (mm2)
Rth(j-a)(K/W)
MBK338
Fig.37 QFP64 (14 × 20 × 2.8 mm).
handbook, halfpage
0
55
50
40
45
3520 40 60 80 100
die size (mm2)
Rth(j-a)(K/W)
MBK339
April 2000 6 - 14
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.38 QFP80 (14 × 20 × 2.8 mm).
handbook, halfpage
0
55
50
45
40
3540 12080
die size (mm2)
Rth(j-a)(K/W)
MBK341
Fig.39 QFP100 (14 × 20 × 2.8 mm).
handbook, halfpage
0
52
48
44
40
368040 120
die size (mm2)
Rth(j-a)(K/W)
MBK343
Fig.40 QFP120 (28 × 28 × 3.4 mm).
handbook, halfpage
0
40
38
34
36
3240 80 160120
die size (mm2)
Rth(j-a)(K/W)
MBK340
Fig.41 QFP128 (28 × 28 × 3.4 mm).
handbook, halfpage
0
40
38
36
34
3240 80 120 160
die size (mm2)
Rth(j-a)(K/W)
MBK342
April 2000 6 - 15
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.42 QFP160 (28 × 28 × 3.4 mm).
handbook, halfpage
0
38
36
34
32
3040 12080 180160
die size (mm2)
Rth(j-a)(K/W)
MBK344
Fig.43 SDIP24 (400 mil).
handbook, halfpage
0
80
70
60
5010 20 30 40
die size (mm2)
Rth(j-a)(K/W)
MBK345
Fig.44 SDIP32 (400 mil).
handbook, halfpage
0
75
65
55
4510 4020 30
die size (mm2)
Rth(j-a)(K/W)
MBK347
Fig.45 SDIP42 (600 mil).
handbook, halfpage
0
70
60
50
40
304020 8060
die size (mm2)
Rth(j-a)(K/W)
MBK349
April 2000 6 - 16
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.46 SDIP52 (600 mil).
handbook, halfpage
0
50
45
35
40
3040 80 120
die size (mm2)
Rth(j-a)(K/W)
MBK346
Fig.47 SDIP64 (750 mil).
handbook, halfpage
0
42
38
34
3020 40 60 10080
die size (mm2)
Rth(j-a)(K/W)
MBK348
Fig.48 SO8 (150 mil).
handbook, halfpage
0
162
158
154
1502 4 6 108
die size (mm2)
Rth(j-a)(K/W)
MBK350
Fig.49 SO14 (150 mil).
handbook, halfpage
0
135
125
115
1052 1084 6
die size (mm2)
Rth(j-a)(K/W)
MBK352
April 2000 6 - 17
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.50 SO16 (150 mil).
handbook, halfpage
0
116
112
108
104
10042 1086
die size (mm2)
Rth(j-a)(K/W)
MBK354
Fig.51 SO16 (300 mil).
handbook, halfpage
0
104
100
92
96
885 10 2015
die size (mm2)
Rth(j-a)(K/W)
MBK351
Fig.52 SO20 (300 mil).
handbook, halfpage
0
94
90
86
825 10 2015
die size (mm2)
Rth(j-a)(K/W)
MBK353
Fig.53 SO24 (300 mil).
handbook, halfpage
0
80
76
72
6810 20 30
die size (mm2)
Rth(j-a)(K/W)
MBK355
April 2000 6 - 18
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.54 SO28 (300 mil).
handbook, halfpage
0
74
70
66
6210 20 30 40
die size (mm2)
Rth(j-a)(K/W)
MBK356
Fig.55 SO32 (300 mil).
handbook, halfpage
0
68
66
64
60
62
10 403020die size (mm2)
Rth(j-a)(K/W)
MBK358
Fig.56 SSOP14 (5.3 mm).
handbook, halfpage
0
160
155
150
145
14042 1086
die size (mm2)
Rth(j-a)(K/W)
MBK360
Fig.57 SSOP16 (4.4 mm).
handbook, halfpage
0
160
155
145
150
135
140
2 4 1086die size (mm2)
Rth(j-a)(K/W)
MBK357
April 2000 6 - 19
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.58 SSOP16 (5.3 mm).
handbook, halfpage
0
155
145
135
1252 4 1086
die size (mm2)
Rth(j-a)(K/W)
MBK359
Fig.59 SSOP20 (4.4 mm).
handbook, halfpage
0
150
140
130
1204 8 12
die size (mm2)
Rth(j-a)(K/W)
MBK361
Fig.60 SSOP20 (5.3 mm).
handbook, halfpage
0
140
130
120
100
110
2 4 86 10die size (mm2)
Rth(j-a)(K/W)
MBK362
Fig.61 SSOP24 (5.3 mm).
handbook, halfpage
0
130
120
110
90
100
5 201510die size (mm2)
Rth(j-a)(K/W)
MBK364
April 2000 6 - 20
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.62 SSOP28 (5.3 mm).
handbook, halfpage
0
120
110
100
90105 2015
die size (mm2)
Rth(j-a)(K/W)
MBK366
Fig.63 SSOP56 (7.5 mm).
handbook, halfpage
0
83
84
82
81
805 1510
die size (mm2)
Rth(j-a)(K/W)
MBK365
Fig.64 TQFP44 (10 × 10 × 1 mm).
handbook, halfpage
0
75
70
60
65
5520 40 8060
die size (mm2)
Rth(j-a)(K/W)
MBK367
Fig.65 TQFP64 (10 × 10 × 1 mm).
handbook, halfpage
0
75
70
65
50
55
60
20 40 60 80die size (mm2)
Rth(j-a)(K/W)
MBK368
April 2000 6 - 21
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.66 TQFP80 (12 × 12 × 1 mm).
handbook, halfpage
0
65
60
55
5020 806040
die size (mm2)
Rth(j-a)(K/W)
MBK370
Fig.67 TQFP100 (14 × 14 × 1 mm).
handbook, halfpage
0
60
55
50
454020 8060
die size (mm2)
Rth(j-a)(K/W)
MBK372
Fig.68 TSSOP14 (4.4 mm).
handbook, halfpage
0
180
170
150
160
2 4 86die size (mm2)
Rth(j-a)(K/W)
MBK369
Fig.69 TSSOP16 (4.4 mm).
handbook, halfpage
0
160
165
155
150
140
145
2 864die size (mm2)
Rth(j-a)(K/W)
MBK371
April 2000 6 - 22
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.70 TSSOP20 (4.4 mm).
handbook, halfpage
0
150
145
135
140
1302 4 1086
die size (mm2)
Rth(j-a)(K/W)
MBK373
Fig.71 TSSOP24 (4.4 mm).
handbook, halfpage
0
136
132
128
120
124
2 4 6 108die size (mm2)
Rth(j-a)(K/W)
MBK374
Fig.72 TSSOP28 (4.4 mm).
handbook, halfpage
0
130
125
120
1152 10864
die size (mm2)
Rth(j-a)(K/W)
MBK376
Fig.73 TSSOP48 (6.1 mm).
handbook, halfpage
0
106
104
100
102
9884 12
die size (mm2)
Rth(j-a)(K/W)
MBK378
April 2000 6 - 23
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
Fig.74 TSSOP56 (6.1 mm).
handbook, halfpage
0
98
96
90
92
94
4 128die size (mm2)
Rth(j-a)(K/W)
MBK375
Fig.75 VSO40 FeNi (7.5 mm).
handbook, halfpage
0
125
120
115
11010 403020
die size (mm2)
Rth(j-a)(K/W)
MBK377
Fig.76 VSO56 FeNi (11 mm).
handbook, halfpage
0
108
104
100
9610 20 4030
die size (mm2)
Rth(j-a)(K/W)
MBK379
April 2000 6 - 24
Philips Semiconductors IC Packages
Thermal design considerations Chapter 6
THERMAL RESISTANCE (R th(j-c) ) DATA TABLES - POWER PACKAGES (1)
Note
1.
a) Almost all of the values in the table were determined with measurements.
b) Low values should be used with a large die, high values should be used with a small die.
PACKAGE NAME PHILIPS OUTLINE CODE R th(j-c) (K/W) GLUED DIE Rth(j-c) (K/W) SOLDERED DIE
DBS9MPF SOT111-1 6.0 to 12.0 n.a.
DBS9P SOT157-2 1.0 to 4.0 0.8 to 3.0
DBS13P SOT141-6 1.0 to 4.0 0.8 to 3.0
DBS17P SOT243-1 1.0 to 4.0 0.8 to 3.0
DBS23P SOT411-1 n.a. 0.8 to 3.0
HSOP20 SOT418-2 1.0 to 4.0 0.8 to 3.0
RBS9MPF SOT352-1 6.0 to 12.0 n.a.
RDBS13P SOT462-1 1.0 to 4.0 0.8 to 3.0
SIL9MPF SOT110-1 6.0 to 12.0 n.a.
SIL9P SOT131-2 1.0 to 4.0 0.8 to 3.0
SIL13P SOT193-2 1.0 to 4.0 0.8 to 3.0