chapter 6 modular squential circuits & applications 6-1counter 6-2register 6-3sequence generator...

CHAPTER 6 MODULAR SQUENTIAL CIRCUITS & APPLICATIONS

6-1 Counter

6-2 Register

6-3 Sequence generator

6-4 Digital Clock

Summary

6-1 Counter6-1 Counter

Clocking way, asynchronous and synchronous

Number of states, modulo-2,10 or arbitrary.

Type of Sequence, up, down and bi-direction.

Scale, SSI and MSI

Aiming at count the number of pulse inputted1.Categories of counter

2.MSI Counter2.MSI Counter

（ 3 ） MSI Asynchronous Counter

（ 2 ） 4-Bit Binary Up/Down Counter

（ 1 ） 4-Bit Synchronous Binary Counter



2. 4-Bit Synchronous Binary Counter CT74163

1. 4-Bit Synchronous Binary Counter CT74161

3. CT74161/ CT74163 Function Extension

1. 4-Bit Synchronous Binary Counter CT74161 1. 4-Bit Synchronous Binary Counter CT74161

It consist of 4 master-slave J-K flip-flops.

(1) Logic Symbol

D A: highlowCP: clock pulse ， Leading Edge Triggered.R: Asynchronous Clear, Active-Low.LD: Synchronous Preset, Active-Low

QD QA: highlow

P 、 T ： Enable

Input Output

CP R LD P(S1) T(S2) A B C D QA QB QC QD

Ф 0 Ф Ф Ф ФФФФ 0 0 0 0

↑ 1 0 Ф Ф A B C D A B C D

Ф 1 1 0 Ф ФФФФ keep unchanged

Ф 1 1 Ф 0 ФФФФ keep unchanged

↑ 1 1 1 1 ФФФФ count

CT74161 Function TableCT74161 Function Table

1)Asynchronous Clear: if R=0 ， output will be “0000”, having nothing to do with CP.

2) Synchronous Preset: if R=1 and LD=0 ， output reflect the data inputs in response to a leading edge of CP.

3)keep: if R=LD=1 ， all flip-flops will keep unchanged.

4)count: if LD = R = P= T = 1 ， count in binary system. If the first state is 0000,after 15 CP,the output is “1111” ，the ripple clock output (RCO) QCC = TQAQBQCQD =1 。 After 16th CP, the output return 0000 and QCC = 0.

(2) Function1. 4-Bit Synchronous Binary Counter CT74161 1. 4-Bit Synchronous Binary Counter CT74161

Input Output

CP R LD P(S1) T(S2) A B C D QA QB QC QD

Ф 0 Ф Ф Ф ФФФФ 0 0 0 0

↑ 1 0 Ф Ф A B C D A B C D

Ф 1 1 0 Ф ФФФФ keep unchanged

Ф 1 1 Ф 0 ФФФФ keep unchanged

↑ 1 1 1 1 ФФФФ Count

↑

2. 4-Bit Synchronous Binary Counter CT74163 2. 4-Bit Synchronous Binary Counter CT74163

CT74163 Function TableCT74163 Function TableCT74161

Function Table

CT74161 Function Table

There is an active-LOW clear input, which

synchronously reset all four outputs in a positive

transition on the CP input.

(1) Pin arrangement is same as CT74161.

(2) The functions of Preset, Count and Remain are same as CT74161.(3)The Clear is different from CT74161.

2. 4-Bit Synchronous Binary Counter CT741632. 4-Bit Synchronous Binary Counter CT74163

Characteristics:

Comparison of 4-Bit Synchronous Binary Counters

CT74163

Asynchronous ClearSynchronous PresetRemain

Count

CT74161

Synchronous Clear

Synchronous PresetRemain

Count

connected to achieve arbitrary modulo counter(1) Synchronous Preset

(2) Feedback Clear

(3) Multi-Preset

3. CT74161/ CT74163 Function Extension3. CT74161/ CT74163 Function Extension

Binary State Sequencecount outputN QD QC QB QA

0 0 1 1 01 0 1 1 12 1 0 0 03 1 0 0 14 1 0 1 05 1 0 1 16 1 1 0 07 1 1 0 18 1 1 1 09 1 1 1 1

Example 1: design a modulo-10 counter

Solution 1: with counting sequence 6,7,…,15

0110

QCC=1

0

(1) Synchronous Preset(1) Synchronous Preset

0110

Binary State SequenceCount OutputN QD QC QB QA

0 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 1


Solution 2: with counting sequence 0,1,…,9

0000

1001

0

(1) Synchronous Preset(1) Synchronous Preset

SimulationSimulation

0000

Example 3: : design a modulo-24 counter using Synchronous Preset

0001

1000

0

1000

0000

（ 24 ） 10= （ 11000 ） 2 2 chipsInitial state: 0000 0001 Last state: 00011000


(2) Feedback Clear

(3) Multi-Preset

3. CT74161/ CT74163 功能扩展 3. CT74161/ CT74163 功能扩展

Example 1: Function Analysis of The Following Circuits

0 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 110 1 0 1 011 1 0 1 112 1 1 0 0

using CT74161

0

0000

1

1

（ 2 ） Feedback Clear（ 2 ） Feedback Clear

Binary State Sequence

N QD QC QB QA


N QD QC QB QA

0 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 1

Using CT74161


0

0000


Example 3: design a modulo-13 counter Binary State SequenceN QD QC QB QA

0 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 110 1 0 1 011 1 0 1 112 1 1 0 0

Using CT74163

0

0000

SimulationSimulation



(2) Feedback Clear

(3) Multi-Preset

3. CT74161/ CT74163 功能扩展 3. CT74161/ CT74163 功能扩展

a modulo-10 counter


N QD QC QB QA

0 0 0 0 0

(3) Multi-PresetExample : Function Analysis of The Following Circuits

2 0 1 0 13 0 1 1 04 0 1 1 15 1 0 0 0

7 1 1 0 18 1 1 1 09 1 1 1 1

1 0 1 0 0

6 1 1 0 0

0010

0011

2. MSI Counter2. MSI Counter



(1) 4-Bit Synchronous Binary Counter

Input Output

CPU CPD R LD A B C D QA QB QC QD

φ φ 1 φ φ φ φ φ 0 0 0 0

φ φ 0 0 A B C D A B C D

↑ 1 0 1 φ φ φ φ up counting

1 ↑ 0 1 φ φ φ φ down counting

1 1 0 1 φ φ φ φ remain

(2) 4-Bit Binary Up/Down Counter CT74193


CT74193 Function TableCT74193 Function Table

D A:HIGHLOW

CPU 、 CPD :dual clock input

R: asynchronous clear,

active-HIGH.

LD: asynchronous preset,

active-LOW.

QD QA:HIGHLOW

DCBAUCC QQQQCPQ

DCBADCB QQQQCPQ

1. Logic Symbol

QCC=0 in last state

QCB=0 in the first state



—— connected to achieve arbitrary modulo counter

(1) achieve M<16 counter

(2) achieve M>16 counter

2. CT74193 Function Extension

(2) 4-Bit Binary Up/Down Counter CT74193(2) 4-Bit Binary Up/Down Counter CT74193

0 0 1 1 01 0 1 1 12 1 0 0 03 1 0 0 14 1 0 1 05 1 0 1 16 1 1 0 07 1 1 0 18 1 1 1 09 1 1 1 1

Example: design a modulo-9 counter using CT74193

Method 1: adopt asynchronous preset and up count.

（ 1 ） achieve M<16 counter


QCC=0

0110


N QD QC QB QA

0

110

Method 2: adopt asynchronous preset and down count.

0 1 0 0 11 1 0 0 02 0 1 1 13 0 1 1 04 0 1 0 15 0 1 0 06 0 0 1 17 0 0 1 08 0 0 0 19 0 0 0 0

QCB=0

1001


100

1

Binary State SequenceN QDQCQBQA



—— connected to achieve arbitrary modulo counter

(1) achieve M<16 counter

(2) achieve M>16 counter

2. CT74193 Function Extension

(2) 4-Bit Binary Up/Down Counter CT74193(2) 4-Bit Binary Up/Down Counter CT74193


Method 1: adopt asynchronous preset and up count.

M = (147)10

=(10010011)2

Need 2 chips of CT74193

100

1

110

0

000

0

000

0

（ 2 ） achieve M > 16 counter（ 2 ） achieve M > 16 counter

Method 2: adopt asynchronous preset and down count, take advantage

of QCB

M = (147)10

=(10010011)2

100

1

110

0

110

0

1001

Example: design a modulo-147 counter by using CT74193

（ 2 ） achieve M > 16 counter（ 2 ） achieve M > 16 counter

2. MSI Counter2. MSI Counter




Input Output

CP R0 （ 1 ） R0 （ 2 ） Sg （ 1 ） Sg （ 2 ） QA QB QC QD

Φ 1 1 0 Φ 0 0 0 0 1 1 Φ 0 0 0 0 0

Φ Φ 1 1 1 0 0 1

↓ Φ 0 Φ 0 Count 0 Φ 0 Φ 0 Φ Φ 0 Φ 0 0 Φ

（ 3 ） Asynchronous Counter CT74290


(1) Flip-Flop A ： M=2 CPA In, QA Out(2) Flip-Flop B, C, D ： M=5 As

ynchronous Counter.

CPB In QD QB Out

CPA 、 CPB: Clock Input

R01 、 R02: Clear

Sg1 、 Sg2 : set 9

QD QA:HighLow

1 . Logic Symbol



(2)Asynchronous Clear: if R01=R02=1 ， one of Sg1, Sg2 is Low ， output is “0000”,without regard to CP.

(1) Set 9 ： if Sg1= Sg2= 1 ， output is 1001.

(3)count: if one of R01 、 R02 and Sg1 、 Sg2 is Low and CP negative transition appear ， the

counter will perform.

2. Function

If QA is connected with CPB ,the counter will become an 8421BCD counter. CPA In QD QA Out

If QD is connected with CPA ,the counter will become a 5421BCD counter. CPB In,QAQD QC QB Out.



Example 1: design a modulo-6 counter using CT74290 .

Method 1: take advantage of R

0 0 0 0 01 1 0 0 02 0 1 0 03 1 1 0 04 0 0 1 05 1 0 1 06 0 1 1 0

0

1

1

0

0

0

0

0

M=6 Binary State Sequence

N QA QB QC QD


M=7

Binary State Sequence N QAQBQC QD

0 0 0 0 01 1 0 0 02 0 1 0 03 1 1 0 04 0 0 1 05 1 0 1 06 0 1 1 07 1 0 0 1

Method 2: take advantage of S

1

001

0

110


M=10

Binary State SequenceN QAQDQC QB

0 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 1 0 0 06 1 0 0 17 1 0 1 08 1 0 1 19 1 1 0 0

Requirement: adopt 5421 code

Example 3: design a modulo-88 counter using CT74290 .Method 3: 2 chips of CT74290 cascaded

0 1


6-1 Counter

6-2 Register


6-4 Digital Clock

Summary

Shift Register

Register

Unidirectional Shift RegisterBi-directional Shift Register

6-2 Register

For storage of data1. Category of Register

（ 1 ） MSI Register CT74175（ 1 ） MSI Register CT74175

It is consist of 4 D-Flip-Flops.

０　 φ 　 φ 0 1１　↑　１ 1 0１　↑　０ 0 1１　０　 φ Q

Q

Q

1.Logic Symbol

2. Function:

Input OutputR CP D Q

2. Register2. Register

（ 1 ） Shift Register（ 1 ） Shift Register

Assume flip-flop 4 is the lowest register and flip-flop 1 is the highest register.

According to the characteristic equation of D flip-flop:

DQ 14n 4n13n QQ 3n12n QQ 2n11n QQ When the clock pulse is applied,

State of lower flip-flop is shift into

the higher as its next state. Left Shift Register

To load data 1011:

1011

Serial Input only One data input line？

Solution: Four bits is entered into the register one by one when four clock pulses occurs.Left Shift Register: High-first, low-later.

Right Shift Register : Low-first, high-later

Owe to the circuit is a Left Shift Register, the sequence of data input is 1 0 1 1

CP Q4 Q3 Q2 Q1

To load data 1011 ， that is D1D2D3D4= 1011

1 1(D1) 0 0 0

2 0(D2) 1(D1) 0 0

3 1(D3) 0(D2) 1(D1) 0

4 1(D4) 1(D3) 0(D2) 1(D1)

10

1

1


Input Output

Q0 Q 1 Q 2 Q 3 3Q

1 ↑ 0 d0 …… d3 φ φ

0 0 0 0 1

d 0 d 1 d 2 d 3 3d

1 0 1 φ φ φ φ Q00 Q 10 Q20 Q30 30Q

1 ↑ 1 φ φ 0 1 Q 0n Q0n Q 1n Q2n n2Q

1 ↑ 1 φ φ 0 0 0 Q 0n Q1n Q2n n2Q

1 ↑ 1 φ φ 1 1 1 Q 0n Q 1n Q2n n2Q

0 φ φ φ φ φ φ

…… 3R CP LD

SH D 0 D J K

1 ↑ 1 φ φ 1 0 n0Q Q0n Q 1n Q2n n2Q

（ 2 ） 4-bit unidirectional Shift Register CT74195（ 2 ） 4-bit unidirectional Shift Register CT74195

(1) Clear: if R=0 ， output is “0000”.

(2) Load: if R=1 ， SH/LD=0, when CP occurs, parallel load.

(3) Right Shift:if R=1 ， SH/LD=1 ， when CP occurs, right shift.

Q0 is by JK, Q0Q1 ， Q1Q2 ， Q2Q3 。

2. Function1.Logic Symbol

（ 2 ） 4-bit unidirectional Shift Register CT74195（ 2 ） 4-bit unidirectional Shift Register CT74195

CT74195

Input OutputＱ０　　Ｑ1 　　Ｑ2 　　Ｑ 3

０　φ　　 φ　　　 φ　　　 φ　　 φ　　 φ　　 φ１　０　　 φ　　　 φ　　　 φ　　 φ　　 φ　　 φ

０　　　０　　　０　　　０remain　　

１　↑　　 φ　　　d0 …… d3 １　　１　　 φ d 0 d1 d2 d3

１　　Q Q 　Q１　↑　　１　　　 φ　　　 φ　　０　　１　　 φ 　 0n 1n 　 2n

１　↑　　０　　　 φ　　　 φ　　０　　１　　 φ 0 　 Q0n Q1n 　　Q2n

Q 　Q 　 Q 　１　↑　　 φ　　　 φ　　　 φ　　１　　０　　１ 1n 2n 3n 　１１　↑　　 φ　　　 φ　　　 φ　　１　　０　　０ Q Q Q1n 　　 2n 　

3n　 0

R 　 CP　 DSR　 D0 ……D3 MB　 MA　 DSL

１　 φ　　 φ　　　 φ　　　 φ　　０　　０　　 φ remain　　　


Note ： 0—Highest bit …... 3—Lowest bit

（ 3） 4-bit bi-directional Shift Register CT74194（ 3） 4-bit bi-directional Shift Register CT74194

(1) Clear: if R=0 ， asynchronous clear.

（ 2 ） if MA ＝ MB ＝１ ,parallel load.（ 3 ） if MA ＝ MB ＝０， remain.（ 4 ） if MA=1 ， MB=0 ， right shift and data is inputted serially from DSR.

（ 5 ） if MA=0 ， MB=1 ， left shift and data is inputted serially from DSL.

2. Function1.Logic Symbol

（ 3） 4-bit bi-directional Shift Register CT74194（ 3） 4-bit bi-directional Shift Register CT74194

2. Ring Counter

1. Data Conversion

3. Twisted-Ring Counter

4. Frequency-Division

（ 4 ） Application of Register（ 4 ） Application of Register

1. 7-bit SerialParallel Conversion1. 7-bit SerialParallel Conversion

Serial Parallel ParallelSerial

2. Ring Counter

1. Data Conversion




Example: design a M=4 Ring Counter by using CT74195

Binary State Sequence Ｑ０　　Ｑ１　　Ｑ２　　Ｑ３

１　　　０　　　０　　　００　　　１　　　０　　　００　　　０　　　１　　　００　　　０　　　０　　　１Notice ：

(1) besides effective states, there are still 5 ineffective states.

(2) It has not the ability of self-start. The set-up signal should be applied on SH/Ld to start the loop.

2.Ring Counter2.Ring Counter

Design of Ring CounterDesign of Ring Counter

（ 1 ） How to connect:The output of shift register Q3 is feedback to the input lines of Ｊ ,K.

(2)determine the number of flip-flops:Modulus of the counter M＝ｎ (n is the number of shift registers.)

2. Ring Counter

1. Data Conversion




Notice ：

(1) besides effective states, there is still an ineffective states.

(2) It has not the ability of self-start. The set-up pulse signal should be applied on R to clear.

Binary State SequenceQ0 Q1 Q2 Q3

0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1

Example: design a M=8 Twisted-Ring Counter

Design of Twisted-Ring CounterDesign of Twisted-Ring Counter

（ 1 ） How to connect:The output of shift register Q3 is feedback to the input lines of Ｊ ,K via an inverter.

(2)determine the number of flip-flops:Modulus of the counter M＝ 2ｎ (n is the number of shift registers.)

2. Ring Counter

1. Data Conversion




Frequency DividerFrequency Divider


6-1 Counter

6-2 Register


6-4 Digital Clock

Summary


1.Counter type Sequence generator

2. Feedback type Sequence generator

—maximum-length linear sequence generator

Periodical serial binary code which is arranged by a certain regulation

Arbitrary length sequential code

1. Counter type Sequence generator1. Counter type Sequence generator

2. Design the combinational Circuits for output data according to the requirement.

Counter + combinational logic circuits（ 1 ） Circuit Structure

（ 2 ） Design Procedure

1.design modulo-s counter according to the length of sequence. States can be determined freely.

Example: design a Sequence generator which can generate the code 110001001110

Step 1: design counter（ 1 ） Length of Sequence S=12 ， therefore a modulo-12 is a preference.（ 2 ） using CT74161（ 3 ） Synchronous preset （ 4 ） let effective states are QDQCQBQA=0100～ 1111.

0

010


Step 2: design combinational circuits

AQ

QD QC QB QA Z

0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0

（ 1） write out truth table.(2)Simplification

by using K-map(3) Implement logic function by using 8-input data selector:D0=D1=D3=D5=0,D2=D6=1D4=QA ， D7=


Step 3: draw the circuit diagram

D0=D1= D3

=D5=0D2=D6=1D4=QA ，

D7= AQ

Z



1.Counter type Sequence generator

2. Feedback type Sequence generator

—maximum-length linear sequence generator

2. Feedback type maximum-length linear sequence generator (m sequence generator)


2. Circuit Structure: shift register + exclusive-OR Gate

1. Length of maximum-length linear sequence ： S=2n-1

3. Design Procedure:

(1) According to S=2n-1 ， determine n.

(2) Look up table 6-31 to find out the feedback function f(Q).

(3) Draw the circuit diagram.

(4) Attach an anti-all-zero logic.

Example : Design an S=7 m sequence generator

Step 1: S=2n-1 ， therefore n =3.Step 2: Look up table 6-31 to find out the feedback function ： f(Q)=Q2⊕Q3 ( 即CT74194 的 DSR= Q1⊕Q2) 。Step 3 ： draw circuit diagram.



Step 4: add an all-zero correction

32132

32132

QQQQQ

QQQQQF(Q)

Step 5: draw the circuit diagram. By using all-zero state, reload data to implement self-start. The logic diagram is as follows.

Example : Design an S=7 m sequence generator




6-1 Counter

6-2 Register


6-4 Digital Clock

Summary

Digital Clock is a timing equipment to directly display time by digit, which is consist of crystal oscillator, frequency divider, counter, decoder, display,correction , power supply and so on.

6-4 igital Clock

A few most commonly used modular sequential circuits such as counter, register, shift register and sequence generator are discussed.

Counters can be divided into synchronous and asynchronous; synchronous counters have higher frequency and asynchronous counters have simpler circuits.

Shift registers can be divided into left shift registers, right shift registers and bi-directional shift registers.

Summary

（ 1 ） familiarize the function table of MSI modular sequential circuits ;

（ 2 ） master the function extension of MSI modular sequential circuits ;

（ 3 ） have the ability of applying the modular sequential circuits and combinational circuits to fulfill specific logic.

Objective

ExercisesExercises

6-1 6-3 6-7 6-9 6-11 6-12

6-14 6-15 6-19 6-22

chapter 6 modular squential circuits & applications 6-1counter 6-2register 6-3sequence generator...

Documents

q b q c q d

b c d q

active low q d q

count slide

categories of counter

binary updown counter

msi counter

synchronous preset simulation