chapter 6. dataflow modeling. continuous assignments the left hand side always be a scalar or vector...
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Chapter 6. Dataflow Modeling
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Continuous AssignmentsThe left hand side always be a scalar or vector
net or a concatenation of scalar and vector nets. It cannot be a scalar or vector register.
Continuous assignments are always active.
right-hand side can be registers or nets or function calls.
Delay values can be specified for assignments in terms of time units. It is very useful in modeling timing behavior in real circuits.
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Example 6-1 Examples of Continuous Assignment
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Implicit Continuous Assignment
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Regular Assignment Delayassign #10 out = in1 & in2; // Delay in a
continuous assign
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Net Declaration Delay
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Expressions
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Operands
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OperatorsOperator Type
Operator Symbol
Operation Performed
Number of Operands
Arithmetic */+-%**
multiplydivideaddsubtractmoduluspower (exponent)
twotwotwotwotwotwo
Logical !&&||
logical negationlogical andlogical or
onetwotwo
Relational ><>=<=
greater thanless thangreater than or equalless than or equal
twotwotwotwo
Equality ==!====!==
equalityinequalitycase equalitycase inequality
twotwotwotwo
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OperatorsOperator Type Operator Symbol Operation Performed Number of OperandsBitwise ~
&|^^~ or ~^
bitwise negationbitwise andbitwise orbitwise xorbitwise xnor
onetwotwotwotwo
Reduction &~&|~|^^~ or ~^
reduction andreduction nandreduction orreduction norreduction xorreduction xnor
oneoneoneoneoneone
Shift >><<>>><<<
Right shiftLeft shiftArithmetic right shiftArithmetic left shift
TwoTwoTwoTwo
Concatenation { } Concatenation Any numberReplication { { } } Replication Any numberConditional ?: Conditional Three
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If any operand bit has a value xin1 = 4'b101x; in2 = 4'b1010; sum = in1 + in2; // sum will be evaluated
to the value 4'bx
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Logical operators
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Equality Operators
// A = 4, B = 3 // X = 4'b1010, Y = 4'b1101 // Z = 4'b1xxz, M = 4'b1xxz, N = 4'b1xxx A == B // Results in logical 0 X != Y // Results in logical 1 X == Z // Results in x Z === M // Results in logical 1 (all bits match, including x and z) Z === N // Results in logical 0 (least significant bit does not
match) M !== N // Results in logical 1
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Bitwise OperatorsBitwise operators are negation (~), and(&),
or (|), xor (^), xnor (^~, ~^).
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Logical operators perform a logical operation// X = 4'b1010, Y = 4'b0000 X | Y // bitwise operation. Result is 4'b1010 X || Y // logical operation.
Equivalent to 1 || 0. Result is 1.
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Reduction OperatorsReduction operators are and (&), nand
(~&), or (|), nor (~|), xor (^), and xnor (~^, ^~).
perform a bitwise operation on a single vector operand and yield a 1-bit result.
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Shift OperatorsShift operators are right shift ( >>), left
shift (<<), arithmetic right shift (>>>), and arithmetic left shift (<<<).
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Concatenation Operator
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Replication Operator
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Conditional Operator
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Operator PrecedenceOperators Operator
SymbolsPrecedence
Unary + - ! ~ Highest precedence
Multiply, Divide, Modulus
* / %
Add, Subtract + - Shift << >> Relational < <= > >= Equality == != === !== Reduction &, ~&
^ ^~|, ~|
Logical &&||
Conditional ?: Lowest precedence
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4-to-1 Multiplexer, Using Logic Equations
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4-to-1 Multiplexer, Using Conditional Operators
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4-bit Full Adder, Using Dataflow Operators
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4-bit Full Adder with Carry Lookahead