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What do we need to control?

5.3

InstructionMemory

Data Memory

AddAdd

4

Read address

Instruction [31-0]

Read address

Write address

Write data

Read dataResult

Zero

Result

Result Sh.Left2

0

1

1

00

1

signextend

PC

16 32

ALU -What is theOperation?

ALU -What is theOperation?

Memory-Read/Write/neither?

Memory-Read/Write/neither?

Mux - are webranching or not?

Mux - are webranching or not?

Mux - Wheredoes 2nd ALUoperand come from?

Mux - Wheredoes 2nd ALUoperand come from?

Registers-Should we write data?

Registers-Should we write data? Mux - Result from

ALU or Memory?

Mux - Result fromALU or Memory?

Almost all of the information we need is in the instruction!

Read reg. num A

RegistersRead reg num B

Write reg num

Write reg data

Read reg data A

Read reg data B

Read reg num A

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Instructions – Opcode and Function Code

5.3

Opcode RS RT RD ShAmt Function

Opcode RS RT Immediate Data

Opcode Immediate Data

R-Type

I-Type

J-Type

Main instruction info is in the Opcode, which can be used to set up the datapath and the primary ALU (for I- and J-types)

For R-type instructions, the Function Code determines the function of the primary ALU (add, sub, mul, div, slt, and, or, etc.)

Ch5b- 4EE/CS/CPE 3760 - Computer OrganizationSeattle Pacific University

Decoding the Instruction - DataThe instruction holds the key to all of the data signals

Writereg./Readreg. B

R-type

Memory,Branch

Opcode RS RT RD ShAmt Function

31-26 25-21 20-16 15-11 10-6 5-0

Opcode RS RT Immediate Data

31-26 25-21 20-16 15-0

To ctrllogic

Readreg. A

Memory address or Branch Offset

To ctrllogic

Readreg. A

Readreg. B

Writereg.

To ALUControl

Not Used

One problem - Write register number must come from two different places.

5.3

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Instruction Decoding

5.3

InstructionMemory

Data Memory

AddAdd

4

Read address

Instruction [31-0]

Read address

Write address

Write data

Read dataResult

Zero

Result

Result Sh.Left2

0

1

1

00

1

signextend

PC

16 32

Read reg. num A

RegistersRead reg num B

Write reg num

Write reg data

Read reg data A

Read reg data B

Read reg num A

Imm:[15-0]

Rs:[25-21]

Rt:[20-16]

Rd:[15-11]

Op:[31-26]Ctrl

Read Reg A: Rs

Read Reg B: Rt

Write Reg: Either Rd or Rt

Immediate Data: [15-0]

Opcode: [31-26]

0

1

We can decode the data simply by dividing up the instruction bus

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Control Signals

5.3

InstructionMemory

Data Memory

AddAdd

4

Read address

Instruction [31-0]

Read address

Write address

Write data

Read dataResult

Zero

Result

Result Sh.Left2

0

1

1

00

1

signextend

PC

16 32

Read reg. num A

RegistersRead reg num B

Write reg num

Write reg data

Read reg data A

Read reg data B

Read reg num A

RegWrite

MemToReg

MemWrite

MemRead

ALUSrc

PCSrc

1: LW0: Others

1:SW0:others

1:LW0:others

1: Memory0: R-type,Branch

1:LW,R-type0:SW,Branch

1: Branch taken0:Others

0

1

Ctrl

Imm:[15-0]

Rs:[25-21]

Rt:[20-16]

Rd:[15-11]

Op:[31-26]

RegDest1:R-type0:I-type ?

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The Primary ALU• The Primary ALU is right in the middle of everything...

• It must:

• Add, Subtract, And, Or, etc. for R-types (from FC)

• Subtract for a BEQ (from Opcode)

• Add to determine address for a LW, SW (from Opcode)

5.3

Function Operation ResultAnd 000 R = A • BOr 010 R = A BAdd 100 R = A + BSubtract 101 R = A - BSLT 111 R = 1 if A < B

0 if A B

Function Operation ResultAnd 000 R = A • BOr 010 R = A BAdd 100 R = A + BSubtract 101 R = A - BSLT 111 R = 1 if A < B

0 if A B

A

B

ZeroResultOverFlow

Operation

Cout

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Setting the ALU controls• The instruction Opcode and Function give

us the info we need

• For R-type instructions, Opcode is zero, function code determines ALU controls

5.3

Instruction Opcode ALUOp Funct. Code ALU action ALU controladd 000000 10 100000 add 100sub 000000 10 100010 subtract 101and 000000 10 100100 and 000or 000000 10 100101 or 010SLT 000000 10 101010 SLT 111

• For I,J-type instructions, Opcode determines ALU controls

load word 010011 00 xxxxxx add 100store word 011011 00 xxxxxx add 100branch equal 000100 01 xxxxxx subtract 101

Main Control Logic generates ALUOp signal00: ALU adds01: ALU subtracts10: ALU looks at F.C.11: Unused

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ALU Control Signals

5.3

InstructionMemory

Data Memory

AddAdd

4

Read address

Instruction [31-0]

Read address

Write address

Write data

Read dataResult

Zero

Result

Result Sh.Left2

0

1

1

00

1

signextend

PC

16 32

Read reg. num A

RegistersRead reg num B

Write reg num

Write reg data

Read reg data A

Read reg data B

Read reg num A

ALUCtrl

6 ALUOp

ALU Control - A function of: ALUOp and the function code

RegWrite

MemToReg

MemWrite

MemRead

ALUSrc

PCSrc

00: Add01: Sub10: R-type

0

1

Ctrl

Imm:[15-0]

Rs:[25-21]

Rt:[20-16]

Rd:[15-11]

Op:[31-26]

FC:[5-0]

RegDest

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Inside the control oval

Reg ALU Mem Reg Mem MemInstruction Opcode Write Src To Reg Dest Read Write PCSrc ALUOp

5.3

• This control logic can be decoded in several ways:

• Random logic, PLA, PAL

• Just build hardware that looks for the 4 opcodes

• For each opcode, assert the appropriate signals

Note: BEQ must also check the zero output of the ALU...Note: BEQ must also check the zero output of the ALU...

BEQ 000100 0 0 x x 0 0 1 01

R-format 000000 1 0 0 1 0 0 0 10

LW 100011 1 1 1 0 1 0 0 00

SW 101011 0 1 x x 0 1 0 00

0:Rt1:Rd

0:Reg1:Imm

1:Mem0:ALU

1:Branch

00:Mem01:Branch10:R-type

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Control Signals

5.3

InstructionMemory

Data Memory

AddAdd

4

Read address

Instruction [31-0]

Read address

Write address

Write data

Read dataResult

Zero

Result

Result Sh.Left2

0

1

1

00

1

signextend

PC

16 32

Read reg. num A

RegistersRead reg num B

Write reg num

Write reg data

Read reg data A

Read reg data B

Read reg num A

ALUCtrl

6

ALUOp

RegWrite

MemToReg

MemWriteMemRead

ALUSrc

PCSrc

0

1

Ctrl

Imm:[15-0]

Rs:[25-21]

Rt:[20-16]

Rd:[15-11]

Op:[31-26]

FC:[5-0]

RegDest

BEQ

ReadWrite

We must ANDBEQ and Zero

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Jumping

5.3

InstructionMemory

Data Memory

AddAdd

4

Read address

Instruction [31-0]

Read address

Write address

Write data

Read dataResult

Zero

Result

Result Sh.Left2

0

1

1

00

1

signextend

PC

16 32

Read reg. num A

RegistersRead reg num B

Write reg num

Write reg data

Read reg data A

Read reg data B

Read reg num A

ALUCtrl

6

ALUOp

RegWrite

MemToReg

MemWriteMemRead

ALUSrc

PCSrc

0

1

Ctrl

Imm:[15-0]

Rs:[25-21]

Rt:[20-16]

Rd:[15-11]

Op:[31-26]

FC:[5-0]

RegDest

BEQ

ReadWrite

1

0

Sh.Left2

J:[25-0]

Concat.26

4

32

28

[31-28]

Jump

Ch5b- 13EE/CS/CPE 3760 - Computer OrganizationSeattle Pacific University

PerformanceWhat major functional units are used by different instructions?

R-type: Instr. Fetch Register Read ALU Register Write

Assume the following times:

Memory Access: 2ns

ALU: 2ns

Registers: 1ns

6ns

8ns

7ns

5ns

2ns

Branch: Instr. Fetch Register Read ALU

LW: Instr. Fetch Register Read ALU Memory Read Register Write

SW: Instr. Fetch Register Read ALU Memory Write

Jump: Instr. Fetch

Since the longest time is 8ns (LW),the cycle time must be at least 8ns.