chapter-5 synchronous sequential logic

7/25/2019 Chapter-5 Synchronous Sequential Logic

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Chapter 5 Synchronous Sequential

Logic 5-1 Sequential Circuits

Every digital system is likely to have combinationalcircuits, most systems encountered in practice alsoinclude storage elements, which require that the

system be described in term of sequential logic.


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Synchronous Clocked

Sequential CircuitA sequential circuit may use many ip-opsto storeas many bits as necessary. The outputs can comeeither from the combinational circuit or from the ip-

ops or both.


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5-2 Latches SRLatch

The ! latchis a circuit with two cross-coupled "#!gatesor two cross-coupled "A"$ gates. %t has twoinputs labeled for set and ! for reset.


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SR Latch with NAND ates


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SR Latch with Control !nput

The operation of the basic ! latch can be modi&edby providing an additional control input thatdetermines when the state of the latch can bechanged. %n 'ig. (-(, it consists of the basic ! latchand two additional "A"$ gates.


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D Latch

#ne way to eliminate the undesirable condition ofthe indeterminate state in ! latch is to ensure thatinputs and ! are never equal to ) at the same time

in 'ig (-(. This is done in the $ latch.


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raphic Sy"#ols $or latches

A latch is designated by a rectangular block withinputs on the left and outputs on the right. #neoutput designates the normal output, and the other

designates the complement output.


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5-% &lip-&lops

The state of a latch or ip-op is switched by achange in the control input. This momentary change

is called a triggerand the transition it cause is said totrigger the ip-op. The $ latch with pulses in itscontrol input is essentially a ip-op that is triggeredevery time the pulse goes to the logic )level. As longas the pulse input remains in the level, any changes

in the data input will change the output and the stateof the latch.


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Clock Response in Latch

%n 'ig *a+ a positive level response in the controlinput allows changes, in the output when the $input changes while the clock pulse stays at logic ).


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Clock Response in &lip-&lop


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'dge-(riggered D &lip-&lop

The &rstlatch is called the masterand the secondthe slave. The circuit samples the $ input andchanges its output only at the negative-edge of the

controlling clock.

/

$ ) ) 0 0 ) ) 12 ) ) 0 0 ) ) 1 3 ) ) 0 0 ) 1.


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D-(ype )ositi*e-'dge-(riggered &lip-&lop

Another more e4cient construction of an edge-triggered $ ip-op uses three ! latches. Twolatches respond to the e5ternal $*data+ and/*clock+ inputs. The third latch provides the outputs

for the ip-op.

!ef. p.)6( te5ts


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raphic Sy"#ol $or 'dge-(riggered D &lip-&lop


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+ther &lip-&lops , &lip-&lop

There are three operations that can be performedwith a ip-op7 set it to ), reset it to 0, orcomplement its output. The 8/ ip-op performs allthree operations. The circuit diagram of a8/ ip-op

constructed with a $ ip-opand gates.


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, &lip-&lop

The 8 input sets the ip-op to ), the / input resets itto 0, and when both inputs are enabled, the output iscomplemented. This can be veri&ed by investigatingthe circuit applied to the $ input7 $ 9 8 : ;/:


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( &lip-&lop

The T*toggle+ ip-op is a complementing ip-opand can be obtained from a 8/ ip-op when inputs

8 and / are tied together.


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( &lip-&lop

The T ip-op can be constructed with a $ ip-opand an e5clusive-#! gates as shown in 'ig. *b+. Thee5pression for the $ input is

$ 9 T 9 T: ;T:


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Characteristic'quations

$ ip-opharacteristic Equations

*t ; )+ 9 $

8/ ip-opharacteristic Equations

T ip-opharacteristic Equations

*t ; )+ 9 8: ; /:

*t ; )+ 9 T 9 T: ; T:


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Direct !nputs

ome ip-ops have asynchronous inputs that areused to force the ip-op to a particular stateindependent of the clock.The input that sets the ip-

op to ) is called present or direct set.The input thatclears the ip-op to 0 is called clear or direct reset.


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D &lip-&lop with AsynchronousReset

A positive-edge-triggered $ip-op withasynchronous reset is shown in 'ig*a+.


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D &lip-&lop with AsynchronousReset


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5-. Analysis o$ Clocked SequentialCircuits

The analysis of a sequential circuit consists ofobtaining a tableor a diagram for the time sequenceof inputs, outputs, and internal states. %t is also

possible to write =oolean e5pressions that describethe behavior of the sequential circuit. Thesee5pressions must include the necessary timesequence, either directly or indirectly.


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State 'quations

The behavior of a clocked sequential circuit can bedescribed algebraically by means of state equations.A state equation speci&es the ne5t state as a

function of the present state and inputs. onsiderthe sequential circuit shown in 'ig. (-)(. %t consistsof two $ ip-ops A and =, an input 5 and an outputy.


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&ig/5-15 '0a"ple o$ SequentialCircuit


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State 'quation

A*t;)+ 9 A*t+ 5*t+ ;=*t+5*t+

=*t;)+ 9 A:*t+ 5*t+

A state equation is an algebraic e5pression thatspeci&es the condition for a ip-op state transition.

The left side of the equation with *t;)+ denotes thene5t state of the ip-op one clock edge later. The

right side of the equation is =oolean e5pression thatspeci&es the present state and input conditions thatmake the ne5t state equal to ).

2*t+ 9 *A*t+ ;=*t++ 5*t+:


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State (a#le

The time sequence of inputs, outputs, and ip-opstates can be enumerated in a state table*sometimes called transition table+.


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State Diagra"

The information available in a state table can berepresented graphically in the form of a statediagram. %n this type of diagram, a state is

represented by a circle, and the transitions betweenstates are indicated by directed lines connecting thecircles.

)>0 7 means input 9)

output90


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&lip-&lop !nput'quations

The part of the combinational circuit thatgenerates e5ternal outputs is descirbed algebraicallyby a set of =oolean functions called output equations.

The part of the circuit that generates the inputs to

ip-ops is described algebraically by a set of=oolean functions called ip-op input equations. Thesequential circuit of 'ig. (-)( consists of two $ ip-ops A and =, an input 5, and an output y. The logic

diagram of the circuit can be e5pressed algebraicallywith two ip-op input equationsand an outputequation7 $A9 A5 ;=5

$=9 A:5y 9 *A ;=+5:


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Analysis with D &lip-&lop

The circuit we want to analy?e is described by theinput equation $A9 A 5 y

The $Asymbol implies a $ ip-op with output A.

The 5 and y variables are the inputs to the circuit."o output equations are given, so the output isimplied to come from the output of the ip-op.


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Analysis with D &lip-&lop

The binary numbers under A5y are listed from 000through ))) as shown in 'ig. (-)6*b+. The ne5t statevalues are obtained from the state equation A*t;)+9 A 5 y

The state diagram consists of two circles-one foreach state as shown in 'ig. (-)6*c+


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Analysis with , &lip-&lops


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Analysis with , &lip-&lop

The circuit can be speci&ed by the ip-op inputequations 8A9 = /A9 =5:

8=9 5: /=9 A:5 ;A5: 9 A 5


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A*t ;)+ 9 8A: ;/:A=*t ;)+ 9 8=: ;/:=

ubstituting the values of 8A and /A from the input

equations, we obtain the state equation for A7A*t ;)+ 9 =A: ;*=5:+:A 9 A:= ;A=: ;A5

The state equation provides the bit values for the

column under ne5t state of A in the state table.imilarly, the state equation for ip-op = can bederived from the characteristic equation bysubstituting the values of 8=and /=7

9 : : : 9 : :


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The state diagram of the sequential circuit is shownin 'ig. (-)@.


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Analysis ith ( &lip-&lops

haracteristic equation *t ;)+ 9 T 9 T: ;

T:

00>0 7 means

state is 00 output is 0


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Analysis ith ( &lip-&lops

onsider the sequential circuit shown in 'ig. (-0.%t has two ip-ops A and =, one input 5, and oneoutput y. %t can be described algebraically by twoinput equations and an output equation7

TA9 =5

T=9 5 y 9 A=

A*t;)+9*=5+BA;*=5+AB 9A=B;A5B;AB=5

=*t;)+95=

se present state

as inputs


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3ealy and 3oore 3odels41

CThe most general model of a sequential circuit hasinputs, outputs, and internal states. %t is customary todistinguish between two models of sequential circuits7

the Dealy modeland the Doore model

CThey dier in the way the output is generated.- %n the Dealy model, the output is a function of both

the present state and input.- %n the Doore model, the output is a function of the

present state only.


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3ealy and 3oore 3odels42


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5-5 6DL &or Sequential Circuit

The Ferilog hardware description language*G$+ is introduced in ection H-@. The descriptionof combinational circuitsand an introduction to

behavioral modeling is presented in ection I-)).

C %n this section, we continue the discussion ofthe behavioral modeling and present descriptione5amples of ip-ops and sequential circuits.


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7eha*ioral 3odeling

initial #egin clock 9 ):b0J repeat *H0+ K)0 clock 9 LclockJ end

initial #egin clock 9 ):b0J

KH00 89nishJ endalways K)0 clock 9 LclockJ

There are two kinds of behavioral statements inFerilog G$7 initialand always.


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7eha*ioral 3odeling

alwaysM*event control e5pression+procedural assignment statements.

alwaysM*A or= or!eset+

alwaysM*posedgeclock or negedgereset+

The alwaysstatement can be controlled by delaysthat wait for a certain time or by certain conditions tobecome true or by events to occur.


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&lip-&lops and Latches

>>$escription of $ latch *ee 'ig. (-N+"odule$Olatch *, $, control+J outputJ input$, controlJ regJ

alwaysM*control or$+ i$*control+ 9 $J >>ame as7 i$*control99)+end"odule

G$ E5ample (-)


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G$ E5ample (->>$ ip-op"odule$O'' *, $, /+J outputJ input$, /J regJ alwaysM*posedge/+ 9 $Jend"odule

>> $ ip-op with asynchronous reset."odule $'' *, $, /, !T+J

outputJ input $, /, !TJ regJ alwaysM*posedge/ or negedge!T+ i$*L!T+ 9 ):b0J >> ame as7 i$*!T 990+ else 9 $J

end"odule


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G$ E5ample (-H>>T ip-op from $ ip-op and gates"oduleT'' *, T, /, !T+J outputJ inputT, /, !TJ reg$TJ

assign $T 9 P TJ>>%nstantiate the $ ip-op $'' T') *, $T, /, !T+J'nd"odule

>> 8/ ip-op from $ ip-op and gates

"odule8/'' *, 8, /, /, !T+J outputJ input8, /, /, !TJ wire8/J assign8/ 9 *8 Q L+ R *L/ Q +J>> %nstantiate $ ipop

$'' 8/) *, 8/, /, !T+Jend"odule


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"odule $'' *, $, /, !T+J outputJ input $, /, !TJ regJ

alwaysM*posedge/ or negedge!T+ i$*L!T+ 9 ):b0J >> ame as7 i$*!T990+ else 9 $Jend"odule


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G$ E5ample (-I

>> 'unctional description of 8/ ip-op"odule 8/O'' *8, /, /, , not+J output, notJ

input 8, /, /J reg J assignnot 9 LJ alwaysM *posedge/+ case *S8, /+

:b007 9 J :b0)7 9 ):b0J

:b)07 9 ):b)J :b))7 9 LJ endcase

end"odule


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State Diagra"

G$ E5ample (-(>>Dealy state diagram *'ig. (-)N+"odule DealyOmdl *5, y, /, !T+J input5, /, !TJ

outputyJ regyJ regU)70V Wrstate, "5tstateJ para"eter0 9 :b00, ) 9 :b0), 9 :b)0, H9

:b))J alwaysM *posedge/ or negedge!T+ i$*L!T+ Wrstate 9 0J >>%nitiali?e to state 0 elseWrstate 9 "5tstateJ >>lock operations

alwaysM *Wrstate or 5+ case*Wrstate+


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State Diagra"

07 i$*5+ "5tstate 9 )J else"5tstate 9 0J)7 i$*5+ "5tstate 9 HJ else"5tstate 9 0J7 i$*5+ "5tstate 9 0J else"5tstate 9 JH7 i$*5+ "5tstate 9 J else"5tstate 9 0Jendcase

alwaysM *Wrstate or5+ >>Evaluate output case*Wrestate+

07 y 9 0J )7 i$*5+ y 9 ):b0J elsey 9 ):b)J 7 i$*5+ y 9 ):b0J elsey 9 ):b)J H7 i$*5+ y 9 ):b0J elsey 9 ):b)J endcase

end"odule


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State Diagra"

G$ E5ample (-N

>>Doore state diagram *'ig. (-)@+"odule DooreOmd) *5, A=, /, !T+J input5, /, !TJ outputU)70V A=J

regU)70V stateJ para"eter0 9 :b00, ) 9 :b0), 9 :b)0, H 9 :b))J alwaysM *posedge/ ornegedge!T+ i$*L!T+ state 9 0J >>%nitiali?e to state 0 else case*state+

07 i$*L5+ state 9 )J elsestate 9 0J )7 i$*5+ state 9 J elsestate 9 HJ 7 i$*L5+ state 9 HJ else state 9 J H7 i$*L5+ state 9 0J elsestate 9 HJ endcase assignA= 9 stateJ >>#utput of ip-ops

end"odule


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Structural Description

G$ E5ample (-6>>tructural description of sequential circuit>>ee 'ig. (-0 *a+"oduleTcircuit *5, y, A, =, /, !T+J input5, /, !TJ outputy, A, =J wireTA, T=J>>'lip-op input equations assignT= 9 5, TA 9 5 Q =J

>>#utput equation assigny 9 A Q =J>>%nstantiate T ip-ops TO'' =' *=, T=, /, !T+J TO'' A' *A, TA, /, !T+J

end"odule


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>>T ip-op"oduleTO'' *, T, /, !T+J outputJ

inputT, /, !TJ regJ alwaysM *posedge/ or negedge!T+ i$*L!T+ 9 ):b0J else 9 P TJ

end"odule


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>>timulus for testing sequential circuit"oduletestTcircuitJ reg5, /, !TJ >>inputs for circuit wirey, A, =J >>output from circuit

Tcircuit T *5, y, A, =, /, !T+J >>instantiate circuitinitial #egin

!T 9 0J / 9 0J K( !T 9 )J repeat *)N+ K( / 9 L/J end

initial #egin 5 9 0J K)( 5 9 )J repeat *X+ K)0 5 9 L5J end

end"odule


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5-: State Reduction andAssign"ent

CThe analysis of sequential circuits starts from acircuit diagram and culminates in a state table ordiagram.

CThe design of a sequential circuit starts from aset of speci&cations and culminates discussescertain properties of sequential circuits that maybe used to reduce the number of gates and ip-

ops during the design.


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State Reduction

C The reduction of the number of ip-ops in asequential circuit is referred to as the state-reductionproblem.tate-reductionalgorithms areconcerned with procedures for reducing the numberof states in a state table, while keeping the e5ternalinput-output requirements unchanged.

C ince m ip-ops produce mstates, a reduction

in the number of states may result in a reduction inthe number of ip-ops. An unpredictable eect inreducing the number of ip-ops is that sometimesthe equivalent circuit may require more

combinational gates.


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State Reduction

state a a b c d e f f g f g ainput 0 ) 0 ) 0 ) ) 0 ) 0 0output 0 0 0 0 0 ) ) 0 ) 0 0

E5ample 7

%nitial point


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State Reduction


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State Reduction

tates gand eare two such states7 they both go tostates aand fand have outputs of 0and )for 590and59), respectively. Therefore, states g and e areequivalent and one of these states can be removed.

The procedure of removing a state and replacing it byits equivalent is demonstrated in Table (-6. The rowwith present gisremoved and state

gis replaced by stateeeach time it occursin the ne5t-statecolumns.


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State Reduction

Wresent state f now has ne5t states eand fandoutputs 0and )for 590and 59), respectively. Thesame ne5t states and outputs appear in the row withpresent state d. Therefore, states fand dare

equivalent and state fcan be removed and replacedby d. The &nal reduced table is shown in Table (-X. Thestate diagram for the reduced table consists of only&vestates and is shown

in 'ig. (-H.


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State Reduction


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State Assign"ent


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5-; Design )rocedure

The procedure for designing synchronoussequential circuits can be summari?ed by a list ofrecommended steps.

). 'rom the word description and speci&cations of thedesiredoperation, derive a state diagram for the circuit.

. !educe the number of states if necessary.H. Assign binary values to the states.

I. #btain the binary-coded state table.(. hoose the type of ip-ops to be used.N. $erive the simpli&ed ip-op input equations and

output equations.

6. $raw the logic diagram.


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Design )rocedure


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Synthesis sing D &lip-&lops

A*t ;)+ 9 $A*A, =, 5+ 9 Y*H, (,6+=*t ;)+ 9 $=*A, =, 5+ 9 Y*), (,6+

y*A, =, 5+ 9 Y*N, 6+


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$A9 A5 ;=5$=9 A5 ;=:5 y 9 A=


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Synthesis sing , &lip-&lops

!ef. Table (-)

$ierent from Table (-)) ZZ


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Synthesis sing ( &lip-&lops

The synthesis usingT ip-opswill be demonstratedby designing a binary counter. An n-bit binarycounter consists of n ip-ops that can count inbinary from 0 to n-). The state diagram of a H-bit

counter is shown in 'ig.(-@.

!ef. Table (-)


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chapter-5 synchronous sequential logic

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