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CHAPTER 5

DESIGN OF SINUSOIDAL PULSE WIDTH MODULATION TECHNIQUES FOR

ZETA CONVERTER USING FPGA

5.1 Introduction

Similar to the SEPIC DC/DC converter topology, the ZETA converter topology

provides a positive output voltage from an input voltage that varies above and below the

output voltage. The ZETA converter also needs two inductors and a series capacitor,

sometimes called a flying capacitor. Unlike the SEPIC converter, which is configured

with a standard boost converter, the ZETA converter is configured from a buck controller

that drives a high-side PMOS FET. The ZETA converter is another option for regulating

an unregulated input power supply, like a low-cost wall wart. To minimize board space, a

coupled inductor can be used. This article explains how to design a ZETA converter [13].

A Zeta converter performs non-inverting buck-boost function similar to that of a

SEPIC, which is an acronym for Single-Ended Primary Inductance Converter. The Zeta

topology is also similar to the SEPIC, in that it uses two inductors, two switches and a

capacitor to isolate the output from the input as shown in fig.5.1. However, Zeta

conversion requires a P-Channel MOSFET as the primary switch, while SEPIC

conversion uses an N-Channel MOSFET. This architecture makes SiPix’s SP6125/6/7

controllers suitable for use in a Zeta topology [26].

5.2 Conventional Topology

The conventional technique of AC-DC conversion using a diode rectifier

with bulk capacitor is no longer in use due to numerous problems such as low order

harmonics injection into AC power supply, high peak current, low power factor,

line voltage distortion, increased electromagnetic interference, extra burden on lines,

and additional losses. Solid-state switch mode rectification converters have reached

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a matured level for improving power quality in terms of power-factor correction

(PFC) and reduced total harmonic distortion (THD). The major challenge is to

control the output voltage and improve PFC simultaneously. The basic dc-to-dc

converter topologies using Buck-converter, Boost converter and Buck-Boost converter

have their intrinsic limitations when used for active power factor correction along

with voltage regulation purposes [25].

In the proposed model a relatively new class of DC-DC converter, Zeta

converter is used for active PFC and voltage regulation having advantages of

being naturally isolated structure, can operate as both step up/down voltage

converter and having only one stage power processing for both voltage

regulation and Harmonics [26].

A Zeta converter performs non-inverting buck-boost function similar to that

of a SEPIC. But in application which implies high power, the operation of a converter

is not attractive in discontinuous conduction mode because it results in high rms

values of the currents causing high levels of stress in the Semiconductors. In

conventional methods, an active power factor correction (PFC) is performed by

using a Zeta converter operating in continuous conduction mode (CCM), where

the inductor current must follow a sinusoidal voltage Waveform. This method

provides nearly unity power factor with low THD [27].

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Fig. 5.1 Circuit diagram of Basic Zeta converter.

5.2.1. Basic principle of zeta converter

When analysing Zeta waveforms it shows that at equilibrium, L1 average

current equals IIN and L2 average current equals IOUT, since there is no DC

Current through the flying capacitor CFLY.

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Stage-1 [M1 ON].

Fig.5.2 Circuit diagram of Zeta converter during MOSFET ON time.

The switch M1 is in ON state, so voltages VL1 and VL2 are equal to Vin. In this

time interval diode D1 is OFF with a reverse voltage equal to - (Vin + VO).

Inductor L1 and L2 get energy from the voltage source, and their respective

currents IL1 and IL2 are increased linearly by ratio and respectively.

Consequently, the switch current IM1=IL1+IL2 is increased linearly by a ratio

,where At this moment, discharging of capacitor CFLY and charging

of capacitor C0 take place [33].

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Fig.5.3 Basic zeta converter waveform.

Therefore, CFLY sees ground potential at its left side and VOUT at its right From

the above results, it is concluded that when the magnitude of the input carrier frequency

is reduced, it is possible to reduce the SPWM carrier frequency to a good extent using

Direct Digital Frequency Synthesizer(DDFS). In this part of the research, the magnitude

of the input carrier frequency was reduced, resulting in DC voltage across CFLY being

equal to VOUT [37].

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Stage-2 [M1 OFF]

Fig 5.4 Circuit diagram of Zeta converter during MOSFET OFF time.

In this stage, the switch M1 turns OFF and the diode D1 is forward

biased starting to conduct. The voltage across L1 and L2 become equal to

-Vo and inductors L1 and L2 transfer energy to capacitor CFLY and load

respectively. The current of L1 and L2 decreases linearly now by a ratio –V0/L1

and – V0/L2, respectively. The current in the diode ID1=IL1+IL2 also decreases

linearly by ratio –V0/L. At this moment, the voltage across switch M1 is

VM=Vin + V0. Figure 4 shows the main waveforms of the ZETA converter, for

one cycle of operation in the steady state continues mode [41].

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5.3 Proposed Converter

Fig.5.5 Circuit diagram of Proposed Zeta converter.

The simplified circuit model of the proposed converter is shown in above fig 5.5.

The coupled inductor T1 includes a magnetizing inductor Lm, primary and secondary

leakage inductors Lk1 and Lk2, and an ideal transformer primary winding N1 and

secondary winding N2. To simplify the circuit analysis of the proposed converter, the

following assumptions are made [44].

1) All components are ideal, except for the leakage inductance of coupled

inductor T1.The ON-state resistance RDS (ON) and all parasitic

capacitances of the main switch S1 are neglected, as are the forward voltage

drops of the diodes D1 ∼ D3.

2) The ESR of capacitors C1 ∼ C3 and the parasitic resistance of coupled-

inductor T1 are neglected.

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3) The capacitors C1 ∼ C3 are sufficiently large that the voltages across them

are considered to be constant.

4) The turn’s ratio n of the coupled inductor T1 winding is equal to N2/N1.

5.3.1 Proposed Zeta Converter

The Zeta converter is shown in fig. 5.5 its basic configuration came from a zeta

converter but the input inductor has been replaced by a coupled inductor. Employing the

turn’s ratio of the coupled inductor increases the voltage gain and the secondary winding

of the coupled inductor series with a switched capacitor for further increasing the voltage

[47].

The coupled inductor zeta converter is configured from a coupled inductor T1 with

the floating active switch S1. The primary winding N1 of a coupled inductor T1 is similar

to the input inductor of the conventional boost converter, apart from that capacitor C1 and

diode D1 are recycling leakage-inductor energy from N1. The secondary winding N2 is

connected with another pair of capacitors C2 and with diode D2, all three of which are in

series with N1. The rectifier diode D3 connects to its output capacitor C3 and load R [66].

The features of zeta converter are: 1) the leakage inductor energy of the coupled

inductor can be recycled, increasing the efficiency and the voltage spike on the active

switch has been restrained. 2) The voltage conversion ratio is efficiently increased by the

switched capacitor and coupled capacitor techniques and 3) the floating active switch the

PV panel’s energy during non-operating conditions, thus preventing any potential electric

hazard to humans or facilities [67].

5.3.2 Operating Principles

Mode of Operation

Mode I [t0, t1]: In this transition interval, the secondary leakage inductor Lk2 is

continuously releasing its energy to capacitor C2. Switch S1 and diodes D2 are

conducting. The current iLm is descending because source voltage Vin is applied on

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magnetizing inductor Lm and primary leakage inductor Lk1;meanwhile, is also

releasing its energy to the secondary winding, as well as charging capacitor C2 along

with the decrease in energy, the charging current iD2 and iC2 are also decreasing. The

secondary leakage inductor current iLK2 is declining according to . Once the

increasing iLk1 equals the decreasing iLm at t = t1, this mode ends.

Mode II [t1, t2]: During this interval, source energy Vin is series connected with

C1, C2, secondary winding N2, and Lk2 charge output capacitor C3 and load R;

meanwhile, magnetizing inductor Lm is also receiving energy from Vin. Switch S1 mains

on, and only diode D3 is conducting. The iLm, iLk1, and iD3 are increasing because the

Vin is crossing Lk1, Lm and primary winding N1; Lm and Lk1 are storing energy from

Vin; meanwhile, Vin is also in series with N2 of coupled inductor Lk1, and capacitors C1

and C2 are discharging their energy to capacitor C3 and load R, which leads to increases

in iLm, iLk1, iDS, and iD3. This mode ends when switch S1 is turned off at t = t2 [68].

Mode III [t2, t3]: During this transition interval, secondary leakage inductor Lk2

keeps charging C3 when switch S1 is off. Only diodes D1 and D3 are conducting. The

energy stored in leakage inductor Lk1 flows through diode D1 to charge capacitor C1

instantly when S1 turns off. Meanwhile, the Lk2 keeps the same current direction as in

the prior mode and is in series with C2 to charge output capacitor C3 and load R. The

voltage across S1 is the summation of Vin, VLm, and VLk1. Currents iLk1 and iLk2 are

rapidly declining, but iLm is increasing because Lm is receiving energy from Lk2. Once

current iLk2 drops to zero, this mode ends at t = t3 [74].

Mode IV [t3,t4]: During this transition interval, the energy stored in magnetizing

inductor Lm releases simultaneously to C1 and C2. Only diodes D1 and D2 are

conducting. Currents iLk1 and iD1are persistently decreased because leakage energy still

flows through diode D1 and continues charging capacitor C1.The Lm is delivering its

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energy through T1 and D2 to charge capacitor C2. The energy stored in capacitors C3 is

constantly discharged to the load R. The voltage across S1 is the same as previous mode.

Currents iLk1 and iLm are decreasing, but iD2 is increasing. This mode ends when

current iLk1 is zero at t = t4.

Mode V [t4, t5]: During this interval, magnetizing inductor Lm is constantly

transferring energy to C2. Only diode D2 is conducting. The iLm is decreasing due to the

magnetizing inductor energy flowing continuously through the coupled inductor T1 to

secondary winding N2 and D2 to charge capacitor C2. The energy stored in capacitors C3

is constantly discharged to the load R. The voltage across S1 is the summation of Vin and

VLm. This mode ends when switch S1 is turned on at the beginning of the next switching

period.

5.4 Generation of Proposed Sinusoidal Pulse Width Modulation Using FPGA

With the extensive use of digital techniques in instrumentation and

communications systems, a digitally-controlled method of generating multiple

frequencies from a reference frequency source has evolved called Direct Digital

Synthesis (DDS). The basic architecture is shown in Figure 5.6.

The spectral purity of the final analog output signal is determined primarily by the

DAC. Phase noise is basically that of the reference clock. Because a DDS system is a

sampled data system, all the issues involved in sampling must be considered:

quantization noise, filtering, aliasing, etc. For instance, the higher order harmonics of the

DAC output frequencies fold back into the Nyquist bandwidth, making them unfilterable,

whereas, the higher order harmonics of the output of PLL-based synthesizers can be

filtered. There is one important limitation to the range of output frequencies that can be

generated from the simple DDS system. The Nyquist Criteria states that the clock

frequency (sample rate) must be at least twice the output frequency. Practical limitations

restrict the actual highest output frequency to about 1/3 the clock frequency.

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Fig. 5.6 Block diagram of Direct Digital Frequency Synthesizer (DDFs).

Phase accumulator replaces the address counter Modulus M determines the phase

increment for each ref clock cycle. Integer-N and DDS synthesizers can be joint for better

SNR, Finer tuning steps with wide loop BW, Higher reference frequency, Avoid

complications of Fractional-N. Filter needed to suppress spurs. Divider reduces phase

noise.

A frequency synthesizer is a device (an electronic system) that generates a large

number of particular frequencies from a single reference frequency. A frequency

synthesizer can replace the expensive array of crystal resonators in a multichannel radio

receiver. A single-crystal oscillator provides a reference frequency, and the frequency

synthesizer generates the other frequencies. Because they are relatively inexpensive and

because they can be easily controlled by digital circuitry, frequency synthesizers are

being included in many new communication system designs. Frequency synthesizers are

Phase

Accumulato

r

Waveform

Map (ROM or

PROM)

Digital to

Analogue

Convertor

Low Pass

Filter

Frequency

Information

(phase increment)

Clock Signal

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found in many devices, including radio receivers, radiotelephones, mobile telephones,

walkie-talkies, satellite receivers, GPS systems, etc.

A frequency synthesizer can combine frequency division, frequency multiplication

and frequency mixing (the frequency mixing process generates sum and difference

frequencies) operations to produce the desired output signal. The filter requirements can

be reduced by using an offset frequency.

Feature of DDFs

1. Micro-Hertz frequency, sub-degree phase resolution.

2. Phase-continuous frequency hops Digital control.

3. Extremely fast hopping –no settling time constraints.

4. Precise quadrature phase generation for I –Q.

5.5 Result and discussions

Fig. 5.7 Overall RTL view for Existing SPWM.

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Fig. 5.8 Overall RTL view of Proposed SPWM.

Fig. 5.9 Proposed DDFS RTL view for SPWM.

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Fig. 5.10 Proposed PWM RTL view for SPWM.

Fig .5.11 Simulation result of SPWM using FPGA.

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Fig. 5.12 Synthesis result of ProposedSPWM for area.

Fig. 5.13 Synthesis result ofProposed SPWM for delay.

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Fig. 5.14 Synthesis result of ProposedSPWM for power.

Table 5.1 Comparison between area, power and frequency of different SPWM

Technique.

Methods Slices Frequency(MHz) Power(mw)

Existing SPWM 161 115.638 336

Proposed SPWM 39 218.079 225

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Fig. 5.15 Comparison between area, power and frequency of different SPWM Technique.

Conclusion

From the above results, it is concluded that when the magnitude of the input

carrier frequency is reduced, it is possible to reduce the SPWM carrier frequency to a

good extent using digital frequency synthesizer. In this part of the research, the

magnitude of the input carrier frequency was reduced compared to the existing SPWM

and it was observed that the output carrier frequency of SPWM was increased from

115MHz to 218MHz and the area and power consumption was reduced by 70%. This

enables the chip size reduction with high speed processing of the FPGA. It is usually

0

50

100

150

200

250

300

350

400

Existing SPWM Proposed SPWM

Slices

Frequency(MHz)

Power(mW)

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challenging to obtain results favourable to area-power reduction with increased frequency

of operations; however, the contributions of this section achieve both. This efficient

SPWM pulse is provided as a triggering input to the Buck-Boost and Zeta convertors for

further THD analysis.

5.6 Proposed Controller

Basically, the SPWM Zeta converter is a step up/down converter of non-

inverting polarity type and it can be design to achieve low-ripple output current either

with coupled inductor or with separate inductors .A SPWM Zeta converter is

currently used in power factor correction and voltage regulation designs. The SPWM

Zeta converter topology consisting in two switches (a single transistor and a single

diode) and four reactive elements (two inductors and two capacitors) exhibits many

common features with the SPWM Cuk and Sepic converters whose analysis has

surfaced in many forms over the years.

PWM generation is considered very important in the converter design and several

multicarrier techniques have been developed to reduce the distortion in level converters

based on the classical with triangular carriers. In this converter, employs a zeta converter

and a coupled inductor without the extreme duty ratios and high turns ratios. Generally

the coupled inductor is needed to achieve high step up voltage conversion. The leakage

inductor energy of the coupled inductor is recycled to the load efficiently. The operating

principles and steady state analyses of continuous and boundary conduction modes, as

well as the voltage and current stresses of the active components are discussed in details.

The zeta converter will give better THD values compared to conventional buck boost

methods.

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5.6.1 Proposed SPWM Method

Analysis of the proposed PWM technique’s performance as well as the combined

technique’s performance was achieved by assessing their impacts on the performance of

the buck converter. The assessment of the buck converter is done using two criteria:

THD, The ripple voltage.

A. Output ripples voltage:

Output ripple voltage is the fluctuation of output voltage due to the charging-discharging

of the capacitor in the LC filter. Such ripple voltage is expressed as

Where, is the output ripple voltage, D is the duty cycle of the control signal, f is the

switching frequency of this control signal, C is the capacitance in the converter, and L is

the inductance in the converter. One can see from Equation that the ripple voltage

decreases with an increase in the duty cycle and an increase in the switching frequency.

Fig.5.16 Circuit implementation of SPWM Zeta converter with R Load.

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B. Total harmonics distortion (THD) analysis:

The proposed converter performance and THD result compared with conventional buck-

boost converter it is tabulated in section V.

5.7 Results and Discussions

Fig 5.17 Simulation result of SPWM Zeta converter With R Load

Fig 5.18 FFT Analysis of SPWM Zeta converter With R Load.

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Table 5.2 THD Comparison of two converters With R load.

Fig 5.19 THD Comparison of two converters With R load.

0

10

20

30

40

50

60

70

Buck-boost SPWM Zeta SPWM

THD(R load)

Buck-boost SPWM

Zeta SPWM

Converter THD(R Load)

Buck-boost SPWM 60.00

Zeta SPWM 49.48

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5.8 Conclusion

From the result, proposed Zeta converter using SPWM offers lesser Total

Harmonic distortion (THD) than the existing Buck Boost converter using SPWM. This

enables the proposed Zeta converter to provide less THD and high frequency. Zeta

converter is used only for boosting or step up operation and not for step down or buck

applications. Thus the SPWM can be used for both buck and boost by controlling and

varying the modulation index.