CHAPTER 5

Configuration, Reconfiguration and Security

Agenda

• Configuration basics– Controller structure– Frame structure– Different modes

• Reconfiguration– Modular– Differential– Partial

• 3DES and AES decryption

Config. Memory Related to Logic

Frame Shifter Related to Config.cells

Config. Sequence of Actions

1. Device Power Up2. Clear the Configuration Memory3. Sample the Mode Pins (described shortly)4. Synchronize5. Check Device ID6. Load the configuration data7. Check the CRC8. Startup

Virtex Configuration Modes

Note: Spartan 3E adds new modes with SPI and Byte Parallel Interface

Bitstream In, Config. Data Out

General Serial Configuration Model

Master Serial ModeNote

Master/Slave Serial ModeNote:

M/S Serial config. From Parallel EPROM

General Parallel Config. Model

Single Master SelectMap Mode

Single Master Config. From Micro/CPLD

Multi SelectMap Config.

JTAG Configuration

Configuration Controller

Reconfiguration

Field upgrade – changing the design when it is installed at a remote site.

Feature enhancement – adding features to an already deployed design.

Reconfigurable coprocessor- changing a coprocessor function

Modify connections on a printed circuit board – reroute existing connections

Self reconfiguration (or dynamic reconfiguration) where an FPGA modifies itself

Self correcting circuits – circuits that recover from failure, automatically

Configuration Column Sequencing

First frame Set Second Frame SetThird Frame Set

External Config. Controller

Scrub Controller

Used with Triple Modular Redundancy to virtuallyeliminate single event upset errors due to nuclear radiation

Modular Partial Reconfiguration

Bus Macro

3DES Encryption/Decryption Flow

Path taken by iMPACT

Path taken by FPGA

Configuration Decryptor

Decryption/Configuration Interaction

Configuration Close• Configuration offers more options than you might

expect– Many modes– Reconfiguration/partial reconfiguration– Decryption

• Lots of future work can be done here, to offer new operation models

• So far, nobody has built a serious “cache controller” that makes a coprocessor automatically sense the need to become a new function . . .