chapter 4 memory element

7/28/2019 Chapter 4 Memory Element

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TOPIC 4 :

MEMORY SYSTEM


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At the end of the class you should :

Understand memory in computer systems

State functions of main memory.

Identify types of ROM: ROM, PROM, EPROM,EEPROM and Flash ROM.

State the difference between SRAM and DRAM.

Determine memory size of standard memory

chips.

Explain memory chip control signals.


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Main Memory

Functions :

Is a memory that hold the instruction and data

while program is running for storing data so the CPU/MPU and other

direct memory access devices can call up to

fetch or store data for processing. It is very much like some part of our brain,

that stores short term and long term memory.


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RAM vs ROM

RAM ROM

Random Access Memory Read Only Memory

It is a volatile type of memory that needselectricity to flow to retain information Non-volatile type of memory essentially itis a piece of permanently written

information stored as memory

RAM offers a very fast memory access ROM is generally slower memory access

than RAM


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RAM vs ROM

RAM ROM

Data can be written to or read from Data can be read only

Data stored in RAM is lost when power is

removed

This means data stored in RAM should bestored in a more permanent location, like

a floppy disk or hard drive, before system

power is removed

Data in the memory chip remains stored

even when power is taken away from the

chip

Because of RAMs inability to store data

when power is removed, it is consideredto be volatile memory

Because of ROMs ability to store data

even when power is removed, it isconsidered to be non-volatile memory


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ROM

Firmware (Program instruction used frequently)

Program stored in a ROM graphics cards, disk controllers.


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Types of ROM

Read Only Memory (ROM) Actual ROM chips are programmed when they are made and can

never be changed. Program stored in a ROM

Boot time code, BIOS (basic input/output system) graphics cards, disk controllers.

Programmable ROM (PROM) Suitable for development work since they can be programmed by

the developer. The developer can burn information into thePROM. PROMS consists of arrays of semiconductor capacitors.Different capacitors can be addressed by applying a pattern of

signals to the address pins of the PROM chip. A charged capacitorrepresents a binary zero while a discharged capacitor represents abinary 1. The capacitors are isolated from one another so there isvery leakage. However, over many years or at very hightemperatures, the charge stored in the capacitor may be lost. Onoccasion it is desirable to erase all the information from a PROMand reprogram it with new data


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Types of ROM

Erasable programmable ROM (EPROM)

Have a transparent window that allows ultravioletlight to penetrate the semiconductor material inside

The ultraviolet light gives electrons additional energyallowing them to tunnel through the insulating layers.Thus, the capacitors are discharged. Each cell withinthe memory chip now represents a binary 1 and thechip can be reprogrammed

Electrically Erasable PROM (EEPROM)

Dont need ultraviolet light to erase the contents, onlyelectrical signals


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Types of ROM

Electrically Erasable PROM (EAPROM) EEPROM is also known as EAPROMthe EA being an

abbreviation for Electrically Alterable.

The major benefit to EE or EAPROM is that the chipsdo not have to be removed from the circuit tochange their program.

Flash ROM Also called flash memory A special type ofEEPROM that can be erased and

reprogrammed in blocks instead of one byte at atime


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SRAM vs DRAM

Static RAM Dynamic RAM

DRAM stores 1s and 0s as charge on a

small MOS capacitor

High capacity

Low power requirement

Moderate operating speed

Data has to leak off after a period of time,

DRAM requires periodic recharging or the

memory cells; this is called refreshing

DRAM


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SRAM vs DRAM


Static RAM is random access memory that

retains data bits in its memory as long as

power is being supplied

SRAM does not have to be periodicallyrefreshed.

Static RAM does not need refreshing

because it operates on the principle of

moving current that is switched in one of

two directions rather than a storage cell

that holds a charge in place

DRAM is dynamic in that, it needs to haveits storage cells refreshed or given a new

electronic charge every few milliseconds.

DRAM stores each bit in a storage cell

consisting of a capacitor and a transistor.

Capacitors tend to lose their charge

rather quickly; thus, the need forrecharging

Static RAM provides faster access to data

and is more expensive than DRAM


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SRAM vs DRAM


Disadvantages :

1. From the usage of MOS capacitor as

the storage element. Left alone, the

capacitor will eventually discharge,thus losing the stored binary

information. For this reason the

DRAM must constantly refreshed to

avoid data loss. During a refresh

operation, all of the capacitors within

the dynamic DRAM are recharged2. The refresh operation takes time to

complete, and the DRAM is

unavailable for use by the processor

during this time


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SRAM vs DRAM


SRAM require no refresh, they are

available to the CPU 100 percent of the

time

Disadvantages :

Older DRAMs required that all storage

elements inside the chip ware refreshed

every 2 ms. Newer DRAMs have anextended 4ms refresh time, but the

overall refresh operation ties up an

average of 3 percent of the total available

DRAM time, which implies that the CPU

only has access to the DRAM 97 percent

of the time


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SRAM vs DRAM


Bits stored as on/off switches Bits stored as charge in capacitors

No charges to leak Charges leak

No refreshing needed when powered Need refreshing even when powered

More complex construction Simpler construction

Larger per bit Smaller per bit

More expensive Less expensive

Does not need refresh circuits Need refresh circuits

Faster Slower

Cache Main memory

Digital

-Uses flip-flops

Essentially analogue

-Level of charge determines value


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SRAM vs DRAM

SRAM DRAMdoes not need to be refreshed requires the data to be refreshed

periodically in order to retain the data

Faster

transistors inside would continue to hold

the data as long as the power supply is

not cut off

slower and less desirable

The additional circuitry and timing

needed to introduce the refresh

SRAM modules are also much simpler DRAM modules are complicated

needs a lot more transistors for every bit

of data - 6

needs a transistor and a capacitor for

every bit of data

Expensive lower priceCommonly used in cache memory speed

is crucial

used in main memory

Low power consumption High power consumption


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Summary sram vs dram

SRAM are fast, require no refresh and have

low bit densities

DRAM are slower and require extra logic forrefresh and other timing controls, but are

cheaper, consume less power, and have very

large bit densities


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memory size of standard memory

chipsPin Connection Of RAMmemory chip is normally recognized by its memory capacity.

Which has 2 main elements :i) Address Size

ii) Data Size

32 x 4

4K x 8

2K x 8

(Address Size) (Data Size)

memory chip has many pins with specific function of each pin or group of pins :

i) Address

ii) Data

iii) Chip Capacity

* 1 Kbyte = 1024 Bitsiv) The Control lines/pins

- Control R/W

- Memory Enable (ME)

v) Pins Layout of memory chip


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ex : chip capacity label 32 X 4i) Address

How to determine address lines or pins?

has address size of 32 memory location / cells(where each cell has a data size of 4 bits)

2n = 32

log 2n = log 32

n log 2 = log 32

n = log 32 / log 2

= 5

5 address lines / pins which labeled as An = A1, A2, A3, A4


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ex : chip capacity label 32 X 4

ii) Data

How to determine data lines or pins?

has data size of 4 bits

4 data lines / pins which labeled as Dn = D0,

D1, D2, D3


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ex : chip capacity label 32 X 4iii) Chip Capacity

Chip Capacity label 32 X 4= 128 bits

iv) The Control lines / pins

Control R / W

R = logic 0 to run READ operationW = logic 1 to run WRITE operation

Memory Enable (ME)

memory is made up of several memory chips connected together.

each chip represents certain range of address, thus we need to set the only

appropriate chipto be made active whereas the others set inactive.

this is done by sending a logic to the control pin ME.

ME = logic 0 = memory Disable

ME = logic 1 = memory Enable


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ex : chip capacity label 32 X 4v) Pins Layout of memory chip


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Exercise :

A memory chip with capacity of 5K x 8, determine :

a) numbers of data linesb) numbers of address lines

c) capacity in Bits, Byte, Kbyte

d) draw the pins layout block diagram


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Understand memory systems design

Explain the operation of bus buffering


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Extra notes : (terminologies)

The term Fan Out is a measure of how manyloads a pin can drive. This is usually normalized tothe load of a standard TTL input, which is

considered to be a Fan In of 1. This is a digitallogic term, not necessarily just a microprocessorterm.

Fan In and Fan Out are important, because youdo not want to exceed the rated load placed on apin without providing extra buffering.


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Operation of bus buffering


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Address Bus Buffering


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Data Bus (Bidirectional) Buffering


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Understand memory systems design

Explain method for storing and reading data from

memory system


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Storing and Reading data from memory

system

A general procedure of memory access (read)

1. CPU pulls up R/!W signal to indicate a Readoperation

2. CPU puts memory address on the address bus 3. CPU asserts !AS, !UDS/!LDS to indicate valid

address, and waits

4. Once memory sees active !AS, it assumes valid

address on address bus, reads out data from memorymodule and puts it on data bus, then assert !DTACK

5. CPU waits till it sees active !DTACK, then read datafrom the data bus


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READ


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READ


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READ


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READ


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READ


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READ


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WRITE


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Memory Address Decoding The need for memory address decoding arises from the fact

that the main memory of a computer system is notconstructed from a single component, which uniquely

addresses each possible memory location.

Imagine a situation where two 1M memory chips areconnected to a 32-bit address bus to make 2M of memory

available. Each memory chip will need twenty address lines to

uniquely identify each location in it. If the address lines of

each memory chip were simply connected to the first twenty

CPU address lines, then both memory chips would be

accessed simultaneously whenever the CPU referred to any

address. There are several memory addressing schemes that

address this problem.


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Partial Address Decoding This is the simplest and least expensive form of address

decoding. We could connect the chip select input of one

memory chip to the last CPU address line, and the chip select

input of the other to the same address line but via an inverter.

In this way the two chips would never be accessed

simultaneously.

However, this is very inefficient. Eleven of the address lines

are not used, and one of the two memory chips is always

selected. The usable address space of the computer has beenreduced from 4G to 2K. Partial address decoding is used in

small dedicated systems where low cost is the most important

factor. The penalty paid is that not all the address space can

be used, and future expansion will be difficult.


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Full Address Decoding

Full address decoding is when each addressable location

within a memory component corresponds to a single address

on the CPU's address bus. That is, every address line is used to

specify each physical memory location, through a

combination of specifying a device and a location within it.

Full address decoding is very efficient in the use of the

available address space, but is often impracticable to use

because of the excessive hardware needed to implement it.

This is particularly true where devices with a small number of

addressable locations (for example memory-mapped I/O

devices) are used.


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Full Address Decoder Design

1. Determine available information.

2. Determine the required number of address lines.

3. Set base address.

4. Determine lower address range.5. Determine upper address range.

6. Design decoder.

7. Draw memory block diagram


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Example

512kWords (1024 kB) of RAM needs to be interfaced

to a 68k-based system, The base address is $400000.

Design the decoder circuit.


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Step 1: Determine Available Information

Three things must be determined:

How much memory to interface.

Base address of memory.

How many chips need to be used.


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1024 kB (512 kWords)

Chip #1

(512 kB)

(even

addresses)

Chip #2

(512 kB)

(odd

addresses)

* Controlled by UDS * Controlled by LDS


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Step 2: Determine Number of

Required Address Lines

Determines how many address lines need to be used by one

chip.

Use the following formula:

2log

log

10

10 yx y = storage size of one chip (kB)

x = number of reserved lines


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Each chip contains 512,000 memory locations:

Needs 19 address lines.

000,5122 x

000,512log2log 1010 x

1997.183010.07093.5

2log000,512log

10

10x

*Always round to higher.


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Step 3: Allocate Address Line

Address lines allocated based on Step 2.

Start with A1.

Fill with dont cares (X).

A23 A22 A21 A20 A19

X

A18

X

A17

X

A16

X

A15

X

A14

X

A13

X

A12

X

A11

X

A10

X

A9

X

A8

X

A7

X

A6

X

A5

X

A4

X

A3

X

A2

X

A1

X

A0

UDS/LDS

(reserved)

19 lines allocated


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Step 4: Set Base Address

Set base address using the remaining address lines.

A23

0

A22

1

A21

0

A20

0

A19

X

A18

X

A17

X

A16

X

A15

X

A14

X

A13

X

A12

X

A11

X

A10

X

A9

X

A8

X

A7

X

A6

X

A5

X

A4

X

A3

X

A2

X

A1

X

A0

UDS/LDS

(reserved)

4

* Base address is $400000


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Step 5: Determine Lower Address

Range Replace all dont cares and A0 with zeros.

Should get the same base address as question.

A23

0

A22

1

A21

0

A20

0

A19

0

A18

0

A17

0

A16

0

A15

0

A14

0

A13

0

A12

0

A11

0

A10

0

A9

0

A8

0

A7

0

A6

0

A5

0

A4

0

A3

0

A2

0

A1

0

A0

0

4 0 0 0 0 0

Lower range: $400000

A23

0

A22

1

A21

0

A20

0

A19

0

A18

0

A17

0

A16

0

A15

0

A14

0

A13

0

A12

0

A11

0

A10

0

A9

0

A8

0

A7

0

A6

0

A5

0

A4

0

A3

0

A2

0

A1

0

A0

0

4Fill with zeros


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Step 6: Determine Upper Address

Range Replace all dont cares and A0 with ones. This determines the upper limit of the memory chip address.

A23

0

A22

1

A21

0

A20

0

A19

1

A18

1

A17

1

A16

1

A15

1

A14

1

A13

1

A12

1

A11

1

A10

1

A9

1

A8

1

A7

1

A6

1

A5

1

A4

1

A3

1

A2

1

A1

1

A0

1

4Fill with ones

A23

0

A22

1

A21

0

A20

0

A19

1

A18

1

A17

1

A16

1

A15

1

A14

1

A13

1

A12

1

A11

1

A10

1

A9

1

A8

1

A7

1

A6

1

A5

1

A4

1

A3

1

A2

1

A1

1

A0

1

4 F F F F F

Upper range: $4FFFFF


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Actual Implementation

512kB

RAM

512kB

RAM

LDS

CS CSE E

UDS

A1

A19

A1

A19

D8

D15

D0

D7

CS

MAD

NAND

A23A22

A21

A20

AS

EVEN ODD

WE WE

R/W


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Step 8: Draw Memory Block Diagram

Memory block diagram shows assignment of memory addresses.

Begins at $000000, ends at $FFFFFF.

Mark the locations where memory has been interfaced.

unused

Interfaced with M68k (1024 kB RAM)

unused

$FFFFFF

$000000

$400000

$4FFFFF

(Lower Range)

(Upper Range)


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Partial Address Decoding

This is the simplest and least expensive form of address decoding.

We could connect the chip select input of one memory chip to the

last CPU address line, and the chip select input of the other to the

same address line but via an inverter. In this way the two chips

would never be accessed simultaneously. However, this is very inefficient. Eleven of the address lines are not

used, and one of the two memory chips is always selected. The

usable address space of the computer has been reduced from 4G to

2K. Partial address decoding is used in small dedicated systems

where low cost is the most important factor. The penalty paid is

that not all the address space can be used, and future expansion

will be difficult.


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Partial Address Decoding Example

SELROMLDSUDS

2kBROM

2kBROM

CS CSOE OE

A1A

11

A1A

11

D8D

15

D0D

7

SELRAM

2kBRAM

2kBRAM

CS CSE E

A1A

11

A1A

11

D8D

15

D0D

7

LDSUDS

A12

AS

MAD

*Not all address lines used:A12 for MAD

A1

A11 for addressing

Comparison between FAD and PAD


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Comparison between FAD and PAD

Partial Address DecoderFull Address Decoder

Address lines used

Uses only a part of address

lines for addressing

or decoding. The rest is

ignored.

Uses all lines for

addressing or decoding.

MAD circuit Less complex circuit, sinceonly a few address lines

are used.

More complex circuit, sinceneed to use all address lines.

When to useWhen M68k system has

small memory requirements.

When the M68k system is

large and requires a lot

of memory.

Upgrade

Difficult to upgrade, requires

complete redesign of

decoder.

Easy to upgrade, extra

memory can be added

with little modifications

to original decoder.


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Full Address Decoder


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Full Address Decoder cont


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Partial Address Decoder


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Partial Address Decoder cont


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DESIGN MEMORY ADDRESS


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DESIGN MEMORY ADDRESS

DECODER

Step 1 :

Identify how many chips we need to address and the capacity of each chip.

For instance .....

Memory Chip Capacity of chipPROM-0 2K x 8

PROM-1 2K x 8

PROM-2 2K x 8

PROM-3 2K x 8

DESIGN MEMORY ADDRESS DECODER


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CONT

Step 2 :

Determine the chip Address Range.

As shown in the memory mapping section, for the fixed data size of 8 bits, each

chip (same capacity) has the same location size of :

2K = 2 x 1024

= 204810

= 80016

Memory Chip Range Start Range EndPROM-0 0000 07FF

PROM-1 0800 0FFF

PROM-2 1000 17FF

PROM-3 1800 1FFF



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CONT

Step 3 :Determine Address lines.

Memory Block = 0000 until 1FFF

= 200016

= 819210

2n = 8192

log 2n = log 8192

n log 2 = log 8192

n = log 8192 / log 2= 13

An = A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12



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CONT

Step 4 :

Draw out the Address Line Tables :

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

PROM-0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0

07FF 0 0 1 1 1 1 1 1 1 1 1 1 1

PROM-1 0800 0 1 0 0 0 0 0 0 0 0 0 0 0

0FFF 0 1 1 1 1 1 1 1 1 1 1 1 1

PROM-2 1000 1 0 0 0 0 0 0 0 0 0 0 0 0

17FF 1 0 1 1 1 1 1 1 1 1 1 1 1

PROM-3 1800 1 1 0 0 0 0 0 0 0 0 0 0 0

1FFF 1 1 1 1 1 1 1 1 1 1 1 1 1



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CONTStep 4 cont :

From the above table :

(a) Since all chip has similar START / END address bits for address lines : A10 A0;

Thus A10A0 are the common lines to all chips.

(b) Address line that changes : A12A11

To simplify the above table,

We group the common lines in hex digit instead of bits.

Two LSD are common,

Whereas the two MSD will distracted into bits.The simplified table will be as follows :

A12 A11 A10 A9 A8 A7 A0

PROM-0 0000 0 0 0 0 0 00

07FF 0 0 1 1 1 FF

PROM-1 0800 0 1 0 0 0 00

0FFF 0 1 1 1 1 FF

PROM-2 1000 1 0 0 0 0 00

17FF 1 0 1 1 1 FF

PROM-3 1800 1 1 0 0 0 00

1FFF 1 1 1 1 1 FF



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CONT

74LS138

C 0

B 1

A 2

3

4

5

6

7

o

o

o

o

o

o

o

o

o

o

o PROM 0 : 0000H 07FFH

PROM 1 : 0800H 0FFFH

PROM 2 : 1000H 07FFH

PROM 3 : 1800H 18FFH

0

A12

A11

Common lines to

all 4 chips

A10 A0

lines that that used to

select one of the fourPROM



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CONT

Step 6 :

Draw out the complete Memory Circuit.

EXERCISE


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EXERCISE

Memory Chip Capacity of Chip

PROM 0 2K x 8

PROM 1 6K x 8

PROM 2 4K x 8

PROM 3 8K x 8

chapter 4 memory element

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