chapter 4 development and implementation of pbl...

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CHAPTER 4

DEVELOPMENT AND IMPLEMENTATION OF PBL

BASED INSTRUCTIONS __________________________________________________________

4.1 DEVELOPMENT AND IMPLEMENTATION OF PBL BASED

INSTRUCTIONS IN ANALOG ELECTRONICS 4.1.1 SYLLABUS OF THEORY AND PRACTICAL COMPONENTS

The theory component covers the following:

HIGH FREQUENCY TRANSISTOR

The high frequency T-model, common base short circuit current frequency response,

alpha cutoff frequency, common emitter short circuit current frequency response,

hybrid-π CE transistor model, hybrid-π conductance in terms of low frequency h-

parameters, CE short circuit current gain obtained with hybrid-π model, current gain

with resistive load.

LARGE SIGNAL AMPLIFIERS

Class-A direct coupled with resistive load, transformer-coupled with resistive load,

design theory, power amplifier design, harmonic distortion, power output, variation

of output power with load, thermal runaway, output transformer saturation, push-pull

amplifiers, operation of class-A push-pull amplifier, class-B push-pull amplifier,

crossover distortion, class-AB push-pull amplifier, transistor phase inverter,

conversion efficiency of class-B amplifiers, design of Class-B push-pull amplifier,

complementary-symmetry amplifier.

MULTISTAGE AMPLIFIERS

Coupling of transistor amplifiers, frequency response of coupled amplifiers,

cascading of RC-Coupled amplifiers and their analysis, tuned amplifiers - single

tuned, double tuned and stagger tuned amplifiers and their analysis.

FEEDBACK IN AMPLIFIERS

Types of feedback, effect of negative feedback on gain, bandwidth, stability,

distortion and frequency response, voltage-series, current-series, voltage-shunt,

current-shunt feedback circuits and their analysis.

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OSCILLATORS

Conditions of oscillations, different types of oscillators - RC Phase Shift, Wein

Bridge, Hartley, Colpitts and Crystal oscillators, derivation of expressions for

frequency and amplitude of these oscillators.

REGULATED POWER SUPPLIES

Zener diode as voltage regulator, transistor series and shunt regulators, current

limiting, line and load regulation.

The list of practical in EC212, as prescribed by PTU is:

1. To study the various coupling techniques for transistor amplifiers.

2. To study the characteristics of a Class-A amplifier.

3. To study the characteristics of Class-B amplifier.

4. To study the characteristics of Class-C amplifier.

5. To study the characteristics of Class-AB amplifier.

6. To study the characteristics of Class-B push-pull amplifier.

7. To study the characteristics of complementary symmetry amplifier.

8. To study transistor series voltage regulator with current limit and observe

current fold-back characteristics.

9. To study the response of RC phase shift oscillator and determine frequency

of oscillation.

10. To study the response of Hartley oscillator and determine frequency of

oscillation.

11. To study the response of Colpitt’s oscillator and determine frequency of

oscillation.

12. To study the response of Wien Bridge oscillator and determine frequency of

oscillation.

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4.1.2 TIME PLAN FOR CG AND TG

As shown in the table 4.1, while the students in CG were being taught by Traditional

method, the students in TG [55a] were solving open ended Technical Problems as

given in section 4.1.3.1. The time line for covering the syllabus and distribution of

ATS, MSTs and End semester Knowledge and skill tests are shown in table 4.1. The

second unit – ‘High Frequency Transistor’ was covered in traditional way only, for

both CG and TG. This table also shows how the time plans for TG and CG were

made parallel for delivery schedule.

The four assessment tools – ATSs, MSTs, End Semester Knowledge Test and End

Semester Skill Test are given in Appendices C, D, E and F respectively.

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S. No.

Topic CG DATE TG ATS

1 Class-A direct coupled with resistive load, transformer coupled with resistive load, design theory, power amplifier design, harmonic distortion, power output, variation of output power with load, thermal runaway, output transformer saturation, push-pull amplifiers, operation of class-A push-pull amplifier, class-B push-pull amplifier, crossover distortion, class-AB push-pull amplifier, transistor phase inverter, conversion efficiency of class-B amplifiers, design of Class-B push-pull amplifier, complementary- symmetry amplifier.

08 19 Jan

to 7 Feb

TP1 TP2

ATS1

2 The high frequency T model, common base short circuit current frequency response, alpha cutoff frequency, common emitter short circuit current frequency response, hybrid-π CE transistor model, hybrid-π conductance in terms of low frequency h- parameters, CE short circuit current gain obtained with hybrid-π model, current gain with resistive load.

03 9 to 14 Feb ATS2

3 Coupling of transistor amplifiers, frequency response of coupled amplifiers, cascading of RC-Coupled amplifiers and their analysis, tuned amplifiers - single tuned, double tuned and stagger tuned amplifiers and their analysis. Types of feedback, effect of negative feedback on gain, bandwidth, stability, distortion and frequency response etc.

07 16 Feb to 04

March TP3 ATS

3

Mid Semester Test I 4 Voltage series, current series, voltage shunt, current shunt

feedback circuits and their analysis. 03 16 to

21 March

5 Conditions of oscillations. Different types of oscillators: RC Phase Shift, Wein Bridge, Hartley, Colpitts and Crystal Oscillators. 06

23 March

to 4 April

6 Derivation of expression for frequency and amplitude of these oscillators. 06 6 to 17

April

TP4

7 Zener diode as voltage Regulator, Transistor Series and Shunt Regulators, Current limiting, Line and Load Regulation 06

20 April to 01 May

TP5

ATS4

Mid Semester Test II End Semester knowledge Test and Skill Test

Table 4.1 : Lecture Plan of Analog Electronics for CG and Time line for both TG and CG

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Lab Plan for CG of Analog Electronics for batch 2004 and 2005 (Conducted in Jan–

May 2006 and Jan–May 2007)

The students in CG conducted the experiments according to the lab plan in table 4.2.

The students in TG decided their own practical objectives and conducted the

experiments in the two hour PBL sessions. They did not have structured or separate

lab sessions.

S. no. Topic PL Date

1 To study the various coupling techniques for Transistor amplifier.

1 01/19 - 01/30

2 To study the characteristics of a Class-A Amplifier.

1 02/02 - 02/06

3 To study the characteristics of a Class-AB Amplifier.

1 02/09 - 02/13

4 To study the characteristics of a Class-B push-pull Amplifier.

1 02/16 - 02/20

5 To study the characteristics of complementary symmetry Amplifier.

1 02/23 - 02/27

6 To study Transistor series voltage regulator with current limits and observes current fold-back characteristics.

1 03/02 - 03/04


1 03/16 - 03/20

7 Revision 1 03/23 - 03/27 8 To study the response of RC phase shift

oscillator and determine frequency of oscillation.

1 03/30 - 04/03

9 To study the response of Hartley oscillator and determine frequency of oscillation.

1 04/06 - 04/10

10 To study the response of Colpitt’s oscillator and determine frequency of oscillation.

1 04/13 - 04/17

11 To study the response of Wein Bridge oscillator and determine frequency of oscillation.

1 04/20 - 04/24

Table 4.2 : Lab Plan of Analog Electronics for CG

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4.1.3 DETAILS OF THE TREATMENT GROUP (PBL THREAD)

The Open Ended Technical Problems (TPs) given in the section 4.1.3.1 were given

to the students in TG [55b], one after the other, as per the time line given in table

4.1. The students traversed the conceptual space while solving these TPs, touching

maximum technical nodes and achieving as many learning objectives, as in table 4.3,

in section 4.1.3.2 The journey through the conceptual space was facilitated by

triggers (examples given in section 4.1.3.3), supplied by facilitator and the students,

themselves.

4.1.3.1 Technical Problems

The tutor gave students an example of a small audio system, as per the block

diagram given in Fig 4.1

Front End (A)

Processing Circuit

(B)

Voltage Amplifier

(C)

PowerAmplifier

(D)

ControlCircuit

(E)

SinusoidalOscillator

(F)

Regulated Power Supply

(G)

Rectifier(H)

220 VACO/P3, To Other Circuit

O/P2, To Other Circuit

I/P

Fig 4.1 : Block diagram of audio system

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TP 1: In the front end block (A) of the audio system, a voltage amplifier is to be

designed. You are given a readymade small signal amplifier for this purpose,

with a fixed bias. The bias resistors are R1 = 3 kΩ and R2 = 3 kΩ, Rc = 12kΩ and

Re = 5 kΩ, and the transistor to be used is BC107. Before proceeding further with

the design you must;

• Determine the Q-point and draw the load lines.

• Determine what happens if you change the values of various biasing

resistors.

The input signal available is 10mVp-p, 0Vdc.

• Draw the output for the given configuration. Also find out what happens if

you apply the input signal to transistors biased at cut-off and below cut-off.

• Comment on the current gain, voltage gain and power gain of such

configurations.

TP 2: The last block (D) in figure 4.1, is required to deliver 0.6W of power to a

20Ω speaker. The signal strength is 10mVp-p.

Give as many circuit designs as possible with a transistor as the active device.

Compare the designs with respect to their respective advantages, power

dissipated, useful power being delivered to the load and their efficiencies.

TP 3: Even after the first stage of voltage amplification, the processing circuit in

the second stage (B) introduces a lot of attenuation, and the signal strength

reduces to 10 -100µV p-p. To ensure that the first stage drives the subsequent

circuit properly, a voltage signal of at least 10Vp-p, is required. You are using the

circuit with a 15V supply.

Design a single stage amplifier to develop the required output.

Design a two/three stage amplifier to have the same gain.

Compare the above designs with respect to:

• Simplicity of design,

• Stability of gain,

• Methods of coupling multistage amplifiers,

• Saturation levels.

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TP 4: In the same audio system, when there is no signal at the input, self-

sustained sinusoidal oscillations of 2Vp-p amplitude and of following frequencies

are to be generated:

(i) 200 Hz

(ii) 20 kHz

(iii) 20 MHz

Then, depending on the control circuit output, any one of these oscillations is to

be selected and given as input to some other part of this audio system.

Design circuits, which serve the above purpose. What changes should you make

in the circuits, so that the frequency can be varied in the range ±10%?

Give as many circuit variations as you can. Discuss their relative advantages and

disadvantages.

Of the designed circuits, which one has the best stability?

TP 5: The rectifier circuit which you are using for this audio system derives its

input from 220V AC and converts it into 15V DC. However, because of poor

regulation, any fluctuation in the input AC volts causes the DC output to vary by

as much as 10V to 20V. This variation causes a problem in the circuit as the

voltage variation, the circuit can tolerate is only ±0.1%. Design a voltage

regulator circuit (G) to control this fluctuation. Explain the working principle of

such a regulator and derive the expressions for line and load regulation.

4.1.3.2 Learning Objectives and Technical Nodes

Example of technical nodes and learning objectives are:

Topic: Large signal Amplifier:

Technical Nodes: (a) Recall the concept of biasing of transistors

(b) Identify and describe three regions of operations of transistor

(c) Develop, understand and apply the formulae of amplifications (current,

voltage and power);

(d) Recognize, compare and describe circuit diagrams of class-A, B and C

amplifiers etc.

Learning Objectives: (a) The students should be able to classify large signal

amplifiers in light of the biasing of the transistor.

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(b) The students should be able to decide which amplifier to use for a particular

application and complete the design process for this large signal amplifier, with

the given specifications.

(c) The students should be able to troubleshoot a faulty design of a large signal

amplifier and rectify it for appropriate working.

Topic Number of maximum technical nodes, Learning Objectives

Number of technical nodes covered by grp1 to grp5

Average number of Learning objectives achieved by groups

Grp1 Grp2 Grp3 Grp4 Grp5 High frequency analysis of transistors

10, 4 10 14 13 9 7 4

Large signal amplifiers

25, 7 24 25 26 19 14 7

Multistage amplifiers 26, 5 23 27 24 26 16 5 Feedback in amplifiers

15, 7 14 15 17 15 12 7

Oscillators 24, 5 23 24 28 20 20 5 Regulated power supply

9, 4 8 9 8 7 8 4

Table 4.3 : Average number of technical nodes covered and learning objectives achieved by teams in PBL thread of Analog Electronics

4.1.3.3 Examples of Triggers

The words like – ‘determine’, ‘draw’, ‘comment’ in the problem statements were

used to cover various domains in the cognitive domain. While the words - Q-point,

biasing resistors, cut-off, below cut-off, current gain, voltage gain and power gain

relate to the previous knowledge base of the students.

Some, but not all, triggers used by facilitator were:

• Is it all? Perhaps you could verify it on the software, try some more

combinations of biasing resistors, try your hands on the practical board to

authenticate,

• The given combination of biasing resistors is completely invalid. It doesn’t

satisfy Kirchhoff’s Voltage Law (KVL) and Kirchhoff’s Current Law (KCL).

• But the power is too large to be delivered to the output.

• Consider redistributing your work.

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• Add this to your learning objectives.

• Verify your calculations.

• We can discuss it in the GD at the end of the class. Collect the facts in support of

your theory.

• Why don’t you consult some specification sheets of power transistors in the data

sheets?

• But the efficiency is too less (or more).

• Some, but not all, triggers used by the students were:

• Let us try replacing the load in the amplifiers developed in problem 1.

• But we just found that the voltage amplifiers need not necessarily give power

amplification too.

• Let us refer to the literature.

• Can I find some pre calculated things on the internet?

• Let us calculate the values to find out the values of power amplification

• Since there are so many classes of amplifiers, let us design each one of them for

this value of power output.

• Will the same transistor, which we used in problem 1, work here?

• My resistor of 20Ω got burnt while doing the practical. Why? Even the transistor

is getting heated up.

• How do I actually measure power to find the power amplification?

• Why are the push–pull configuration and complementary-symmetry

configurations so called?

• I have only a particular transistor available for authenticating my result

practically, while I did my design calculations without bothering whether the

transistor is available in the lab or not. Now what should we do?

• We are getting a large variation in theoretical, software and practical results. Are

we wrong? Can we account for our errors?

• We will have to try some different combinations of resistors.

• We have heard of active, cut off and saturation regions of the transistors, but

what is –below cut off?

• When we apply the signal to this configuration, the signal clips off from the

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bottom. I wonder, what might be the use of such an amplifier configuration?

• Although the voltage amplification is good, I see that there is no appreciable gain

the power. Why it might be so?

• This software has various components in the library, and I can place them too, in

the worksheet area joining them as I like. Let me find out if it has some

simulation tools too.

• There can be so many combinations of biasing resistors for the same transistors,

which one can be the best?


INSTRUCTIONS IN DIGITAL ELECTRONICS 4.2.1 SYLLABI OF THEORY AND PRACTICAL COMPONENTS

The theory component of Digital Electronics (EC 204) is set to cover following

topics:

THE NUMBER SYSTEM AND BINARY CODE: Introduction, binary, octal and

hexadecimal number system, signed and unsigned number, binary operations -

addition; subtraction, multiplication and division; subtractions using 1's and 2's

compliment; ASCII code; excess-3 code, gray code.

MINIMIZATION OF LOGIC FUNCTION: OR, AND, NOT, NOR, NAND, EX-OR

gates, basic theorem of Boolean algebra, sum-of-products and product-of-sums,

canonical form, minimization using theorems, minimization using K-map and Q-M

method. incompletely specified functions.

COMBINATIONAL LOGIC CIRCUITS: Introduction, combinational circuit

design, multiplexers, demultiplexer, encoders, decoders, adders, subtracters and code

converters, parity checker, BCD display drive, magnitude comparators.

SEQUENTIAL CIRCUITS: Introduction, flip-flop - SR, JK, D, T, edge-triggered

and decked flip-flop, registers, type of registers, circuit diagram, timing wave form

and operations counters, counter design with state equation and state diagrams.

D/A AND A/D CONVERTERS: Introduction, weighted register D/A converter,

binary ladder D/A converter, steady state accuracy test, D/A accuracy and resolution,

parallel A/D converter, counter type A/D converter, successive approximation A/D

converter, single and dual slope A/D converter A/D accuracy and resolution,

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voltage-of-frequency conversion, voltage-of-time conversion.

SEMICONDUCTOR MEMORIES: Introduction, memory organization,

classification and characteristics of memories, sequential memories, ROMs, R/W

memories, content addressable memories, programmable logic arrays, charged-

coupled device memory.

LOGIC FAMILIES: RTL, DCTL, DTL, TTL, ECL and its various types,

comparison of logic families.

The practical Component of the subject Digital Electronics (EC212) comprises of

following experiments:

1. Verification of the truth tables of TTL gates, e.g., 7400, 7402, 7404, 7408, 7432,

7486.

2. Design, fabrication and testing of low frequency TTL clocks using NAND gates.

3. Verification of the truth table of the Multiplexer 74150.

4. Verification of the truth table of the De-Multiplexer 74154.

5. Design and verification of the truth tables of half adder and full adder circuits

using gates 7483.

6. Study and verification of the operations of ALU 74181 with regards to addition /

subtraction / comparison.

7. Design fabrication and testing of differentiator and integrator circuits using OP

AMP.

8. Design fabrication and testing of clipper and clamper circuits using OP AMP.

9. Design fabrication and testing of

a. Monostable multivibrator of t = 0.1 ms using 74121/123. Testing for both

positive and negative edge triggering, variation in pulse with and retriggering.

b. Free running multivibrator at 1KHz and 1Hz using 555 with 50% duty cycle.

Verify the timing from theoretical calculations.

10. Design of an S-R flip-flop using OR/NAND gates.

11. Verification of the truth table of a J-K flip-flop (7476).

12. Verification of the truth table of a D flip-flop (7474) and study its operation in

the toggle and asynchronous modes.

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14. Operation of the counters 7490, 7493 and 74192. Verification of the frequency

division at each stage.

15. Verification of the truth table of decoder driver 7447 / 7448. Operation of a 7

segment LED display through a counter using a low frequency clock.

16. Repetition of above with the BCD to Decimal decoder 7442 and an array of

LEDs.



method, the students in TG were solving open ended Technical Problems as given in

section 4.2.3.1. The time line for covering the syllabus and distribution of ATS,

MSTs and End semester Knowledge and skill tests are shown in table 4.4. The

seventh and eighth units - ‘Semiconductor memories’ and ‘Logic Families’ were

covered in traditional way only, for both CG and TG. This table also shows how the

time plans for TG and CG were made parallel for delivery schedule.


Semester Skill Test for Digital Electronics are given in Appendices G, H, I and J

respectively.

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S.No Topic No. of

LecturesDates TP ATS

1

Number System And Binary Code: Introduction, binary, octal and hexadecimal number system, signed and unsigned number, binary operations - addition; subtraction, multiplication and division; subtractions using 1's and 2's compliment; ASCII code; excess-3 code, gray code.

3 07-01

to 15-01

2

Minimization of logic function: OR, AND, NOT, NOR, NAND, EX-OR gates, basic theorem of Boolean algebra, sum-of-products and product-of-sums, canonical form, minimization using theorems, minimization using K-map and Q-M method. incompletely specified functions.

6 16-01

to 24-01

TP1 TP2 TP3 TP4

ATS1

3

Combinational Logic Circuits: Introduction, combinational circuit design, multiplexers, demultiplexers, encoders, decoders, adders, subtracters and code converters, parity checker, BCD display drive, magnitude comparators.

10 25-01

to 22-02

TP5 TP6 TP7

ATS2

MST I

4

Sequential Circuits: Introduction, flip-flop - SR, JK, D, T, edge-triggered and decked flip-flop, registers, type of registers, circuit diagram, timing wave form and operations counters, counter design with state equation and state diagrams.

7 25-02

to 14-03

TP8

5 Counters, counter design with state equation and state diagrams. 3

24-03 to

31-03 TP9

ATS3

6

D/A and A/D Converters: Introduction, weighted register D/A converter, binary ladder D/A converter, steady state accuracy test, D/A accuracy and resolution, parallel A/D converter, counter type A/D converter, successive approximation A/D converter, single and dual slope A/D converter A/D accuracy and resolution, voltage-of-frequency conversion, voltage-of-time conversion.

3 01-04

to 08-04

TP10

7

Semiconductor Memories: Introduction, memory organization, classification and characteristics of memories, sequential memories, ROMs, R/W memories, content addressable memories, programmable logic arrays, charged-coupled device memory. LOGIC FAMILIES: RTL, DCTL, DTL, TTL, ECL and its various types, comparison of logic families.

3 09-04

to 15-04

8 Logic Families: RTL, DCTL, DTL, TTL, ECL and its various types, comparison of logic families. 3

16-04 to

23-04

ATS4

MST II End Semester knowledge and skill test

Table 4.4 : Lecture plan of Digital Electronics for CG and Time line for both TG and CG

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Lab Plan of Digital Electronics




lab sessions.

S.no Topic No. of Labs

Dates

1 To study the various coupling techniques for Transistor amplifier. 1 19/1 – 30/1

2 To study the characteristics of a Class-A Amplifier. 1 02/02 – 06/02

3 To study the characteristics of a Class-AB Amplifier. 1 09/02 – 13/02

4 To study the characteristics of a Class-B push-pull Amplifier. 1 16/02 – 21/02

5 To study the characteristics of complementary symmetry Amplifier. 1 23/02 – 27/02


1 02/03 – 04/03

7 To study Transistor series voltage regulator with current limits and observes current fold-back characteristics.(continued)

1 16/03 – 20/03

8 Revision 1 23/03 – 27/03

9 To study the response of RC phase shift oscillator and determine frequency of oscillation.

1 30/03 – 03/04

10 To study the response of Hartley oscillator and determine frequency of oscillation. 1

06/04 – 10/04

11 To study the response of Colpitt’s oscillator and determine frequency of oscillation. 1

13/04 – 17/04

12 To study the response of Wein Bridge oscillator and determine frequency of oscillation. 1

20/04 – 24/04

Table 4.5 : Lab plan of Digital Electronics

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4.2.3 DETAILS OF TREATMENT GROUP (PBL THREAD)


to the students in TG, one after the other, as per the time line given in table 4.4. The

students traversed the conceptual space [55c] while solving these TPs, touching

maximum technical nodes and achieving as many learning objectives, as in table 4.8,

in section 4.2.3.2. The journey through the conceptual space was facilitated by

triggers supplied by facilitator and the students, themselves, as given in section

4.2.3.3.


TP 1

a) Search out for literal meanings of ANALOG and DIGITAL.

b) List at least ten instances / examples / activities in real life which you can

distinctly classify under Analog or Digital heads. Take an example of an

activity analog in nature. Try doing / representing it digitally. Does the overall

ambiguity associated with that activity reduce? Explain your view point.

c) What happens if the valid digits in the present number system are reduced to 9

instead of 10? How will the counting proceed? Show by example.

d) Extrapolate (c) to further reduce the number of digits to 8,7,6,5, and so on to 2.

e) How do basic arithmetic operations take place in these modified number

systems vis-à-vis the number system using base 10.

TP 2

a) Apart from the number systems you developed in TP 1, can you develop some

alphanumeric number system too? Would it ever be advantageous to have such

a number system?

b) Compare Hexadecimal, Octal, and Binary number systems. Show how various

conversions between these number systems take place. Can you devise out

some basic thumb rules for such conversions?

c) Search the literature for alphanumeric and other codes. List them along with

their inventors. You should be able to devise out conversion mechanism from

one code to another.

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TP 3

a) If it is raining outside and I don’t have an umbrella, I will not go out.

If it is raining outside and I have an umbrella, I will go out.

If it is not raining outside and I don’t have an umbrella, I will go out.

If it is not raining outside and I have an umbrella, I will go out.

b) My house has two overhead tanks. I have installed sensors in both the tanks,

which can sense when the water level goes down below 1/4th level. The pump

which is used to lift water to the tanks is required to be switched ON whenever

the level in both tanks goes below 1/4th. Design a control circuit, which takes

inputs from both the sensors and switches the water pump ON.

c) An electronic telephone exchange is being powered by normal power supply.

However, looking at the criticality of the exchange, a power backup generator

is also installed, which can supply the power in case of power failure. An alarm

circuit is to be designed. There will be two LEDs (one green and the other red)

on the front panel of the exchange, such that the green LED glows when power

supply is available. In case of failure of power supply, the exchange draws its

power from generator, and in this case, the green LED goes OFF and the red

LED glows. In case, the generator also goes down, both green LED and red

LED go OFF and a buzzer starts ringing indicating that there is a major failure.

Design this control circuit for both the LEDs and the buzzer.

Define independent and dependant variables in (a), (b) and (c) above.

Develop a mathematical expression for above sets of statements.

Tabulate the above sets of statements symbolically by using variables defined

above, wherever required.

Show the above sets of statements pictorially.

Verify your results practically.

TP 4

The arithmetic and Logic Unit (ALU) of a computer performs the arithmetic and

logic operations for the processor. In this ALU a circuit is to be designed, where in

two 4 bit binary numbers are to be subtracted using 2’s compliment. Design a

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combinational circuit for the same.

TP 5

You are reporting for duty in your first ever assignment as graduate trainee in the

design department of an electronics firm. The following problem has been given to

you:

A portion of the transceiver electronics of the exchange is depicted in the form of

block diagram in Figure 4.2

Fig 4.2 : A portion of transceiver electronics of the Telephone Exchange

Both the exchanges cater for 2n users. Depending on n selection lines you have to

design and test the multiplexer and demultiplexer circuits in the exchange. You

have to find out the commercially available ICs from at least three vendors and

prepare a BOM (Bill of Material). Your boss has given you a time limit of 4 hrs to

design the same and submit the solution in written form. The data available from

users are in analog form.

TP 6

In a Computer, the Central Processing Unit (CPU) works as the brain. It not only

does the Calculations and Logical operations but also takes care of input and

User 1

User 2

User 2n

Mux

Dmux

Dmux

Mux

Channel

User 1

User 2

User 2n

n selection lines n selection lines

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output operations. In such a generalized operation, there are 8 devices that this

processor is handling. The tabulation is given below:

Port number Device 0 Printer 1 Scanner 2 Fax machine 3 Key board 4 Mouse 5 Speaker 6 Mike 7 Monitor

Table 4.6 : Port number allocation to various devices

The processor has a 6 bit address bus. Devise a method to generate the port number

of each I/O devices one at a time, and send/receive the data.

Before transmitting analog data using bus, the same is converted into bits and

encoded too. For coding the data, many coding schemes exist. One of the error

detecting codes is an even parity code, which you have studied earlier.

At the receiver, bit streams are being received. They are first passed through an 8-

bit serial to parallel converter. Before feeding them to subsequent processing

circuit, the parity is to be checked in an error detector. Design the detector to do

the needful.

TP 7

In TP 6, you have designed a parity checker. But this parity checker can be used,

only after 8 bit parallel data is available. The incoming data from the

communication channel is always available in serial form only. So, design a 7 bit

serial to parallel converter, to be attached before parity checker, and explain the

use of storage elements in the circuit. Authenticate your design by experimental

verification.

TP 8

The upcoming event of E- Buzz, Kaun Kaun Banega Champion is going to be

hosted in a hall. At any point of time, it is required to know the exact number of

persons present in the hall. There are separate entry and exit points. A sensor, each,

is installed at both the entry and exit points. The sensor at entrance gives an output

+5V, whenever a person enters in the room from entrance door. Similarly, the

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sensor at exit point also gives a voltage of +5V as output whenever a person exits.

At all other times the output of sensors is 0V. Taking these two outputs of the

sensors as input, design a circuit that gives the total count of the persons present in

the hall.

TP 9

A traffic signal is installed at a junction of a railroad and a road. The traffic light is

controlled by two switches in the rails placed one mile apart on either side of the

junction. A switch is turned on when the train is over it and is turned off otherwise.

The traffic light changes from green to red when the beginning of the train is one

mile from the junction. The light changes back to green when the end of the train is

one mile away from the junction. Assume that the length of the train is less than

two miles.

Design, implement and present a circuit which does the needful as described

above.

TP 10

A digital input containing stream of 0’s and 1’s are applied to all the digital circuits

– combinational and sequential. A novice engineer in a laboratory set up applied a

sinusoidal signal (5Vp-p) to a digital counter, hoping that it would count the number

of cycles in the input signal – as the name of the circuit suggests. Will this happen?

Why?

Fig. 4.3 : Control set up of an automated plant

Consider the situation in an automated plant as given in figure 4.3. The signal at

the output of the sampler is a typical analog signal in the range 2Vp-p. However the

Mechanical Process Transducer

Sampler Control Circuit

??

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control circuit is a digital one which can accept the strings of 0’s and 1’s. Suggest

ways and means to make the three blocks ‘Sampler’, ‘Control Circuit’ and

‘Mechanical Process’ compatible to each other. 4.2.3.2 Learning Objectives and Technical Nodes

Technical nodes and Learning Objectives in each unit were identified and listed.

These were further augmented, authenticated and approved by the panel of experts.

The maximum number of technical nodes and learning objectives and the average

number achieved by the teams are given in the table 4.7. Some of the examples of

technical nodes and learning objectives are given below:

Technical Nodes:

• Prepare truth table of a Demultiplexer and Multiplexer.

• Interpret the truth table of a Multiplexer and write the algebraic equation

representing this combinational circuit

Table 4.7 : Average number of technical nodes and learning objectives achieved by Teams in TG (PBL Method) of Digital Electronics

Topic Number of maximum technical nodes, learning objectives



Grp1 Grp2 Grp3 Grp4 Grp5 Number System And Binary Code

15, 5 9 10 11 9 12 4

Minimization of logic function

25, 10 20 18 23 16 24 7

Combinational Logic Circuits

18, 11 13 13 14 13 16 9

Sequential Circuits

19, 9 14 15 17 15 14 6

D/A and A/D Converters

9, 5 5 6 7 7 8 3

Logic Families 8, 4 6 8 5 7 8 3

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• Learning Objectives:

• Students should be able to recognize the circuit of a Demultiplexer and prepare

its truth table.

• Should be able to use Decoder as Demultiplexer and vice versa.

• Should be able to wire the circuit of a Demultiplexer and a Multiplexer and use it

as a complete set.

4.2.3.3 Examples of Triggers

When the students traverse through conceptual space as shown in figure 3.3, the

triggeres are supplied to aid them so that they cover all the technical nodes and

achieve all the learning objectives.

The words like – ‘determine’, ‘make’, ‘comment’, ‘Devise out’, ‘Design’ in the

problem statements were used to cover various domains in the cognitive domain.

While the words- truth Table, Combinational Circuits, Sequential circuits, High /

Low sates, Analog, relate to the previous knowledge base of the students.

Some, bit not all triggers supplied by the facilitator:

• Have you taken care of the indeterminate states?

• May be – you can use Karnaugh map to minimize the expression first.

• I want you to verify the conclusions practically too.

• Authenticate by showing.

• The LED at the output is blinking. May be the voltage levels are not sufficient.

• Consider redistributing your work.

• Your list of learning objectives is still incomplete.

• Do you think the same design can be realized only using NAND gates?

• Try to find out what the terms VOH, VOL, VIL and VIH in the specification sheets

of the TTL ICs mean?

• We can discuss it in the GD at the end of the class. Collect the facts in support of

your theory.

• Can you realize the ALL – NAND circuit when and POS term is given?

Some, bit not all triggers supplied by the students were:

• Let us try realizing an OR gate using NOR and NAND gates.

• But you never seem to do the allotted piece of work.

88

• The library of components in the MULTISIM also has three input NAND gate

available. Let us simulate our circuit with the same.

• Let us calculate the values of voltages and currents in the TTL circuit and

compare them with those at the ECL output.

• Then, what is difference between a latch, register and a Flip flop?

• I will make the state diagram, but you verify this design using timing diagram.

• How will the same circuit work as Up-Down counter?

• The set of statements is what we encounter in our day-to-day lives. It would be

really interesting to depict and denote them mathematically.

• We have done some combinational circuit design in our previous class, are we

doing something new in this class?

• This is difficult, how can the present state depend on previous states!

• Can indeterminate state be verified experimentally? Will it show some voltage

level in between?

• Earlier I thought, only 5V is the high level voltage at the input – it is interesting,

though, to note that even if we have 3.5 volt at the output pin, it is a HIGH

voltage.

• It is amazing to work on MULTISIM. I can actually simulate all my circuits

• Finally, our design works!!


INSTRUCTIONS IN PDSC 4.3.1 Syllabi of Theory and practical Components

The theory component of PDSC is set to cover the following topics:

LINEAR WAVE SHAPING: High pass circuits, response to standard waveforms,

differentiator, double differentiation, low pass circuits, response to standard

waveforms, integrator, attenuator, RLC circuits, ringing circuits.

WIDE BAND AMPLIFIERS: Frequency response of an amplifier, short circuit

current gain, gain & band width consideration, compensation, shunt compensation,

low frequency compensation, and distributed amplifiers.

SWITCHING CHARACTERISTICS OF DEVICES: Steady state and transient

behaviors of electronic (diode & transistor) switches, dynamic analysis of switches,

89

charge storage phenomena, switching characteristics, delay time, rise time, storage

time and fall time, use of Schotkey diode for reducing storage time, behavior of

MOS transistor as switch.

NON- LINEAR WAVE SHAPING: Realization of clipping circuits (diode &

transistor), comparators, champing circuits and sweep generators.

MULTIVIBRATORS: Realization of astable, monostable, bistable, multivibrators

using transistors, unsymmetrical, symmetrical triggering, Schmitt trigger circuits.

The Practical Component of PDSC is set to have following experiments:

1. To verify the working of High Pass Circuit: Application of sawtooth and square

waveforms as input.

2. To verify the working of Low Pass Circuit: Application of sawtooth and square

waveforms as input.

3. To study various clipping circuits.

4. To study various clamping circuits.

5. To design, implement and test various multivibrator circuits.



method, the students in TG were solving open ended Technical Problems as given in

section 4.3.2.1. The time line for covering the syllabus and distribution of ATS,

MSTs and End semester Knowledge and Skill Tests are shown in table 4.8. The sixth

unit – ‘Steady state and transient behavior of electronic devices’ was covered in

traditional way only, for both CG and TG. This table also shows how the time plans

for TG and CG were made parallel for delivery schedule.


Semester Skill Test are given in Appendices K, L, M and N respectively.

90

S.No Topic No. of

Lectures for CG

Dates TPs for TG

ATS

1 High Pass circuits, Response to Standard waveforms, Differentiator, Double differentiation

6 6/08 to 17/08

2 Low pass circuits, response to standard waveforms, Integrator, 3 19/08 to

24/08

3 Attenuator, RLC circuits, Ringing circuits. 6 26/08 to 07/09

TP1 TP2 TP3

4 Frequency response of an amplifier, Short circuit current gain, Gain & Band width consideration

2 09/09 to 14/09

5 Compensation, Shunt compensation, Low frequency compensation, Distributed amplifiers. 3 16/09 to

21/09

TP4

ATS1

MST I

6

Steady state and transient behaviors of electronic (Diode & transistor) Switches, Dynamic analysis of switches, Charge storage phenomena, Switching characteristics, Delay time, Rise time, Storage time and fall time, Use of Schotkey diode for reducing storage time. Behavior of MOS transistor as switch.

8 01/10 to 19/10

7 Realization of clipping circuits (diode & transistor), comparators, champing circuits and sweep generators

2 21/10 to 26/10 TP5

ATS2

8

Realization of astable, monostable, bistable, multivibrators using transistors, unsymmetrical, symmetrical triggering, Schmitt trigger circuits 8 29/10 to

16/11 TP6 TP7 ATS3

MST II

End Semester Knowledge Test

Table 4.8 : Lecture plan of PDSC for CG and time plan for both CG and TG

91

Lab Plan for students in CG




lab sessions.

S.no Topic No. of Labs

Dates

1 To study the response of High Pass circuit to (i) Step (ii) Ramp and (iii) exponential inputs

1 12/08 - 31/08

2 To study the response of Low Pass Circuit to (i) Step (ii) Ramp and (iii) exponential inputs

1 03/09 - 14/09

3 To study shunt compensation of a Wide Band Common Emitter Amplifier

1 16/09 - 21/09

4 To study the Low frequency compensation of Wide Band Amplifier and to calculate the Gain Bandwidth product before and after compensation

1 01/10 - 05/10

5 To design and test a circuit for clipping a sinusoidal waveform at two voltage levels

1 8/10 - 12/10

6 To design and test an electronic circuit which clamps a givnen waveform at predetermined voltage level

1 15/10 - 19/10

7 To design and test a monostable multivibrator 1 21/10 - 26/10 8 To design and test a astable multivibrator 1 29/10 - 02/11 9 To design and test a bistable multivibrator 1 05/11 - 09/11 10 To study a sweep generator of varying frequency 1 12/11 - 16/11

Table 4.9 : Lab Plan of PDSC for CG

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4.3.3 DETAILS FOR TREATMENT GROUP (PBL THREAD)


to the students in TG, one after the other, as per the time line given in table 4.8. The

students traversed the conceptual space while solving these TPs, touching maximum

technical nodes and achieving as many learning objectives, as in table 4.10, in

section 4.3.3.2. The journey through the conceptual space was facilitated by triggers

supplied by facilitator and the students, themselves, as given in section 4.3.3.3.


TP 1

To the two circuits in the given figure 4.4(a) and figure 4.4(b), are applied with

following waveforms:

Fig 4.4(a): Low Pass Circuit

Fig 4.4(b): High Pass Circuit

(a) Sinusoidal (b) Ramp (c) Square (d)Exponential

Sketch the output waveforms for each of the circuits.

Can you authenticate the drawings by calculations and appropriate derivations?

TP 2

Use a function generator to generate a pulse train of highest possible frequency.

Use a laboratory oscilloscope to view the output. Do you still see a perfect pulse

train on the screen? If not, note down the shape of the pulse train as visible on the

scope. Attribute reasons for the distortion – qualitatively and quantitatively.

Give widespread theoretical and practical support and evidence for your answer.

--->I(t)

--->I(t)

93

TP 3

The simple diode circuit given in the figure 4.5 is to be used with the input

waveform indicated in the diagram. When the waveform across the load resistor

1M is to be displayed on the oscilloscope the typical capacitive value of 20pf is

shunted across the load resistor. Draw the output waveform as seen on the scope.

Also determine all voltage and time values on the output waveform plot.

Fig 4.5 : A simple diode circuit

TP 4

The following circuit in the figure 4.6 is given to you fabricated on the bread

board. Plot its characteristics (gain vs frequency plot) on a graph paper. Can you

attribute some reasons to the roll off on both the sides of the characteristics?

Suggest some ways to compensate this roll off and authenticate practically.

Fig 4.6 : A two stage Common Emitter Amplifier

tp

t 0V

-10V

+10V

Q1

50 Kohm

VCC

Vi

2 Kohm

2 Kohm50 Kohm

Ce

Cb

50 Kohm

50 Kohm 2 Kohm

2 Kohm

Q2

Cz

Vo

+

-

94

TP 5

The signal shown in the following figure is applied to the given circuit. Assuming

Rf = 0 and Rr = ∞, find the steady state waveform Vo. Compute the voltage levels

in the waveform assuming different values of V= 1 to 20 V. Also sketch the

waveform if the diode terminals are reversed and if the value of R is changed from

1k to 1M. Assume any value of C between 0.01 to 0.1 µf

Fig 4.7 : A Clamper Circuit

TP 6

It is required to generate a square waveform of 12 kHz using only two identical

BC107 transistors as active devices. You can use resistors and capacitors as

passive components. Design the circuit and authenticate it practically.

TP 7

It is required to supply a pulse of 1µs to an up-down counter to change its mode of

operation. The counter uses TTL ICs. Generate this pulse using two identical

transistors (BC144). Design and authenticate practically.

4.3.3.2 Learning Objectives and Technical Nodes

Technical nodes and Learning Objectives in each unit were identified and listed.

These were further augmented, authenticated and approved by the panel of experts.

The maximum number of technical nodes and learning objectives and the average

number achieved by teams are given in the table 4.10. Some of the examples of

technical nodes and learning objectives are given below:

Technical Nodes

• The students should be able to draw the output waveform of a Low pass R-C

circuit for the four standard signals applied as inputs.

T2 T1

V

95

• Recognize and differentiate in Low pass and High pass R-C circuits.

• Attribute the reason for roll of in the gain vs frequency curve of a trasistor

amplifier.

• Derive an expression for the output waveform of the astable multivibrator.

Learning Objectives

• The students should be able to draw the equivalent circuit of a wideband

amplifier using lumped parameters.

• Should be able to design an astable multivibrator for a given frequency.

• Should be able to design and test a circuit which clamps the given sinusoidal

waveform to a given voltage level.

Table 4.10 : Average number of Technical Nodes covered and Learning Objectives achieved by Teams in PBL thread of PDSC

4.3.3.3 Example of Triggers

When the students traverse through conceptual space as shown in figure 3.3, the

triggers are supplied to aid them so that they cover all the technical nodes and

achieve all the learning objectives.

Some but not all triggers supplied by the facilitator were:

• Try redistributing your work.

• You are going too fast. Do not jump to conclusions.

• You have suggested only one possible combination of resistor and capacitor.

Try some more combinations.

Topic Number of maximum technical nodes, Learning Objectives



Grp1 Grp2 Grp3 Grp4 Grp5 Linear Wave shaping 35, 13 25 24 31 32 20 9 Wideband Amplifiers 11, 7 9 10 8 5 6 4 Switching characteristics of Devices

10, 8 9 8 9 8 7 6

Non Linear Wave shaping

23, 11 22 21 17 17 17 7

Multivibrators 11, 7 13 12 11 10 11 6

96

• This seems to work as an integrator. Now reduce the frequency of the applied

input further, See if it is still working as an integrator.

• Wow! You have just realized an active electronic switch.

Some but not all the triggers supplied by the students were:

• Does it really roll off on the two sides. Why should the gain reduce when

everything else remains the same in the circuit?!

• If the coupling capacitor can have effect on the frequency response, so will the

bypass capacitor.

• Let us supply very high frequency to this circuit. But we don’t have more than

10 MHz generator available in the lab!!

chapter 4 development and implementation of pbl...

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