1

Chapter: 2 Interfacing Memory systems

Outline

Types of Memory devices

Classification,

technologies

Organization and operation modes of

EPROM 2764 and

SRAM 6264

Memory mapping and interfacing with

microcomputers (8085/8086)

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Introduction

A memory unit is an integral part of any

microprocessor system and its primary

purpose is to store programs and data.

In a broad sense, a microcomputer memory

system can be logically divided into three

groups. They are

Processor Memory

Primary or Main Memory

Secondary Memory

3

Contd.

4

Contd.

The processor memory refers to a set of CPU

registers.

These registers are used to hold temporary

results when a computation is in progress.

Since the registers of the processor are

fabricated using the same technology as that

microprocessor, there is no speed disparity

between these registers and processor.

However, the cost involved in this approach

forces a manufacturer to include only a few

registers in the microprocessor.

5

Contd.

The primary or main memory refers to the

storage area which can be directly accessed by

the microprocessor.

Therefore, all programs and data must be

stored only in primary memory prior to

execution.

In primary memories the access time should

be compatible to read/write time of the

processor.

Primary memory normally includes ROM,

EPROM, static RAM and DRAM.

6

Contd.

Secondary memory refers to the storage

medium comprising slow devices such as

magnetic tapes and disks.

They are called as auxiliary or backup storage.

These devices are used to hold large data files

and huge programs such operating systems,

compilers, data bases, permanent programs, etc.

The microcomputer system copies the required

programs and data from secondary memory to

main, memory and work directly with main

memory only.

• A read memory operation consists the following sub-operations:

1. Select the chip using chip enable/select controls. 2. Place the address of the word to be read on the address input lines of the chip. 3. Activate read signal. 4. The data is placed on the data output line of the chip.

These sequence of actions take place in accordance with certain memory-dependent timing constraints.

• Write memory operation steps are similar, but insteps 3 and 4 respectively are as: - the data must be placed on the data input lines of the chip by the MP, or by any other

device that desires to perform the write operation, and then - the write signal must be activated.

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Memory Chip

Address

Data

Read

Write

Chip Enable/Select

Output Enable

Power Supply

Fig. Typical signals in a memory chip

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Contd.

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SEMICONDUCTOR MEMORY

Semiconductor memory is an electronic data

storage device, often used as computer memory,

implemented on a semiconductor-

based integrated circuit. It is made in many

different types and technologies.

The main or primary memory elements are

semiconductor devices, because the

semiconductor devices alone can work at high

speeds and consume less power.

Moreover they can be fabricated as ICs and so

they occupy less space.

10

Contd.

A typical semiconductor memory IC will have

n address pins (lines) and m data pins (lines).

The capacity of the memory will be 2n x m

bits.

The functional blocks of semiconductor

memory are Row address decoder, Column

address decoder, Memory array, Input buffer

and Output buffer, the figure below shows a

simplified block diagram of semiconductor

memory.

11

Contd.

12

Contd.

A typical semiconductor memory IC will have

The input and output buffers are used to hold

the data until valid time and also for current

level matching.

The "n" address lines are spited into q lines

& r lines and applied to row & column decoder

respectively (2n = 2(q+r) = 2q x 2r).

When an address is send to memory IC, the

row and column decoder will select one line

each, which in turn select one memory cell in

each layer.

13

Contd.

14

Contd.

15

Memory Types

These semiconductor memories can be

classified into volatile and non-volatile memory.

If the information stored in a semiconductor

memory is lost when the power supply to that IC

is switched OFF, then the memory is called

volatile.

The ROM, PROM, EPROM and NOVRAM

are nonvolatile memories.

The static RAM and DRAM are volatile

memories.

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Contd. Memory Types

The Semiconductor memories can also be classified

into Read Only Memory and Read / Write Memory.

In read only memories the information is stored

permanently either during manufacturing or after

manufacturing and then interfaced to microcomputer

system.

The processor can only read the stored information

from these memories and cannot write into it.

But in Read/Write memory, the processor can store

(write) the information as well as read from it.

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Contd. Memory Types

The other features of semiconductor memories are

Random access and Non-destructive readout.

In random access memory, the memory access time

is independent of the memory location being accessed

(i.e., the access time will be same for first or last

location).

In semiconductor memories a read operation by the

processor will not destroy the stored information and

for this reason the semiconductor memory is also

called NDRO memory (Non Destructive Read-out

memory).

Nonvolatile memory ◦ ROM ◦ PROM ◦ EPROM ◦ EEPROM ◦ Flash memory

Volatile memory ◦ SRAM ◦DRAM

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The ROM is a semiconductor memory which permits

only a read access, The ROM functions as a memory

array whose contents, once programmed, are

permanently fixed and cannot be altered by the

microprocessor using this memory.

Other names for this type of memory are dead memory,

fixed memory, permanent memory and read- only store

(ROS), In ROM memory the memory cell (storage unit)

will have a MOS transistor either with open gate or closed

gate.

The transistors with closed gate represent 1’s and with

open gate represent 0's. Since the configuration is fixed

they permanently store 1’s and 0's.

ROM AND PROM

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The ROM is nonvolatile memory, i. e, loss of

power or system malfunction does not change

the contents of the memory.

Also, the ROM memories have the feature of

random access, which means that the access

time for a given memory location is the same as

that for all other locations, The process of

storing information in ROM is called

programming,

Contd. ROM AND PROM

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The technique employed for storing

information in the ROM provides a convenient

method for classifying ROMs into one of the

following three categories.

Custom programmed or Mask programmed

ROM.

Programmable or Field programmable

ROM.

Reprogrammable or Erasable -

Programmable ROM.

Contd. ROM AND PROM

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The custom programmed ROMs are

programmed by the manufacturer as specified by

the user during fabrication and the contents

cannot be changed after packaging.

The programmable ROM's are one time

programmable by the user.

The reprogrammable ROMs have facilities for

programming as well as for erasing its content

and reprogramming the memory.

The reprogrammable ROMs are erased either by

passing Electrical current or Ultra-violet light.

Contd. ROM AND PROM

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The most common family of EPROMs is the

27XXX series, or the CMOS 27CXXX where XXX

indicates the memory capacity in Kbits.

The 2764 is an 8KB EPROM memory

containing an array of 65536 bit cells i.e 8*

l024*8bits.

The access time is of order of 200-250 ns which

makes it possible to use the device with high speed

microprocessors .

It is a modification of n-MOS enhancement

mode transistor.

EPROM 2764

Reprogrammable

Erased by UV light

Example EPROM chips

• 27C64 : 8KB

• 27C128 : 16KB

• 27C256 : 32KB

• 27C512 : 64KB

240-208 Fundamental of Computer

Architecture

EPROM 2764, 27128, 27256

From Figure 11-15, Page 301 of “Microprocessor : Principle and Application”, Charles M. Gilmore, McGraw Hill pub.

26

Contd.

27

It has 13 address lines to access 8Kb of the

locations with in the device i.e (A0-A12).

DO-D7 are the data output lines and are

connected to the system data bus.

Vpp is used for programming the 2764 providing

a high voltage ranges from 12.5 to 21volts. This

voltage will be retaining, as charge in the

EPROM.

This is nothing but Write operation of a memory.

It functions as a write signal. i.e write into selected

locations, which are accessed by the address lines.

Technical specifications

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Chip-enable( CE) when it is low the chip will be

selected and it is ready to accept read and write

operations.

Output enable ('OE) is used in conjunction with

chip-enable to avoid with bus contention

Contd. Technical specifications

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It has 5 modes of operation.

The modes are selected on the basis of the

signals present on the pins.

The first three modes are (Read, Output, and

Standby) depending on the status of the chip-

enable, Output-Enable, Program.

Operational Modes of 2764

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In this mode, the Vpp pin is held at Vcc level (+5

V), and PGM is held at high.

The chip-enable pin is made low in order to

select the device and

output enable is made low in order to gate the

data from the output pins(Do-D7),

READ is set and data is available at the output

pins(Do-D7),

The contents of the memory locations specified

by AO-A12 can then be read out on to the system

data bus.

Read mode

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When Chip enable pin is high, the device is

deselected and enters the standby mode in

which the current consumption is reduced from

an active value of approximately 100mA to

40mA.

In this mode, the outputs are in a high

impedance state.

In this mode the current consumption is

minimum when other devices are accessed.

Standby mode

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The data outputs of two or more 2764s may be

wire-ORed together to the same data bus.

In order to prevent bus contention problems

between devices, all but the selected 2764s should

be deselected by rising the CE to a high.

OE input should be made common to all devices

These connections offer the lowest average

power consumption.

Output disable:

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In this mode, data can be written into a

desired location.

The Vpp pin is pulled up to the programming

level voltage (22 V for 2764), with chip- enable

and program-enabled and the desired data is

placed on the D0-D7 pins of the device.

To program a location, the chip enable input

must be low while the Vpp pin is made high and

PGM pin at high level..

Program mode

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After a location is programmed, a verify

operation ought to be performed to ensure that

the location has been programmed correctly.

The Vpp pin is made high, Chip-enable and

output enable made low while PGM is high.

The data on the D0-D7 pins can then be

compared with the data that was placed on the

pins during the programming.

Verify Mode

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After a location is programmed, a verify

operation ought to be performed to ensure that

the location has been programmed correctly.

The Vpp pin is made high, Chip-enable and

output enable made low while PGM is high.

The data on the D0-D7 pins can then be

compared with the data that was placed on the

pins during the programming.

Verify Mode

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The static RAM (Random Access Memory) is

Read/Write memories which consist of an array

of flip-flops or similar storage devices. (Even

though ROMs are technically random access

memory, the Read/Write memories are called

RAM.

Besides random access feature, the static

RAMs are volatile in nature. In static RAM the

memory cell (storage location for 1 each bit of

information) consists of a flip-flop or similar

device.

STATIC RAM- 6264

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The information is stored in the memory cell

as long as power is supplied to the circuit.

Each memory cell typically consists of six to

eight MOS transistors.

The static RAMs are manufactured by many

semiconductor industry like Motorola, Hitachi,

Toshiba, Cypress, etc. The manufacturers have

a common industry standard, so that a product

from different industry will be pin to pin

compatible and slightly differ in Electrical and

switching characteristics.

STATIC RAM- 6264

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The 6264 is a high performance CMOS static

RAM organized as 8192 bytes (8Kb).

The device has a power down mode.

When CY6264 is not enabled (deselected), it

will enter the power down mode and in this

mode the power consumed is reduced to 30% of

active mode power.

6264 (CMOS 6264)

39

Contd.

40

The chip has 13 address inputs denoted as

A0-A12.

The address is used to access anyone of the 8

Kilo (8192) locations within the chip.

It has eight I/O pins for reading/writing the

data and they are denoted as I/O0 to I/O7.

Contd.

41

Contd.

42

The 6264 is an 8 KB Static RAM memory containing

an array of 65536 bits(8*1024*8bits)

Its fast access time is 25 nsec.

Hence it is recommended with fast microprocessors

It is a 28 pin IC

Thirteen address lines (Ao-A12) are required to

access the 8 Kb memory locations with In the Device

I/O0-I/O7 are connected to the system data bus can

be written into or read from a selected location through

these pins.

The write pin Is used for writing data into a selected

location

Description

.

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

Vcc

CS2

A8

A11

A10

I/O7

I/O6

I/O5 I/O4

I/O3

A9

OE

CS1

WE

NC

A7

A12

A6

A5

A4

A2

A3

A1

A0

I/O1 I/O2

GND

I/O0

6264 SRAM

Fig. Signals & pinouts of 6264 SRAM. WE -- write enable CS -- chip select OE -- output enable

- It has 13 address lines, A0-A12 and 8 data input/output. chip capacity = 213 = 8192x8 =8kx8-bits =8kb

-The CS1 and CS2 act as two chip enable or chip select signals for

the 6264.

-The 6264 is in Standby mode (power consumption is reduced to

30% of active mode power) when it is not selected, i.e. when CS1

and CS2 are 01.

- An active WE input indicates a write operation.

- An active OE is needed during read operation. It enables the

data output lines of the chip to place data on the system data bus.

- When OE is inactive, the data output lines are in Hi-Z.

Mode

Inputs I/O Pin

Note WE CS1 CS2 OE

READ WRITE WRITE OUTPUT Disable

Not selected (Power Down)

H L H L L L H H L L H L H L H H X H X X X X L X

Data OUT Data IN Data IN Hi-Z Hi-Z Hi-Z

Read cycle Write Cycle 1 Write Cycle 2 X is don’t care

Table. Truth table for operating mode of HM6264A series

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There are two ways of interfacing I/O devices

in 8085 based system.

1) Memory mapped I/O device.

2) Standard I/O mapped I/O device or Isolated

I/O mapping.

I/O Device Mapping and Interfacing

Memories To Microprocessors

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In memory mapping of I/O devices the ports are

allotted a , 16-bit address like that of memory

location.

Some of the chip-selected signals generated to

select memory IC's are used for selecting the I/O

port devices.

Memory mapped IO is one where the processor

and the IO device share the same memory

location(memory)

Hence the processor treats the I/O ports as

memory locations for reading and writing

Memory mapped I/O device

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The P uses memory control signals RD and

WR (MEMR and MEMW) instead of IOR and

IOW.

Memory related instructions such as LDA, STA,

MOV M, LDAX, etc are used for data transfer

between I/O and any register.

e.g.

1.STA 8000H ;send the contents in ACC to

output port whose address is 8000h

2. LDA 5000H ; read from input port whose

address is 5000H to ACC.

Contd.

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In standard I/O mapping a separate 8-bit

address is provided for I/O ports and the

peripheral IC's.

In this type of I/O, the P uses 8 address lines to

identify an input or output device.

IO mapped IO is one where the processor and

the IO device have different memory located to

each other

The P can identify 28 =256 input and 256 output devices with address ranging from 00H to

FFH.

I/O mapped (or isolated) I/O

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The P differentiates the input and output

devices by the control signals IOR and IOW respectively.

the instructions IN and OUT are used for

data transfer between I/O devices and ACC. IN portAdr8 ; input (read) data from an

input device to ACC.

OUT portAdr8 ; send (display) the

contents of ACC to an output device.

Contd. I/O mapped (or isolated) I/O

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Basic Memory Interfacing with 8085 /8086

50

Contd.

51

Contd.

52

Contd.

53

Contd.

54

Contd.

55

Contd.

56

Contd.

57

Contd.

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Draw the circuit diagram of an 8085 system, having a 4 KB EPROM and two 8 KB RAM ICs. The starting address of the EPROM is 0000H and that of RAM-I 4000H and RAM-II 8000H. The address of the decoder circuits should be clearly shown.

Exercise