chapter 10 error detection & correctio

8/3/2019 Chapter 10 Error Detection & Correctio

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Chapter 10

Error Detectionand Correction


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Types of Errors

Detection

Correction


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Single-bit error


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Burst error

Figure 9-4


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RedundancyFigure 9-5


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VRC (Vertical Redundancy Check)

A parity bit is added to every data unit so that the total number of

1s(including the parity bit) becomes even

for even-parity check or odd for odd-parity checkVRC can detect all single-bit errors. It can detect

multiple-bit or burst errors only the total number of errors is odd.


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LRC(Longitudinal Redundancy Check)

Parity bits of all the positions are assembled into a new

data unit, which is added to the end of the data block


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VRC and LRC


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CRC


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Binary Division


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Detection(contd)Binary Division

in aCRC Checker


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Polynomial

Figure 9-12

WCB/McGraw-Hill The McGraw-Hill Companies, Inc., 1998

CRC generator(divisor) is most often

represented not as a string of 1s and 0s, but

as an algebraic polynomial.


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Figure 9-13


Polynomial and Divisor


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Standard Polynomials

Figure 9-14



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ChecksumFigure 9-15



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Figure 9-16


Data Unit and ChecksumTo create the checksum the sender does the following:

The unit is divided into K sections, each of n bits.

Section 1 and 2 are added together using ones

complement.

Section 3 is added to the result of the previous step.

Section 4 is added to the result of the previous step.

The process repeats until section k is added to the resultof the previous step.

The final result is complemented to make the checksum


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Detection(continued)


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Error CorrectionFigure 9-17


~ can be handled in two ways

when an error is discovered, the receiver can have

the sender retransmit the entire data unit.

a receiver can use an error-correcting code, which

automatically corrects certain errors.


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Error Correction

If the total number of bits in a transmittable

unit is m+r, then r must be able to indicate at

least m+r+1 different states

2r m + r + 1

ex) For value of m is 7(ASCII) , the smallest r

value that can satisfy this equation is 4

24 7 + 4 + 1


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Hamming CodeFigure 9-18


each r bit is the VRC bit for one combination of

data bits

r1 = bits 1, 3, 5, 7, 9, 11r2 = bits 2, 3, 6, 7, 10, 11

r4 = bits 4, 5, 6, 7

r8 = bits 8, 9, 10, 11

i


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Figure 9-19


Hamming Code

Fi 9 19 i d


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Figure 9-19-continued


Hamming Code

Fi 9 20 l f d


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Figure 9-20


Example of Hamming Code

Fi 9 22


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Figure 9-22


Error

Detection

chapter 10 error detection & correctio

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