Semiconductor Quality and Reliability Handbook

Chapter 1 Approach to Quality Assurance

1-1

Chapter 1 Approach to Quality Assurance

1.1 Approach toward Quality Assurance ........................................................................................................... 1-2

1.1.1 Basic Policy ...................................................................................................................................... 1-2

1.1.2 Operation of a Quality Management System Based on the ISO 9000 Series ............................ 1-2

1.1.3 Scientific Approach .......................................................................................................................... 1-3

1.2 Quality Assurance System for Semiconductor Products ........................................................................... 1-6

1.2.1 Quality Assurance in the Development Design Stage .................................................................. 1-7

1.2.2 Quality Assurance in the Mass Production Stage ......................................................................... 1-9

1.2.3 Handling Customer Complaints .................................................................................................... 1-12

1.3 Environmental Approaches ........................................................................................................................ 1-14

1.3.1 Environment in Factories ............................................................................................................... 1-15

1.3.2 Environment in Products ............................................................................................................... 1-15

1.4 Product Liability (PL) Act ............................................................................................................................. 1-16

1.4.1 Purpose of Activities....................................................................................................................... 1-16

1.4.2 Management Structure for Promoting Safety and Peace of Mind .............................................. 1-16

1-2

1.1 Approach toward Quality Assurance

1.1.1 Basic Policy

The Sony Group is not content simply to improve product and service quality, and is instead deploying Company-

wide activities to realize the world’s top management quality in order to provide the highest level of satisfaction in

all aspects to our customers. As a member of the Sony Group, the Semiconductor Business Unit is charged with the

development, design, manufacture and sale of semiconductor products.

Within the Semiconductor Business Unit as well, all divisions, related departments and factories aim to realize

“No. 1 Quality (No. 1 customer satisfaction in the industry with minimum quality losses),” based on the quality

values of “Quality First / giving priority to quality over individual profits.” To achieve this, the Semiconductor

Business Unit deploys various quality improvement activities, with attention also given to improving management

quality.

1.1.2 Operation of a Quality Management System Based on the ISO 9000

Series

The Semiconductor Business Unit has established and operates a quality management system that conforms to the

ISO 9001 Standard, and all divisions, related departments and factories have acquired ISO 9001 certification from

the certification body.

The Semiconductor Business Unit’s quality policy has been established as follows, based on achievement of the

Unit’s quality values and vision.

Quality policy: “To build a great relationship of trust with customers, improve the Quality

Management System based on the ISO 9001 continually with the concept of making

quality the first priority, in effort to achieve No. 1 Quality (No. 1 customer

satisfaction and minimizing the quality loss).”

The Semiconductor Business Unit constantly strives to improve the quality of its semiconductor products based

on this quality policy, through activities such as maintaining and controlling the quality management system,

continuously working to improve the effectiveness of processes, and improving quality through quality engineering

and other scientific approaches.

(1) Document system

The Semiconductor Business Unit’s quality management system is classified and documented with quality

manuals at the top supported by overall Business Unit standards, individual division standards, procedures,

related documents and records.

1-3

Qualitymanual

Overall Business Unit standards

Business Division standards

Records

Related documents

Procedures

(2) Quality target management

Every fiscal year the Semiconductor Business Unit sets customer satisfaction and quality loss goals,

establishes various improvement indices and targets for achieving those goals, and compiles various

improvement measures for achieving the targets into a quality business plan, with the aim of realizing “No. 1

Quality (No. 1 customer satisfaction in the industry with minimum quality losses).” The implementation and

progress of this quality business plan are reported at quality meetings held periodically by top management, and

the top management themselves review the level of target achievement.

(3) Improvement of process effectiveness

It is expected that the established quality management system is implemented as planned, and that records are

maintained as evidence of implementation according to plan. As such, the Semiconductor Business Unit’s

quality management system carries out periodic quality assessments to check maturity levels for planning and

execution quality and for results quality process by process; and then, extracts themes with the aim of achieving

even higher maturity levels, as a part of measures to improve work process performance. These themes are

reflected to the quality business plan, and improvement activities are carried out to increase maturity levels.

1.1.3 Scientific Approach

(1) Sony Six Sigma

Sony Six Sigma takes the Six Sigma developed in the U.S. and modifies it to realize a Sony-style Six Sigma

that aims to improve not only product quality but also the quality of all work, based on the following three

concepts.

・Focusing not only on results but also on processes

・Looking not only at averages but also at variance

・Making judgments based on facts and data

1-4

The basic Sony Six Sigma approach is represented by the acronym DMAIC, which stands for Define -

Measure - Analyze - Improve (Execute) - Control (Standardize). In this process, “Define” correctly [sets]

themes, and “MAIC” [solves] those themes. DMAIC comprises 14 steps as follows.

The Semiconductor Business Unit deploys this Sony Six Sigma technique to carry out activities aimed at

realizing the “ 6σ level management quality.”

・Define

Step1 Define important themes for realizing CTQ (Critical to Quality, commitment) from the

standpoints of VOC (Voice of Customer, what customers really want) and corporate profit.

Step2 Break down CTQ.

・Measure

Step3 Define an index (Y) that numerically expresses CTQ.

Step4 Verify the reliability of the index (Y) measurement system.

Step5 Verify the current status of the index (Y) and determine improvement targets.

・Analyze

Step6 List and analyze factors causing index (Y) fluctuation.

Step7 Extract the Vital Few (X, factors that truly influence output) that have a decisive effect on

the index (Y).

Step8 Verify the reliability of the Vital Few (X) measurement system.

・Improve

Step9 Obtain the relationship between the Vital Few (X) and the index (Y).

Step10 Set the optimum conditions including the Vital Few (X) tolerance.

Step11 Experimentally confirm the optimum conditions in an actual process.

・Control

Step12 Construct a Vital Few management system and ensure that improvement effects take root.

Step13 Organize and accumulate the knowledge obtained by the project.

Step14 Share and horizontally deploy the improvement process.

(2) Deployment of quality engineering

Quality engineering is a specific technical methodology for simultaneously realizing high quality and high

productivity, and centers on methods for evaluating and improving functionality.

Evaluation of functionality does not refer to individually evaluating large numbers of quality characteristics,

but instead evaluating the proper function of products and systems. The degree to which operation is unaffected

or not subject to variance (functionality) due to differences in customer operating and environmental conditions

is expressed by the single measure known as the S/N ratio. Many quality characteristics items are negative items

1-5

(badness) or similar to differences in operating conditions, and occur due to changes or variance from proper

operation. The inability to adequately demonstrate functions is a substantial problem. Conversely, good

functionality naturally also results in the improvement of multiple quality characteristics.

Next, one tool used to improve functionality is an orthogonal array. When attempting to improve a design,

experiments are performed using different design factors (control factors). Generally, in most cases there is no

preexisting knowledge about which factors can effectively improve functionality, so many design factors must

be investigated. Experiments using an orthogonal array are a method of investigating many factors at once

instead of one at a time.

Evaluation and improvement of functionality enables the following.

・ The pros and cons of technology to be used in the product can be understood and technical limits can be

evaluated in a short time before starting product planning. This vastly increases the development efficiency

and helps to greatly shorten the development period.

・ Fundamental technical ability is increased, enabling to tackle similar products that use the same

technology and future new product development without problem.

・ Technology can be made intrinsically resistant to changes or deterioration in operating and environmental

conditions. This means that results confirmed in the development stage can be reproduced at the

production site or in the market, which greatly reduces the costs for dealing with complaints.

The Semiconductor Business Unit works to spread quality engineering throughout the Unit by conducting

quality engineering training and applying quality engineering to specific examples.

(3) SPC

The manufacturing process is controlled using check sheets, graphs, control diagrams and other control tools.

In particular, control diagrams are an effective means for continuously monitoring changes in quality for each

process, and make it possible to take proper action when trouble occurs.

Control diagrams set control limits indicating the range of normally occurring data based on the variance of

process data over a certain range, and enter measurement data onto charts.

When an abnormal factor enters the process variance, the data exceeds the control limit lines, so control charts

are effective for quickly detecting process changes. In addition to detecting when the data exceeds the control

limit lines, process changes such as rising and falling data trends can also be detected. In this way, the use of

control diagrams and other statistical techniques helps to periodically understand and analyze variance that

affects quality, and is useful in improving quality.

In addition, important control items are also determined based on characteristic items demanded by customers,

items affecting device quality and reliability, and items that correlate with defect mechanisms, etc. Capability

measures (Cp, Cpk) are calculated for each process based on these items, and process improvements are then

1-6

carried out for items with low process capability measure levels to achieve higher-level values and realize stable

quality.

Process capability measures:

The process stability with respect to the standards for that process can be obtained from the process

data over a certain period and the standard values.

These are called process capability measures (Cp, Cpk), and are obtained by the following formulas.

(Upper specification limit Lower specification limit)

6σ Cp =

Process capability measures in consideration of data (average value) bias toward the standard center:

|Specification limit closest to average value Average value|

3σ Cpk =

The Semiconductor Business Unit works to improve process variance by periodically understanding these

process capability measures.

(4) Failure Mode and Effects Analysis (FMEA)

Failure Mode and Effects Analysis (FMEA) consists of confirming and evaluating the risks posed by the failure

modes that are latent in devices or processes. Confirming these risks makes it possible to systematically discover

what is necessary to eliminate or reduce decisive trouble and achieve an optimum design.

1.2 Quality Assurance System for Semiconductor Products

To ensure quality and reliability and to supply products that meet customer needs in a timely manner, all Sony

Semiconductor Business Unit departments carry out activities based on a consistent quality assurance system, from

the product planning conception stage through development, design, manufacture of prototypes, evaluation, mass

production, shipping, and after-sale service.

Fig. 1-1 shows the Sony Semiconductor Business Unit’s quality assurance system diagram.

1-7

Approval test

Material incoming inspection

Needs(VOC)

Product receiptDealing with complaints

Decision of shipment stop/collection

Development

Production

Sales and service

Customer Business DivisionTechnology Department

Manufacturing Department

Quality Assurance Department

Decision of shipment

IPQC/Selection, inspection

Manufacturing (CP)

Shipment

Knowledge data

Test plan proposal

Evaluation and verificationEvaluation

Design completion review

Shipping inspection

Product concept review

Planning concept (Issue analysis, FMEA implementation)

Design review

Design

Product planning

Product planning review

Decision of production start

Production preparation

NG

NG

NG

NG

NG

NG

OK

OK

OK

OK

OK

OK

Fig. 1-1 Quality Assurance System Diagram

1.2.1 Quality Assurance in the Development Design Stage

The Semiconductor Business Unit establishes rules for the development and design process and performs work

according to those rules in order to provide customers with homogeneous and attractive products that meet the items

demanded by customers and the marketplace.

(1) Product planning

Market research activities are performed to ascertain the intended applications, operating conditions, and the

product quality and reliability levels demanded by each customer, and also to understand technical trends,

required performance, delivery periods, prices, quality, reliability and other demands on products in the general

marketplace. This information is used to formulate product development plans that are used for product

planning.

(2) Planning conception

The product planning results and various data obtained within the Semiconductor Business Unit from

accumulated quality and reliability results and fundamental research on reliability technology are used to set

quality and reliability targets that are appropriate for product applications and operating environments, and to

formulate development plans. In addition, this quality and reliability information is compiled into quality

concepts, which are a part of the design specifications, and used as input for design.

1-8

(3) Design

Design is an extremely important process for ensuring high reliability in semiconductor devices. Design is

performed as follows based on the design requirements (quality concept, design specifications, related laws and

regulations, cases of past trouble), with sufficient design leeway to tolerate variance in the manufacturing

process.

・Understanding the latest requirements

The latest requirements are understood, and any necessary changes from the plan formulation stage are

clarified, visualized (compiled into documents) as the latest requirements, and shared with related

parties. In addition, past review analysis results are also understood as requirements.

・Plan formulation

The requirements are broken down into specific plans. When there are changes to the requirements or

other specifications, the need for plan revision is verified. When revision is necessary, the plans are

updated as appropriate, and the latest version of the plans is visualized (compiled into documents) and

shared with related parties. In addition, risk countermeasures are also included in the plans.

・Execution

Work is executed in accordance with each plan until the targets are achieved.

・Progress control

Plan progress is controlled, achievement conditions are reviewed to ensure that the expected results are

obtained, and any problems are dealt with as appropriate.

(4) Evaluation and verification

The design results are checked to make sure they satisfy the product requirements (verification) and that the

intended applications and purposes are achieved (validity check). This validity check includes reliability

certification tests performed by the Quality Assurance Department of the Semiconductor Business Unit, and

reliability is checked from the standpoint of the customer. Shipment of products to customers cannot start until

these verification and validity checks are complete.

(5) Design review

The design results and observance of the design specifications used as the design inputs are checked as the

design review. Design review is carried out partway through the design work, if necessary, and these results fed

back to the design to improve design quality.

In design review, during circuit design, layout design, wafer process design and assembly process design,

whether the design standards that are the rules to be followed are being observed is checked and design contents

are thoroughly investigated by technical experts. In addition, experts from related departments review design

contents from the viewpoint of cases of past trouble or each technology. These design reviews aim to avoid

1-9

trouble after prototype manufacture and mass production, and build the target performance, quality and

reliability into products in line with demands.

1.2.2 Quality Assurance in the Mass Production Stage

(1) Process quality control in manufacturing

In order to supply the high quality and high reliability products demanded by customers, related departments

perform capacity verification with respect to production, shipping and material purchasing plans that have been

created based on the latest sales plan, and then operations shift to the production stage.

Based on the concept of building in quality in the manufacturing process, the manufacturing conditions that

have been determined according to the various drawings presented from the Development Design Department

are prescribed in control plans (descriptions or systemization of the process flow, equipment used, equipment

handling procedures, work conditions, work methods, parts and materials used, parts and materials handling

methods, various QC items and control criteria, inspection criteria, and definitions and methods of dealing with

trouble). These control plans are then compiled into documents and used as guides for performing each

manufacturing work. In addition, SPC method and other tools are used to understand changes for important

control items that have a significant effect on quality, and efforts are made to stabilize quality and to discover

and prevent trouble.

Also, all necessary information concerning quality, from materials and parts purchasing to quality control in

manufacturing process, inspections, warehousing and quality information for customers, is controlled and

analyzed by a data collection system and used to make quality improvements. In addition, this information is

also used to quickly determine the affected range in the event that trouble occurs.

When trouble occurs in the manufacturing process, a trouble report is issued, the Technology Department in

charge investigates the matter, and necessary corrective action is taken to prevent recurrence of the trouble.

In this manner, whether manufactured products satisfy product specifications and customer demands is

checked during a final inspection process, and only passing products are shipped to customers.

(2) Process quality control for outsourced items

Even when outsourcing part of the manufacturing process, quality assurance activities are promoted for

outsourced production lines based on the same approach as our in-house line. These activities include product

quality, process control, quality improvement activities and measures when trouble occurs, and efforts are made

to maintain and improve product quality and to prevent the occurrence of trouble.

・Certification of product reliability

Outsourced production items undergo the same reliability evaluations as in-house production items as

“Certification of product reliability” to make sure there are no problems.

1-10

・Line certification audits

Manufacturing line audits are conducted by specialists, including Quality Assurance Department

members as main members, when starting outsourced production to make sure there are no problems.

・Measures when trouble occurs

When trouble occurs in outsourced production processes, product and corrective actions are carried out

according to the decisions of related in-house departments based on information provided from the

outsourcing supplier.

・Periodic quality meetings

Periodic quality meetings are held with outsourcing suppliers, and problems such as trends for process

control items and inspection passing rates are extracted. Quality improvement activities are promoted

through correction and prevention of problems.

(3) Quality assurance for purchased products (materials and parts)

As semiconductor devices move toward higher reliability and higher density, design demands on purchased

products are also becoming higher-level. It hardly needs mentioning that purchased products’ quality is

important for assuring the quality of semiconductor devices. The Semiconductor Business Unit compiles the

purchased parts system into documents, covering from evaluation, selection and registration of suppliers, to line

certification, exchange of specifications, incoming inspections, materials and parts inventory and control, and so

on, and promotes quality assurance activities based on these documents.

・Evaluation, selection and registration

“Management conditions,” “CSR (Corporate Social Responsibility including observance of laws and

regulations),” “environmental considerations (application of the Sony Green Partner System),”

“technical capability,” “cost,” “quality” and “supply capability” are evaluated mainly by the Purchasing

Department, with the cooperation of the Technology and Quality Assurance Departments, based on the

functions and performance required of the purchased parts. These results are then used to select new

suppliers, and suppliers meeting the criteria are registered.

・Line certification

“Quality management systems,” “process quality control” and "technology support capability" are

reviewed mainly by the Purchasing, Quality Assurance and Technology Departments, and the lines of

suppliers that have come up to the prescribed standards are certified.

・Exchange of specifications

After completing evaluation (function characteristics, quality and reliability) of the purchased parts, the

Technology Department creates specifications. The Purchasing Department exchanges these

specifications with the suppliers, and then assigns individual numbers to each purchased part, and

1-11

registers and controls this data.

・Incoming inspections

These inspections are performed by the Material Quality Assurance Department based on the data sheets.

・Inventory and control

This is performed by the Purchasing Department based on the data sheets.

・Monitoring and control of suppliers

The Purchasing Department obtains information on QDCS results from related departments for

suppliers with whom there are ongoing transactions, and periodically evaluates these suppliers.

Appropriate guidance is provided to suppliers based on these evaluation results to accelerate the quality

improvement activities of suppliers.

• Change control

Applications for changes are received by the Purchasing Department and verified in advance by the

Technology and Quality Assurance Departments and other related departments. Changes are made only

when the verification results indicate that there are no problems, and steps are taken to ensure

traceability related to the changes.

(4) Measuring instrument control and environment control

During the course of semiconductor development design and production, product performance and quality are

assured and improved by having measuring instruments constantly operating in the normal condition and within

the required accuracy. Measuring instrument accuracy is controlled by establishing a preventative maintenance

system. Incoming inspections are carried out when instruments are purchased and periodic checks are carried

out during use to check accuracy and instruments are periodically calibrated, enabling prevention of

malfunctions and drops in accuracy.

The environment has a significant effect on semiconductor device quality reliability. Therefore, control items,

control methods and control standards for temperature, humidity, dust and other items are set according to the

manufacturing process and micro-machining level, and the environment is maintained and controlled by

installing centralized monitoring systems, etc. In addition, quality is also maintained and controlled by

monitoring the specific resistance, purity and other characteristics of the deionized water, gases and chemicals

used in manufacturing in-house lines.

(5) Change control

Changes are made to products or manufacturing processes in order to improve semiconductor product

functions, quality reliability and also to improve productivity. The feasibility of these changes is judged after

confirming that these changes will not produce any negative effects. In addition, when a change is planned, all

related departments review the change. The necessary and ideal evaluation of items thought to have a technical

1-12

effect is planned, and these effects are confirmed by manufacturing prototypes, etc. If these changes have a

significant effect on the product, these results are conveyed in advance to customers to confirm that there is no

effect at the customer.

After all check items are completed, change instructions are issued and initial control of floating data is

performed as necessary.

(6) Product traceability

Traceability of products shipped to customers uses the mark lot number printed on the final product as the key,

and this mark lot number is tied with the parts and materials lots used and the manufacturing history. In addition,

the product name and mark lot number of the enclosed products are noted on the label affixed to the outside of

the packing carton, so the manufacturing history can be traced even in the packed state.

1.2.3 Handling Customer Complaints

When a customer experiences trouble, these complaints pass through Sony’s sales company and are received by

the Quality Assurance Department. Investigation and analysis of complaint items and feedback of these results are

both a duty and a service to customers, and at the same time provide valuable information for improving product

quality.

Results of investigations of complaint items and the contents of countermeasures are reported to customers in

document form and efforts are made to obtain understanding. According to the situations, customers may be visited

to report these results directly.

(1) Complaints information

The more accurate information that can be provided, the easier the investigation and analysis can proceed in

order to provide a swift and accurate response when trouble occurs. Therefore, when investigation of complaint

items is requested, customers are requested to present detailed information on the trouble contents, the process

in which the trouble occurred, the electrical, mechanical and thermal stress application history, lot dependency,

occurrence rate, surrounding circuit conditions, applications, etc. Particularly with lead bending and packing

defect (incorrect items or mixing of different types), detailed information at the time of occurrence is required.

(2) Return of complaint samples

Complaint items are required to be returned as much as possible in the condition in which the trouble occurred.

When returning samples, appropriate measures should be taken to avoid external stress (electrical, thermal and

mechanical) so that the effects of stress during handling and transport do not change the trouble conditions.

(3) Return of analyzed samples (items for which the trouble cannot be reproduced)

Items judged as acceptable and for which the complaint symptoms cannot be reproduced as a result of

analysis by the Sony Semiconductor Business Unit are returned to the customer for reconfirmation. Even after

1-13

that, if the complaint symptoms can be produced, investigation should be requested again together with detailed

information.

(4) Corrective action

After determining the cause from the complaint item investigation and analysis results, countermeasures are

implemented and corrective action is also taken for the quality management systems in the applicable process to

prevent recurrence.

1-14

1.3 Environmental Approaches

In early recognition of the importance of environmental issues, Sony presented an environmental conservation

policy and established an Environmental Conservation Committee in 1990. In 1993, Sony formulated the Sony

Global Environmental Policy and Environmental Action Program, and in 2000, Sony instituted the Sony Group

Environmental Vision consisting of a “Philosophy” and “Principles” as the global environmental policy for the

entire Sony Group, with the aim of contributing to the realization of a sustainable society.

(1) Philosophy

Sony recognizes the importance of preserving the natural environment that sustains all life on the earth for

future generations and thereby ensuring that all humanity can attain a healthy and enriched life. In order to

realize such a sustainable society, Sony strives to achieve a zero environmental footprint throughout the

lifecycle of our products and business activities.

(2) Principles

Sony reduces our environmental footprint and prevents environmental pollution throughout the lifecycle of

our products and business activities by complying with all applicable environmental regulations and also by

continuously improving our global environmental management systems. Sony formulates the following goals in

four key environmental aspects and takes proactive actions to achieve these goals.

・Climate change

Sony reduces energy consumption and strives to achieve zero emissions of greenhouse gases generated

throughout the lifecycle of our products, services and business activities.

・Resource conservation

In order to minimize resource inputs for our business activities, Sony identifies “Key Resources” and

strives to achieve zero usage of these virgin materials. Sony also uses water efficiently, minimizes

wastes from sites, and maximizes our efforts for take back and recycling of products from markets.

・Chemical substances

Sony minimizes the risk of chemical substances that we use causing serious harm to human health and

the environment. Sony maintains strict control over the substances we use, while, in line with our

precautionary approach, taking steps wherever possible to reduce, substitute and eliminate the use of

substances that have potentially significant impacts on the environment, even in the cases where

scientific evidence is not fully proven.

・Biodiversity conservation

Sony protects and utilizes ecosystem services in a sustainable manner, while actively promoting

maintenance and recovery of biodiversity through our business and local contribution activities.

1-15

1.3.1 Environment in Factories

Sony conducts activities to improve the site environment at all Semiconductor Business Unit-related factories

with the aim of achieving mid-term reduction targets for CO2 emissions, waste recycling rates, water usage, and

usage and emissions of volatile organic compounds (VOCs).

1.3.2 Environment in Products

The Semiconductor Business Unit works to reduce CO2 emissions from product use and actively promotes the

reuse of resources. In addition, we also promote reduction of the use of hazardous chemical substances.

1-16

1.4 Product Liability (PL) Act

1.4.1 Purpose of Activities

Sony Group carries out product liability (PL) activities under the name “Safety and Peace of Mind.”. Customer

expectations toward safety and peace of mind are “to provide safe products and work together with customers to

establish an environment in which products can be used with peace of mind,” and Sony Group’s mission is to

realize customer satisfaction. To fulfill this mission, Sony Group has prescribed the following basic guideline and

policy for promoting safety and peace of mind, and the Semiconductor Business Unit has further established its own

basic policy based on these.

Basic guideline

Sony will supply safe products and “make Sony the world reference” in the field of safe use by customers.

Basic policy

Sony recognizes that one of its most important management requirements is to conduct business activities

aimed at realizing a “society where people can live safely and with peace of mind,” and will work to

prevent accidents in all corporate activities. Furthermore, in the unfortunate event that accidents do occur,

the Sony Semiconductor Network Company will handle these incidents in a fair and swift manner.

1.4.2 Management Structure for Promoting Safety and Peace of Mind

The Sony Semiconductor Business Unit promotes safety and peace of mind from the following starting points of

PS, CS and PL.

(1) PS (Product Safety): Supplying safe products

The possibility of semiconductor products being the direct cause of death, injury or damage to property is

extremely rare. However, semiconductor product trouble in set products that use semiconductor products may

trigger accidents in the final market.

The Sony Semiconductor Business Unit feels that improving the quality and reliability of semiconductor

products is the most important part of preventing PL accidents in set products, and works constantly to improve

quality and reliability.

(2) CS (Customer Satisfaction): Realizing safe use

Product data sheets, catalogs, user manuals and other materials contain clearly marked notes on operation in

order to prevent PL accidents resulting from improper use by customers, such as use at voltages exceeding the

absolute maximum rating.

1-17

(3) PL (Product Liability): Fair and swift redress

In the event that quality or reliability of a semiconductor product causes a set product PL accident in the final

market, efforts are made to respond swiftly to clarify the cause and prevent the damage from spreading.

Semiconductor Quality and Reliability Handbook

Chapter 2 Semiconductor Device Reliability Verification

2-1

Chapter 2 Semiconductor Device Reliability Verification

2.1 Fundamental Knowledge on Semiconductor Reliability.............................................................................. 2-2

2.1.1 Measures for Representing Reliability ............................................................................................. 2-2

2.1.2 Distributions Used in Reliability Analysis ......................................................................................... 2-4

2.1.3 Semiconductor Device Failure Pattern ........................................................................................... 2-7

2.1.3.1 Semiconductor Device Failure Regions ........................................................................... 2-7

2.1.3.2 Early Failures ..................................................................................................................... 2-8

2.1.3.3 Random Failures ............................................................................................................. 2-10

2.1.3.4 Wear-out Failures ............................................................................................................ 2-11

2.2 Semiconductor Reliability Verification ........................................................................................................ 2-13

2.2.1 Basic Approach Toward Reliability Verification ............................................................................. 2-13

2.2.1.1 Reliability Verification in the Development Stage ........................................................... 2-13

2.2.1.2 Reliability Verification in the Prototype Stage ................................................................. 2-13

2.2.1.3 Reliability Verification in the Mass Production Stage ..................................................... 2-14

2.2.2 Reliability in the Development and Design Stages ....................................................................... 2-15

2.2.2.1 Time-Dependent Dielectric Breakdown (TDDB) ............................................................ 2-17

2.2.2.2 Hot carrier (HCI) ............................................................................................................... 2-19

2.2.2.3 Negative Bias Temperature Instability (NBTI) ................................................................ 2-20

2.2.2.4 Soft Error .......................................................................................................................... 2-21

2.2.2.5 Electromigration ............................................................................................................... 2-23

2.2.2.6 Stress Migration ............................................................................................................... 2-25

2.3 Acceleration Model ...................................................................................................................................... 2-28

2.3.1 Acceleration Models for Environmental Stress ............................................................................. 2-28

2.3.2 Acceleration Models for Operating Stress .................................................................................... 2-30

2-2

2.1 Fundamental Knowledge on Semiconductor Reliability

With recent advances in the systematization, functions and performance of equipment, the social impact and

damages produced by failures are increasing, and high reliability has come to be demanded of equipment. This

means that even higher reliability is demanded of the individual components that comprise equipment.

Large quantities of semiconductors are used in a single piece of equipment, and these semiconductors often

handle the main functions of that equipment, so high reliability is extremely important. Semiconductors themselves

are also becoming more miniaturized and highly integrated, with larger-scale circuit configurations. In addition, as

semiconductor functions and performance advance and evolve into system LSIs, ensuring semiconductor reliability

has become a vital matter.

The reliability measures, distribution functions, trends in failure rates over time, and failure regions needed to

discuss semiconductor reliability are described below.

2.1.1 Measures for Representing Reliability

JISZ 8115 (Reliability Terminology) defines reliability as “The property of an item which enables it to fulfill its

required functions for the prescribed period under the given conditions.” Therefore, reliability includes the concept

of time, and reliability measures are functions of time.

(1) Reliability Function (Reliability): R(t)

Reliability indicates the probability for functioning correctly without failure until time t.

When n samples are used under the same conditions, if the number of failures occurring until time t has

elapsed is expressed as r(t), then the reliability R(t) is expressed by the following equation.

n

trntR

)()(

・・・・Eq. 2.1.1

(2) Failure Distribution Function (Unreliability): F(t)

This indicates the probability of failure occurring until time t, and is expressed by the following equation.

n

trtF

)()( ・・・・Eq. 2.1.2

In addition, the following relationship is established between unreliability F(t) and reliability R(t).

1)()( tFtR ・・・・Eq. 2.1.3

As shown in Fig. 2-1, R(t) decreases from 1 over time, while conversely F(t) increases from 0 toward 1 over

time. Note that the distribution functions described hereafter are used as the failure distribution functions of

semiconductor devices.

2-3

Fig. 2-1 Relationship between F(t) and R(t)

(3) Failure Density Function: f(t)

This represents the probability of failure occurring per unit time when time t has elapsed.

dt

tdR

dt

tdFtf

)()()( ・・・・Eq. 2.1.4

(4) Failure Rate Function: λ(t)

This represents the probability of failure occurring in the next unit time for samples that have not yet failed

when time t has elapsed.

)(

)(

)(1

)()(

tR

tf

tF

tft

・・・・Eq. 2.1.5

The failure rate function is also called the instantaneous failure rate, and is calculated from the failure

distribution function F(t) using Equations 2.1.4 and 2.1.5. Failure In Time (FIT: number of failures per billion

(109) total operating hours) is generally used as the unit for semiconductor devices.

Note that when the F(t) of the subject product is not known, the average failure rate obtained by the following

equation is used.

Average failure rate ≡ Total number of failures during the period / Total operating time during the period

・・・Eq. 2.1.6

[Supplement]

In addition to the failure rate defined above, the cumulative failure rate after a set equipped with the

semiconductor device has operated for the specified time in the market is sometimes used in the early failure

region described hereafter. Unless otherwise requested by the customer, the Sony Semiconductor Business

Unit also uses the cumulative failure rate after one year as the early failure rate.

In addition, after the early failure region, most semiconductor devices do not reach wear-out failure (genuine

failure) in the actual operating environment, and the failure rate exhibits the constant value of the random

2-4

failure region. This value becomes the same as that obtained by Equation 2.1.6, so the average failure rate can

be said to essentially be the failure rate after the early failure region.

(5) Mean Time To Failure: MTTF

The Mean Time To Failure (MTTF) of an item such as a semiconductor device that is not subject to repair or

maintenance is expressed by the following equation.

0

)( dtttfMTTF ・・・Eq. 2.1.7

2.1.2 Distributions Used in Reliability Analysis

Typical distribution functions used to analyze reliability data of semiconductor devices are described below.

(1) Normal distribution

The normal distribution is a typical continuous distribution used for quality control. It is said that in

reliability analysis, the normal distribution is often applied to wear-out life where failures concentrate around a

certain time.

The probability density function f(t) and distribution function F(t) are expressed by the following equations.

)(

2exp

2

1)(

2

2

t

ttf

・・・・Eq. 2.1.8

tdxx

tFt

2

2

2exp

2

1

・・・・Eq. 2.1.9

This distribution is given by the mean parameter μ and the dispersion (variance) parameter σ.

As shown in Fig. 2-2 below, the normal distribution has a symmetrical bell shape centering on μ, and the

probability of the value t being contained within the range of ±σ, ±2σ and ±3σ to both sides of μ is 68.26%,

95.44% and 99.7%, respectively.

Fig. 2-2 Normal Distribution

2-5

(2) Exponential distribution

The exponential distribution represents the life distribution (failure distribution function) in the random

failure region where the failure rate λ is constant over time, and the probability density function f(t) and

distribution function R(t) are expressed by the following equations. This distribution corresponds to the case

when the shape parameter m = 1 in the Weibull distribution described hereafter.

tetf )( ・・・・Eq. 2.1.10

tetR 1)( ・・・・Eq. 2.1.11

Fig. 2-3 Exponential Distribution

Note that as shown in the following equation, the MTTF is given from t0, which is the inverse of the failure

rate λ.

MTTFt 01 ・・・・Eq. 2.1.12

(3) Logarithmic normal distribution

The logarithmic normal distribution is a distribution function where ln t, which is the logarithm of the life

time t, follows the above-mentioned normal distribution.

The probability density function f(t) and distribution function F(t) are expressed by the following equations.

tt

ttf 0

ln

2

1exp

2

1)(

2

・・・・Eq. 2.1.13

t

dxx

xtF

0

2ln

2

1exp

1

2

1)(

・・・・Eq. 2.1.14

2-6

Fig. 2-4 Logarithmic Normal Distribution

In semiconductor device reliability, the electromigration life is generally known to follow a logarithmic

normal distribution.

(4) Weibull distribution

The Weibull distribution is a weakest link model proposed by W. Weibull (Sweden) in 1939 as a mechanical

breakdown strength distribution. This model was applied by J. H. K. Kao in 1955 to analyze the life of vacuum

tubes, and has often been used since then to model life distributions in analysis of semiconductor device

reliability.

The probability density function f(t) and distribution function F(t) are expressed by the following equations.

mmttm

tf

exp)(

1

・・・・Eq. 2.1.15

mt

tF

exp1)( ・・・・Eq. 2.1.16

2-7

Fig. 2-5 Weibull Distribution

Here, m is called the form parameter, η the measure parameter (characteristic life), and γ the position

parameter.

In addition, assuming t0=ηm, the failure rate (t) is expressed by the following equation.

1

0

1

(t)

m

m

tt

mtm

・・・・Eq. 2.1.17

The following information concerning the failure pattern can be obtained from the value of the form

parameter m.

0 < m < 1: Early failure (DFR) pattern where the failure rate decreases over time

m = 1: Random failure (CFR) pattern where the failure rate is constant (matches with the exponential

distribution)

m > 1: Wear-out failure (IFR) pattern where the failure rate increases over time

2.1.3 Semiconductor Device Failure Pattern

2.1.3.1 Semiconductor Device Failure Regions

Like general electronic equipment, semiconductor device failure regions are classified into the three types of

early, random and wear-out failure regions, and the time-dependent trend in the failure rate creates a curve called a

bathtub curve as shown in Fig. 2-6.

This curve is the sum of the early failure rate which decreases steadily over time, the random failure rate which

exhibits a constant value, and the wear-out failure rate which increases steadily over time. However, in case of

semiconductor devices, the random failure rate is thought to consist of only small soft errors as described hereafter,

and the failure rate in the random failure region (the height of the bottom of the bathtub) can be said to be

dominated by the sum of the failure rates of the region where the early rate converges towards a constant value and

f(t)

2-8

the region where the wear-out failure rate begins to rise.

Early failure region Random failure region Wear-out failure region

Wear-out failure rate

Random failure rate

Life (Useful years)Operating timeProduct shipped

Early failure rate

Fai

lure

rate

Fig. 2-6 Time-Dependent Change in Semiconductor Device Failure Rate

2.1.3.2 Early Failures

The failure rate in the early failure period is called the early failure rate (EFR), and the failure rate

monotonically decreases over time. The vast majority of semiconductor device early failures are caused by defects

built into devices mainly in the wafer process. The most common causes of these defects are dust adhering to

wafers in the wafer process and crystal defects in the gate oxide film or the silicon substrate, etc. Most devices

containing defects rooted in the manufacturing process fail within the manufacturing process and are eliminated as

defective in the final sorting process. However, a certain percentage of devices with relatively insignificant defects

may not have failed when making the final measurements and may be shipped as passing products. These types of

devices that are inherently defective from the start often fail when stress (voltage, temperature, etc.) is applied for a

relatively short period, and exhibit a high failure rate in a short time within the customer’s mounting process or in

the initial stages after being shipped as products. However, these inherently defective devices fail and are

eliminated over time, so the rate at which early failures occur decreases.

This property of semiconductor devices where the failure rate decreases over time can be used to perform

screening known as “burn-in,” where stress is applied for a short time in the stage before shipping to eliminate

devices containing initial defects. Product groups from which devices with inherent initial defects have been

removed to a certain degree by burn-in not only improve the early failure rate in the market, but also make it

possible to maintain high quality over a long period as long as these products do not enter the wear-out failure

region.

An overview of burn-in is described below.

(1) Derivation of failure distribution function of early failure period

In order to determine the burn-in conditions for reliably removing devices with inherent early failures, it is

necessary to obtain the failure distribution function of the early failure period.

2-9

To obtain this function, highly accelerated life tests are performed in a short time using a sample quantity on

a scale that is certain to contain devices with inherent initial defects (normally several thousand to ten thousand

pieces). The obtained failure time data is then plotted on Weibull probability paper and the failure distribution

function is estimated from the resulting regression line.

Fig. 2-7 shows an example of this process. The shape parameter m and the characteristic life η that determine

the Weibull distribution in the following equation can be obtained from the linear regression.

mt

tF

exp1)( ・・・・Eq. 2.1.18

This method of obtaining the failure distribution function is called burn-in study.

Fig. 2-7 Weibull Plot of the Burn-in Study

Note) Weibull probability paper is scaled to display linear regression of failure times that follow a Weibull

distribution.

(2) Determining the burn-in conditions

The screening (burn-in) conditions required to reduce the early failure rate after shipment (Note 1) to the

target value can be determined using the failure distribution function F(t) obtained from the burn-in study.

Labeling the burn-in time as t0 and the coefficient of acceleration for the burn-in conditions and the market

environment as K, the cumulative early failure rate that can be eliminated by burn-in is given as F(K·t0), and

the new cumulative early failure rate F(t) up to time t after burn-in can be obtained by the following formula.

)()()( 00 tKFttKFtF ・・・・Eq. 2.1.19

This relationship can be expressed in graph form as shown in Fig. 2-8.

The burn-in conditions are selected according to the combination of the acceleration conditions and time that

will reduce this value to the target early failure rate or lower. Normally, initial defects that are the cause of

2-10

early failures occur at the highest rate in the initial stages of process development, and then decrease thereafter

due to process improvements and process mastery. The early failure rate decreases in proportion to these initial

defects, so the burn-in time is reviewed as appropriate in accordance with process improvements.

Early failures eliminated by screeningF

ailu

re P

roba

bilit

yD

ensi

ty F

unct

ion

f(t)

Cumulative early failure rate F(t)

tK・t0

Burn-in Shipment

Fig. 2-8 Early Failure Screening by Burn-in

Note 1) The early failure rate described in this section is not the instantaneous failure rate but the

cumulative failure rate over the specified period. See the [Supplement] under “2.1.1 Measures for

Representing Reliability.”

2.1.3.3 Random Failures

When devices containing initial defects have been eliminated to a certain degree, the early failure rate becomes

extremely small, and the failure rate exhibits a gradually declining curve over time. In this state, the failure

distribution is close to an exponential distribution, and this is called the random failure period. The semiconductor

device failure rate during this period is an extremely small value compared to the early failure rate immediately

after shipment, and is normally a level that can be ignored for the most part. Viewed in terms of failure

mechanisms, there are extremely few semiconductor device failures that can be clearly defined as random failures.

However, memory software errors and other phenomena caused by α rays and other high-energy particles are

sometimes classified as randomly occurring failure mechanisms.

When predicting semiconductor device failure rates, failures occurring sporadically after a certain long time has

passed since the start of operation and failures for which the failure cause could not be determined are treated as

random failures in some cases. However, most of these failures are thought to be devices containing relatively

insignificant initial defects (dust or crystal defects) that fail after a long time, and should essentially be positioned

on the early failure rate attenuation curve. This type of failure rate cannot be estimated from the results of tests

performed with few samples such as reliability tests. There are also phenomena such as ESD breakdown,

overvoltage (surge) breakdown (EOS) and latch-up that occur at random according to the conditions of use.

However, these phenomena are all produced by the application of excessive stress over the device absolute

2-11

maximum ratings, so these are classified as breakdowns instead of failures, and are not included in the random

failure rate.

2.1.3.4 Wear-out Failures

Wear-out failures are failures rooted in the durability of the materials comprising semiconductor devices and the

transistors, metal lines, oxide films and other elements, and are an index for determining the device life (useful

years). In the wear-out failure region, the failure rate increases with time until ultimately all devices fail or suffer

characteristic defects.

The main wear-out failure mechanisms for semiconductor devices are as follows.

• Electromigration

• Hot carrier-induced characteristics fluctuation

• Time-dependent dielectric breakdown (TDDB)

• Laser diode luminance degradation

Semiconductor device life is defined as the time (or stress) at which the cumulative failure rate for the wear-out

failure mode reaches the prescribed value, and can be estimated using the results of reliability tests and test element

group (TEG) evaluation.

Semiconductor device life is often determined by the reliability of each element (metal lines, oxide film,

interlayer film, transistor, etc.) comprising the device, and these reliabilities are evaluated using TEG for each

element in the process development stage. These TEG evaluation results are incorporated into design rules in the

form of allowable stress limits (electric field strength, current density, etc.) to suppress wear-out failures in the

product stage and ensure long-term reliability. As a result, semiconductor devices experience almost no wear-out

failures within the reliability test time (stress) range in the product stage.

(1) Life estimation method

Semiconductor device life can be obtained as follows based on the wear-out failure data generated by TEG

evaluation and reliability tests. First, linear regression is performed for the time-dependent cumulative failure

rate using a Weibull probability distribution or logarithmic normal probability distribution, then the life is

obtained from the time (or stress) at which the reference cumulative failure rate is reached and the acceleration

factor of the accelerated test conditions (Fig. 2-9).

2-12

99.999.0

90.080.070.060.050.040.030.0

F(t) (%

)

20.0

10.0

5.0

2.0

1.0

0.5

0.2

0.110 100 1000 10000 100000

Time (h)

Acceleration test failure rate Predicted marketenvironment failure rate

×Acceleration factor

Fig. 2-9 Failure Rate Prediction Method Using Weibull Probability Plotting Paper

2-13

2.2 Semiconductor Reliability Verification

2.2.1 Basic Approach To Reliability Verification

The Sony Semiconductor Business Unit performs reliability verification that takes into account semiconductor

device failure modes (see Fig. 2-10) in each stage from process development through mass production.

Fig. 2-10 Semiconductor Device Failure Rate Curve

2.2.1.1 Reliability Verification in the Development Stage

The failure time due to wear-out failure (intrinsic failure) of semiconductor devices, that is to say the life, is

determined by the failure mechanisms of the process elements described in 2.2.2.

Reliability is evaluated in the process development stage using test element groups (TEG) suitable for verifying

these failure mechanisms to confirm that the prescribed reliability is satisfied.

2.2.1.2 Reliability Verification in the Prototype Stage

(1) Reliability verification for wear-out failures (Intrinsic failures)

Reliability is evaluated over long times using small quantities of prototypes to verify that wear-out failures

do not occur in the assumed operating environments and operating periods. (See Table 2-1.)

(2) Reliability verification for early failures (Extrinsic failures)

Semiconductor devices tend to have a high failure rate at the start of operation, and this failure rate tends to

decrease steadily over time. This is because a certain percentage of semiconductor devices have inherent

manufacturing defects such as dust, causing these devices to fail. This tendency is more noticeable for new

processes, so burn-in studies are performed when introducing production to verify the early failure rate.

When the prescribed failure rate is not satisfied, burn-in and other screening methods are used to remove

Early failure mode (Extrinsic failures)

Wear-out failure mode(Intrinsic failures)

New process

Operating time After burn-in

Fai

lure

ra

te

2-14

semiconductor devices with inherent manufacturing defects.

The Sony Semiconductor Business Unit continuously executes activities to stabilize and improve processes,

and strives to reduce the number of semiconductor devices with inherent manufacturing defects so that

prescribed early failure rates can be satisfied without the need to perform burn-in.

2.2.1.3 Reliability Verification in the Mass Production Stage

Mass production items are sampled* and reliability is periodically evaluated at the product level corresponding

to (1) above to confirm that the wear-out failure reliability level built in at the development stage is continuously

maintained from mass production onward.

* Samples are taken from each product family in consideration of combinations of wafer process, assembly

process, factory, and other factors.

2-15

Table 2-1 shows typical LSI product reliability test items used by the Sony Semiconductor Business Unit.

Table 2-1 Typical Sony LSI Product Reliability Test Items

Name of test Code Test conditions

High Temperature Operating Life HTOL Tj≧125C

Vop_max 1000h

Low Temperature Operating Life LTOL Ta=-55C

Vop_max 1000h

Temperature Humidity Bias THB Ta=85C85%RH

Vop_max On/Off 1000h

High Temperature Storage HTS Ta=150C 1000h

Temperature Cycling TC Ts=-65~125C 700cyc

Ts=-40~125C 850cyc

Ts=-65~150C 500cyc

Moisture Sensitivity Level MSL Level 3 (standard lank)

(J-STD-020)

Electrostatic Discharge Human Body Model

(HBM)

ESD

HBM

C=100pF, R=1500Ω

(JS-001-2014)

Electrostatic Discharge Charged Device

Model (CDM)

ESD

CDM

Charged Device Model

(JESD22-C101)

Latch-Up Trigger Pulse Current Injection

Method

LU

I-Test

Trigger pulse current injection method

(JESD78)

Latch-Up Supply Overvoltage Method LU

V-Test

Power supply overvoltage method; Ta=25, 125C

(JESD78)

Burn-In Study (Early Life Failure Rate) BIS

(ELFR)

Tj≧125C, Vop_max

2.2.2 Reliability in the Development and Design Stages

Semiconductor devices have failure mechanisms unique to semiconductors, and resolving these problems in the

process development stage is an important element for securing reliability. Stable product reliability can be

secured by verifying the required reliability when developing each process element and reflecting these results to

the design rules.

Table 2-2 shows typical failure mechanisms that can pose problems in the process development stage. As

processes become more miniaturized, higher internal electric fields, current densities, metal line stress and other

factors increase the stress applied to transistors and metal lines. On the other hand, faster circuit speeds and

increased parasitic impedance (metal line resistance, parasitic capacitance) reduce operating margins, which is a

major issue in securing reliability with respect to transistor characteristics fluctuation.

Typical semiconductor device failure mechanisms that can pose problems in the process development and

design stages are described below.

2-16

Table 2-2 Typical Failure Mechanisms in the Process Development Stage

Process element

Failure mechanism Failure mode and cause

Gate dielectric film

Time-dependent dielectric breakdown (TDDB)

Dielectric breakdown of the gate dielectric film. This is the phenomenon where bias applied to a gate electrode for a long time produces defects in the gate dielectric film, increasing the micro leak current and leading to dielectric breakdown.

Transistor Hot carrier (HCI) Transistor characteristics fluctuation due to trapping of hot carriers in the gate dielectric film. This is the phenomenon where high-energy electrons and holes generated by impact ionization of electrons accelerated by high electric fields are trapped in the oxide film, causing the transistor characteristics to fluctuate.

NBTI (slow trap) PMOS transistor characteristics fluctuation due to application of a gate negative bias (NBT). This is also called the slow trap phenomenon, and is the phenomenon where application of a bias at high temperatures increases the interface state and positive fixed charge, causing the transistor characteristics to fluctuate.

Memory device

Soft error Memory data rewrite error due to high-energy cosmic ray particles (neutron rays, proton rays, etc.), α rays, etc. This is a temporary data error phenomenon that occurs mainly in DRAM and SRAM.

Retention/disturb Non-volatile memory data loss. This is the phenomenon where long-term storage or operating environment stress (read/write electric field, temperature, stress) causes the trapped charge in a Flash memory to disappear, inverting the data.

Metal lines Electromigration Increased metal line resistance and disconnection due to voids forming in metal lines. This is the phenomenon where physical impacts between electrons and metal atoms cause the metal atoms to move, creating voids.

Stress migration The metal creep phenomenon due to metal line stress causes voids to form and grow in metal lines and connection (via hole) portions, resulting in open defects. In copper lines, this is the phenomenon where vacancies (atom holes) in copper lines due to metal line stress induce the creep phenomenon, causing voids to form and grow.

Low-k interlayer films

TDDB between metal lines

Short-circuit due to dielectric breakdown between copper lines. This phenomenon mainly consists of dielectric breakdown via the CMP interface of an interlayer dielectric film that uses low-k materials, resulting in a short-circuit between metal lines.

2-17

2.2.2.1 Time-dependent Dielectric Breakdown (TDDB)

MOS FET gate dielectric film has a failure mechanism whereby applying even an electric field of the dielectric

withstand voltage or less for a long time causes the dielectric film to deteriorate and lead to breakdown. This

breakdown of the dielectric film over time is called time-dependent dielectric breakdown (TDDB). The TDDB life

of gate dielectric film is one of the most important failure mechanisms determining the long-term reliability of a

MOS-type semiconductor device. The TDDB life said to be the factor that determines the limit for reducing the

gate dielectric film thickness, and the gate dielectric film thickness in system LSI is also sometimes determined by

the TDDB life in accordance with the logic circuit supply voltage.

(1) Gate dielectric film life distribution

Time-dependent dielectric film breakdown phenomena can generally be divided into an initial breakdown

area rooted in defects and a genuine life area. Fig. 2-11 shows the TDDB measurement data of a gate oxide

film (SiO2) plotted using a Weibull distribution function. The initial breakdown and genuine life areas can be

separated according to differences in the shape parameter (graph slope) of the Weibull distribution function.

Dielectric film distributed in the initial breakdown area with a short TDDB life is oxide film that includes

defects that may fail in a short time in the market, so it is important to suppress the defect occurrence rate to

lower the early failure rate.

In contrast to this, the genuine breakdown area indicates the natural life of gate dielectric film that does not

include major defects, and is a necessary index for assuring long-term reliability. The genuine life at the actual

operating voltage can be predicted using an electric field acceleration model from the evaluation results of

TDDB accelerated by high electric field stress conditions. The electric field acceleration model uses the E-

model (τexp(E)), Power-law model (τE-n) and other models according to the film thickness and film type.

(See Fig. 2-12.)

(2) Gate dielectric film breakdown mechanism

Gate dielectric film contains a large number of micro defects and impurities that occur in the wafer process,

and micro leak currents flow via these defects even in the state where the applied electric field (supply voltage)

is less than the genuine withstand voltage. These leak currents generate new defects in the dielectric film over

time, and the accumulation of these defects leads to dielectric film breakdown.

The percolation model is a typical failure mechanism for TDDB breakdown of thin gate dielectric film. In

this failure model, when defects initially present in the gate dielectric film and new defects generated by tunnel

current flowing due to the application of electric fields are continuous in the thickness direction, this leads to

dielectric breakdown. (See Fig. 2-13.)

As gate dielectric film becomes thinner, fewer defects may generate continuous defects which are needed for

dielectric breakdown, so the TDDB life variance increases. In addition, data written in Flash memories can also

2-18

be lost (phenomenon of retention) due to micro leak currents prior to breakdown.

Fig. 2-11 TDDB Data Distribution (Weibull)

Fig. 2-12 Electric Field Acceleration Model and Life Prediction

EFIELD: Actual electric field

ETEST: Test electric field

Genuine life distribution

Oxide film that includes defects

(early failure area)

2-19

Fig. 2-13 Gate Dielectric Film Breakdown Model (Percolation Model)

2.2.2.2 Hot carrier (HCI)

Hot carrier is a failure mechanism where a charge (carrier) that has attained high energy mainly due to

acceleration by the electric field inside the MOS FET becomes trapped in the gate dielectric film, causing the

transistor characteristics to fluctuate and resulting in a circuit operation error. In a general operating environment,

the greatest transistor deterioration is caused by Drain Avalanche Hot Carrier (DAHC) injection, which occurs

when electrons flowing along an NMOS FET channel are accelerated by the high electric field near a drain. On the

other hand, the hot carrier mechanism that injects a charge to the dielectric film is also used to write and erase data

in a non-volatile memory.

(1) Drain Avalanche Hot Carrier (DAHC) injection

Electrons flowing in a NMOS FET channel are accelerated by the high electric field near a drain and undergo

impact ionization, generating electron-hole pairs. Of the electron or the hole, the carrier with the higher energy

(hot carrier) is injected to and trapped by the gate dielectric film, causing the transistor characteristics to

fluctuate (threshold value fluctuation, drop in drain current, etc.). This is called Drain Avalanche Hot Carrier

(DAHC) injection. (See Fig. 2-14.)

The dominant DAHC injection mode in a NMOS FET is mainly electron injection, and the maximum

deterioration occurs under the condition where the gate voltage is approximately 1/2 • VDS. This means that in a

CMOS circuit, hot electron injection occurs when the signal is inverted (H→L/L→H), so deterioration

progresses as the circuit is operated.

This problem can be avoided by selecting operating conditions (voltage, duty) in the circuit design stage

under which hot carriers are not easily generated, and reliability can also be increased by providing circuits

with the required operating margin. Device countermeasures are also taken, such as adopting a device structure

(LDD structure) that suppresses hot carrier generation by reducing the electric field around drains.

(a) Initial stage (b) Defect generated by micro leak current

(c) Breakdown occurs

Defect

2-20

Fig. 2-14 DAHC Mechanism

2.2.2.3 Negative Bias Temperature Instability (NBTI)

PMOS FET negative bias temperature instability (NBTI) is the phenomenon where transistor characteristics

fluctuate when a negative gate bias is applied to a PMOS FET. This is one of the transistor deterioration

mechanisms known as slow trap. PMOS FET is one of the latest MOS processes, and the use of surface channel-

type transistors causes deterioration to increase, which is a transistor reliability problem on a level with hot carriers.

(1) NBTI deterioration mechanisms

When a negative bias is applied to a PMOS FET, the holes on the Si surface are trapped by the Si-H bond of

the Si-SiO2 interface, and the hydrogen (H) is disassociated from the Si-H bond and generates an interface state.

The hydrogen disassociated from the Si bond diffuses and is trapped within the gate dielectric film, generating

a positive fixed charge that promotes deterioration of the transistor characteristics.

Si ≡ Si- H + hole Si ≡ Si-・+ + H

H + H H2

The interface state generated at the interface between the Si and the gate dielectric film traps the positive

charge when the PMOS FET operates, and becomes positively charged. This generates a positive fixed charge

in the dielectric film, and causes the transistor threshold voltage (Vth) to fluctuate and the drain current to drop.

One characteristic of NBTI is that when negative bias is applied to a gate, deterioration occurs regardless of

transistor operation, so deterioration proceeds even in circuits that are not operating. On the other hand, there is

also the phenomenon that fluctuating characteristics recover rapidly when negative bias stress is not applied,

and the amount of fluctuation in the operating state is known to be largely independent of the operating

frequency. In the process conditions, the amount of NBTI deterioration is closely related to the concentrations

and profile of the impurities (N, H, B, etc.) in the gate dielectric film, and the amount of deterioration increases

in particular for gate dielectric films (SiON, SiN) with high nitrogen (N) contents.

Gate

Source Drain

Electron

Hole

2-21

This problem can be avoided by design countermeasures such as providing sufficient margin for circuit

operation on account of transistor deterioration, and by reducing the electric fields applied to gate dielectric

film. Device countermeasures are also taken such as forming the gate dielectric film so that interface states and

fixed charges are not easily generated.

Fig. 2-15 NBTI Failure Mechanisms

2.2.2.4 Soft Error

When α rays and high-energy neutron rays generated from cosmic rays, etc. penetrate memory elements and

other semiconductor devices, large quantities of electron-hole pairs are generated within the silicon crystals. These

charges invert the memory nodes, resulting in memory data errors known as the soft error phenomenon. The soft

error phenomenon temporarily inverts the memory and logic circuit data, and these errors can be recovered by

rewriting the data. This phenomenon was previously a problem for DRAM, but is currently also considered a

problem for SRAM reliability.

(1) Principle of soft error generation by α rays

The quartz materials used in the sealing resin packages of semiconductors contain trace amounts of

radioactive elements (uranium: 238U; thorium: 232Th). In addition, the lead bumps used in flip chips sometimes

contain polonium (210Po). When the high-energy α rays emitted by these radioactive elements penetrate the

silicon substrate, electron (e-) and hole (e+) pairs are generated along the α ray path inside the silicon. The

electric field causes electrons generated inside the depletion layers to migrate and cluster together in the n

HoleDiffusion to within the oxide film Generation of a positive fixed charge

Hole trapping

Generation of an interface state

Si-SiO2 interface terminated by hydrogen (H) (Negative bias applied)

Hole trapping by the tunnel phenomenon

Disassociation of hydrogen (H) and generation of an interface state

2-22

diffusion area, which causes the memory node capacity potential to drop. (See Fig. 2-16.)

Fig. 2-17 shows the soft error mechanisms in the SRAM memory cell. When the High side memory node

potential falls below the driver transistor threshold value, the two inverters forming a Flip-Flop both turn off at

the same time, making the Flip-Flop unstable and causing misoperation. Generally when the word line is

selected, the High side memory node potential (Vh) drops to Vcc - Vth (word transistor threshold value). When

the word line is not selected, the High side memory node is charged by the memory cell load and the potential

returns to Vcc. The faster this recovery time from Vcc - Vth to Vcc, that is to say the greater the current supply

capacity of the memory cell load, the more resistant the SRAM is to soft errors.

Countermeasures for soft errors caused by α rays include forming a protective film on the chip surface to

absorb α rays. In addition, countermeasures are also taken to reduce α ray emission levels such as by using

highly pure package materials with reduced levels of radioactive element contents.

Fig. 2-16 Generation of Electron and Hole Pairs by α Rays

2-23

Fig. 2-17 Soft Error in the SRAM Cell

(2) Soft errors due to cosmic rays

High-energy cosmic rays collide in the atmosphere with the atoms that comprise the atmosphere, generating

high-energy protons and neutrons. These high-energy neutron rays passing through silicon, electron-hole pairs

are generated along the range and the neutron rays collide with silicon atoms to generate secondary ions by

spallation reaction; which can cause soft errors. The quantity of high-energy neutrons generated by cosmic rays

that reaches the ground is known to increase in high-elevation regions due to differences in geographical

conditions and lower atmospheric shielding effects, and this causes the soft error occurrence rate to increase.

This can pose serious reliability problems in applications such as aircraft and satellites.

It is difficult to suppress factors causing soft errors due to cosmic rays, so this is known as a failure mode

that occurs at a certain probability. One countermeasure method for SRAM is to mount error correcting code

(ECC) so that data experiencing soft errors is corrected. In addition, device structures such as SOI structures

that are resistant to the effects of soft errors are also sometimes used.

2.2.2.5 Electromigration

Electromigration is a failure mechanism where electrons flowing through metal (Al, Cu) lines collide physically

with the metal atoms, causing the metal atoms to migrate and form voids in the metal lines which lead to increased

metal line resistance and disconnection. Electromigration is a key failure mechanism that determines the long-term

reliability of metal lines.

(1) Aluminum electromigration

2-24

The thin films used in aluminum (Al) lines are formed by spattering, and the aluminum atoms accumulate in

a polycrystalline (grain) structure. (See Fig. 2-18.) When current of a certain density or more flows through

these metal lines, the electromigration phenomenon is caused where the metal atoms physically move by stress

due to collisions between the electrons and metal atoms. The metal atoms around the grain boundaries have

weak bonding energy and move easily, so electromigration occurring at the grain boundaries of metal lines

with uneven grain sizes causes voids to form and grow along the grain boundaries, leading to disconnection.

(See Figs. 2-19 and 2-20.)

Process countermeasures include adding trace amounts of copper to aluminum to suppress aluminum atom

migration by slowing down the movement time, and covering the top and bottom of metal lines with Ti, W or

other metal alloys (cap layer) to suppress aluminum atom movement. Circuit design countermeasures are also

taken such as keeping the current density that flows in metal lines to a certain value or less.

Fig. 2-18 Aluminum Grain Structure

Fig. 2-19 Electromigration Mechanism

Al accumulation Al shortage (void)

Al grain boundary

Grain boundary diffusion

Electron

2-25

Fig. 2-20 Photo of Electromigration

(2) Copper electromigration

Copper lines are formed by an embedded metal line (damascene) process that uses electroplating. Copper has

a higher melting point and activation energy than aluminum, and exhibits reliability with respect to

electromigration that is several ten to several hundred times higher than that of aluminum. However, the

miniaturization of metal lines in the latest processes is increasing the current density, so resistance to

electromigration is becoming an important issue for reliability.

The electromigration resistance of copper is known to be greatly affected by the crystal grain size and

alignment, and the adhesion at the interface between the copper and the barrier metal. Particularly in copper

lines that has a structure surrounded by barrier metal, when the adhesion drops between the copper and the cap

layer on the top surface where smoothing is performed, the copper at the interface moves easily, resulting in

migration. Therefore, it is important that the process incorporate countermeasures to increase the adhesion at

the interface between the copper and the cap layer. Circuit design countermeasures are also taken such as

keeping the current density that flows in metal lines to a certain value or less.

2.2.2.6 Stress Migration

Stress migration is a failure mechanism where stress applied to metal lines causes the metal atoms to creep,

forming voids in metal lines which lead to increased metal line resistance and disconnection. Stress is generated

in the metal lines (Al, Cu) used in LSI due to temperature differences between the heat treatment process in the

manufacturing process and the operating environment temperature. Thanks to this stress, vacancies in the metal

lines can creep and converge in a single location, forming a void.

Stress migration occurs due to the interaction between the metal line stress and the metal atom creep

phenomenon. Whereas the metal atom creep speed increases at high temperatures, the stress acting on the metal

lines decreases at high temperatures, so there is known to be a peak to the temperatures at which stress migration

occurs.

Interlayer dielectric film

2-26

(1) Aluminum stress migration

Aluminum lines have many vacancies and aluminum atoms with weak bonding force at the grain boundaries

of the polycrystalline structure, so when tensile stress is applied to metal lines, these aluminum atoms and

vacancies at the grain boundaries creep and form voids. Aluminum voids produced by tensile stress mainly

form and grow along the crystal grain boundaries, and can lead to increased metal line resistance and

disconnection defects. (See Fig. 2-21.)

Aluminum stress migration is generally said to have an occurrence ratio peak around 150 to 200°C, and can

become a problem for long-term reliability in devices that are used for long times in high-temperature

environments.

As a design countermeasure, patterns are designed to avoid applying excessive stress to metal lines. Process

countermeasures include using a metal line structure that layers the aluminum between upper and lower layers

of a cap layer (Ti, W, etc.) to prevent stress migration. In addition, countermeasures such as using an interlayer

film structure that reduces stress and optimizing the heat treatment process are also taken to reduce the residual

metal line stress.

Fig. 2-21 Disconnection Defect due to Aluminum Stress Migration

(2) Copper stress migration

Regarding copper stress migration, the stress induced voiding (SIV) mode that produces voids in via holes

that connect upper and lower lines is a problem for reliability. When wide lines and narrow lines are

connected by a single via hole, the tensile stress on the wide line side concentrates in the via hole, causing the

vacancies in the copper to creep and migrate to the via hole and form a void. (See Fig. 2-22.) Stress migration

at copper via holes is known to have an occurrence temperature peak around 200°C. However, this failure is

largely dependent on the stress generated in the high- temperature annealing process after copper line

formation, so it occurs in a short time and is an early failure factor.

A countermeasure method in the design stage is to use multiple via holes in areas where wide lines and

narrow lines are connected. When metal lines are connected by multiple via holes, even if stress concentrates

2-27

on a single via hole and creates a void, the stress applied to other via holes is reduced so voids do not easily

occur at those other via holes, enabling prevention of open defects between metal lines. Process

countermeasures are also taken such as reducing the copper stress and selecting process conditions that reduce

the vacancies in copper.

Fig. 2-22 Void Caused by Stress Migration in a Copper Wiring Via Hole 1)

<References>

1) R. Kanamura et al.: Symp. on VLSI Tech., p. 107, 2003

2-28

2.3 Acceleration Model

In general, failure of components including semiconductor devices occurs due to some reaction at the atomic or

molecular level, and can be described by the Eyring absolute reaction theory (hereafter, “Eyring model”).

This Eyring model expresses the lifetime L in the absolute temperature T range that should be the focus for

reliability by the following separation of variables-type equation, using the activation energy Ea shown in Fig. 2-23,

the non-temperature stress S that is a factor inducing failure, and the Boltzmann’s constant k(8.617×10E-5[eV/K]).

L = A・S-n exp(Ea/kT)・・・・Eq. 2.3.1

“A” and “n” in the above equation are constants.

Outlines of the environmental and operating stress acceleration models used for semiconductor devices are

described below.

2.3.1 Acceleration Models for Environmental Stress

(1) Temperature acceleration model

exp(Ea/kT) on the right side of Equation 2.3.1 is also called the Arrhenius model since this is the same to the

equation derived empirically by Arrhenius in the 19th century.

Ea is the activation energy of which unit is “eV.” The activation energy is an essential one for the progress of

chemical and physical reactions. If chemical and physical reactions consisting of failure mechanisms are same,

the activation energies are inevitably equal.

L = A・exp(Ea/kT) ・・・・Eq. 2.3.2

(2) Humidity acceleration model

Humidity-induced acceleration models express the absolute vapor pressure Vp or the relative humidity RH as

humidity stress.

Typical models are described below.

① Absolute vapor pressure model

This model expresses temperature stress and humidity stress using the absolute vapor pressure VP, which

is empirically known as correct. Because Vp depends on the temperature, the Eyring Model cannot be used.

L = VP-n ・・・・Eq. 2.3.3

② Relative humidity model

This model is expressed conforming with the Eyring model by a separation of variables-type equation

using the absolute temperature T and relative humidity RH since Vp depends on the temperature, and

corresponds to the case when S = RH in Equation 2.3.1.

L = A・(RH)-n exp(Ea/kT) ・・・・Eq. 2.3.4

2-29

③ Lycoudes model

Those models which multiply temperature, relative humidity and a function of voltage are also available.

As a typical model, the Lycoudes model reported by N. Lycoudes is shown below.

MTTF=A・exp(Ea/kT)・exp(B/RH)・V-1・・・・Eq. 2.3.5

“V” and “B” in the above equation are voltage and a constant respectively.

(3) Temperature difference acceleration model

This model is applied to failures caused by the repeated application of stress (thermal stress) produced by

temperature differences. Labeling the temperature difference as ∆T, the number of cycles N is expressed using

the following equation, by substituting S=ΔT for Equation 2.3.1.

N=A・ΔT –α ・・・・Eq. 2.3.6

[Supplement]

In case of low cycle fatigue, failures due to thermal fatigue of materials (cycle life) Nf conforms to the

Coffin-Manson model described by the following equation, where ∆ε is the plasticity strain amplitude.

ΔεP・Nfα=C ・・・・Eq. 2.3.7

“a” and “C” in the above equation are material constants.

In case of low cycle fatigue, failure due to repeated thermal stress conforms to the Coffin-Manson model,

and the temperature difference acceleration model is thought to be a form of that model. Semiconductor chip

failure can be broadly described using the temperature difference acceleration model, but the Coffin-Manson

model must be taken into account for mounting failures including package factors, such as the thermal fatigue

life of soldered portions. The following is a variation of the Coffin-Manson model on which the effects of the

temperature cycling frequency and maximum temperature, suggested by Norris and other persons.

Nf=C・fm・ΔεP-n・exp(Q/kTMAX) ・・・・Eq. 2.3.8

In the above equation; “Nf” is the fatigue life, “C” is the material constant, “m” and “n” are exponents, “f” is the

cycling frequency, “ΔεP” is the plasticity strain amplitude, “Q” is the activation energy, “k” is the Boltzmann's

constant and “TMAX” is the maximum temperature.

2-30

2.3.2 Acceleration Models for Operating Stress

Operating stresses that determine semiconductor device life include voltage, current, electric field strength,

current density, etc., and differ according to the failure mechanism as described in section 2.2.2. The main failure

mechanism acceleration models are described below.

Note that life in these models also depends on the temperature, so it is expressed by an Eyring model of the

operating stress and temperature stress.

(1) Time-dependent dielectric breakdown (TDDB) acceleration models

The life of devices (TTF) due to TDDB depends on the gate oxide film thickness. The Eox model is said to

be appropriate for those devices of which gate oxide film thickness is 5nm or more; the Vg model for more

than 2nm, and less than 5nm; and the Power-law model for 2nm or less.

① Eox model

TTF=A・exp(-γEOX・Eox) exp(Ea/kT) ・・・・Eq. 2.3.9

② Vg model

TTF=A・exp(-γVg・Vg) exp(Ea/kT) ・・・・Eq. 2.3.10

③ Power-law model

TTF=A・Vgn・exp(Ea/kT) ・・・・Eq. 2.3.11

In the above equations; “γEOX” is the field intensity acceleration factor, “γVg” and “n” are voltage acceleration

factors, “Eox” is the stress electric field applied to the gate and “Vg” is the stress voltage applied to the gate.

Normal state

Degraded state

Activated state

Fig. 2-23 Activation Energy

Act

ivat

ion

ene

rgy

2-31

(2) Hot carrier (HCI) acceleration models

The life of devices due to hot carriers is indicated by the substrate current model expressed by the substrate

current and the 1/Vds model expressed by the drain voltage. Since process nodes for the 0.25um and 0.15um

generations and newer devices, other impacts are greater than that of the substrate current, the 1/Vds model is

becoming the main one.

① substrate current model

TTF=A・Isub -m ・exp(Ea/kT) ・・・・Eq. 2.3.12

② 1/Vds model

TTF=A・exp(B/Vds)・exp(Ea/kT) ・・・・・Eq. 2.3.13

In the above equations; “m” is the factor depending on the substrate current, “B” is the factor depending on the

voltage, “Isub” is the maximum substrate current while stress is being applied and “Vds” is the drain voltage while

stress is being applied.

(3) Negative Bias Temperature Instability (NBTI) acceleration models

The life of devices due to NBTI is often indicated by the following equations:

TTF=A・exp(γ・Eox) exp(Ea/kT) ・・・・Eq. 2.3.14

TTF=A・Eoxγ ・exp(Ea/kT) ・・・・Eq. 2.3.15

TTF=A・Vgn ・exp(Ea/kT) ・・・・Eq. 2.3.16

In the above equations; “γ” is the field intensity acceleration factor, “n” is the voltage acceleration factor, “Eox” is

the stress electric field applied to the gate oxide film and “Vg” is the stress voltage applied to the gate oxide film.

(4) Electromigration (EM) acceleration model

In general, the life of devices due to EM is logically explained by the Huntington’s equation.

∂C/∂t=D∇｛∇C-(eZ*/kT) E・C｝ ・・・・Eq. 2.3.17

In the above equation; “C” is the atomic concentration, “D” is the diffusion factor, “Z*” is the effective valence,

“E” is the electric field, “e” is the electronic charge, “k” is the Boltzmann's factor and “T” is the absolute

temperature.

To calculate the actual life of devices due to EM (TTF), the Black’s equation which was derived empirically, is

widely used.

In the following equation; “T” is the absolute temperature, “j” is the current density, “Ea” is the activation energy,

“A” is the constant of proportionality, “n” is the function of the current density and“k” is the Boltzmann's factor.

TTF=A・j-n・exp(Ea/kT) ・・・・ Eq. 2.3.18

2-32

<References>

1) JEITA EDR-4704A: Application guide of the accelerated life test for semiconductor devices

2) JEITA EDR-4707：Report on Failure Mechanism of LSI and reliability test method

3) JEITA ETR-7024：Research Report on Effect of Voids on Reliability of Lead-Free Solder Joints and

Standard of Evaluation Criteria

4) N. J. Flood：Reliability aspects of plastic encapsulated integrated circuit, IRPS(1972)

5) D. S. Peck：Temperature-humidity acceleration of metal-electronics failure in semiconductor devices,

IRPS(1973)

6) N. Lycodes：The reliability of plastic microcircuit in moist environments, Solid State Technology(1978)

7) T. Gasser：Hot Carrier Degradation in Semiconductor Device

8) Comparison of NMOS and PMOS hot carrier effects, IEEE transaction on electron devices(1997)

9) H. B. Huntington：Diffusion in Solids, Academic Press(1975)

Semiconductor Quality and Reliability Handbook

Chapter 3 Semiconductor Device Failure Analysis

3-1

Chapter 3 Semiconductor Device Failure Analysis

3.1 What is Failure Analysis? ................................................................................................................................. 3-2

3.2 Necessity of Failure Analysis Technology ....................................................................................................... 3-2

3.3 Failure Analysis Technology ............................................................................................................................ 3-3

3.3.1 General Failure Analysis Flow ............................................................................................................. 3-3

3.3.2 Investigation of Failure Circumstances ............................................................................................... 3-5

3.3.3 Handling of Failure Samples ............................................................................................................... 3-5

3.3.4 External Visual Inspection of the Package ......................................................................................... 3-6

3.3.5 Evaluation of Electrical Characteristics ............................................................................................... 3-6

3.3.6 Package Analysis Technology ............................................................................................................ 3-7

3.3.6.1 Description ............................................................................................................................... 3-7

3.3.6.2 X-ray Observation and Scanning Acoustic Tomography Observation ................................ 3-7

3.3.6.3 New Technologies that have Begun to be Used in Recent Years ....................................... 3-9

3.3.7 Chip Analysis Technology ................................................................................................................. 3-13

3.3.7.1 Description ............................................................................................................................. 3-13

3.3.7.2 Package Decapping Technology and Stacked Chip Removal Technology ..................... 3-14

3.3.7.3 Failure Locating Technology ................................................................................................ 3-15

3.3.7.3.1 Failure Inference Technology .................................................................. 3-16

3.3.7.3.2 Photoemission Analysis Technology ....................................................... 3-18

3.3.7.3.3 IR-OBIRCH Analysis Technology ............................................................ 3-19

3.3.7.3.4 Analysis Technologies that have Begun to be Used in Recent Years ..... 3-20

3.3.8 Chip Physical Analysis Technology .................................................................................................. 3-25

3.3.8.1 Description ............................................................................................................................. 3-25

3.3.8.2 Interlayer Removal Technology ........................................................................................... 3-25

3.3.8.3 Chip Front and Rear Surface Observation Analysis ........................................................... 3-26

3.3.8.3.1 Scanning Electron Microscope (SEM) ..................................................... 3-27

3.3.8.4 Cross-sectional Analysis Technology .................................................................................. 3-28

3.3.8.4.1 FIB ........................................................................................................... 3-28

3.3.8.4.2 TEM ......................................................................................................... 3-29

3.3.9 Analysis Technologies ....................................................................................................................... 3-30

3.3.9.1 Description ............................................................................................................................. 3-30

3.3.9.2 Fourier Transform Infrared Spectroscopy (FT-IR) Analysis ................................................ 3-30

3.3.9.3 EDX/WDX ............................................................................................................................. 3-31

3.3.9.4 Auger Electron Spectroscopy (AES) Analysis ..................................................................... 3-33

3.3.10 Confirmation of Relation between Trouble and Failure Mechanisms ........................................... 3-34

3-2

3.1 What is Failure Analysis?

Failure analysis consists of swiftly confirming various failure conditions that occur in the various manufacturing

processes and the market, investigating the electrical characteristics using a LSI tester and other tools, and then

using these results together with the optimum physical and chemical methods and analysis equipment to clarify the

causes and mechanisms that led to the failures.

3.2 Necessity of Failure Analysis Technology

Chips used in semiconductor devices are becoming more highly integrated and products are incorporating more

advanced functions in recent years, such as multiple chips mounted in a single package (SIP: System in Package).

As a result, manufacturing processes are becoming more miniaturized and complex, and failure causes and

mechanisms are also diversifying and becoming more complex.

However, extremely high levels of quality and reliability are required of semiconductor devices. When

manufacturing semiconductors, consistent quality and reliability must be built in from the development stage to

the manufacturing stage in order to prevent semiconductor devices from failing in the market and causing trouble

for customers. For this reason, it is extremely important to swiftly analyze failed products occurring in reliability

tests, customer processes and the market, accurately clarify failure causes and mechanisms, and provide feedback

to the manufacturing and design processes to improve manufacturing and product quality.

In this manner, failure analysis technology is not simply a means to investigate the failure causes and

mechanisms of failed products. It is a vital and essential technology for quality and reliability improvement

activities aimed at reducing failures in customer processes and the market to as close to zero as possible.

3-3

3.3 Failure Analysis Technology

3.3.1 General Failure Analysis Flow

The most important factor in failure analysis is how far the failure location can be narrowed down while still

maintaining the failure symptoms (undestroyed state). The failure cause clarification rate varies widely according

to whether the location can be narrowed down only to the function block level or whether the location of the

trouble can be pinpointed.

Finding a failure location with a radius of approximately 1 µm in the latest highly integrated semiconductor

devices is comparable to searching for a coin dropped somewhere in an eight-story building covering a site the

size of a baseball stadium. In this type of situation it is impossible to find the location simply by searching with

only a vague notion of where to look.

The chances of finding the coin can be increased by first carefully investigating the behavior and other details

of the person who dropped the coin, isolating as much as possible the location where the coin is thought to have

been dropped, and then searching carefully once that location has been determined.

Likewise, isolation of a semiconductor device failure location begins by investigating the electrical

characteristics with an LSI tester and other tools in order to roughly narrow down the part of the device where the

failure is likely to have occurred.

Fig. 3-1 shows an example of general failure analysis procedure.

3-4

Fig. 3-1 General Failure Analysis Procedure

Each item is described in detail in the following sections.

Understanding of failure information

Confirmation of failure phenomenon

Request for analysis

Request acceptance

Reproduction of failure Determination of failure mode

Isolation of failure location

Physical analysis

Analysis report

Request for physical analysis

Customer claim request /Request for electrical analysis

Cross-sectional analysis (FIB, STEM, etc.)/Planar removal analysis /Analysis (EDX, etc.)

Photoemission analysis, EB

Tester, etc.

Isolation of failure location (Electrical

analysis)

Determination of failure cause

(Physical analysis)

3-5

3.3.2 Investigation of Failure Circumstances

When failures occur, the failure circumstances (whether the failure occurred in the customer’s manufacturing

process or after the product had been used in the market for a while, what was the operating environment, etc.) are

extremely important information for estimating the failure cause and determining the failure analysis methods and

procedures so that failure analysis can proceed smoothly.

Therefore, when a failure sample is obtained, as much information as possible about that sample is gathered at

the same time from the customer and other sources. Information about the environment in which the failure

occurred (place where the trouble occurred, environmental conditions, circuits used, operating conditions,

mounting conditions, etc.) is particularly helpful in estimation of the failure mechanism and selection of analysis

techniques and methods. In addition, such information is sometimes helpful in performing failure simulations and

confirming reproducibility in order to help determine whether the failure is a random failure or due to a design

problem.

3.3.3 Handling of Failure Samples

Failure samples are highly valuable as their number is limited. If failure analysis is unsuccessful, it is possible

that no information may be obtained. Therefore, the following precautions should be observed when handling

failure samples.

(1) Maintenance of failure conditions

If stress (thermal, electrical, mechanical) that may change the failure conditions is applied prior to analysis,

analysis is impossible. However, if samples are removed from boards after being solder-mounted onto boards,

lead processing or reball operation is required for LSI tester measurement.

The utmost care should be taken during these heating processes to conduct them in as short a time as possible

and not to apply heat to the device or to damage the leads or lands. The Sony Semiconductor Business Unit has

also prepared an environment that enables electrical measurement in the land grid array (LGA) state (the same

state as when the solder balls are removed from a BGA product) as a method of analyzing ball grid array

(BGA) products without applying heat.

(2) Storage

Care must be taken to store failure samples in an environment with the ideal temperature and humidity, and to

prevent electrical, mechanical and other damage.

Additional care must also be taken for storage to prevent the adherence of dust or surface scratching of samples

with decapped packages or that have been reduced to discrete chips partway through physical analysis. Recently it

has also become necessary to store samples in locked storage vaults or rooms that ensure a certain level of security

to prevent information leaks concerning security chips and other confidential technology.

3-6

3.3.4 External Visual Inspection of the Package

Visual inspection of the external condition of the obtained samples is extremely important, and is a source of

useful information for failure analysis. The main check contents are cracking, voids, scratching, burn marks,

damage to external pins, adherence of foreign matter, discoloration, etc.

3.3.5 Evaluation of Electrical Characteristics

(1) Evaluation using an LSI tester

First, the electrical characteristics of failure samples are evaluated by test programs similar to those used for the

shipping inspection. These results are then used to determine whether the product failed due to a semiconductor

defect, or whether a product that should normally have failed the shipping inspection inadvertently flowed out to a

customer due to some deficiency with the test program. In addition, the temperature dependence, voltage

dependence, operating frequency dependence and other details of the failed product are evaluated, and the obtained

data is used to determine the detailed analysis methods.

(2) AC and DC characteristics evaluation

Open connections, short circuits, withstand voltage deterioration and other DC characteristics are investigated

using a curve tracer, parameter analyzer and other tools. In addition, an oscilloscope is used for simple AC

characteristics evaluation, etc.

(3) Evaluation using actual electronic equipment (evaluation jig created by modifying an actual

set product)

When the failure cannot be reproduced by the checks described above and the failure sample receives a passing

judgment (the product passes the assurance items for a discrete semiconductor device), failure reproducibility is

checked using an evaluation jig created by modifying an actual set product, etc.

If the trouble is confirmed at this point, the function trouble occurring in the actual set product may be a case not

included in the shipping inspection program using the LSI tester, so addition to the function test items is

investigated. This method is also used as a means of analysis (in place of an LSI tester, etc.) to narrow down the

failure location when the failure is reproduced but the location is difficult to narrow down using methods (1) and

(2) above.

3-7

3.3.6 Package Analysis Technology

3.3.6.1 Description

Recently, compact semiconductor products with advanced functions that incorporate peripheral devices into a

thin package are demanded. These needs are met by SiP products, which have recently become the main product

type. Fig. 3-2 shows a schematic of a typical SiP product. Package on Package (POP) products have also appeared,

in which multiple chips are stacked in a single package and not only chips but actual products are incorporated. As

a result, structures are becoming extremely complex, making it necessary to clarify whether the failure occurred

inside a chip or if it is rooted in the assembly before starting detailed analysis. In addition, increasing numbers of

pins and other factors are resulting in extremely narrow metal wiring intervals, and even microscopic foreign

matter that previously was not a problem can cause short-circuits between wiring, so material control and assembly

process cleanliness requirements have also become extremely strict compared to previous levels. This also applies

to decapping methods. For example, decapping that uses only fuming nitric acid or other chemicals is insufficient

to analyze diverse structures, so new decapping methods must also be investigated.

In this section, conventional package analysis methods are simply described, and new equipment and methods

being actively introduced by the Sony Semiconductor Business Unit to analyze the latest package structure

products are mainly focused on.

Fig. 3-2 Schematic of Typical SiP Product

3.3.6.2 X-ray Observation and Scanning Acoustic Tomography Observation

X-ray observation allows non-destructive observation of the wire bonding condition (wire loop condition, gold

bump condition, switch shape, etc.), lead frame condition, voids in the molded resin, and the board wiring and

through-hole condition. In addition, recent improvements in radiograph resolution also enable observation of the

condition of micro-bumps used in Chip on Chip (CoC) and other packages. (See Fig. 3-3.)

Mixed mounting package

Upper layer chipLower layer chip

3-8

Fig. 3-3 X-ray Photo

The addition of CT functions has also enabled three-dimensional confirmation of internal structures in the

undestroyed state, making radiographs useful equipment for observing assembly trouble.

Scanning acoustic tomographs (SAT) and scanning acoustic microscopes (SAM) use the principle that ultrasonic

waves are reflected at the junction interface between materials with different acoustic impedance. SAT and SAM

detect the reflected waves of the ultrasonic waves emitted to the sample, enabling non-destructive observation of

package internal conditions at arbitrary depths, such as junction interface delamination, voids in the package resin,

cracks, and chip cracking. (See Fig 3-4.)

Fig. 3-4 Scanning Acoustic Tomography Photo

Recently, higher frequencies (approximately 300 MHz) are used to increase the resolution, enabling

observation of interface delamination like micro-bumps as small as approximately 40 µm and internal voids.

<SHORT>

Bump diameter = 100m

(Angle: 45)

Defect bump

Crack locations

<OPEN>

Bump diameter = 100m

<Chip cracking> <Delamination>

Normal product Failed product

Delamination detected in the white area

3-9

The equipment outline and principle are typical and have been described in various documents, so these

descriptions are omitted here.

3.3.6.3 New Technologies that have Begun to be Used in Recent Years

(1) Scanning SQUID (Superconducting QUantum Interference Device) Microscope Analysis

SQUID is the abbreviation for an ultra-sensitive magnetic sensor that uses the superconducting quantization

phenomenon. SQUID has far greater sensitivity than conventional magnetic sensors, and can detect weak

magnetic fields on the order of 1/50,000,000 of terrestrial magnetism or less.

It is known that a magnetic field is generated around flowing current. (See Fig. 3-5.) As described above,

SQUID uses an ultra-sensitive magnetic sensor, so it can detect the magnetic fields generated by currents.

The currents flowing inside a semiconductor device can be observed by using the obtained magnetic field

distribution information to create images of the currents that generate that magnetic field distribution. (See

Fig. 3-6.)

磁場イメージ

Bzの磁場強度を擬似カラー化する。磁場強度Bz>0であれば青、Bz<0であれば赤と表示する。

また磁場強度によって色の濃淡が表現され、ワイヤー直上は白く表示され、この部分が電流経路となる。

ワイヤーからの磁場強度を検出

磁場強度ベクトルBz と ワイヤー位置

SQUIDセンサーにより磁場強度を取得しグラフ化する。ワイヤーの直上ではZ方向の磁場強度がゼロとなる。

Bz>0

Bz=0Bz<0

ワイヤー/ワイヤー断面

Bz(磁場強度)

X(センサー位置)

Bz=0

SQUIDセンサー

磁場の向き

ワイヤー位置（電流経路）

電流の向き

XY

Z

Fig. 3-5 Scanning SQUID - Graphical Representation of Current and Magnetic Field

SQUID sensor

Magnetic field orientation

Current direction Wire and wire cross-section

Bz (Magnetic field strength)

X (Sensor position) Wire position (current path)

Detection of magnetic field strength from a wire Graphical representation of magnetic field

Magnetic field strength vector Bz and wire position

The SQUID sensor acquires the magnetic field strength and plots it on a graph. The magnetic field strength is zero in the Z direction directly above the wire.

The magnetic field strength Bz is simulated using color. Blue is displayed when magnetic field strength Bz > 0, and red when Bz < 0. In addition, the magnetic field strength is expressed by the color density. The area directly above the wire is displayed as white, indicating that this is the current path.

3-10

＜電流像＞＜磁場像＞

電流経路

Fig. 3-6 Scanning SQUID - Magnetic Field and Current Images

In addition, magnetism passes through silicon and most other materials used in semiconductor devices and

packages, so current paths can be observed in a non-destructive manner, which is a merit for failure analysis.

However, given the nature of the principle that current paths are shown by detecting magnetic fields, failure

analysis using this equipment is valid only in the DC measurement state where the current direction is constant.

Actual failure analysis is performed by first comparing the observed current paths of good and failed products

to narrow down the location of the failure cause, and then performing detailed analysis to clarify the cause.

An example of analysis using this method is shown below. (See Fig. 3-7.)

隣接する基板配線SHORT

＜電流像＞ ＜光学観察＞

Fig. 3-7 Example of Using Scanning SQUID to Determine Foreign Matter

These results show that SQUID can also determine failure causes due to microscopic conductive foreign

matter that would be difficult to discover by X-ray observation.

<Magnetic field image> <Current image>

Current path

<Current image> <Optical observation>

Adjacent board wiring is short-circuited.

3-11

(2) TDR (Time Domain Reflectometry) Analysis

TDR is a technique that measures the transfer quality of a measured item by inputting a high-speed pulse

signal to the measured item and observing the reflected signal. This method has a long history of use to

discover broken power transmission lines and other failures. (See Fig 3-8.)

①

②

③

⑤

TDRサンプリングオシロスコープ

①TDRサンプリングモジュール

パルス発生

Sampler

⑤波形表示

Z0=50Ω

②50Ωケーブル

③ 50Ωプローブ

GND

入射波

反射波

入射波＋反射波

信号線路

④ ④基板上の線路

Fig. 3-8 General Principle of TDR

This technique is applied to semiconductor package analysis. Here, a probe is connected to the package

electrode linked to the presumed trouble location, a high-speed pulse signal is applied to the sample, and a

sampling oscilloscope is used to observe the reflected waves generated at locations with material impedance

mismatch. When the wiring line contains an open wiring connection or other open defect, the impedance

mismatch increases at the trouble location, generating a large reflected wave that appears as a difference

between the good product and failed product waveforms. The failure location can be inferred from this

reflected wave difference. This principle can also be applied to determine short-circuit locations, but currently

it is mainly used to determine open locations.

Like the previously described SQUID analysis, TDR also enables non-destructive analysis, and especially as

there are no other methods at present that can swiftly determine open locations in a non-destructive manner, it

is an extremely useful analysis method for analyzing semiconductor device packages. In particular, the boards

used in SiP and other advanced function products are arranged in multiple layers, so overlapping wiring and

other influences make it difficult to determine trouble simply using X-ray observation. Therefore, failure

locations are first reliably narrowed down using TDR, and then X-ray observation and other analysis methods

are performed.

TDR sampling oscilloscope

TDR sampling module

Incident wave

W

avef

orm

d

ispl

ay Pulse

generation

Incident wave + Reflected wave

50 Ω cable

Reflected wave Signal line

50 Ω probe

Lines on the boardGND

Z0=50 Ω

Sampler

3-12

An example of analysis using this technique is shown below. (See Fig. 3-9.)

最上層VIA形成不良

不良品基板のみ

正常品

基板の範囲

不良箇所は基板側と判断できる

＜TDR波形＞ ＜不良箇所断面のSEM写真＞

Fig. 3-9 Example of Failure Determination Using TDR

(3) Cross-section machining by a cross-section polisher (CP)

When observing a cross-section in assembly-related failure analysis, the subject observation range is wide in

many cases, so mechanical polishing was mainly used. However, mechanical polishing uses sandpaper and

abrasives, so there are limits to the finish of the machined surface, and in particular the solder, gold, copper,

aluminum and other materials often used in assembly are soft, which produces sagging on the surface. This

made it difficult for unskilled workers to realize a completely mirror finish, and led to problems such as the

inability to see microscopic cracking depending on the finishing method.

In addition, a mirror finish can easily be obtained by using a focused ion beam (FIB) such as that used in

chip cross-sectional analysis, etc. However, FIB is normally used to machine microscopic areas (on the level of

several µm), so there are various issues compared to mechanical polishing, such as 1) machining takes an

extremely long time, and 2) unsuitability for machining wide areas.

CP cross-section machining combines the convenience and swiftness of mechanical polishing with the ease

of obtaining a surface mirror finish of FIB machining.

<TDR waveform> <SEM photo of failure location cross-section>

Failed productBoard only

Normal product

Board range

The failure location can be judged to be on the board side. Via hole formation defect in the uppermost layer

3-13

A cross-section polisher (CP) can create a relatively damage-free cross-section by aligning the location to be

machined with a shielding plate and irradiating an Ar ion beam. Use of this equipment enables easy and

reliable observation of interface conditions where multiple materials are joined, such as for example the

bonding interface between gold wire and an aluminum pad, and microscopic voids and cracking. (See Fig. 3-10

and Fig. 3-11.)

Fig. 3-10 Observation Photo after Mechanical Polishing Fig. 3-11 Observation Photo after CP

3.3.7 Chip Analysis Technology

3.3.7.1 Description

As previously mentioned, products are becoming more highly integrated and incorporating more functions in

recent years. As a result, circuits are also increasing vastly in both scale (several ten to hundred million gates) and

complexity, which means that it is not an easy task to narrow down the locations of failures on a level of several

µm and clarify the causes. A variety of methods are used to narrow down chip failure locations. In addition to

photoemission analysis, thermal emission analysis, and IR-OBIRCH (Infra Red-Optical Beam Inducted

Resistance CHange), which have traditionally been used to analyze chip failures, software-based failure inference

technology and other methods have also appeared.

In addition, new analysis methods such as dynamic laser stimulation (DLS) analysis and micro probing

technology have also appeared recently, and the current situation is that multiple analysis methods are combined

to narrow down failure locations that previously could not be determined. This has also greatly increased the time

required for failure analysis. Therefore, in addition to improving the failure cause determination rate, shortening

the turn-around time (TAT) from analysis start to finish has also come to be an issue for current failure analysis

technology.

The roles, functions and other features of the main analysis methods used to determine failure locations in

various chips are described below.

<Solder Bump>

Cracking observed

<Solder Bump>

3-14

3.3.7.2 Package Decapping Technology and Stacked Chip Removal Technology

There are various package types such as packages that use mold resin and packages that use ceramics. This

section describes decapping of mold resin, which is the type most commonly used. The basic decapping method

consists of using chemicals to dissolve the resin and expose the chip surface.

Decapping methods include the following:

1) Automatically using an acid decapsulator

2) Manually by workers using tools

It is generally recognized that when 1) using an acid decapsulator, decapping skill and experience are not

required, and packages can be decapped easily even by unskilled workers. However, there are various issues such

as that work conditions during decapping cannot be viewed from the outside so the decapping progress cannot be

known, and the etching rate varies easily due to even small shifts in the chemical solution temperature, flow rate

and other conditions. Therefore, this method is not very suitable for decapping when the electrical characteristics

are to be maintained.

When analyzing a complaint with a small number of samples, if a mistake is made during the decapping work,

further analysis can become next to impossible, so the Sony Semiconductor Business Unit performs decapping

manually in most cases. Recently, resins that cannot be decapped using chemicals are increasing, so efforts are

underway to find alternate methods. However, the ideal methods have yet to be found, and the establishment of

technology in this field is an urgent issue.

In addition, SiP and other products are assembled by stacking multiple chips. In these cases, when the chip

subject to failure analysis is located in a lower level, the chips and other items stacked in the upper levels hinder

analysis and must be removed. However, it is essential to avoid damaging the sample subject to failure analysis

when removing upper-layer chips. To achieve this, the Sony Semiconductor Business Unit has established

technology that reliably removes unnecessary stacked chips and other items without mistakes by using milling

machines that enable highly accurate machining control. (See Fig. 3-12.)

3-15

Fig. 3-12 High-Performance Milling Technology

3.3.7.3 Failure Locating Technology

Mechanical probing, electron beam (EB) testing, photoemission analysis, thermal emission analysis and other

technologies are widely known as conventional technologies for determining failure locations inside chips.

Semiconductor devices are becoming more miniaturized, highly integrated, multi-functional, and higher speed in

recent years, with the result that cases where failures cannot be found by using only one of these analysis methods

are increasing. This is making it necessary to use multiple analysis methods including even newer methods to

narrow down and pinpoint failure locations. However, the combination of methods used to narrow down the

location must be determined each time from information obtained when checking the electrical characteristics, so

it is difficult to provide a specific written rule.

Methods often used for failure analysis and the latest technologies are described below, focusing on the

applications and information that can be obtained by each technology when used alone.

High-density SiP product <High-performance milling machine>

Lower-layer chip * Analysis subject

Milling

Surface finishing by chemical treatment

Decapping finished

Milling

3-16

3.3.7.3.1 Failure Inference Technology

Recent increases in LSI circuit scales and speeds are greatly increasing the difficulty of circuit electrical

analysis. This is because most parts of LSI are configured by complex digital logic circuits, and it has become

impossible to narrow down logic circuit failure locations without some clues.

This section describes failure diagnosis technology developed to address this issue. As the name implies, failure

diagnosis technology is technology used to diagnose failures, and logic circuit locations experiencing problems can

be inferred by using a failure diagnosis test environment created beforehand in the design stage. This failure

diagnosis test environment includes a database in which all failures (open wiring connections, short-circuits, etc.)

that may possibly occur in the logic circuits are registered. This is called the failure database. In addition, test

programs that inspect for failures based on this database are also created, and open wiring connections, short-

circuits and other failures that may hypothetically occur in the subject LSI can be detected by running tests using

these programs. These test results can also be compared with the failure database to estimate the logic circuit where

the failure occurred. These diagnosis results are used as a guide to perform various detailed analyses, which

dramatically increases the physical abnormality discovery rate.

3-17

Conventional failure diagnosis technology only targeted complete failures such as open wiring connections and

short-circuits. However, diagnosis technology that targets signal delay-type failures due to process miniaturization

has also recently been developed, and further expansion is expected in the future. (See Fig. 3-13.)

Fig. 3-13 General Failure Inference Flow

Logic and layout design • Registration in failure database• Chip layout design

Test program creation

Measurement

Measurement results

Comparison of results

Failure database

Test program

不良Predicted defect location

Design

Analysis

Chip layout

3-18

3.3.7.3.2 Photoemission Analysis Technology

Photoemission analysis is a well-known method of analyzing current leaks in semiconductor devices.

Current leaks generally involve extremely feeble photoemissions produced by hot electrons and the reuniting of

minority carriers.

In addition, through-currents flow due to latch-up and intermediate potential, and current also flows during

normal transistor operation, resulting in photoemissions. This method narrows down failure locations by detecting

these photoemissions using an ultra-high-sensitivity cooled CCD camera (effective sensitivity approximately

200 nm to 1000 nm) and creating images of the semiconductor device circuit location where the photoemission is

occurring. (See Fig. 3-14.)

Fig. 3-14 Photoemission Analysis Photos

Recently, MCT cameras that have improved sensitivity in the infrared wavelength range and new-type InGaAs

cameras (effective sensitivity approximately 800 nm to 2000 nm) have also appeared. These cameras have

extremely good sensitivity characteristics in the infrared range, and are highly effective at capturing

photoemissions from the rear surface of the chip. The photoemission analysis method is used to analyze highly

integrated semiconductor devices with multilayer wiring by observing infrared light transmitted through the silicon,

from the rear surface of the chip.

● Photoemission photo

● Trouble location photo

Gate oxide film

breakdown

3-19

In addition, InGaAs cameras tend to be incorrectly thought of as having higher sensitivity than general cooled

CCD cameras, but the wavelength band captured by each camera type differs, so it cannot be absolutely said that

one has higher sensitivity than the other. However, silicon is mainly used as the material surrounding the

transistors, so InGaAs cameras with extremely good sensitivity for infrared light that easily passes through silicon

are advantageous for analysis of recent semiconductor devices. (See Fig. 3-15.)

Fig. 3-15 Photoemission Sensitivity Characteristics of Each Detector

One merit of the photoemission analysis method is that analysis can be performed in either the AC or DC state.

However, current flow involves some photoemission, so thorough care must be taken to correctly interpret the

significance of photoemission captured by photoemission analysis.

All photoemission locations are not necessarily failure locations. Therefore, it is important to not rely only on

photoemission analysis, but to combine multiple analysis methods so that comprehensive judgment can be made to

narrow down failure locations.

3.3.7.3.3 IR-OBIRCH Analysis Technology

This analysis technology uses the following principle to determine short-circuits between wiring, high-resistance

areas, and other failures.

・ A near-infrared laser is irradiated to partially heat wiring to which a constant voltage is applied.

・ The change in temperature causes the wiring resistance to change, with the result that the current flowing

through the wiring also changes.

・ Failure locations are identified by using a high-sensitivity amplifier to detect this change in current.

Qua

ntum

effi

cien

cy (

%)

Wavelength (mm)

■ Comparison of sensitivity characteristics of each detector

3-20

As explained by the above principle, this method detects the current change when a failure location is irradiated

by a near-infrared laser. Therefore, unlike the previously described photoemission analysis, almost all responding

locations are detected as failure locations. However, analysis can be performed only at the DC level, so this method

is unsuitable for trouble modes where the failure cannot be reproduced without using an LSI tester or other tool.

The near-infrared laser passes through the silicon substrate, so the rear surface of chips can also easily be analyzed.

(See Fig. 3-16.)

＜ＯＢＩＲＣＨ写真①：TCR 正＞ ＜ＯＢＩＲＣＨ写真②：TCR 負＞

●異常個所写真

過電流による

ゲート破壊

Fig. 3-16 Example of OBIRCH Reaction

3.3.7.3.4 Analysis Technologies that have Begun to be Used in Recent Years

(1) Dynamic laser stimulation (DLS) analysis technology

As semiconductor devices become more miniaturized and faster, marginal failure due to time delays is

increasing. Marginal failure is an unstable mode that passes inspection depending on the operating conditions.

This makes it difficult to narrow down by existing analysis methods, and recently DLS is gathering attention as

an analysis method that can determine this failure.

The DLS analysis method focuses on the fact that most time delay failures are dependent on temperature, and

makes use of temperature changes produced by local laser irradiation. When a device is operated using an LSI

tester and the device is irradiated from the front or rear surface by an infrared laser with a wavelength of

3.3 µm, the temperature of the irradiated location changes, with the result that the pass/fail status of the device

● Trouble location photo

Gate breakdown

due to overcurrent

<OBIRCH photogram : TCR positive> <OBIRCH photogram : TCR negative>

3-21

inverts. This change in the pass/fail status is read from the LSI tester and overlaid with the laser image display

to determine the failure location.

DLS is anticipated as an effective analysis method for determining wiring defects such as voids and failures

with high temperature dependence such as abnormal transistor characteristics. On the other hand, this analysis

method also requires that devices be repeatedly operated for long periods, which makes the condition settings

extremely severe, such as temperature control that takes into account the heat generated by the device, and test

parameter settings such that the pass/fail status changes when locally irradiated by the laser. (See Fig. 3-17.)

Fig. 3-17 Example of DLS Analysis

(2) Micro probing technology (SEM prober, AMF prober)

This technology obtains the electrical characteristics by directly probing exposed semiconductor element

wiring and contacts using a microscopic probe. Mechanical probing using an optical image was formerly the

main method, but due to increased miniaturization of semiconductor elements in recent years, the micro

probing technologies described below are now the main methods used.

Probing using an SEM prober

The main probing method is changing from the conventional prober that uses an optical image to a device

called a nanoprober that performs probing with a metal probe inserted inside a scanning electron microscope

(SEM) while viewing the SEM image. The nanoprober uses a highly accurate probe that can be controlled at

the nano level by piezo elements, and a field-emission electron gun that provides high resolution, enabling

25ns 40ns

2.0V

1.1V

1.6V

25ns 40ns

2.0V

1.1V

1.6V

25C

Passing product.

*: Pass, .: Fail

DLS reaction

Contact high-

resistance failure

Failed product

Analysis point:

Conditions set

at the margin

boundary

<Shmoo> Marginal failure

3-22

direct probing of wiring and contacts in the latest processes. In addition, the nanoprober can also be used

together with electron beam absorbed current (EBAC*) technology that uses an electron beam, and is

expected to occupy an important position as an analysis method for the latest LSI. (See Fig. 3-18.)

Fig. 3-18 Probing Image

* EBAC is described hereafter.

Probing using an atomic force microscope (AFM)

Devices that scan the sample surface using a probe that is sharp at the atomic level and measure surface

shapes and electron states at the atomic level are collectively known as scanning probe microscopes (SPM),

and there are various types of SPM according to the physical quantity of the detection subject. Of the

different types, atomic force microscopes (AFM) use a microscopic flat spring called a cantilever as the

probe, and scan while contacting the sample surface. The cantilever displacement due to the sample surface

condition is detected to obtain the AFM image.

In addition to the previously described SEM prober, the Sony Semiconductor Business Unit also currently

has an AFM prober, and can obtain the electrical characteristics of elements by probing wiring and contacts

with the cantilever based on the acquired AFM image. This is used to evaluate the characteristics of analog

products in particular. (See Fig. 3-19.)

3-23

Fig. 3-19 AFM Image

(3) EBAC technology

As semiconductor device elements become more miniaturized and wiring layers increase, failures rooted in

the wiring via holes that connect each layer are also increasing. In addition, wiring via hole defects are difficult

to narrow down by existing analysis methods such as emissions analysis and IR-OBIRCH, and often cannot be

confirmed by two-dimensional observation using layer removal analysis. Therefore, effective analysis methods

are required.

EBAC is an effective analysis method for the above-mentioned wiring via hole open connection and high-

resistance failures, and uses the current absorbed by the metal wiring (= absorbed current) when a device is

irradiated by an electron beam. The equipment principle is as follows. The subject device is irradiated with an

electron beam in the condition while directly probing a specific wiring or contact location with a highly

accurate mechanical probe that uses an SEM prober. The generated absorbed current passes through the probe,

is amplified by an amplifier, and the equipotential path is displayed as the absorbed current image. When open

wiring connections or high-resistance locations are present, bright-dark contrast appears in the absorbed current

image with those locations as the borders, enabling determination of failure locations. (See Fig. 3-20.) In

principle, the detection sensitivity increases together with the resistance, but probing method and amplifier

improvements currently enable detection of even low-resistance failures around 100 Ω.

The electron beam diameter expands and spatial resolution drops as the beam injection depth increases.

Therefore, the practical EBAC analysis depth is two to three layers from the uppermost layer, and analysis of

ーー

CantileverTungsten probe

Tip diameter 100 nm or less

<Cantilever and probe> <AFM image>

3-24

lower layers requires removal of the upper layers. Alternately performing EBAC and layer removal analysis in

this manner establishes an analysis method that identifies failure locations by a combination of electrical and

physical analysis.

＜EBAC画像＞

Fig. 3-20 EBAC Image

<EBAC image>

3-25

3.3.8 Chip Physical Analysis Technology

3.3.8.1 Description

In semiconductor device failure analysis, various analysis methods are first used to narrow down the failure

location, and finally chip physical analysis technology is used to directly observe the failure location. Even when

time is taken to narrow down a failure location, if physical analysis fails, ultimately no information can be obtained,

so this is extremely important technology. However, while some cases can be clearly determined such as adherence

of foreign matter or pattern damage, there are also cases where failures are not found even when physical analysis

is performed.

Cases where failures are not be found are thought to mainly include the following:

1) The failure location was not properly narrowed down, and the failure is located in a different place.

2) The failure location was sufficiently narrowed down, but:

The trouble was overlooked during physical analysis.

An improper physical analysis method was selected (incorrect selection as to whether planar removal

analysis or cross-sectional analysis is best), so the trouble could not be observed.

The trouble is of a level that cannot be physically observed (insufficient gate oxide film withstand

voltage, crystal defect, etc.).

In these cases, the failure cause cannot be determined only by the skill of the physical analysis engineer. In

addition, how far the range can be narrowed down in the isolation stage and how to select the analysis method

(planar approach, cross-sectional approach, etc.) after isolating the range are extremely important factors, and

affect the subsequent clarification rate.

The Sony Semiconductor Business Unit works to improve the failure cause clarification rate by ensuring

constant coordination between engineers in various fields involved with failure analysis, selecting the optimum

methods for isolating the failure location, and performing thorough physical analysis.

The technologies used to perform physical analysis on individual chips are introduced below.

3.3.8.2 Interlayer Removal Technology

After failure locations have been narrowed down using various analysis methods, the wiring layers and

interlayer insulation film that form the circuits must be delaminated one layer at a time in order to physically

observe the failures using SEM or other methods. The typical processing methods for this are as follows.

(1) Wet Etching

・ Wiring layers, interlayer insulation film, and other items are etched away using chemicals.

・ Use of chemicals suited to the materials provides good selectivity, but wet etching is isotropic etching

3-26

(etching progresses in both the vertical and horizontal directions), so it is difficult to apply to microscopic

processes.

(2) Dry Etching

・ This etching method uses the physical and chemical reactions between a gas and a solid (the material to be

processed). A typical method is reactive ion etching (RIE).

・ Dry etching is anisotropic etching (etching progresses in only one direction), so microscopic processing is

possible.

(3) Surface Polishing

・ This method indiscriminately removes all kinds of materials using a surface polisher and abrasives. The

sample surface can be polished to a flat finish.

Recent semiconductor devices use a flattening process (chemical mechanical polishing: CMP) and a copper

wiring process, so interlayer insulating films are mainly delaminated using dry etching, and wiring layers are

mainly delaminated using surface polishing.

3.3.8.3 Chip Front and Rear Surface Observation Analysis

The observation equipment used to actually discover failure causes includes stereoscopic microscopes,

metallographic microscopes, infrared microscopes, electron microscopes and other equipment in accordance with

the purpose (size of observation subject, location to be observed, etc.). Stereoscopic microscopes are mainly used

to observe the exterior of packages and other items, and metallographic microscopes are mainly used to observe

chip surfaces, etc. In addition, infrared microscopes enable observation through silicon, so they are used for

observation from the rear surface of the chip without performing exfoliation, such as when protective circuit

breakdown is suspected. Theoretically, optical microscopes have submicron level resolution, but the actually

observable level is such that they are used to observe trouble on a level of several microns. However, unlike

electron microscopes, there is no need for a large-scale apparatus or preprocessing of samples, which means that

optical microscopes are easy to use. As a result, they are used for “pre-observation” before observation using an

electron microscope during failure analysis.

Stereoscopic microscopes, metallographic microscopes and infrared microscopes are called optical microscopes

because they irradiate light (visible light or infrared light) at the sample for observation. In contrast, as the name

implies, electron microscopes perform observation by irradiating electrons at the sample. The advantage of electron

microscopes is a resolution that enables observation of objects at the atomic level. However, the apparatus is large

scale, expensive (several hundred thousand to millions of dollars), and requires a special room that is not subject to

magnetic fields, vibrations and other interference. Furthermore, some samples require preprocessing or other

preparations, so some time is required before observation can be performed.

3-27

Electron microscopes are broadly classified into the following two types:

1) Scanning electron microscopes (SEM)

2) Transmission electron microscopes (TEM)

SEM used for surface observation are described below. TEM are described in a separate section.

3.3.8.3.1 Scanning Electron Microscope (SEM)

SEM performs observation by irradiating samples with an electron beam to generate reflected electrons,

secondary electrons and characteristic X-rays. Of these, the reflected electrons and secondary electrons are

collected by a detector, and that information is used to create images. The reflected electrons can be used to

obtain a composition image, and the secondary electrons can be used to obtain a surface unevenness image. (See

Fig. 3-21.) The remaining characteristic X-rays can also be used to analyze the constituent elements by EDX or

other means. SEM is mainly used to observe planar removal samples. In addition, during SEM observation, metal

objects connected to GND appear bright, and floating metal objects and insulating film appear dark (see Fig. 3-

22), so SEM can also be used for the voltage contrast (VC) analysis method.

Semiconductor devices use insulating film (SiO2, etc.) in locations other than the wiring materials. Therefore, if

the electron beam is irradiated continuously for a long time during observation, the device becomes charged,

preventing observation of clear images and causing burning and other various problems for continued analysis. For

this reason, observation should be finished quickly in the minimum time necessary, or charging should be

prevented by coating the surface of samples with carbon, gold or other conductive substances.

Fig. 3-21 Reflected Electron Image and Secondary Electron Image

<Secondary electron image of solder bump><Reflected electron image of solder bump>

3-28

Fig. 3-22 VC Method Photo

3.3.8.4 Cross-sectional Analysis Technology

Cross-section samples for chip cross-section observation are mainly prepared using FIB. In addition, TEM is

used for detailed observation of the prepared sample cross-sections. A thin slice of the area to be observed is

created using FIB, picked up by the micro-sampling method, and set in a TEM holder, and the cross-section is then

observed in detail using TEM. FIB and TEM are described below.

3.3.8.4.1 FIB

Gallium (Ga) is mainly used as the ion source, and the ions are accelerated by an electric field to create an ion

beam that irradiates the surface of the sample. The required area can be etched by bumping out the surface atoms

with the beam. The beam can be tightly focused to a diameter of several hundred nm to enable submicron level

etching. As an additional function, FIB can also be used to vapor-deposit conductive films and insulating films. In

addition to processing for cross-sectional analysis, this function can be used to repair semiconductor circuit wiring,

making it possible to create bug-corrected samples of development products in a short time. A scanning ion

microscope (SIM) can also be simultaneously used to enable easy observation of the sample cross-section during

the above-mentioned etching or vapor deposition. In the SIM image, metal wiring connected to GND appears

bright, and floating metal wiring and insulating film appear dark, so this can also be used for the VC analysis

method in the same manner as SEM observation. However, during observation the Ga ions constantly strike the

sample surface and etch the observed location, so observation must be performed as swiftly as possible.

The area enclosed by the red circle is a contact connected to the silicon substrate, so when the

product is normal the charge is discharged and this location appears as bright contrast. On the

other hand, this appears as dark contrast in a failed product, indicating that the charge could not

be discharged (= high resistance or open).

<SEM photo of failed product> <SEM photo of normal product>

3-29

3.3.8.4.2 TEM

TEM perform observation by irradiating a sample with an electron beam, collecting the electrons that pass

through the sample with a detector located on the opposite side of the sample, and converting that information into

an image. The transmitted electron beam level varies according to the components comprising the sample, so that

information can be visualized to observe the sample structure. Therefore, TEM are mainly used to observe cross-

sections. (See Fig. 3-23.)

Fig. 3-23 TEM Images

However, in order for the electrons to pass through the sample, accelerated electrons must be transmitted at an

ultra-high voltage (approximately 100 kV to 1000 kV). This means that a large apparatus (total length

approximately 2 m to 8 m) is needed to obtain the acceleration voltage, so installation locations are limited, which

is a disadvantage. Recently, even thinner samples can be machined using the above-mentioned FIB or other means,

and technology (Ar milling) to remove damaged layers and achieve a flat finish during FIB processing is also

advancing, so electrons can be transmitted at lower acceleration. In addition, scanning transmission electron

microscopes (STEM) that combine both SEM and TEM functions are also often used.

<W via hole high-resistance failure>

Locations appearing as lines indicate a

dislocated state (line-shaped defect) where the

silicon crystal array has broken

Dislocation

<GaAs Epi dislocation>

Dislocation

3-30

3.3.9 Analysis Technologies

3.3.9.1 Description

When failure analysis is performed on a semiconductor device, various trouble may be confirmed, such as

adherence of foreign matter or discoloration of metal wiring materials. Analysis technologies are used to identify

these elements and materials, clarify the processes causing the trouble, and improve these processes.

There are various types of analysis equipment, and the equipment most often used for failure analysis of

semiconductor devices is described below.

3.3.9.2 Fourier Transform Infrared Spectroscopy (FT-IR) Analysis

This analysis method is a measurement method that uses the infrared absorption of compound molecules when

substances are irradiated by infrared rays to obtain information on the atomic bonding states of organic foreign

matter. The functional groups contained in the measured object are understood from the obtained spectrum,

enabling identification of the substance. Components can be easily determined by comparison with the spectrum in

a database of known materials. In addition, measurement is performed in air, so solids, liquids and gases can be

qualitatively and quantitatively analyzed. (See Fig. 3-24.)

Fig. 3-24 Examples of FT-IR Analysis (Example of Comparison with Known Materials)

FT-IR analysis results of adhered matter

FT-IR analysis results of polyimide (wafer surface)

Foreign matter adhered

to wafer surface

3-31

When performing semiconductor device failure analysis, foreign matter is extremely small, so it is measured by

the microscopic reflection and microscopic transmission methods using microscopes. When foreign matter has

adhered to a bonding pad, land or other metal item, the microscopic reflection method that enables non-

destructive measurement is mainly used. When foreign matter has adhered to the board or other organic substance,

a sample is taken, and then the microscopic transmission method is used. Note that the minimum analysis area for

these methods is approximately 15μm × 15μm.

In addition, the attenuated total reflectance (ATR) method is also a reflection method, and this method

measures only the surface layer (approximately 1 µm) of a solid. This method contacts a crystal to the sample, so

it cannot be used with non-flat samples, and it is also limited to subjects with an analysis area of approximately

100 µm x 100 µm or more. Note that non-destructive analysis can be performed, so measurement that maintains

the trouble state is possible. In addition, the surface layer can be analyzed, so for example component data can be

obtained for both surfaces of tapes.

FT-IR analysis allows easy analysis, and extensive databases are available, making it the most effective method

especially for identification of organic compounds. However, the sensitivity is relatively low. It is said that a

content of approximately 10% or more is required for detection, and this method is not suitable for analysis of

microscopic areas of several µm or less in diameter or minute quantities such as contamination.

3.3.9.3 Energy Dispersive X-ray Spectrometer (EDX) and Wavelength Dispersive X-ray

Spectrometer (WDX) Analysis

These analysis methods can identify atomic elements by irradiating an extremely tightly focused electron beam

to the analysis subject (solid) and measuring the characteristic X-rays generated at that time with a detector. In

addition, the element quantities contained in the sample can also be measured. Elements are detected to a depth of

several microns, so these methods are unsuitable for analysis of only the uppermost surface layers. There are two

types of analysis methods as follows according to the difference in detection methods.

1) EDX (energy dispersion analysis): This analysis method amplifies all of the generated specific X-rays

using a semiconductor detector, and distributes the X-ray

wavelengths by energy.

2) WDX (wavelength dispersion analysis): This analysis method uses X-ray analysis crystals with arbitrarily

set wavelengths to sort the generated specific X-rays and analyze

the selected the X-rays.

Each method has advantages and disadvantages. EDX has a lower wavelength resolution compared to WDX, but

multiple elements can be analyzed simultaneously, so qualitative analysis can be performed in a short time. The

lower wavelength resolution means that adjacent peaks often overlap, so the data must be carefully interpreted to

avoid incorrect judgments. In addition, EDX is not suited to analysis of lighter elements.

3-32

WDX has better wavelength resolution compared to EDX, and there is little overlap between adjacent peaks,

which eliminates identification mistakes. WDX uses analysis crystals to identify a single element with a single

channel, so microscopic element amounts (approximately 10 ppm) can be analyzed, and lighter elements that

cannot be detected by EDX are also covered. On the other hand, there is the demerit that the analysis time increases.

When performing actual analysis, the above characteristics are used to roughly analyze the approximate element

configuration in a short time by EDX, and then WDX is used to confirm the identification results and perform

detailed analysis of the target elements. (See Fig. 3-25 and Fig. 3-26.)

Fig. 3-25 Example of EDX and WDX Analysis

Fig. 3-26 Example of EDX and WDX Analysis

Si TaWTa

Si

1.65 1.7 1.75 1.8 1.85keVﾌﾙｽｹｰﾙ ED 1976 ｶｳﾝﾄ ﾌﾙｽｹｰﾙ WD 152908 (100xcp

ｽﾍﾟｸﾄﾙ 1

<EDX and WDX spectrums>

N

C

O

0.2 0.3 0.4 0.5 0.6keVﾌﾙｽｹｰﾙ ED 148 ｶｳﾝﾄ ﾌﾙｽｹｰﾙ WD 45296 (100xcps） ｶ

ｽﾍﾟｸﾄﾙ 1

Yellow: EDX

Blue: WDX

Analysis point

EDX analysis reveals only the Si peak, but WDX analysis also detects other elements, confirming that WDX has better resolution sensitivity.

SEM image NiSn

C O Al

Si Ti Cu

Ni

EDX analysis can analyze multiple elements simultaneously in a short time.However, the peak resolution is poor and susceptible to noise, so accurate element distributions cannot be confirmed in some cases. (The above example uses Ni.)

<EDX mapping> <WDX mapping>

When Ni only is extracted by WDX analysis, the noise is eliminated and a proper Ni image can be obtained.

3-33

3.3.9.4 Auger Electron Spectroscopy (AES) Analysis

This analysis method can identify elements with ultra-high sensitivity by irradiating an extremely tightly

focused electron beam to the analysis subject (solid) and detecting the spectrum of the Auger electrons generated

from the uppermost surface layers (up to several nm from the surface) of the subject at that time. In addition, the

element quantities contained in the sample can also be measured.

Etching can also be performed using argon ions, which enables confirmation of the element distribution in the

depth direction (depth-profile) and also the extent of trouble range and progression of contamination, etc. (See

Fig. 3-27.)

Fig. 3-27 Example of AES Analysis

In semiconductor device failure analysis, AES is used in particular to analyze foreign matter, discoloration and

corrosion of bonding pads, metal wiring and other metal items, and thin film contamination, etc.

Reference product

<SEM image (inclined)> <Depth profile>

Discolored

Reference

C: Approx. 2%

C: Approx. 2%

Region 1-2

Region 1-1

Semiconductor chip with discolored pad

3-34

3.3.10 Confirmation of Relation between Trouble and Failure Mechanisms

When failure analysis is performed, it is important to be able to describe the trouble determined at that time as

having reliably caused the failure. This is because many cases of “trouble” are not necessarily causes of failure.

For example, even when a wiring pattern is found to have an abnormal shape, unless there is actual contact

with adjacent wiring or other functional trouble, it can be said to not look good, but it cannot be said to be the

cause of the trouble. In these cases there is always some other true cause of the trouble, and that true cause must

be reliably found to lead to proper improvement.

In this manner, when trouble is confirmed using various analysis methods, it must be possible to explain that

the trouble is consistent with the trouble symptoms and electrical characteristics. Only when this can be explained

can it be said that the failure cause has been determined. However, as a result of recent increases in

semiconductor device integration and circuit scale, trouble symptoms are also becoming more complex, and this

is making it difficult for analysis technology engineers alone to confirm whether trouble symptoms and failure

causes match.

In the Sony Semiconductor Business Unit, circuit design engineers, product technology engineers, reliability

technology engineers, process engineers and others all cooperate to reliably clarify failure mechanisms, implement

the appropriate improvements, and conduct continuous quality improvement activities.

Semiconductor Quality and Reliability Handbook

Chapter 4 Notes on the Handling of Semiconductor Devices

4-1

Chapter 4 Notes on the Handling of Semiconductor Devices

4.1 Soldering Heat Resistance ........................................................................................................................... 4-3

4.1.1 Generation Mechanism ................................................................................................................... 4-3

4.1.2 Surface Mount Device Code ........................................................................................................... 4-7

4.1.3 Notes on Package Cracking ............................................................................................................ 4-8

4.2 Notes on Handling for Electric Breakdown ................................................................................................ 4-10

4.2.1 Electrostatic (ESD) Breakdown ..................................................................................................... 4-10

4.2.1.1 Electrostatic Charge Phenomenon ................................................................................. 4-10

4.2.1.2 ESD Test Methods .......................................................................................................... 4-13

4.2.1.3 Failure Mechanisms due to ESD Breakdown ................................................................ 4-15

4.2.2 Electrostatic Countermeasures ..................................................................................................... 4-16

4.2.2.1 Basic Electrostatic Discharge Control Concepts ............................................................ 4-17

4.2.2.2 Approach toward Process Control References .............................................................. 4-18

4.2.2.3 Basic Electrostatic Discharge Controls23), 24) ................................................................... 4-20

4.2.3 EMC (Electromagnetic Compatibility) ........................................................................................... 4-28

4.2.4 Strong Electric and Magnetic Fields .............................................................................................. 4-28

4.2.5 Overvoltage Breakdown (EOS Breakdown) ................................................................................. 4-28

4.2.6 Handling of High-frequency Devices ............................................................................................. 4-29

4.2.7 Latch-up .......................................................................................................................................... 4-29

4.2.8 Thermal Runaway .......................................................................................................................... 4-31

4.3 Notes on Handling for Mechanical Breakdown ......................................................................................... 4-32

4.3.1 Forming and Cutting External Leads ............................................................................................ 4-32

4.3.2 Mounting Devices on Printed Boards ............................................................................................ 4-32

4.3.3 Washing Methods .......................................................................................................................... 4-33

4.3.4 Attaching Radiation Fins ................................................................................................................ 4-34

4.4 Notes on Handling to Prevent Thermal Breakdown .................................................................................. 4-35

4.4.1 Soldering ......................................................................................................................................... 4-35

4.4.2 Notes on Mounting Surface Mount Devices (SMD) ..................................................................... 4-35

4-2

4.5 Notes on Product Specifications, Packing, Transport and Storage .......................................................... 4-37

4.5.1 Product Specifications .................................................................................................................... 4-37

4.5.1.1 Notes on the Use of Semiconductor Devices ................................................................ 4-37

4.5.1.2 Maximum Ratings (Absolute Maximum Ratings) .......................................................... 4-37

4.5.1.3 Operation Assurance Range .................................................................................... 4-39

4.5.1.4 Derating ............................................................................................................................ 4-39

4.5.2 Notes on Packing, Transport and Storage ................................................................................... 4-40

4.5.2.1 Notes on Packing ............................................................................................................. 4-40

4.5.2.2 Notes on Transport .......................................................................................................... 4-41

4.5.2.3 Notes on Storage ............................................................................................................. 4-42

4-3

4.1 Soldering Heat Resistance

As electronic equipment products become more compact and multi-function, Surface Mount Devices (SMD)

have become widely used in recent years, and the trend is towards greater numbers of pins and larger packages.

One kind of trouble that must be kept in mind when handling SMD is package cracking that can occur when

soldering is performed using a reflow oven or other method that heats the entire package.

To prevent this problem, the Sony Semiconductor Business Unit improves package materials and structures,

ranks each product according to the package cracking resistance (hereafter “SMD code”), and requests that

customers perform solder mounting based on these ranks.

This section describes the package cracking mechanism, SMD code, and other notes to prevent package cracking

in the mounting process. Notes on soldering for all semiconductor products are described in section 4.4.

4.1.1 Generation Mechanism

(1) Package cracking phenomena

Package cracking during mounting occurs through the following process. (See Fig. 4-1.)

Moisture-proof

packing

Reflow Water vapor pressure rises

Concentration of stress

Moisture absorption

Bou

nda

ry m

oist

ure

den

sity

x

Moisture-proof packing opened

Diffusion Adsorption

Fick’s Law Henry’s Law

Exposure to shelf atmosphere (Time elapsed)

0

Fig. 4-1 Package Cracking Phenomena

When the moisture-proof packing is opened and an SMD is exposed to ambient conditions during

storage or the mounting process, the moisture in the air adsorbs to the surface of the resin that forms the

package and diffuses to the inside of the package. This diffusion progresses over time, and the moisture

4-4

reaches the boundary between the chip or die pad and the resin inside the package.

When soldering is performed by reflow or another method that heats the entire package in the condition

in above, the entire SMD is exposed to high temperature, causing moisture present at the boundary to

gasify and expand. As a result, the water vapor pressure inside the minute gaps at the boundary rises

rapidly, causing stress to concentrate at the edges of the chip or die pad. When this stress exceeds the

thermal strength of the resin, package cracking occurs.

Trouble that occurs due to cracking differs according to the cracking location.

When cracking occurs on the chip side, the wires that provide electrical conductivity between the chip

and the leads may be severed, or the boundary between the resin and the chip may delaminate, causing

the humidity resistance to deteriorate. When cracking occurs on the die pad side, the package expands

during solder melting, which may result in a soldering defect.

(2) Factors causing package cracking: Boundary moisture density

As described above, moisture absorption in the package is a major factor causing package cracking. However,

in precise terms it is not the absolute sum total of the moisture absorbed that is the problem, but the moisture

density at the boundary between the chip or die pad and the resin inside the package that is the factor causing

package cracking.

The course of moisture absorption and derivation of the boundary moisture density are described below. (See

Fig. 4-1.)

Generally, when solid materials are exposed to air, water molecules are adsorbed to the surface mainly by the

van der Waals interaction. The organic materials used in SMD packages are thought to have stronger affinity to

water molecules compared to inorganic materials.

The moisture density Qs adsorbed to the package surface is expressed by the following equation in

accordance with Henry’s Law as a function of the inherent solubility coefficient S of the materials and the

atmospheric water pressure Pa.

Qs=S Pa ・・・・Equation 4.1.1

Here, the solubility coefficient S can be expressed by the following equation as a function of the activation

energy Es and temperature T.

S=So exp(Es/kT) ・・・・Equation 4.1.2

k: Boltzmann constant, So: Constant

The moisture adsorbed to the package moves to the inside of the package by the diffusion phenomenon; that

is to say, until the density gradient disappears. At this time, moisture is constantly supplied from the air to the

4-5

package surface and the moisture density determined by Equation 4.1.1 is maintained. The diffusion

phenomenon follows Fickian diffusion within the environmental temperature range of the SMD storage and

mounting processes, and can be expressed by the following equation as a function of the diffusion coefficient D,

position coordinate x, and time t.

2

2 ),(),(

x

txQD

t

txQ

・・・・Equation 4.1.3

Here, the diffusion coefficient D can be expressed by the following equation as a function of the activation

energy Ed and temperature T.

D=Do exp(Ed/kT) ・・・・Equation 4.1.4

k: Boltzmann constant, Do: Constant

This boundary moisture density, which is a factor causing package cracking, can be obtained from Equations

4.1.1 to 4.1.4 above. The Sony Semiconductor Business Unit evaluates resistance to package cracking with the

focus on this boundary moisture density, and determines the SMD code described hereafter for each product.

(3) Factors causing package cracking: Package exposure temperature during soldering

As described above, package cracking occurs when moisture that has reached a boundary gasifies and

expands rapidly during soldering, causing the internal stress to exceed the thermal strength of the resin that

comprises the package. In addition, the probability of occurrence rises together with the package exposure

temperature. This is due to the temperature dependence of the water vapor pressure generated inside the gaps at

the package boundaries and the strength of the resin that comprises the package.

For example, comparing exposure temperatures of 220°C and 260°C, the temperature dependence of the

saturation water vapor pressure shows that at 260°C, the water vapor pressure rises by approximately twice as

much and the resin strength falls to approximately half compared to 220°C. (See Fig. 4-2 and Fig. 4-3.)

4-6

1

10

0.0016 0.0018 0.002 0.0022

5

y = 27846e-4631.7x

0

5

10

50 100 150 200 250 300

1/T (1/K)

飽和

水蒸

気気

圧(M

Pa

)

曲げ

強度

(kg

f/mm

2 )

温度 (C)

1

10

0.0016 0.0018 0.002 0.0022

5

y = 27846e-4631.7x

y = 27846e-4631.7x

0

5

10

50 100 150 200 250 300

1/T (1/K)

飽和

水蒸

気気

圧(M

Pa

)

曲げ

強度

(kg

f/mm

2 )

温度 (C) Fig. 4-2 Temperature Dependence of Fig. 4-3 Temperature Dependence of

Saturation Water Vapor Pressure Mold Resin Bending Strength

(4) Factors causing package cracking: Package structure and materials

Even when SMD are exposed to the same ambient conditions for the same time before soldering, the

boundary moisture density that is an occurrence factor exhibits different values due to differences in the

thickness, solubility coefficient and diffusion coefficient of the resin over the semiconductor chip or under the

die pad that acts as the diffusion path.

In addition, the stress σ generated inside the solder is expressed by the following equation based on a fixed-

edge uniform load model. Here, a is the short edge of the chip or die pad, k is a coefficient determined by the

ratio between the short edge a and the long edge b, h is the thickness of the resin over the chip or under the die

pad, and P is the water vapor pressure inside the package. (See Fig. 4-4.)

σ=6k (a/h)2P ・・・・Equation 4.1.5

This means that even when the boundary moisture density and the solder exposure temperature that is

another occurrence factor are the same, the cracking occurrence rate differs due to differences in the

semiconductor chip or die pad size.

Sat

urat

ion

wat

er

vapo

r pr

essu

re (

MP

a)

Ben

ding

str

engt

h (

kgf/m

m2 )

Temperature (C)

Fig. 4-4 Fixed Edge Uniform Load Model

b

a

P

h

5

220℃ 260℃

4-7

4.1.2 Surface Mount Device Code

The Sony Semiconductor Business Unit expresses the solder heat resistance for SMD reflow and solder dipping

using a four to eight character SMD code. This code indicates the allowable shelf time and allowable number of

soldering times for SMD exposed to ambient conditions of 30°C and 70%RH after the moisture-proof packing is

opened until soldering.

There are 20 different SMD codes as shown in Table 4-1.

Note 1) Reflow conditions: Temperature profile shown in Fig. 4-5.

Table 4-1 SMD Code

No. SMD code No. SMD code

1 R390F390 11 R304F390

2 R390F308 12 R304F308

3 R390F304 13 R304F304

4 R390F302 14 R304F302

5 R390 15 R304

6 R308F390 16 R302F390

7 R308F308 17 R302F308

8 R308F304 18 R302F304

9 R308F302 19 R302F302

10 R308 20 R302

R 3 90 F 3 90

Allowable shelf days after moisture-proof packing is opened until solder dipping

Allowable solder dipping times

Solder dipping symbol * Omitted when solder dipping is not allowed

Allowable shelf days after moisture-proof packing is opened until reflow

Allowable reflow times

Reflow symbol

4-8

Fig. 4-5 Recommended Reflow Temperature Profile

4.1.3 Notes on Package Cracking

(1) When mounting products, customers are requested to not deviate from the allowable time after opening the

moisture-proof packing and allowable number of soldering times specified by the SMD code corresponding to

the product, and the SMD exposure atmosphere after opening the moisture-proof packing and soldering

temperature conditions that are prerequisites for the SMD code.

(2) When the allowable time after opening the moisture-proof packing is exceeded, products can be used by

baking to remove moisture. However, the baking conditions that reduce the boundary moisture density to an

appropriate value vary according to the package, so consult your Sony sales representative beforehand when

baking is necessary.

(3) When the moisture-proof packing has been opened but products were not mounted, store under conditions of

30°C and 30%RH or less.

(4) Moisture enters the inside of the moisture-proof packing even through tiny holes, with the result that package

cracking may occur even under the conditions recommended by the SMD code. Therefore, sufficient care

must be given to the handling of SMD packing.

(5) Minute amounts of moisture permeate the laminate bags of even unopened moisture-proof packing, so long-

term storage should be avoided.

1 to 4C/s1 to 4C/s

3 to 6C/s

4-9

<References>

1) Kansai Electronic Industry Development Center, Reliability Subcommittee, “Survey Report of Documents

Concerning the Pressure Cooker Test” (1983)

2) Nanjo, “Materials and Moisture Handbook,” Society of Polymer Science, Polymer and Moisture Absorption

Committee (1968)

3) Saito and Hirai: Practices in Mechanics of Materials

4-10

4.2 Notes on Handling for Electric Breakdown

Semiconductor device transistor sizes are becoming smaller due to decreasing gate oxide film thickness and

miniaturization of wiring. As a result, lower resistance to electrostatic discharge (ESD), overvoltage and

overcurrent (electric over stress: EOS), noise and other electrical stress is becoming a serious problem. Even slight

voltage fluctuations and noise that were not a problem thus far are becoming increasingly likely to cause device

misoperation or breakdown.

This section describes countermeasures to prevent semiconductor devices from misoperating or breaking down

due to electrical stress.

4.2.1 Electrostatic (ESD) Breakdown

4.2.1.1 Electrostatic Charge Phenomenon

Electrostatic charge refers to when an electric charge migrates due to contact between two objects, and then

remains on the objects when they are separated, causing them to become electrically charged. When there is a

surplus of electrons in an object it is negatively charged; when there is a shortage of electrons the object is

positively charged.

In terms of general electrical properties, objects can be classified as items that easily acquire electrons and items

that easily give electrons.

Table 4-2 shows the Faraday triboelectric series. Here, when a higher item in the triboelectric series contacts or

rubs against a lower item, the higher item gives electrons and becomes positively charged, while the lower item

acquires electrons and becomes negatively charged.

Table 4-3 shows an example of typical static electricity charge voltages.

4-11

Table 4-2 Frictional Triboelectric Series Table1)

The two main mechanisms for generating static electricity that causes the electrostatic discharge phenomenon

within processes where semiconductor devices are handled are as follows.

(1) Charging due to contact and separation (rubbing) between objects

When two objects contact each other, a charge migrates between the objects at the contacting surfaces.

(Fig. 4-6(a))

If the objects are separated in this condition, the surface of each object retains this biased charge condition,

and becomes electrostatically charged. (Fig. 4-6(b)-(c)) Triboelectric charging is generally held to be the cause

of static electricity, and can be thought of as the condition where this contact and separation occur repeatedly.

Fig. 4-6 Mechanism for Generating Charges through the Contact and Separation of Objects

Positive (+)

Negative(-)

Acetate Glass Nylon Wool Silk Aluminum Polyester Paper Cotton Steel Nickel, copper, silver Zinc Rubber Acrylic Polyurethane foam PVC (vinyl) Teflon

Static electricity source

Walking on carpet

Walking on vinyl tile

Person working at a general workbench

Card case

Plastic bag taken from a workbench

Urethane foam cushion chair

Charge voltage

Relative humidity

10% to 20%

Relative humidity

65% to 90%

35,000V

12,000V

6,000V

7,000V

20,000V

18,000V

1,500V

250V

100V

600V

1,200V

1,500V

Table 4-3 Examples of Static Electricity Generation2)

(a) Normal condition (b) Charge migration due to contact between objects

(c) Separation of objects (charged)

Negatively (-) charged

Positively (+) charged

4-12

(2) Charges due to induction from charged objects

When a charged object approaches an insulated conductor, the effect of the electric field from the charged

object produces a charge bias due to electrostatic induction inside the conductor. In this condition, the

conductor is in an inductively charged state. (Fig. 4-7(a)) When inductive charging occurs and the charge

becomes uneven, if a part of the conductor contacts a ground (GND) or another conductor, a charge having the

same polarity as the charged object that approached moves from the conductor to the GND or the other

conductor, and the ESD phenomenon occurs. (Fig. 4-7(b)) Furthermore, if the conductor is then separated from

the GND and the charged object is moved away from the conductor, the charge in the conductor that was

attracted to the charged object becomes free and exists in surplus inside the conductor, which becomes charged

with that polarity. (Fig. 4-7(c)) If a part of the conductor then contacts the ground or another conductor again in

this condition, the charge is discharged. (Fig. 4-7(d))

Fig. 4-7 Generation of an Inductive Charge Due to the Approach of a Charged Object and the Double-Discharge Phenomenon

When this charge phenomenon is applied to semiconductor devices, the chip and lead frame are treated as

conductors. Simply bringing a charged object close to an insulated semiconductor device generates an inductive

charge in the chip, and there is the risk of ESD occurring if the pins are contacted with metal. Also, if the surface

of a plastic package becomes charged by rubbing or other contact, the surface may act as a charged object to

generate an inductive charge in the chip, thus causing ESD in the same manner by inductive charging.

Electrostatic induction occurs A charged object

approaches Discharge due to contact with metal

(a) Inductive polarization of a conductor caused by the approach of a charged object

(b) Discharge due to contact with a grounded conductor (Discharge of positive (+) charge)

(d) Re-discharge of the remaining charge due to contact with a grounded conductor (Discharge of negative (-) charge)

(c) Removal of the charged object and charging due to the remaining charge

4-13

This type of inductive charging does not occur only in semiconductor devices. The same type of inductive

charge is produced in ungrounded metal objects, tweezers or other tools held by an insulated glove or finger sacks,

PCB wiring patterns, FPC metal wiring and other objects. These items may cause ESD with respect to

semiconductor devices in the mounting process.

In this manner, eliminating charged objects that cause inductive charges in devices is also an important

countermeasure within processes in which semiconductor devices are handled.

4.2.1.2 ESD Test Methods

Electrostatic discharge phenomena produced by handling semiconductor devices are classified into a number of

models according to the charged object and the discharge mode. The testing methods used to evaluate the

resistance of semiconductor devices to electrostatic discharge were devised based on these electrostatic discharge

models.

(1) Human Body Model (HBM) 3),4),5)

The human body model (HBM) is a testing method that models the discharge of electrostatic charge

accumulated in a charged human body to a semiconductor device. This testing method uses the capacitance of

the human body (=100pF) and the contact resistance between the human body and the device (=1500Ω). This

testing method has been used for quite some time in the U.S. MIL standard (MIL-STD-883D method3015.7),

and is thus widely used as a standard test method in Japan and overseas.

(2) Machine Model (MM) 3),6)

The machine model ESD testing method originated as a human body discharge model based on the worst

values for human body capacitance and discharge resistance (200 pF/0 Ω). This testing method was used by

domestic semiconductor device manufacturers mainly as a means of discovering circuits that are susceptible to

electrostatic breakdown during the device design verification. However, it is known that human body discharge

can be verified using the human body model (HBM), and that the machine model (MM) simulates excessive

discharge phenomena that almost never occur in an actual process due to excessive inductance component

(750 nH) of the discharge path. For these reasons, the MM has been deleted from the above standard.

(3) Charged Device Model (CDM) 7)～11)

The charged device model (CDM) is a testing method that models the phenomenon where the semiconductor

device itself carries a charge and the charge inducted to the device from a charged object near the device is

discharged. This model is characteristic in that it reproduces the discharge mechanism in the form closest to the

discharge phenomenon occurring in the field, so correlations with the ESD failure modes occurring in

processes have also been widely confirmed.

The charged device model testing methods are shown in Fig. 4-8. The charged device model connects a high-

4-14

voltage source to the device side and accumulates a charge in the parasitic capacitance formed between a

grounded electrode plate and the device. This accumulated charge is then discharged to the GND via a metal

discharge rod by closing SW1 that is connected to a device pin. Charging and discharging are repeated for each

pin of the test device, and the device withstand voltage is evaluated by ultimately applying stress to all pins.

Fig. 4-8 CDM/FICDM Testing Methods

Metal discharge rod

Grounded metal plate

Metal discharge rod

(a) CDM (Relay discharge) (b) FICDM (Aerial discharge)

SW1H.V.

H.V.

4-15

(4) ESD test standards

ESD testing methods adopted in the current standards are shown in Table 4-4. The HBM and CDM testing

models are each used as standards, and the human body model (HBM) tests performed in Japan and overseas

are virtually the same. In the Japanese domestic JEITA standard, the charged device model (CDM) employs a

testing method that performs charging and discharging by contacting a discharge electrode directly to a device

pin. In contrast, the CDM in the U.S. JEDEC standard employs the Field Induce CDM (FICDM) testing

method that charges the device by inductive charging from an electrode plate to which high voltage is applied,

and performs discharging by contacting a discharge electrode.

Table 4-4 Semiconductor Device ESD Testing Methods

ESD model Test circuit Test standards

Human Body Model

(HBM)

DUTH.V. DUTH.V.

R=1500Ω

C=100pF

C=100Pf

R=1500Ω

Number of applications: 1

JEITA

EIAJ ED-4701/304

(2001)

JEDEC

JESD22-A114F

(2007)

Charged Device

Model

(CDM)

HVHV

放電電極

SW1

R2 R1

接地金属板

JEITA

EIAJ ED-4701/305A

(2004)

JEDEC

JESD22-C101E

(2008)

4.2.1.3 Failure Mechanisms due to ESD Breakdown

The main ESD breakdown mechanisms for semiconductor devices include the following two phenomena.

(1) Thermal breakdown (junction breakdown, melted wiring)

(2) Insulating film breakdown (gate oxide breakdown, interlayer insulator breakdown)

Metal discharge rod

Grounded metal plate

HV

4-16

(1) Thermal breakdown

Thermal breakdown phenomena mainly include junction breakdown and melted Metal/Poly wiring. Junction

breakdown can occur at relatively low energy, but melted wiring generally requires high energy, so it is thought

to occur more from electric over stress (EOS) phenomena such as surge, soldering iron leaks, etc. than due to

ESD.

The junction breakdown phenomenon occurs when an excessive current flowing through the junction causes

the temperature to rise locally in the junction and exceed the melting point of silicon (1415C). The Wunsch &

Bell model12) that uses a thermal diffusion equation is most generally used as a model to describe this junction

breakdown. This model determines the junction breakdown phenomenon from the applied pulse width and the

power density applied to the element.

Thermal breakdown requires relatively high energy, so within the process it is caused by discharge from a

charged worker (human body) or discharge of the charge accumulated in a large-capacity capacitor or other

mounted component. In the ESD breakdown test, this can be observed as the main breakdown mode of the

human body model (HBM).

(2) Insulating film breakdown

Insulating film breakdown is a failure mechanism where the gate oxide film or the interlayer insulator shorts.

Insulating film breakdown occurs often in devices with thin gate oxide such as MOS devices, and is the most

common ESD breakdown failure mechanism seen within the process. The energy required for breakdown is

small, so this phenomenon occurs at lower charge levels than thermal breakdown, and ESD breakdown within a

process is thought to occur more due to insulating film breakdown than thermal breakdown.

This insulating film breakdown is known as the main breakdown mechanism of the charged device model

(CDM).

4.2.2 Electrostatic Countermeasures

The gate oxide film thickness of MOS transistors manufactured using the latest processes has already been

reduced to several nm or less, and the endurance voltage of these oxide films is only several voltage.

Semiconductor devices employ countermeasures such as circuits to protect against the entry of external static

electricity for each input/output pin to prevent static electricity from being applied to the internal transistors.

However, it becomes extremely difficult to protect the internal transistors against external static electricity in

excess of several 100 V using only protection circuits.

Furthermore, as device operating speeds increase, the effect of the parasitic impedance of protection circuits on

operating speed cannot be ignored, and an increasing number of pins requires the reduction of the size of these

protection circuits or elimination of the circuits themselves. It is thought that in the latest process the electrostatic

endurance voltage of the devices has already dropped due to device miniaturization and increases in operating

4-17

speed.

Against this background, countermeasures for preventing electrostatic breakdown become even more important

in processes where semiconductor devices are handled. General knowledge required to protect semiconductor

devices from electrostatic breakdown during handling, methods for controlling static electricity within processes,

and countermeasures against electrostatic breakdown are described below.

4.2.2.1 Basic Electrostatic Discharge Control Concepts

Basic concepts for electrostatic discharge controls in processes where semiconductor devices are handled are as

follows.

(1) Designing processes and facilities that do not generate static electricity

During process design or when investigating the introduction of manufacturing facilities, processes with

effective electrostatic discharge controls can be constructed by introducing electrostatic discharge control

facilities (grounds, floors, environment, etc.) and building countermeasures for preventing the generation of

static electricity by friction or contact into the equipment specifications.

(2) Not bringing items that are easily charged by static electricity into processes

Electrostatic breakdown due to triboelectric charging or inductive charging can be prevented by not bringing

packing materials, paper, fixtures, office supplies or other insulated objects that easily generate static electricity

into processes except when absolutely necessary.

(3) Quickly leaking static electricity that does occur to prevent electrostatic discharge

Chances for electrostatic discharge (ESD) to semiconductor devices can be reduced by quickly leaking

generated static electricity using various methods such as grounding equipment and jigs, controlling resistance

values on floors and work surfaces, and neutralizing charges with an ionizer. In addition, charges can be

gradually leaked without causing sudden discharge and electrostatic breakdown can be prevented by changing

metal parts that contact devices to materials with appropriate resistance values.

(4) Periodically checking electrostatic discharge control conditions and maintaining

countermeasure effects

After implementing electrostatic countermeasures, the effects of these countermeasures cannot be maintained

unless periodic checks are made and control is performed to ensure that the effects are reliably maintained.

(5) Instilling an awareness of the need for electrostatic discharge controls in workers and

process controllers

Electrostatic discharge controls require knowledge and understanding of static electricity on the part of

employees and process controllers. Electrostatic protective items can be even more effective at preventing

4-18

electrostatic breakdown depending on the awareness of the person using them.

Electrostatic discharge controls are not a problem that can be solved simply by introducing electrostatic

protective items. Ensuring thorough and consistent countermeasures and spreading general knowledge of

electrostatic discharge control concepts can make process managers and workers aware of the risk of

electrostatic breakdown, and are effective means of reducing electrostatic breakdown problems within

processes.

4.2.2.2 Approach toward Process Control References

In order to control electrostatic charge levels within processes, it is necessary to determine the charge level to

use as the control criteria. This control reference is set based on the ESD withstand voltage of the devices handled

in that process. However, what is important in determining a control reference is which testing method should be

used to obtain the ESD withstand voltage employed as the process control reference guideline among the

electrostatic breakdown testing models for devices described in item 4.2.1.2. Even if control criteria are set based

on ESD phenomena that do not occur in the process, actual electrostatic breakdown cannot be effectively prevented.

Fig. 4-9 shows the relationship between charged objects present in processes and electrostatic capacity (earth

capacity). Objects causing ESD within processes generally have different electrostatic capacities. For example, the

electrostatic capacity of the human body is usually said to be approximately 80 to 200 pF13)~16) , which is

equivalent to the capacitance used by the human body model (HBM). In contrast to this, most items other than

workers that may produce ESD with devices such as tweezers and metal parts on chip mounters such as device

adsorption jigs and positioning stages have electrostatic capacity of fF to 10 and more pF.16) In addition, the

electrostatic capacity of most semiconductor devices is also mostly within the range of several pF to several 10 pF.

(Table 4-5) When the electrostatic capacitance of charged objects becomes smaller in this manner, the accumulated

electrostatic energy is lower even when charged to the same voltage, so semiconductor devices are less likely to

experience electrostatic breakdown.

4-19

Fig. 4-9 Relationship between Charged Objects in Processes and Testing Methods from the Viewpoint of Electrostatic Capacity

Table 4-5 Device Package Electrostatic Capacity Measurement Results

(on the GND board during CDM test)

Package Electrostatic

capacity (pF) Package

Electrostatic

capacity (pF)

SSOP-20pin 2.0 LQFP-140pin 13.2

SOP-20pin 3.7 BGA-119pin 9.5

LQFP-64pin 7.4 BGA-256pin 10.6

QFP-100pin 5.6

Failures produced by the discharge of static electricity accumulated in small electrostatic capacity clearly differ

in most cases from failure modes when static electricity is discharged from the comparatively large capacitances

(100, 200 pF) such as HBM or MM tests.17)~20) As seen in Fig. 4-9, the charged device model (CDM) testing

method that uses the parasitic capacitance is thought to be the most suitable testing method for reproducing

phenomena where static electricity is discharged from small capacitance charged objects within processes.18), 20)~22)

4-20

In this manner, an appropriate charge level control value for charged objects within processes should be set

according to the type of charged object. Thus, more realistic charge level control criteria can be set by using ESD

withstand voltage data from the human body model (HBM) as a reference for workers (human bodies), and ESD

withstand voltage data from the charged device model as a reference for devices and jigs.

4.2.2.3 Basic Electrostatic Discharge Controls23), 24)

(1) Countermeasures for the human body

Workers who directly handle semiconductor devices or boards on which devices have been mounted should

wear both wrist straps and ESD protective shoes. The charge potential of the human body varies greatly

according to worker movements, and the charge potential may rise sharply due to a motion such as standing up

from a chair. (Fig. 4-10) Always use a wrist strap with a cord. If the wrist strap is not used in the condition with

the body and the ground constantly connected by the cord, the human body cannot be maintained at a stable

low potential. Note that the cord may be severed if a sudden load is placed on the cord during the work.

Be sure to use the wrist strap adhered closely to bare skin. If the wrist strap is worn over clothing, the

necessary resistance value between the human body and the ground cannot be secured.

If the soles of ESD protective shoes become dirty, the contact resistance between the human body and the

floor increases and the prescribed leak resistance may not be obtained. Also, if a worker sitting in a chair places

both feet on a footrest or other pedestal, conductivity between the floor and the human body is not obtained and

the constantly required electrostatic leakage effects cannot necessarily be maintained. Therefore, safety can be

most effectively assured by having workers who directly handle devices wear both wrist straps and ESD

protective shoes.

Gloves and finger sacks with ESD protection should be used. In particular, the finger sacks used when

handling devices with bare hands must be conductive or electrostatic diffusive. If the surface of finger sacks

becomes charged, an electrostatic charge is induced in the device when a device is held, and the risk of the

charged device model (CDM) discharge phenomenon occurring increases. (Figs. 4-11 and 4-12)

4-21

Connection cord

Metal plateProbe

Supported byan insulated

object

Electrostatic voltmeter(with external output jack)

Recorder or oscilloscope

(a) Measurement method

Charge

 potential

of the human

 body

500V

0V

‐500V

Standing upfrom a chair

Stationary

Light movement

Standing ina grounded state

Seated ina grounded state

Standing upfrom a chair

Human body grounded

Sitting in the chair

Sitting in the chair

(b) Measurement results

Sitting ina charged chair

Fig. 4-10 Changes in the Charge Potential of the Human Body

ESD protective floor ESD protective shoes

Gloves andfinger sacks

ESD protectiveclothing

Wrist strap

Dedicated earth bonding pointCord

Wrist strap

Fig. 4-11 Human Body (Worker) Countermeasures Fig. 4-12 Wrist Strap Usage

4-22

(2) Work surface

Work surfaces should be covered with ESD protective sheets (made from conductive materials or materials

having electrostatic dissipative characteristics) or work tables should be made from materials having these

same characteristics. Also, work surfaces must be grounded. (Fig. 4-13) Insulated objects that easily generate

static electricity should not be placed on work surfaces. Fixtures and jigs required for work should be made

from conductive or electrostatic diffusive materials, and when that is not possible, ionizers should be used. The

use of insulated objects for items that may contact or approach devices should be avoided as much as possible,

especially during work. Also avoid working with insulated sheets or plates on worktables. The seat and

backrest surfaces of chairs that workers sit in should have ESD protective covers, or ESD protective chairs

should be used. (Fig. 4-14) Static electricity with an extremely high potential may be generated momentarily

when standing up from a chair. (Fig. 4-10)

ESDprotective sheet Earthed line

Conductive covers

Ground cordMetal chain or

conductive rubberESD protective sheetor

ESD protective floor

Conductive sheetor

conductive floor

Fig. 4-13 Work Surface Fig. 4-14 Chair

(3) Floor

Floors in the work area should be ESD protective floors or covered with ESD protective sheets. When the

entire work area floor cannot be covered, at the very least lay ESD protective sheets in the work area where

workers wearing ESD protective shoes handle devices or boards on which devices have been mounted. When

laying ESD protective sheets, be sure to ground all of the sheets. (Fig. 4-13)

(4) Equipment and facilities

The frames of equipment such as mounters, solder baths and measuring instruments, and facilities for

conveying must be grounded. Metal parts that are isolated from the grounded frame by insulating material and

that may contact devices should be grounded individually. Insulating material parts that may contact or

approach devices should be changed to materials with electrostatic dissipative characteristics, or charges should

be eliminated using ionizers.

4-23

Both the body and tips of electric screwdrivers, soldering irons and other tools should be grounded.

Otherwise, electric over stress (EOS) breakdown may occur if there is an AC voltage leak.

(5) Environment

It is generally considered difficult for static electricity to occur at higher humidity (moisture density in the

air). However, what actually happens is that static electricity may be generated but the proportion of the

generated charge that leaks due to moisture adhered to the surface increases, so charging appears difficult to

occur as a result. In process humidity control it is important to maintain a humidity environment that makes it

difficult for static electricity to occur. In actual processes, however, heat generation by equipment and other

factors create spaces with locally high temperatures (low relative humidity).

Furthermore, boards that generate heat when the power is on, components packed in plastic trays and bags,

and products stored for long periods inside dry warehouses may not necessarily always be in a condition that

inhibits the generation of static electricity. Therefore, it is extremely dangerous to think that static electricity

can be uniformly inhibited by increasing the humidity, or that other electrostatic discharge control can be

omitted. Humidity environment control must be understood only as an auxiliary electrostatic control.

(6) Storage and transport

Semiconductor devices should be stored in the packing format for shipment. Correctly storing devices in the

same ESD protective packing materials as when shipped reduces the risk of electrostatic breakdown even when

devices are handled during storage.

In addition, boards on which devices are mounted must be stored in containers or on storage shelves made

from conductive or electrostatic dissipative material. (Figs. 4-15 and 4-16) At this time, the use of insulated

partitions or storage in insulated bags should be avoided. Mounting boards are made from insulating materials,

so boards may become charged by vibration or rubbing during storage or transport. In addition, if they are

placed near charged objects, an inductive charge may be generated in the board wiring pattern, and may

discharge from the connectors during measurement or assembly and damage the device.

Conductive orelectrostaticdissipativematerial

Conductive plastic container

Earthed location

Fig. 4-15 Board Storage Container

4-24

ESD protective sheetEarth

Fig. 4-16 Storage Shelf

(7) Mounted or assembled components other than devices

Many components other than semiconductor devices that are mounted on boards become electrostatically

charged during board mounting. Mounted components such as capacitors, filters, LCD panels and flexible

connectors that consist of metal and insulating material and have capacitances capable of accumulating static

electricity may cause ESD during board mounting and damage devices.

Parts boxes used to store these components and delivery packing must have electrostatic countermeasures.

(Fig. 4-17) Workers should be aware that some mounted components other than devices can also carry

electrostatic charges, and countermeasures must be taken to prevent these components from causing ESD

during board mounting.

Conductive sheet Conductive or electrostaticdissipative material

Earth

Fig. 4-17 Parts Box

(8) Module and set components

Optical pickups, camera modules and other module products that include semiconductor devices may

experience ESD breakdown when handled in module units. Even after semiconductor devices are mounted in a

module, when device pins are directly exposed to the outside via connectors, the module should be handled in

the same manner as the device unit.

Within the set assembly process, metal chassis, cables and other components that consist of metal and

4-25

insulating materials, and already assembled components such as display LCD panels, optical disc drives,

optical pickups and various modules may carry charges that are discharged to mounting boards via connectors

during set assembly, resulting in damage to semiconductor devices. Thorough care should also be taken for

charges carried by set components during set assembly.

(9) Eliminating charges using an ionizer

Ionizers are charge elimination equipment that generate corona discharge by applying a high voltage to the

tip of a discharge electrode, and neutralize static electricity with the generated ions. Ionizers are an effective

means of eliminating static electricity from insulating material that cannot be discharged by grounding. Unlike

charges on metal, there is no risk of charges on insulating material being discharged to and damaging devices.

However, these charges may generate inductive charges in devices and metal parts. Ionizers are effective when

using insulating material near devices.25)

(10) Clothing

Workers should make efforts to wear clothing made from materials that do not generate static electricity.

Clothing made from materials that easily generate static electricity may induce strong static electricity in

human bodies with movement.

(11) Characteristics required of ESD protective items

The values given in the table below are references for the characteristics required of main ESD protective

items. Even when the characteristics noted in the Specifications satisfy the required standards, the actual effects

of countermeasures should be thoroughly verified without fail before selecting ESD protective items for

introduction.

Table 4-6 Characteristics Required of Main ESD Protective Items26)

ESD protective item Range of resistance values Remarks

Floor Rg1× 109Ω

ESD protective sheet

(Floor, work surface, storage rack)

Resistance between two points Rp1× 109Ω

Resistance between EPA and ground Rg1× 109Ω

Note 1

ESD protective shoes

(when worn on the metal plate)

Resistance between EPA and ground

1× 105Rg1× 108Ω

Wrist strap (band) Resistance value Rp1× 105Ω

Wrist strap (cord) Resistance value between pins Re5× 105Ω

Wrist strap (when worn) Resistance between EPA and ground Rg3.5× 107Ω

Chair Resistance between EPA and ground Rg1× 1010Ω

Clothes Resistance between two points Rp1× 1012Ω

Note 1) EPA: ESD Protected Area

4-26

<References>

1) Itoh and Adachi, “Electrostatic Discharge Countermeasures for Electrical Equipment Components”, Denshi-

Gijutsu (Electronic Technology), July issue, pp.17-44 (1987)

2) “MIL-HDBK-263A MILITARY HANDBOOK,” 1991.2. 22, Electrostatic Discharge Control Handbook for

Protection of Electrical and Electrostatic Parts

3) JEITA EIAJ ED-4701/304, JEITA (2001)

4) “MIL-STD-883D Test Method 3015.7: Electrostatic Discharge Sensitivity Classification,” Military Standard

for Test Methods and Procedures for Microelectronics

5) EIA/JESD 22-A114F, JEDEC, (2007)

6) EIA/JESD 22-A115E, JEDEC, (2008)

7) JEITA EIAJ ED-4701/305A, JEITA, (2004)

8) JESD22-C101E, JEDEC, (2008)

9) “ESD-DS5.3-1996: Electrostatic Discharge Sensitivity Testing Charged Device Model (CDM),” Draft

Standard for Electronic Discharge Association

10) B. A. Unger, “Electrostatic Discharge Failure of Semiconductor Devices,” 19th. IRPS Proc., (1981)

11) T. S. Speakman, “A Mode for Failure of Bipolar Silicon Integrated Circuit Subjected to Electrostatic

Discharge,” 12th. IRPS Proc., (1974)

12) C. Wunsch, R. R. Bell, “Determination of Threshold Failure Levels of Semiconductors Diodes and Transistors

due to Pulse Voltages,” IEEE NS-15 No. 6, p. 244, (1969)

13) Fukuda and Otsuki, “IC Breakdown by Electrostatic Charges on IC Packages”, Nikkei Electronics, pp.179

(Apr. 1984)

14) Ueno and Yamazaki et al., “A Study on Electrostatic Damage to Devices from Human Body Charges”, The

Union of Japanese Scientists and Engineers 17th Symp. on Reliability and Maintainability, pp.47 (1987)

15) Tanaka et al., “Clarification of Human Body Discharge Phenomenon and Problems with ESD Testing

Methods”, RCJ 6th EOS/ESD Symp., pp.73 (1996)

16) Suzuki and Ueda, “Case Studies on Measurement of Excessive Dynamic Charges”, RCJ 6th EOS/ESD Symp.,

pp.85 (1996)

17) Setoya et al., “Basic Study on the Charged Device Model and Testing Method”, RCJ 4th EOS/ESD Symp.,

pp.73 (1994)

18) Tanaka and Okada, “Investigation of Charged Device Model ESD Test Reference in Terms of Charging and

Discharging Phenomena within Fields”, RCJ 5th EOS/ESD Symp., pp.57 (1995)

19) Wada, “Investigation of Methods for Evaluating Charged Device Model Electrostatic Breakdown”, RCJ 4th

EOS/ESD Symp., pp.43 (1994)

20) Tanaka et al., “Electrostatic Breakdown Phenomenon in LSI due to Displacement Current”, RCJ 6th EOS/ESD

4-27

Symp., pp.21 (1993)

21) Fukuda et al., “Electrostatic Breakdown Evaluation Methods for MOS Devices”, Shingaku Giho, R88-33

(1983)

22) Fukuda et al., “Electrostatic Breakdown Testing Method for Semiconductor Devices Using the Charged

Device Model”, IEICE CMP-86-133, pp.37 (1997)

23) “Guidelines on Technology for Avoiding Electrostatic Damage to Semiconductor Devices”, Reliability Center for

Electronic Components of Japan (1995)

24) “Report on the Results of Investigative Findings on the Standardization of Device ESD Resistance Tests”, Reliability

Center for Electronic Components of Japan (1994)

25) “Utilization Guide for Ionizers Used at Semiconductor Device and other Production Sites”, Reliability Center for

Electronic Components of Japan (1995)

26) IEC 61340-5-1, “Part 5-1: Protection of electronic device from electrostatic phenomenon –General

requirements,” (2007)

4-28

4.2.3 EMC (Electromagnetic Compatibility)

Semiconductor devices and system circuits may misoperate or functions may be impaired according to the

ambient electromagnetic environment. This is because in addition to the effects from external equipment, noise

generated from high-speed switching power supply circuits, digital circuits and printed wiring boards is emitted

and conducted via various paths, and affects semiconductor device and system circuit operation. Recent increases

in mounting density, higher frequencies, and expansion of analog-digital mixed systems are further complicating

this situation.

To address these problems, it is important to determine noise sources and understand transmission paths.

Appropriate measures must be taken to prevent problems such as reinforcement of GND, optimization of circuit

layout patterns, and application of electromagnetic shielding and electromagnetic wave absorbers to semiconductor

devices and set circuits.

4.2.4 Strong Electric and Magnetic Fields

Strong external electromagnetic fields are generally not the direct cause of device failure. However, when

devices are exposed to strong magnetic fields, the impedance may change, the leak current may increase, or other

abnormal phenomena may occur due to polarization of the package plastic materials or inside the IC chip.

In addition, if power supplies or parts that generate high voltages are located near devices, large noise in the

power supply or ground lines may cause circuits to misoperate or the IC to generate noise.

To prevent these external electromagnetic interferences from impeding circuit functions, circuit layout patterns

and component arrangements on printed boards are optimized and shielded wires are used. In addition, care must

be given to the set design, such as changing mounting locations or providing electric and/or magnetic field

shielding as necessary.

4.2.5 Overvoltage Breakdown (EOS Breakdown)

Failure modes where overvoltage or overcurrent other than static electricity causes breakdown are called

overvoltage breakdown or electric over stress (EOS) breakdown. Electric over stress has various causes, but device

burnout failure is generally caused by the application of pulse-type electric over stress called surge. Causes of

surge include discharge from capacitive loads due to equipment power-on/off or relay switching, and lightning

surge due to lightning strikes, etc.

The surge-induced EOS breakdown mechanism varies according to the type of applied surge, but applying

voltage in excess of the ratings to the device power supply or input/output pins causes junction breakdown inside

the device or the phenomenon where parasitic transistors are activated. At this time, if an overcurrent flows and the

energy consumed by the metal wiring and transistors exceeds the wiring or junction endurance level, the wiring

may melt or junctions may suffer thermal breakdown.

4-29

Countermeasures against EOS breakdown include inserting voltage clamp diodes or capacitors to the power

supply and input/output pins on the board to prevent surges from entering the inside of the board. This requires

noise countermeasures for measuring instruments used to adjust boards within processes.

4.2.6 Handling of High-frequency Devices

As semiconductor devices incorporate more advanced functions and performance, the device structures are

being further miniaturized with higher densities, and oxide films and wiring layers are becoming thinner. This has

resulted in an intrinsic drop in electrostatic strength.

To increase the electrostatic strength, countermeasures such as adding electrostatic protection circuits to device

input/output pins are generally taken, but this also has the drawback of causing characteristics degradation.

Particularly for high-frequency and high-speed devices, adequate electrostatic countermeasures cannot be taken

for some pins in order to satisfy the required performance. For example, since electrostatic protection elements

with adequate electrostatic strength and low capacitance are necessary for input/output pins of high-speed

transmission interface devices such as LVDSs, MIPIs, measures against ESD for which both performance and

strength are essential have become a problem.

Therefore, thorough countermeasures must be taken in all aspects from device storage and transport to set

mounting, inspection and other work environments, and also for handling during work.

4.2.7 Latch-up

Latch-up is the phenomenon where overvoltage or current stress such as static electricity or noise entering from

an external source triggers the parasitic thyristors in CMOS devices and creates a short-circuit between the power

supply and GND.

The latch-up phenomenon occurs in the operating condition (the condition with the supply voltage applied), but

as long as voltage stress that exceeds the device ratings is not applied, there is little or no risk of latch-up occurring

within the normal operating voltage range. Latch-up that occurs randomly while using electronic equipment is

thought to be mostly caused by the entry of stress in excess of the ratings to products incorporating semiconductors

or the occurrence of this type of situation during operation. Possible causes of latch-up are as follows.

(1) Entry of static electricity from an external source

When static electricity enters an operating device that is mounted on a board, the discharge current passes

through the input/output pin protective elements and flows to the power supply or GND wiring. In

consideration of discharge from human bodies, the peak current value that flows at an ESD of several kV can

reach several A to several ten A. If this current flows to the board power supply or GND wiring, the power

supply or GND potential fluctuation may reach several V and exceed the device ratings. If this voltage

fluctuation occurs during device operation, the junctions inside the device may break down and cause latch-up.

4-30

Portable electronic equipment (cellular phones, camcorders, laptop computers, portable data terminals,

digital cameras, etc.) has spread rapidly in recent years, and the frames of this electronic equipment that is

frequently and directly touched by people is not grounded. Therefore, this equipment is easily affected by

supply voltage fluctuations caused by ESD from human bodies, and has a high risk of latch-up.

(2) Entry of lightning surge

Semiconductor devices used in communications facility or power supply facility equipment may experience

latch-up due to lightning surge entering via communication cables or transmission lines. Household electronic

products may also experience latch-up due to lightning surge entering through utility poles, transmission cables

or telephone lines, etc.

(3) Electromagnetic susceptibility (EMS)

If sources of electromagnetic noise (car engines, cathode ray tubes, ESD) are present around electronic

equipment, noise induced by sudden changes in the electromagnetic field may cause latch-up.

(4) Live wire insertion or removal

When performing maintenance or repair work on operating systems, depending on the manner in which the

connectors are connected, voltage may be applied to the input/output pins before power is supplied to the board

when a board is inserted with the system in the operating condition. At this time, the input/output pin potential

momentarily becomes higher than the supply voltage, causing an influx of current from the pin and resulting in

latch-up.

(5) Supply voltage application sequence for multi-power supply devices

In devices with multiple different power supplies, the potential of certain pins may rise above the supply

voltage depending on the sequence in which the supply voltages are applied, and this may cause latch-up. Care

must be taken for the order in which the power supplies are applied to the device for devices that use multiple

power supplies.

Latch-up caused by these types of external factors can be suppressed by taking countermeasures to prevent

the entry of surges and noise that serve as the respective triggers. Effective countermeasures for static

electricity or surges that directly enter pins include inserting surge countermeasure diodes, capacitors or other

elements to the board entrances that are the entry routes, or using board power supply and GND wiring patterns

that are resistant to potential fluctuations and noise. In addition, lowering the power supply and GND wiring

impedance, suppressing potential fluctuations due to sudden currents, and separating the power supply and

GND wiring of circuit blocks that are susceptible to external surges from other circuits are also effective

countermeasures. Countermeasures for the power supply application order include inserting capacitors or

taking other measures to delay the respective rise timings, etc.

Electromagnetic noise requires shielding countermeasures to prevent electromagnetic waves from entering

4-31

electronic equipment or the use of wiring patterns that are resistant to induction by electromagnetic fields.

When sources of electromagnetic noise are present inside equipment, countermeasures must be taken for the

noise source or the power supply and GND wiring must be separated, etc.

4.2.8 Thermal Runaway

Thermal runaway is the phenomenon where positive feedback increases the power due to the temperature

characteristics of the IC internal circuits, causing the temperature to rise without limit and resulting in failure. Most

failure after mounting is thought to be caused by thermal runaway. In addition to thermal runaway caused by local

heat generation in the device, thermal runaway may also occur depending on the heat radiation structure in power

devices. Therefore, special care must be given to heat radiation design.

4-32

4.3 Notes on Handling for Mechanical Breakdown

Devices should be handled carefully. Devices may be damaged by dropping or shocks, so care should be taken

to keep mechanical vibrations and shocks to a minimum.

Devices are comprised of chips, bonding wires, external pins, radiation fins, mold resin and other elements, and

the mechanical strength and coefficient of thermal expansion of each component material differ. Therefore,

mechanical breakdown may occur in various cases such as when forming or cutting external pins, mounting

devices on printed boards, washing, or attaching radiation fins.

These mechanical external forces may cause package or chip cracking, and lead to degraded moisture resistance

due to delamination at the boundary between the mold resin and the external pins.

4.3.1 Forming and Cutting External Leads

When mounting semiconductor devices onto printed boards, care should be taken not to apply excessive force to

the external leads when forming or cutting the external leads beforehand. (Fig. 4-18)

Clamp

Lead wire

Bending

Clamp

Device

Fig. 4-18 Notes on Forming or Cutting External Leads

(1) When bending external leads, clamp the external lead between the point at which the lead is to be bent and

the package body. Do not bend external leads while holding the package body.

When using a metal mold, also do not apply stress to the package body.

Likewise, when cutting external leads, do not apply stress to the package body.

(2) Do not repeatedly bend external leads.

(3) Do not bend external leads in the thick direction of the lead.

(4) Care should be taken as the external lead plating may be damaged depending on the bending method.

4.3.2 Mounting Devices on Printed Boards

When mounting semiconductor devices on printed boards, care must be taken not to apply excessive stress to the

external leads. If the external leads bend or float, good solder contact with the printed board may not be obtained,

resulting in a mounting defect. (Fig. 4-19)

4-33

(1) The external lead attachment interval on the printed board should match the external lead interval of the

device.

(2) When inserting the device into the printed board, avoid forcibly inserting the device.

(3) Leave an appropriate gap between the semiconductor device and the printed board.

(4) When mounting a surface mounted-type device on a printed board, if the external leads are deformed or

float, good solder contact with the printed board may not be obtained, resulting in a mounting defect.

Therefore, care must be taken not to deform the external leads.

(5) When mounting semiconductor devices on printed boards using mounting sockets, use an appropriate

socket for each package.

Correct Incorrect

Semiconductor device

Mounting does not applystress to the lead base (arrows).

The leads were forced intothe lead holes of the printed board,

so stress is needlessly appliedas indicated by the arrows.

Fig. 4-19 Notes on Printed Board Mounting

4.3.3 Washing Methods

In principle, flux must be removed after soldering. Otherwise, flux residue may affect the reliability of

components, printed board wiring or solder junctions.

(1) Ultrasonic washing offers excellent washing effects in a short time, but the following care must be given in

order to prevent device breakdown:

① Determine proper frequency applied, output, and washing time.

② Avoid direct contact with the device and another device, the printed board and/or the main frame of the

ultrasonic washers.

(2) Do not rub marked surfaces during washing or while detergent has adhered to the device, as this may cause

the marking to disappear.

Care should also be taken as the marking may disappear if washing is performed for a long time.

(3) Even when using solvents or washing just with water, washing should be performed so that sodium,

chlorine and other reactive ions do not remain. Also, be sure to dry all parts thoroughly.

(4) When using solvents, be sure to take into account public environmental standards and safety standards.

4-34

4.3.4 Attaching Radiation Fins

Care should be taken for the following points when attaching radiation fins to devices.

(1) Use an appropriate attachment method so that excessive stress is not applied to the device.

(2) Take care for flatness so that there is no burring or unevenness on radiator fins.

If radiator fins are inappropriate, sufficient radiation effects may not be obtained, and forced attachment

may cause device characteristics degradation or mechanical breakdown.

(3) When there are two or more radiator fin mounts, first lightly pre-tighten all of the mounts, then tighten to

the prescribed torque.

(4) Do not attach radiator fins to a semiconductor device after the device has been mounted on a board.

Otherwise, excessive stress may be applied to the semiconductor device depending on the manner in which

the device is mounted on the board. First attach the radiator fins to the semiconductor device, and then

mount the device on the board.

(5) Thermal conductivity is generally improved by coating the junction between radiator fins and

semiconductor devices with silicon grease. In this case, be sure to apply an even coat.

4-35

4.4 Notes on Handling to Prevent Thermal Breakdown

Semiconductor devices have structures that combine a silicon chip, plastic encapsulating materials, copper and

other metallic lead frames, and other materials, each of which has completely different thermal properties. In

particular, when the plastic materials are exposed to high temperatures such as during soldering, the moisture

accumulated in the plastic rapidly turns into steam and causes package cracking. The causes of delamination

between the adhered portions of component materials, disconnection of conductors and other problems brought

about by repeated heat stress are as follows.

(1) The mechanical strength drops significantly at high temperatures.

(2) Moisture in the air is absorbed and accumulated.

This section describes general precautions, particularly for product mounting, to prevent this type of thermal

breakdown of devices.

4.4.1 Soldering

(1) Precautions during soldering

Semiconductor devices generally should not be left for long periods at high temperatures.

Even during soldering, regardless of whether hand soldering or reflow methods are used, if the soldering

temperature is high and the soldering time is long, the device temperature may rise and result in degradation or

breakdown. Therefore, soldering should be performed at the lowest temperature and shortest time possible.

(2) When soldering through-hole device (THD) packages with a wave solder vat

This method dips the portions of the package lead pins to be soldered into the liquid surface of a jet solder

bath. However, note the package may be damaged if the jet solder contacts the package body, so care should be

taken not to allow the solder to directly contact the package body.

In addition, when using a wave solder bath, the bottom of the board is heated by the solder heat, so board

warping may occur due to the temperature difference between the top and bottom of the board.

If soldering is performed with the board in the warped condition, the board attempts to return to its original

condition when it is taken from the solder bath, so excessive stress may be applied to the leads and package,

causing solder junction cracking and lead and package damage.

Therefore, when using a wave solder bath, soldering should be performed in a manner that does not produce

board warping.

4.4.2 Notes on Mounting Surface Mount Devices (SMD)

Board mounting methods for SMD include infrared reflow, air reflow, and vapor phase reflow, etc. Thus,

soldering methods that heat the entire package are often used.

4-36

In contrast to conventional THD where only the external lead pins are heated, the entire SMD package is

suddenly exposed to high temperatures, so mold resin cracking and degraded moisture resistance must be taken

into account as potential reliability problems.

In addition, SMD have short external lead pins, narrow pin intervals and large numbers of pins to facilitate high-

density mounting. Therefore, sufficient care must be taken when handling SMD.

General precautions when mounting SMD products are described below.

(1) Notes during mounting

When soldering is performed by infrared reflow or other methods that heat the entire device in the condition

where the mold resin has absorbed moisture due to long-term storage in the normal environment or storage in a

high-humidity environment, the mold resin may crack or delamination may occur at the chip boundary.

See section “4.1.3 Notes on Package Cracking” for points during mounting.

(2) Deformation of external lead pins

If the external lead pins bend or float, good solder connection with the board may not be obtained, resulting

in mounting defects. Particular care must be taken for the flatness of external leads so that pins do not float

during mounting.

In addition, when mounting SMD, if strict control is performed for only the external lead pins and the board

control is insufficient, good solder connection may not be obtained. Full care should be given to board warping

and cream solder film thickness and uniformity, etc.

(3) Handling of taping parts

When using taping-packed SMD, static electricity is generated when the top cover tape is peeled from the

carrier tape, and the SMD may become charged. This charge voltage increases as the speed at which the top

cover tape is peeled becomes faster. High-speed tape peeling and rubbing should be avoided as much as

possible to prevent electrostatic breakdown.

(4) Other precautions

When coating SMD and other devices with plastic after mounting on a board, moisture absorption may cause

the leak current to increase depending on the coating plastic, or the stress of the coating plastic may also

produce mechanical stress on the plastic portions of devices. Therefore, post-coating reliability must be

thoroughly confirmed when selecting the coating materials.

4-37

4.5 Notes on Product Specifications, Packing, Transport and Storage

4.5.1 Product Specifications

4.5.1.1 Notes on the Use of Semiconductor Devices

Sony makes the utmost efforts to improve quality and reliability, but due to the nature of semiconductor devices,

a certain percentage of devices may malfunction or fail. When using semiconductor products manufactured by the

Sony Semiconductor Business Unit, customers are requested and responsible for ensuring safe equipment and

system designs to prevent accidents resulting in death, injury or damage to property from occurring as a result of

semiconductor failure.

Note that when designing equipment and systems, the latest product specifications should be checked, and

products should be used within the assured ranges.

Semiconductor products listed in catalogs and sold assume use in general electronic equipment (home

appliances, telecommunications equipment, measuring instruments, office equipment, etc.). Customers should be

sure to consult their Sony sales representative beforehand when planning use for applications requiring special

quality and reliability, or in equipment and systems (automobiles, traffic equipment, medical equipment including

life-support devices, safety devices, aerospace equipment, nuclear power control equipment, etc.) where product

failure or malfunction may pose a direct life- or injury-threatening risk or damage to property. Special

consideration and selection is required for products that demand high reliability.

4.5.1.2 Maximum Ratings (Absolute Maximum Ratings)

The maximum ratings of semiconductor devices are normally prescribed by the [Absolute Maximum Ratings].

According to JIS C 7032, absolute maximum ratings are prescribed as “Limit values which must not be exceeded

even momentarily, or limit values for which the values of two or more items must not be reached simultaneously

when specification values are established for two or more items.” Exceeding absolute maximum ratings even

temporarily causes degradation or failure, and even if the product continues to operate for some time thereafter, the

life is significantly shortened.

Therefore, when designing electronic circuits using semiconductor devices, care must be taken not to exceed the

maximum ratings of these devices even due to fluctuations caused by external conditions during operation.

Maximum ratings indicate the operating limit values for that IC, and parameters such as those shown in Table 4-

7 are generally prescribed. When actually using ICs, operation must stay within these prescribed ranges.

4-38

Table 4-7 Examples of Absolute Maximum Ratings

Item ConditionsRating

value Contents

Supply

voltage

(VDD)

(VCC)

Ta=25C

Measured

relative to

the VSS

pin

7.0V

(for a 5.0

V device)

This is the maximum voltage that can be applied between

the power supply pins and the GND pins.

1. This is related to the endurance voltage of the

transistors inside the IC, and breakdown may occur if

this voltage is exceeded.

2. CMOS devices may break down due to latchup or the

injection of large quantities of hot carriers.

Input and

output

voltages

(VIN)

(VOUT)

Ta=25C

Measured

relative to

the VSS

pin

-1.0 to

7.0V

This is the maximum voltage that can be applied between

the input/output pins and the GND pins.

This voltage generally cannot be larger than the supply

voltage.

1. Parasitic elements configured on the input and output

pins may experience endurance voltage-related

breakdown.

2. Breakdown may be caused by latch-up triggered by the

input or output pins.

Allowable

power

dissipation

(PD)

Ta=25C 1W

This is the maximum power consumption allowed inside

the IC.

1. Breakdown may be caused by internal heat generation

during operation.

2. This value differs according to the degree of IC

integration and the heat radiation characteristics of the

package.

Storage

temperature

(Tstg)

55

to150C

This is the allowable ambient temperature range during

storage.

1. The temperature is limited by the package materials

and the intrinsic properties of semiconductors.

Junction

temperature

(Tj)

This is the maximum allowable junction temperature

value at which continuous operation is possible.

Operating

temperature

(Topr)

10 to

70C

Recommended operating temperature condition range.

IC operation and functions can be assured within this

temperature range, but the electrical characteristics

indicated at Ta = 25C cannot necessarily be assured.

Note) Rating values are prescribed by the individual specifications for each device.

4-39

Fig. 4-20 shows the relationship between various IC maximum ratings.

– –

Non-breakdown assurance range

VDD

Operation assurancerange

Not assured

Electrical characteristicsassurance range

Temperature (C)

Topr - Operating temperature

Tstg - Storage temperature

PD-Ta

VD

D -

Sup

ply

vo

ltage

(V)

14

12

7

5

3

55 10 25 70 150

70

Fig. 4-20 Relationship between Various Maximum Ratings

4.5.1.3 Operation Assurance Range

The operation assurance range indicates operating conditions that must be observed to realize the operations

and functions noted in the data book. Even when the maximum ratings are not exceeded, use outside the operation

assurance range may impair device operations and functions, prevent electrical specifications from being satisfied,

or lead to reduced reliability, so sufficient care should be taken for the system design.

In addition, to ensure reliability when using devices, perform derating with respect to the current, power and

temperature of the operation assurance range.

4.5.1.4 Derating

Derating refers to preventing drops in device reliability by setting operating conditions that are less than the

various rating values of a device, and taking into account power supplies, surge and noise to input pins, and other

factors.

Derating is generally performed with respect to electrical stress such as voltage, current and power, and

environmental stress such as ambient temperature and humidity. Power devices in particular generate large

amounts of heat, so sufficient care should be taken as reliability varies greatly due to the degree of junction

temperature (Tj) derating.

4-40

4.5.2 Notes on Packing, Transport and Storage

Semiconductor devices (hereafter “devices”) maintain high quality and high reliability, but improper handling,

transport, storage or use may lead to device breakdown or deterioration. Causes of device breakdown include

electrostatic breakdown during handling, package cracking during mounting due to package moisture absorption,

and mechanical breakdown due to shocks and lead bending. Items that should be kept in mind are described below.

4.5.2.1 Notes on Packing

The following three storage case packing formats are mainly used in accordance with the device package shape

and mounting format.

(1) Tray (2) Magazine (3) Embossed taping

The packing materials used by these packing formats should use structures and materials suited to each device to

maintain device quality.

Notes on each packing format are described below.

(1) Tray packing

Trays come in heat-resistant specifications and normal temperature specifications. Heat-resistant specification

trays are marked “HEAT PROOF” or indicate the heat resistance temperature such as “135°C MAX”. When

devices are to be baked (dried at high temperature), observe the device baking conditions and perform baking

within the heat resistance temperature range of the tray (125°C MAX for trays marked with “HEAT PROOF”).

Baking cannot be performed using normal temperature specification trays, so when devices in normal

temperature specification trays are to be baked, these devices must be transferred to heat-resistant specification

trays. Anti-static measures should be taken to prevent ESD breakdown before transferring devices from a tray.

Also, be careful not to bump or press the electrode pins against the tray to prevent electrode pin deformation.

Fig. 4-21 Tray

(2) Magazine packing

Magazine surfaces are coated with a water-soluble anti-charging agent. Therefore, note that the anti-charging

effects will be lost if the magazine is dampened by water or stored in a high-temperature and high-humidity

location, or if devices are allowed to slide back and forth.

In addition, magazines do not have heat-resistant specifications, so when devices are to be baked, transfer the

devices to a metal magazine or other heat-resistant storage case. At this time, care should be taken to prevent

4-41

lead bending, and anti-static measures should be taken to prevent ESD breakdown.

Fig. 4-22 Conductive Magazines

(3) Embossed taping packing

Taping does not have heat-resistant specifications, so when devices are to be baked, transfer the devices to a

heat-resistant storage case.

When transferring the devices, care should be taken to prevent electrode pin deformation and ESD

breakdown.

In addition, the taping peeling strength is affected by the temperature and humidity of the storage

environment, so care should be taken when setting a tape reel in a mounter.

The peeling strength measurement method conforms to JIS C 0806-3:1999.

Fig. 4-23 Taping

4.5.2.2 Notes on Transport

Devices contained in trays, magazines and embossed taping are stored and shipped in our specified packing

cartons to avoid the effects of external shocks during transport, rain water during storage, or contamination from

the outside air, etc.

If handling is rough and strong shocks are applied during transport, devices may experience lead bending or

other damage, resulting in trouble during mounting.

In addition, rough handling may also cause the aluminum laminate bags used as moisture-proof packing to

become torn. If the aluminum laminate bags become torn, the devices may absorb moisture, resulting in problems

that affect device quality.

Therefore, care should be taken for the following points during transport.

(1) Efforts are made to minimize shocks, vibration, humidity and other adverse effects applied to devices.

However, application of excessive shocks or vibration may damage devices, so care should be taken for

handling to reduce shocks and mechanical vibration.

(2) Avoid exposure to direct sunlight and take care to prevent condensation.

4-42

(3) If packing boxes are received in a damaged condition, do not open the packing boxes, and contact your

Sony sales representative.

(4) Care marks indicating cautions are displayed on packing boxes as necessary. Be sure to follow these

instructions for storage and transport. Examples of care mark indications are shown below.

Avoid static charges This side up Fragile Keep dry

Fig. 4-24 Packing Carton Markings

● Fragile

If packing cartons are thrown or dropped during handling, the packing materials and possibly the devices

themselves may be damaged. Handle packing cartons with care.

● This side up

Packing cartons should be placed facing the correct direction as indicated on the packing carton during transport.

If packing cartons are turned upside down or on their sides, unnatural force may be applied to and damage devices.

● Keep dry

When cartons absorb water, the strength drops drastically, so cartons must not be allowed to become wet,

especially during transport in rain or snow.

● Avoid static charges

This is not a caution during transport, but is indicated as a caution during set mounting.

4.5.2.3 Notes on Storage

The storage environment affects quality, so control the following items when storing devices.

(1) Storage environment

Store indoors under ambient conditions of normal temperature and humidity [temperature (5°C to 35°C),

humidity (30% to 75%)].

(2) Storage period

The storage limits for each packing format in the above storage environment are as follows.

Products in tray packing: 1 year from delivery date

Products in magazine packing: 1 year from delivery date

Products in taping packing: 1 year from delivery date

4-43

The storage limit for each packing format is 1 year. Exceeding this limit may result in reduced device

solderability, deteriorated water-soluble anti-charging agent effects, unstable peeling strength of taping packed

products, or other problems.

(3) Atmosphere

Avoid storage in locations exposed to direct sunlight, locations where corrosive gases are generated, or dusty

locations.

• Storing cases (magazines or non-heat-resistant trays) may deform if exposed to direct sunlight.

• Corrosive gases cause the external lead pins of devices to corrode and solderability to deteriorate.

(4) Temperature changes

Moisture condenses on packed products in locations where the temperature changes suddenly. To avoid

condensation, store semiconductor devices in locations where the temperature changes as little as possible.

(5) Avoid stacking or placing heavy objects on packing boxes as much as possible to avoid

applying loads to devices.

(6) Store devices in locations not exposed to radiation, strong electromagnetic fields or static

electricity.

(7) When storing devices for long periods, different moisture-proof packing and packing

components must be used.

Devices stored for long periods may experience deteriorated pin solderability, rust, or electrical characteristic

failure. Contact your Sony sales representative beforehand when long-term storage is anticipated.

(8) Products in moisture-proof packing

Moisture absorption affects device quality, and moisture-proof packing aims to prevent moisture absorption

during storage. Devices, desiccants and moisture indicators are placed in aluminum laminate bags that are

deaerated and heat-sealed to block outside air and prevent the entry of moisture.

If moisture enters the moisture-proof packing, the devices may absorb moisture. Exposing devices that have

absorbed moisture to high-temperature ambient conditions such as the soldering process during mounting may

result in package cracking or other quality problems. Moisture-proof packing is used to prevent these kinds of

effects on quality.

Devices begin to absorb moisture as soon as the moisture-proof packing is opened, so control should be

performed so that devices are used within the specified time in accordance with the SMD rank instructions.

When the period specified by the SMD rank is exceeded, baking must be performed again. Contact your

Sony sales representative for the baking time for each device.

In addition, moisture indicators are enclosed as simple indicators of the humidity condition inside moisture-

4-44

proof packing. When the indicated humidity immediately after opening the moisture-proof packing exceeds

30%, some trouble may have occurred, so contact your Sony sales representative.

Humidity indicator

Desiccant

Moisture-proofpacking bag

Tray (pallet)

Fig. 4-25 Moisture-proof Packing

Semiconductor Quality and Reliability Handbook

Chapter 5 Notes for Each Product Category and Other Noteworthy Items

5-1

Chapter 5 Notes for Each Product Category and Other Noteworthy Items

5.1 Image Sensors .............................................................................................................................................. 5-2 5.1.1 Notes on Mounting ........................................................................................................................... 5-2

5.1.1.1 Precautions during Soldering ............................................................................................ 5-2 5.1.2 Notes on Handling Image Sensors ................................................................................................. 5-3

5.1.2.1 Handling during Mounting (Adhesion) .............................................................................. 5-3 5.1.2.2 Dust and Dirt Countermeasures ....................................................................................... 5-4 5.1.2.3 How to Remove Dust and Dirt .......................................................................................... 5-5

5.1.3 Precautions for handling of magazine-packed products ................................................................ 5-6 5.1.3.1 Removing Products ........................................................................................................... 5-6 5.1.3.2 Storing Odd Lots of Products after Opening Magazines ................................................. 5-6

5.1.4 Other ................................................................................................................................................. 5-7 5.2 Laser Diode ................................................................................................................................................... 5-8

5.2.1 Notes on Handling Laser Diodes .................................................................................................... 5-8 5.2.1.1 Eye Protection against Laser Beams ............................................................................... 5-8 5.2.1.2 Gallium Arsenide ................................................................................................................ 5-9 5.2.1.3 Electrical Stress .................................................................................................................. 5-9 5.2.1.4 Contamination (dust and dirt) .......................................................................................... 5-10 5.2.1.5 Mechanical Stress ........................................................................................................... 5-10 5.2.1.6 Thermal Stress ................................................................................................................. 5-11 5.2.1.7 Condensation ................................................................................................................... 5-11

5.2.2 Laser Diode (LD) Reliability ........................................................................................................... 5-12 5.2.2.1 LD Failure ......................................................................................................................... 5-12 5.2.2.2 Degradation Factors ........................................................................................................ 5-13 5.2.2.3 Methods for Estimating Life ............................................................................................. 5-13 5.2.2.4 Failure Analysis ................................................................................................................ 5-14

5.3 LCD .............................................................................................................................................................. 5-17 5.3.1 LCD Optical Reliability .................................................................................................................... 5-17

5.3.1.1 Description ....................................................................................................................... 5-17 5.3.1.2 Deterioration Mechanisms .............................................................................................. 5-17 5.3.1.3 Light Exposure Test Method ........................................................................................... 5-18

5.3.2 Handling LCDs ............................................................................................................................... 5-19 5.3.2.1 Electrostatic Countermeasures ....................................................................................... 5-19 5.3.2.2 Dust and Dirt Ccountermeasures ................................................................................... 5-19 5.3.2.3 Notes on Light Resistance .............................................................................................. 5-19 5.3.2.4 Other Handling Precautions ............................................................................................ 5-20

5.4 Quality Assurance of Bare Die ................................................................................................................... 5-21 5.5 Product Name and Lot Indications ............................................................................................................. 5-23

5-2

5.1 Image Sensors

5.1.1 Notes on Mounting

5.1.1.1 Precautions during Soldering

Image sensors have a hollow package structure. When heated during soldering, the pressure inside the package

increases and the sealed glass-adhered portions easily delaminate, so reflow mounting cannot generally be assured.

The recommended soldering conditions differ according to the package materials, adhesive, and the package size,

so soldering should be performed within the range of the recommended conditions and other items noted in the

individual product specifications.

(1) Recommended soldering conditions when using a soldering iron

Care should be taken for the following items during soldering work.

・ Use a 30 W or equivalent soldering iron with ESD countermeasures and a tip temperature of 350°C or

less, and solder each pin in 3 s or less.

(The package temperature varies according to the board and the work environment, so check the

temperature in the following locations before performing soldering work.)

Plastic or CERDIP packages: Glass-adhered portions 80°C or less

Laminated ceramic packages: Glass-adhered portions 95°C or less

・ Also observe the above temperatures when readjusting or removing image sensors.

・ When using an electric vacuum desoldering tool, an overvoltage may be applied due to surge at start-up,

so use a temperature control-type zero-cross ON/OFF tool and connect it to ground.

・ Avoid local heating, rapid heating and rapid cooling.

(2) Recommended Conditions for Reflow

The following recommended conditions and notes should be observed when performing reflow for products

with recommended reflow conditions noted in the individual product specifications.

・ Recommended reflow profile

・ Storage conditions and time until reflow is performed after opening the moisture-proof packing

・ Reflow times

Note that when the solder inspection is performed using transmitted X-ray images, irradiation by high levels

of X-rays may cause the dark current to increase or otherwise damage products.

5-3

5.1.2 Notes on Handling Image Sensors

5.1.2.1 Handling during Mounting (Adhesion)

・ If a load is applied to the entire surface by a hard component, bending stress may be generated and the

package may fracture, etc. depending on the flatness of the bottom of the package. Therefore, for

mounting, use either an elastic load, such as a spring plate, or an adhesive.

・ The adhesive may cause markings on the rear surface to fade or become blurred.

・ If metal, etc. strikes or rubs against the package surface, the package may chip or fragment and generate

dust.

・ For products with leads, if the leads are bent repeatedly, the package may chip or fragment and

generate dust.

・ Note that use of an ultraviolet or infrared laser during mounting may damage the product.

・ Remain within the following limits when applying a static load to packages. In addition, do not apply a

local load or a load to the inside of the glass area (hollow portion).

Take special care for the following when using CERDIP or plastic-ceramic packages.

50N

カバーガラス

パッケージ

50N 1.2Nm

圧縮力 ひねりトルク

Cover glass

Package

Compressive force Twisting torque

50N 50N 1.2Nm

Fig. 5-1 Allowable Stress to Laminated Ceramic Packages

5-4

39N上側セラミック

下側セラミック

29N

0.9Nm

圧縮力 ひねりトルク

低融点ガラス

29N

引張力せん断方向力

39N

プラスチック部

セラミック部

29N

0.9Nm

圧縮力 ひねりトルク

接着剤

29N

引張力せん断方向力

カバーガラス

39N上側セラミック

下側セラミック

29N

0.9Nm

圧縮力 ひねりトルク

低融点ガラス

29N

引張力せん断方向力

39N

プラスチック部

セラミック部

29N

0.9Nm

圧縮力 ひねりトルク

接着剤

29N

引張力せん断方向力

カバーガラス

Upper ceramic

Lower ceramic

39N

39N

29N

29N

29N

29N0.9Nm

0.9Nm

Compressive force

Compressive force

Cover glass

Plastic

Low melting point glass

Ceramic Adhesive

Shearing direction force

Shearing direction force

Tensile force

Tensile force Twisting torque

Twisting torque

Fig. 5-2 Allowable Stress to CERDIP and Plastic-ceramic Packages

50N

カバーガラス

プラスチックパッケージ

50N 1.2Nm

圧縮力 ひねりトルク

Cover glass

Plastic package

50N 50N 1.2Nm

Compressive force Twisting torque

Fig. 5-3 Allowable Stress to Plastic Packages

5.1.2.2 Dust and Dirt Countermeasures

Image sensors are packed and delivered with care taken to protect the element glass surfaces from harmful dust

and dirt. However, glass surfaces should be cleaned by the following operations as required before use.

In particular, the element glass of products with anti-reflective coating applied to the glass surfaces is easily

scratched, so special care should be taken not to scratch the glass when cleaning.

(1) Perform all lens mounting and other work in a clean environment (class 1000 or less).

(2) Care should be taken not to either touch glass surfaces by hand or have any object come in contact with

glass surfaces. Use an air blower to blow dust or dirt off the glass surface. (For dirt stuck through static

electricity, ionized air is recommended.)

(3) Wipe away grease stains with a cotton swab moistened with ethyl alcohol. Be careful not to scratch the

glass surface.

5-5

(4) Store in a dedicated case as a countermeasure against dust and dirt, and preheat or precool when moving to

a room with great temperature differences as a countermeasure against condensation.

(5) When protective tape is applied before shipping, remove the tape applied for electrostatic protection

immediately before use. Do not reuse the tape.

(6) Protective tape is used to prevent glass surfaces from scratches, but dust caught between the glass surface

and the tape is not assured. When stored for a long period, this dust may become difficult to remove or paste

residue of the tape may easily remain, so long-term storage should be avoided if at all possible.

5.1.2.3 How to Remove Dust and Dirt

① For the effective area and surrounding glass surfaces, incline the cotton swab (45° or less) and wipe

away the dirt in the same direction as the lead arrangement as shown in Fig. 5-4.

Fig. 5-4 Wiping the Glass Surface

② For the gap between the sealing glass and the package, hold the cotton swab straight up and wipe away

the dirt as shown in Fig. 5-5.

Fig. 5-5 Wiping the Sealing Glass Surface

[Notes]

• Do not wipe glass surfaces with a cotton swab if dust or dirt have not adhered.

• In step , do not allow the cotton swab to contact the glass edges or the ceramic surface.

• Do not reuse cotton swabs.

5-6

5.1.3 Precautions for handling of magazine-packed products

5.1.3.1 Removing Products

When removing products from magazines, remove the products by the following procedure to prevent lead

bending due to dropping or other problems.

① Remove the rubber stopper. Be careful so that the products do not fall from the magazine at this time.

② Incline the magazine at approximately 30° over a conductive mat and let the products slide slowly out of

the magazine. (Be careful as the products will fly out with great momentum if the magazine is inclined

too much.)

Also, keep the magazine outlet at a height of 5 mm or less from the mat while removing the products.

(Fig. 5-6)

Magazine

Product

5 mm or less

Conductive mat

Approximately 30°

Fig. 5-6 Removing Products from Magazines

5.1.3.2 Storing Odd Lots of Products after Opening Magazines

After products have been removed, magazines may contain an odd lot of products. When storing these odd-lot

magazines, inserting a rubber spacer of an appropriate length into the magazine and then fitting a rubber stopper is

recommended to prevent the products from moving inside the magazine and being damaged by mechanical shocks,

etc. (Fig. 5-7)

Magazine

Rubber spacer

Rubber stopper

Fig. 5-7 Storing Odd Lots of Products in Magazines

5-7

5.1.4 Other

・ Do not expose to ultraviolet rays, sunlight or other strong light for long periods. The transmittance and color

characteristics of the on-chip lens and color filter may be affected.

・ Avoid storing or using products at a high temperature or high humidity, as this may adversely affect the

transmittance or color characteristics.

・ The imaging characteristics may be affected by noise or other factors when strong electromagnetic waves or

magnetic fields are approached during operation. Special care should be taken for CMOS image sensors as

these are easily affected.

・ Note that the image of CMOS image sensors may be affected by light leaking to the optical black when using

an infrared cut filter that has transmittance in the near infrared range while shooting subjects with high

luminance.

・ Sony image sensor specifications do not assume use in environments with above-ordinary radiation levels.

・ White pixels occur spontaneously in image sensors over time and due to cosmic radiation. White pixels that

occur should be compensated using a white pixel compensation circuit.

5-8

5.2 Laser Diode

5.2.1 Notes on Handling Laser Diodes

Unlike normal transistors and integrated circuits, special care must be given to the following points when

handling laser diodes.

5.2.1.1 Eye Protection against Laser Beams

Take care not to allow laser beams to enter your eyes under any circumstances. Using safety goggles that block

laser beams is strongly recommended when performing inspection or measurement of a laser diode in the emitting

state.

Be sure to observe the laser safety standards specified by IEC60825-1 and JIS standard C6802 “Safety of Laser

Products.”

Warning labels such as those shown in Fig. 5-8 below are noted in the product specifications.

For details, see IEC60825-1.

Fig. 5-8

Examples of labels listed in the product specifications

Class 3B

Class 4

5-9

5.2.1.2 Gallium Arsenide

Laser diodes (except for blue and violet laser diodes) use gallium arsenide (GaAs). This is not a problem for

normal use, but GaAs produces poisonous gas when it reacts with acids or steam. Therefore, never crush, heat to

the maximum storage temperature or higher, or place a laser diode in your mouth.

In addition, the following disposal methods are recommended when disposing of this product.

1) Engaging the services of a contractor certified in the collection, transport and intermediate treatment of

items containing arsenic.

2) Managing the product through to final disposal as specially managed industrial waste which is handled

separately from general industrial waste and household waste.

5.2.1.3 Electrical Stress

Laser diodes (LD elements) are one of the most sensitive to electrical stress among semiconductor products, so

sufficient care should be taken for handling. It is recommended to monitor the optical power output using the

photodiode built into the laser diode or an external photodiode, and to drive the laser diode at a constant power

output within the range that does not exceed the recommended power output. When driving at a constant current,

the design should take into account the increase in power output at low temperatures in consideration of the

temperature dependence of the I-L characteristics.

The Sony Semiconductor Business Unit provides consulting services with the aim of supporting measures for

trouble caused by electrical stress at the customer’s premises. Please contact your Sony sales representative when

necessary.

(1) Overcurrent and surge current

The laser diode life becomes shorter as the operating optical power output increases. The life cannot be

assured when used under conditions that exceed the recommended conditions, so use within the recommended

conditions range. In addition, note that if the optical output power exceeds the absolute maximum rating even

for an instant, the laser diode may be damaged, which may shorten the life or in the worst case lead to the

immediate stop of oscillation. Of the different kinds of damage due to electrical stress, the most common is

damage caused by optical power output in excess of the absolute maximum rating. The mechanism is that

“excessive light emission causes the light emission facet to become excessively hot, resulting in structural

breakdown of the light emission area.”

<Main causes of overcurrent and surge current>

a. Power supply (excessive overshoot of power-on current, etc.)

b. Adjustment errors (optical output power adjustment knob overrun, etc.)

c. Electrical leakage or inter-line potential difference factors (current flowing simply when a connection is

made, etc.)

5-10

d. Static electricity (charge carried by the laser diode, charges carried by the human body or other

surrounding items, etc.)

e. Connection defects (chattering, etc.)

f. Work errors (circuit cut-off while the power is on, etc.)

g. Operating conditions (used under conditions that exceed the recommended conditions, etc.)

(2) Static electricity

Care should be taken as static electricity as this is cause of surge current flowing to the laser diode.

When static electricity flows in a laser diode, the conditions and the damage mechanism are the same as

those of overcurrent. There are various methods for dealing with static electricity depending on the situation,

but the basic approaches are as follows in consideration of cost effectiveness.

a. Prevent charges accumulated as static electricity from flowing to laser diode leads.

b. When static electricity cannot be prevented from flowing, implement protective countermeasures and

limit the flowing current.

c. Reliably ensure that the laser diode anode and cathode are always the same potential when the power is

off.

d. Suppress the generation of static electricity, or eliminate the charge.

* Special care should be taken for static electricity carried by the package of resin package products.

5.2.1.4 Contamination (dust and dirt)

1) Care should be taken to prevent dust and dirt from adhering to the window glass of products, as this may result

in reduced optical power output or light emission pattern deformation.

a. Do not touch the window glass.

b. Use an air blower or other non-contact method to remove dirt adhered to the window glass.

Care should be taken when cleaning as mist or other substances in the air may cause secondary

contamination, contact by the nozzle may scratch the window glass, or static electricity generated by the air

blower may result in ESD breakdown of the product.

2) Care should be taken for the ambient conditions, as corrosive gas or other harmful gases (outgas from the

adhesive, etc.) may have an adverse effect on products.

3) The internal elements of open package products may be contaminated if foreign matter (adhesive, solvent, dust,

etc.) enters the inside of the package, so take care to prevent the entry of foreign matter. Contamination of the

laser diode facet, photodiode light receptor surface or other parts may cause the characteristics to deteriorate.

5.2.1.5 Mechanical Stress

When products are damaged by mechanical stress, leaks from the window glass or airtight parts may cause a

5-11

drop in hermeticity, or the laser element and internal connections may be damaged. As a result, product life may be

significantly shortened or characteristics may deteriorate.

(1) Outer lead bending

Products with outer leads should be handled with care to prevent lead bending. Damage to the insulating

glass at the base of the outer leads may cause a drop in hermeticity.

(2) Outer lead pull-out

Pulling strongly on the outer leads of products with outer leads may cause the leads to fall out, or pressing in

strongly may cause the leads to cave in. In particular, the outer leads of a mounted laser diode should be

completely freed before pulling out the laser diode.

(3) Package damage

Care should be taken as applying strong force to the laser diode package may cause adhered materials to

delaminate, or the package may deform or become chipped or cracked.

(4) Window glass, lens and other glass damage

Applying strong force to the window glass, lens or other glass parts of laser diodes may damage, soil, crack

or cause the glass to fall out. In addition, applying strong force to the package may deform the package and

cause the window glass, lens or other glass parts to crack or fall out.

(5) Internal element damage

Using tweezers or allowing other items to enter the inside of open package products may damage the internal

elements, so take care not to allow these items to enter the inside of the package.

5.2.1.6 Thermal Stress

(1) Operation under a high-temperature environment

The laser diode life becomes shorter as the operating case temperature increases. Care should be taken as the

life cannot be assured when used under temperature conditions that exceed the recommended conditions.

(2) Heating due to soldering

Care should be taken as excessive heating during soldering may cause the internal elements of laser diodes to

deteriorate.

5.2.1.7 Condensation

(1) Optical path obstruction

When laser diodes are moved quickly from a low-temperature environment to a room temperature or high-

temperature environment, condensation may temporarily form on the glass surfaces. Care should be taken as

5-12

this may cause the product characteristics to deteriorate temporarily or dirt to adhere to the window glass

surface.

(2) Electrochemical reactions

When open package products are operated in the condition with condensation, electrochemical reactions may

cause the product characteristics to deteriorate. Avoid use in the condition with condensation.

Customers are requested to visually inspect laser diodes before handling, and to use laser diodes safely and

properly.

5.2.2 Laser Diode (LD) Reliability

5.2.2.1 LD Failure

When laser diodes, which are light-emitting elements, operate, the increase in current that does not contribute to

light emission causes the light emission characteristics to change over time. Among these characteristics, the

element life is generally defined by the time-dependent change in optical power output vs. operating current

characteristics, which have a large effect on the drive circuit. This is shown in Fig. 5-9(a). When automatic power

control (APC) drive that maintains a constant optical power output is performed, light emission at the constant

optical power output P0 is no longer possible at time t5.

For example, when laser diode life is defined as the time when the operating current becomes 1.2 times the

initial value, the laser diode is viewed as having failed between t2 and t3 as shown in Fig. 5-9(b) below. However,

as shown in Fig. 5-9(a), this does not mean that the laser diode is no longer able to emit light.

×

Optical power output

P0

0

t0 t1 t2 t3t4

t5

t6

I0 I1 I2 I3 I4I - Current

(a) Time-dependent change in optical poweroutput vs. operating current characteristics

I - Current

1.2I0

I0

t0 t1 t2 t3 t4t - Time

(b) Time-dependent change in optical poweroutput vs. constant value operating current

I0I1

I2

I3

I4

Fig. 5-9 Time-dependent Changes in Optical Operation Current Characteristics

5-13

5.2.2.2 Degradation Factors

Laser diode reliability is closely related to the operating temperature, and the degradation speed rises

exponentially with the operating temperature (rise in drive current per unit time: ΔIop/Δt). This relationship can be

expressed as follows.

As an example, AlGaAs system laser diode degradation is obtained, based on the relation between the

temperature and drive current rise ratio, at Ea ≒ 0.7eV1), so near room temperature the life drops to approximately

1/2.2 for a temperature rise of 10C. In particular, when the laser diode is mounted on small equipment, sufficient

care must be given to thermal design to suppress laser diode temperature rises. In this manner, degradation that

determines the long-term life is called degradation in the gradual degradation mode, or wear degradation. This

wear degradation accelerates as the optical power output increases. Therefore, use within the range of the specified

upper limit optical power output or less is important for obtaining sufficient reliability.

Laser diode failure during use is often facet damage caused by a surge current or overcurrent. In laser diodes, as

the current is raised to increase the optical power output, at a certain point the optical power output drops suddenly

and irreversible damage occurs. This type of degradation is also called catastrophic optical damage (COD), and

occurs when high optical power output density operation causes momentary melting of a part of the laser diode

facet and the formation of crystal defects. Laser diodes have a high response speed of 1 GHz or more and are

instantly damaged, so surge breakdown is an inherent failure mechanism of laser diodes. In order to avoid the COD

failure due to surges, it is necessary to prevent even momentary excessive optical power output from being

generated by a momentary overcurrent entering from the power supply or surges. In addition, even if a relatively

weak surge is applied and there is little initial deterioration in the laser diode characteristics, this has been

confirmed to shorten the operating life thereafter, so care should be taken.

5.2.2.3 Methods for Estimating Life

The life of laser diodes differs from that of other semiconductor devices, and is sometimes expressed using the

mean time to failure (MTTF). The method for obtaining the MTTF is described below.

The life of laser diodes generally follows a Weibull distribution, so the MTTF is expressed by the following

equation using the characteristic life (scale parameter) η, the shape parameter m, and a gamma function.

MTTF=ηΓ (1+1/m)

5-14

η and m can be obtained by plotting the failure time on Weibull probability paper.

Note that when m = 1, Γ(2) = 1, so the MTTF is equal to the characteristic life η.

1.0

0.5

0.2

0.1

2.0

5.0

10.0

15.0

20.0

30.0

40.050.060.070.080.0

90.0

99.0

99.9

10 100 1000 10000

時間　　（ｈ）

累積故障確率　（％

）

η

F(η)=63.2%

Slope m

Fig. 5-10 Weibull Plot: Method of Obtaining η and m

5.2.2.4 Failure Analysis

When trouble occurs in laser diodes, an overall inquiry is made as to the cause by investigating the electrical and

optical characteristics and observing the laser diode with optical microscopes and SEM, etc.

When current flows through a laser diode, the stripe portion emits light, and the cause of the failure is generally

inferred by observing this emitted light. The observed positions are the laser diode facets which emit light, and the

entire stripe portion that is observed by removing the photo-shielding electrode and semiconductor layers from the

inside of the laser diode.

This section presents failure analysis methods using the light emission characteristics that differ from general

semiconductor devices.

(1) Analysis of light emission at the laser light emission facets

Laser diode failure during use is often facet degradation due to a surge current or overcurrent. This

degradation is also called catastrophic optical damage (COD), and occurs when high optical power output

density operation causes momentary melting of a part of the laser diode facet and the formation of crystal

defects. This melted portion absorbs light, so it is observed as degradation of the laser diode characteristics.

When the operating current needed to obtain a certain optical power output increases (large Iop), the rated

output is not produced, the laser diode does not oscillate, or an extremely large overcurrent flows, this is

viewed as a failure such as current being unable to flow.

A low current of several mA is flowed to the laser diode to make it emit light, and the light intensity

Acc

umul

ativ

e fa

ilure

pro

babi

lity

(%)

Time (h)

5-15

distribution at the light emission facet is observed (near field pattern observation). Normal laser diodes exhibit

a Gaussian distribution as shown in Fig. 5-11. During laser oscillation, the light density is highest in the center

of the light emission area of the light emission facet, so crystal melting occurs in this location. Therefore, when

the center of the near field pattern appears dark and forms a double peak or when the pattern appears divided

into a number of peaks, this indicates that a surge or overcurrent has been applied and facet degradation has

caused a light absorbing area near the center of the light emission area. (Fig. 5-12)

Fig. 5-11 Normal Facet Light Emission Pattern Fig. 5-12 Degraded Facet Light Emission Pattern

(2) Analysis of light emission over the entire laser diode surface

For test samples where abnormalities are not visible by observing light emission from the facets or when

defects occur inside the laser diode chip, the entire stripe must be analyzed. The cathode luminescence method

allows observation of the entire stripe of failed laser diodes. This is done by removing the photo-shielding

electrode and semiconductor layers using chemical etching to allow observation of light emission from the

light-emitting layer inside the laser diode chip. Then, the light-emitting layer of the laser diode is made to emit

light by irradiating it with electron rays instead of flowing current. If the emitting layer contains a DLD, this

makes it possible to accurately know the DLD (Dark Line Defect) shape, orientation and resolution. Figs. 5-13

and 5-14 show cathode luminescence images of a laser diode in which a crystal defect called a DLD has

formed near the facet.

Light Intensity

Position

Light Intensity

Position

5-16

Fig. 5-13 Cathode Luminescence Image of a Laser Diode with a Crystal Defect near the Facet

Fig. 5-14 Enlarged View

<References>

1) R. L. Hartman and R. W. Dixon, “Appl. Phys. Lett. 26,” p. 239-242 (1975)

DLD

5-17

5.3 LCD

5.3.1 LCD Optical Reliability

5.3.1.1 Description

The Sony Semiconductor LCD products include high-temperature polysilicon TFT process LCDs used for video

camera viewfinder and LCD projector applications, and silicon reflective LCD (SXRD) used for digital cinema

projector and simulation projector applications. External stress factors adversely affecting the reliability of these

LCDs include general semiconductor stress factors and also the existence of light incident to LCDs. Projector

LCDs have an extremely large light density incident to the panel, and strong light stress is applied for long periods,

so reliability problems due to incident light may occur depending on the method of use. This section discusses the

optical reliability mainly of LCDs used for projector applications.

5.3.1.2 Deterioration Mechanisms

Reliability and characteristics problems caused by light incident to projector LCDs fall under two main

phenomena. The first phenomenon is changes to the molecular structure of the organic compounds due to

photochemical reactions caused by optical energy absorbed by the organic materials used. The other phenomenon

is changes in the pixel potential due to electron-hole pairs generated when light straying to the pixel transistors is

absorbed by the TFT bulk.

(1) Deterioration due to photochemical reactions in the organic materials

Changes to the molecular structure of the organic compounds due to incident light are thought to be caused

by the phenomenon where optical energy absorbed by the organic compound produces a photochemical

reaction that causes dissociation of the organic bonds. As the photochemical reaction of the organic compound

progresses, the picture quality may be affected by a drop in the orientation of the liquid crystals or the

generation of ions.

The rate of the light-induced chemical reaction can be obtained using an Arrhenius equation expressing the

function f (λ) of the absorbed energy that contributes to the photochemical reaction, the function f (P) of the

incident light quantity, and the temperature dependence of the chemical reaction rate.

The photochemical reaction rate is proportional to the amount of optical energy absorbed, so the reaction rate

becomes faster as the incident light quantity increases or as ultraviolet light with high photon energy is

absorbed.

Thus, the light exposure lifetime can be extended by cutting as much as possible of the undesired ultraviolet

5-18

or near ultraviolet light from the wavelength component of the light incident to the LCD panel, or by lowering

the panel temperature to suppress the photochemical reaction.

(2) Signal charge fluctuation due to light absorption by pixel transistors

A pixel transistor comprises one pixel of the LCD. These transistors are photo-shielded on the top and

bottom by a metal layer to prevent fluctuations in the characteristics due to light incident to the transistors.

However, light diffracted by the edges of the photo-shielding film or light incident to the panel from an angle

may stray and reflect from the edge of the photo-shielding metal and penetrate to the TFT portion. In this case,

light absorption by the bulk generates electron-hole pairs and causes the phenomenon where the pixel potential

changes.

When light incident to a pixel transistor is absorbed by the transistor bulk, electron-hole pairs are generated

inside the bulk by photoelectric conversion. For the electron-hole pairs generated in the depletion layer on the

pixel electrode side of the TFT, the electric field inside the depletion layer causes the electrons to migrate

toward the pixel electrode side and the holes to migrate toward the drain side. When electrons migrate toward

the pixel electrode side, the pixel potential on which the video signal is written fluctuates and the electric field

applied to the liquid crystal changes. If the incident light intensity increases, causing the generated electron-

hole pairs to increase and the amount of electrons flowing to the pixel electrode to exceed a certain level, the

normal hold voltage cannot be maintained and the picture quality may deteriorate.

This phenomenon is not progressive, so there is no effect on long-term reliability. However, it is an index

indicating the characteristics limit with respect to the incident light quantity.

5.3.1.3 Light Exposure Test Method

Fig. 5-16 shows the optical system of the device used in the light exposure test of projector LCDs. The light

source is the high-voltage mercury (UHP) lamp generally used in projectors, and changes in the optical

characteristics are evaluated by irradiating light so that the condensing lens condenses light evenly to the LCD

panel surface.

The main acceleration factors in the light exposure test are the incident light quantity and panel temperature, and

each of them can be controlled.

5-19

Evaluated sample

UV/IR-cut filter

Fly’s eye lens

Light source(UHP lamp)

Fig. 5-16 Light Exposure Test System

5.3.2 Handling LCDs

5.3.2.1 Electrostatic Countermeasures

TFT-LCD panels are easily damaged by static charges, so be sure to take the following protective measures.

a) Use non-chargeable gloves, or simply use bare hands.

b) Use a wrist strap when directly handling panels.

c) Do not touch any electrodes of a panel.

d) Wear non-chargeable clothes and conductive shoes.

e) Install conductive mats on the work floor and worktable.

f) Keep panels away from any charged materials.

g) Use ionized air to discharge the panels when handling.

5.3.2.2 Dust and Dirt Countermeasures

a) Operate in a clean environment.

b) When delivered, the panel surface (glass) is covered by a protective sheet. Take appropriate measures to

prevent static charges, and then peel off the protective sheet carefully so as not to damage the glass surface.

c) Do not touch the glass surface, as the surface is easily scratched. When cleaning is required, gently wipe the

glass surface with a clean-room wiper moistened with isopropyl alcohol. Be careful not to leave a stain on

the surface.

d) Use ionized air to blow dust off the glass surface.

5.3.2.3 Notes on Light Resistance

As described in section 5.3.1.2, the liquid crystal and other organic materials used in LCD panels may degrade

due to photochemical reactions, possibly resulting in irreversible changes to the display characteristics. Assuming a

5-20

constant quantity of light, the dominant factors that determine the progression of the photochemical reactions are

short wavelength light (UV cut filter characteristics) and temperature. Mount an appropriate UV cut filter between

the light source and the LCD panel to suppress the progression of photochemical reactions. (A filter with a half-

value wavelength of 434 nm or is recommended.)

In addition, use an appropriate IR cut filter and take care to cool the LCD panel in order to lower the temperature

of the panel as much as possible. Also take sufficient care to drive the panel before irradiating light in order to

stabilize initial drive operation.

5.3.2.4 Other Handling Precautions

a) Avoid twisting or bending flexible print circuits especially at the connecting region because they are easily

deformed.

b) Do not drop panels.

c) Do not twist or bend panels or panel frames.

d) Keep panels away from heat sources.

e) Do not dampen panels with water or other solvents.

f) Avoid storing or using panels at a high temperature or high humidity, as this may adversely affect the panel

characteristics.

g) The minimum bending radius of flexible print circuits and the screw tightening torque when mounting

panels are specified for each device. For details, see the product specifications.

h) Use filters as appropriate to protect panels.

i) Do not apply pressure to panel locations (cover, etc.) other than the mounting holes.

j) Be sure to dispose of LCD panels as industrial waste in accordance with related laws and regulations.

5-21

5.4 Quality Assurance of Bare Die

Quality specifications for bare die products shall be decided together with the customer in accordance with

“JEITA EDR-4703A: Quality Guidelines for Bare Dies.” Items that should be kept in mind when purchasing bare

die products are described below.

(1) Electrical characteristics assurance and reliability verification

Electrical characteristics assurance and reliability verification of bare dies are categorized as shown in Table

5-1 specified by EDR-4703A. In principle, the Sony Semiconductor Business Unit ships PD. When purchase of

KTD is desired, thorough discussions must be held with the customer based on the specific demands for

assurance and verification items.

Please understand that for KGD to satisfy the same characteristics assurance and reliability verification as

package products requires significant facility investment (final inspection equipment, burn-in equipment, etc.),

and is also technically difficult.

Table 5-1 EDR-4703A Bare Die Reliability Verification and Characteristics Assurance Matrix

Functional tests

Reliability

Simplified test (DC and simplified function tests only)

Assurance covers most of the functions except analogue characteristics, at-speed

performance, and functional verification over the assured

operational temperature range.

The equivalent test to that of the

packaged device (Design-based

assurance is also acceptable.)

EFR of the bare die is verified to be similar to that of the packaged device by conducting the equivalent lifetime test to the packaged device.

N/A

KTD

(Level 2)

KGD

(Level 1)

Lifetime test or EFR verification has not been performed. Or EFR is inferior to that of the packaged devices.

PD

(Level 3)

KTD

(Level 2)

KTD

(Level 2)

Note 1) KGD (Known Good Die), KTG (Known Tested Die), PD (Probed Die)

Note 2) The above table is subject to change, so be sure to check the JEITA technical standards.

(2) Other main points to be kept in mind

When storing bare die products, the ambient storage conditions and the allowable number of storage

days are restricted both in the unopened condition and after opening the packing. Be sure to observe the

conditions prescribed in the specifications.

Scratches and other physical damage, contamination, and electrostatic discharge have fatal effects on

quality, so sufficient care should be taken when handling bare die products.

Bare die products cannot be marked with identifying information like package products. This makes it

difficult to clarify the affected range in the event of a quality problem. Customers are requested to

5-22

cooperate with management systems or other means capable of ensuring traceability.

The returned product format, analyzable range and other items concerning complaint items shall be

agreed upon through advance discussions.

5-23

5.5 Product Name and Lot Indications

The product name and lot indications used for products manufactured by the Sony Semiconductor Business Unit

(Sony Semiconductor products) are as follows.

(1) Product Name Indications

■■□□ ■■■□□ □ □□ － □－ □ － □□

Taping code

Special lead code

Classification, etc.

Package code

Version code

Product number

Category

■: Essential

□: Optional Table 5-2 Category Table

Category Contents

1T Super-mini variable capacitor, super-small mini variable capacitor, mini variable capacitor

2SK Silicom transistor, FET

3SK MES FET

CXA Bipolar/MOS analog

CXB Bipolar digital

CXD MOS logic, MOS gate array, ASIC microcomputer

CXG GaAs integrated circuit

CXJ Other module products

CXK Memory related

CXM Multichip module

CXN Bluetooth module products, Transfer JET module products and related products

CXP

16-bit microcomputers (SPC-A1), microcomputers for specific applications, mask ROM

versions, 4-bit and 8-bit microcomputers other than those listed to the left, 16-bit

microcomputers (SPC900)

CXQ 2nd source microcomputers

CXR RISC related

DCX X-ray sensor

DM Magnetoresistance elements

5-24

Category Contents

DS Optical engines

DS- Optical engine service parts

ECX Organic EL

GXB GPS module products

ICX CCD image sensor

ILX CCD linear sensor

IMX CMOS image sensor

ISX CMOS image sensor SoC (System On Chip)

IU CCD lens module / CMOS lens module

IUS Camera module

IWF Wafer substrates to be supplied for a fee

JSX Mounting business products

LCX High-temperature LCD

MCB Camera module (sensor + ISP)

MXC MEMS chip

MXL MEMS module (optical system)

MXR MEMS module (RF system)

MXS MEMS module (sensor system)

PHD Photodiode

RCX High-temperature process LCD-related products

SAS Optical communications module

SGH HEMT

SGM MES FET

SLD Laser diode (basic)

SLG Laser diode (multibeam VCSEL)

SLK Laser coupler and other light integrating elements

SLL LED related

SLN Laser diode (frame)

SLP Photodiodes using compound semiconductors

SLU Laser diode (application)

SXRD Reflective LCOS

5-25

(2) Lot indications

Lot numbers are comprised of seven digits representing the year and week of manufacture, a serial code and a

code indicating the assembly location.

０ １５ Ａ０１ Ｅ

□ □□ □□□ □

Assembly location code (1 digit). Print the code for the assembly location where the sealing process was performed.

Serial code (3 digits). Print the alphabet characters corresponding to the product name unit serial number within the site.

Week of manufacture (2 digits). Print the number from 01 to 53 corresponding to the week when marked as calculated from the start of the year.

Year of manufacture (1 digit). Print the number from 0 to 9 corresponding to the last digit of the western year.

When seven digits cannot be printed due to printing space limitations, the printed characters are omitted in the

following priority order.

０ １５ Ａ０１ Ｅ

□ □□ □□□ □

↑ ↑ ↑

(2) (1) (3)

(1) Omit the week of manufacture.

(2) Note the year of manufacture using binary code.

(3) Omit the assembly location code.