Chap. 9 Instruction Set ArchitectureChap. 9 Instruction Set Architecture

Computer Architecture ConceptsComputer Architecture Concepts

Instruction format– Opcode field

• Specify the operation to be performed

– Address field• Provide either a memory address or an address for

selecting a processor register

– Mode field• Specify the way the address field is to be interpreted

Computer Architecture ConceptsComputer Architecture Concepts

Basic computer operation cycle– Fetch the instruction from memory into a

control register– Decode the instruction– Locate the operands used by the instruction– Fetch operands from memory (if necessary)– Execute the operation in processor registers– Store the results in the proper place– Go back to step 1 to fetch the next instruction

Computer Architecture ConceptsComputer Architecture Concepts

Register Set– All registers in the CPU that are

accessible to the programmer• Mentioned in assembly lang.• cf) register file for -program, pipeline

registers

– Ex)• Processor status register (PSR)

– C, N, V, and Z from ALU

• Stack pointer (SP)

Operand AddressingOperand Addressing

Fetching operand within instruction– Implied address vs. explicit address

The number of explicitly addressed operands per instruction– Three-address instructions– Two-address instructions– One-address instructions– Zero-address instructions

long instructions

Many steps of executions

Operand AddressingOperand Addressing

Three-address Instructions– Memory-to-memory architecture– Ex) X=(A+B)(C+D)

• ADD T1, A, B M[T1]M[A]+M[B]• ADD T2, C, D M[T2]M[C]+M[D]• MUL X, T1, T2 M[X]M[T1]+M[T2]

• ADD R1, A, B R1M[A]+M[B]• ADD R2, C, D R2M[C]+M[D]• MUL X, R1, R2 M[X]R1+R2

Operand AddressingOperand Addressing

Three-address Instructions– register-to-register (load/store) architecture

• Allow only one memory address– “load”, “store” instructions

– Ex) X=(A+B)(C+D)• LD R1,A R1M[A]• LD R2,B R2M[B]• ADD R3,R1,R2 R3R1+R2• LD R1,C R1M[C]• LD R2,D R2M[D]• ADD R1,R1,R2 R1R1+R2• MUL R1,R1,R3 R1R1*R3• ST X,R1 M[X]R1

Operand AddressingOperand Addressing

Two-address Instructions– Ex) X=(A+B)(C+D)

• MOVE T1, A M[T1]M[A]• ADD T1,B M[T1]M[T1]+M[B]• MOVE X,C M[X]M[C]• ADD X,D M[X]M[X]+M[D]• MUL X,T1 M[X]M[X]+M[T1]

– If register-memory architecture• ADD R1,A R1R1+M[A]

Operand AddressingOperand Addressing

One-address Instructions– Single-accumulator architecture

• A special register called “accumulator” for obtaining one of the operands and as the location of the result

– Ex) X=(A+B)(C+D)• LD A ACCM[A]• ADD B ACCACC+M[B]• ST X M[X]ACC• LD C ACCM[C]• ADD D ACCACC+M[D]• MUL X ACCACC*M[X]• ST X M[X]ACC

Operand AddressingOperand Addressing

Zero-address Instructions– Stack architecture– Ex) X=(A+B)(C+D)

• PUSH A TOSM[A]• PUSH B TOSM[B]• ADD TOSTOS+TOS-1• PUSH C TOSM[C]• PUSH D TOSM[D]• ADD TOSTOS+TOS-1• MUL TOSTOS*TOS-1• POP X M[X]TOS

Stack architectureStack architecture

Processing expressions– Postfix expression

• reverse Polish notation (RPN)• Ex) (A+B)*C+(D*E) A B + C * D E * +

3

1 2

Stack architectureStack architecture

– Program for evaluating “A B + C * D E * +”• PUSH A• PUSH B• ADD• PUSH C• MUL• PUSH D• PUSH E• MUL• ADD

Addressing ModesAddressing Modes

Implied mode Immediate mode Register and register-indirect mode Direct addressing mode Indirect addressing mode Relative addressing mode Indexed addressing mode Base-register mode

Addressing ModesAddressing Modes

Implied mode– The operand is specified implicitly in

the definition of the opcode.Immediate mode

– The actual operand is specified in the instruction itself.

Addressing ModesAddressing Modes

Register-indirect mode– For addressing each of elements in

arrays– Ex)

• ADD (R1)+, 3 M[R1]M[R1]+3, R1R1+1

Addressing ModesAddressing Modes

Direct addressing mode

Addressing ModesAddressing Modes

Indirect addressing mode– Addr. Field of instruction

• Address at which the effective addr. is stored in memory

• If indirect mode, …

Addressing ModesAddressing Modes

Indexed addressing mode– Effective address

= addr. field of instr. + index register (offset)

Base-register mode– Effective address

= base register + addr. field of instr. (offset)

Addressing Modes (Summary)Addressing Modes (Summary)

Instruction Set ArchitectureInstruction Set Architecture

RISC (Reduced Instruction Set Computer) Architectures– Memory accesses are restricted to load and store instruction, and

data manipulation instructions are register to register.

– Addressing modes are limited in number.

– Instruction formats are all of the same length.

– Instructions perform elementary operations

CISC (Complex Instruction Set Computer) Architectures– Memory access is directly available to most types of instruction.

– Addressing mode are substantial in number.

– Instruction formats are of different lengths.

– Instructions perform both elementary and complex operations.

Instruction Set ArchitectureInstruction Set Architecture

3 categories of elementary instructions– Data transfer instructions– Data manipulation instructions– Program control instructions