chalmers university of technology flexsoc seminar series – 2004-03-15page 1 power estimation...
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Chalmers University of Technology
FlexSoC Seminar Series – 2004-03-15 Page 1
Power Estimation
FlexSoc Seminar Series – 2004-03-15
Daniel [email protected]
Chalmers University of Technology
FlexSoC Seminar Series – 2004-03-15 Page 2
Outline
• Why power estimation?
• Power macromodeling
• Future directions for power estimation
Most pictures (non-Matlab-plots) are courtesy of Intel Corp.
Chalmers University of Technology
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Why Power Estimation? (Conference-Presentation Answer)
• Heat removal is expensive (fans, heat-sinks)
• Energy stored in battery is limited
• Power delivery is expensive (area, reliability, verification, packaging)
Chalmers University of Technology
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Why Power Estimation?(FlexSoC Answer)
• Compiler optimizations
• “Designing” range of chips for certain applications
• ??? You tell me!
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Power Reduction Techniques
• Activity reduction• Supply voltage scaling• Leakage reduction (cut-off techniques, stacking
etc)
But, by how much does the power of a specific design needs to be reduced? And which power mechnism constitutes a problem?
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Power Dissipation Basics
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From Where Does thePower Increase Stem?
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Increased Integration
120 billion transistorsper wafer!!!
SRAM chips fabricatedon a 300mm wafer
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Heat Removal (package)
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Architecture Level Power Macromodeling à la Wattch
• P=0.1*Psw(αmax)+Psw(α,state)
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What Do We Want from aPower Estimation Methodology?
• Accurate
• Fast
• Provide information for power reduction
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Levels of Power Estimation
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Why Use Macro Models?
• Circuit simulations excessively time- and memory-consuming
• Designers need to run long traces to compare solutions (only possible using macro models)
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Estimation Tool Run-Times
Run-time HSpice* PowerMill * Macro**
16b Han-Carlson
12d14h 8h49m(30x)
6m43s(2700x / 80x)
8b Multiplier 29d6h 17h37m(40x)
9m42s(4300x / 100x)
32b Multiplier N/A 14d10h 2h2m(N/A / 170x)
* Highly optimized code by team of software designers** Highly unoptimized C++ code by one overworked circuit designer
Chalmers University of Technology
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Precision
• Circuit simulations give full or close to full precision (depending on extraction)
• Macro modeling can give range of precision levels (with a maximum precision determined by methodology)
• Macro model precision is limited by the characterization
Chalmers University of Technology
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Power Estimation Flow
• Characterization– Requires lower level simulations– Has to support maximum precision– One-time only, can afford to be slow
• Estimation– Macro-model only– Can support multiple levels of precision– Frequently run, has to be fast
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Switching Power(Circuit Level)
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Switching Power(Early Power Macro Models)
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Switching Power(VLSI Research Group Style)
Equation-based 0→1 tracking, even for intermediate nodes depending on accuracy
• Physical model based on nodal capacitances and voltage swings
• Enables semi-automatic characterization
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Short-Circuit Power(Circuit Level)
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Short-Circuit Power(Macro Model)
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Subthreshold-Leakage Power
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Subthreshold-Leakage Power(Circuit Level)
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Subthreshold-Leakage Power
• Stacking effects
• Long settling times
• …?
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Subthreshold-Leakage Power(Macro Model)
• Equation-based model considering on- and off-states of the transistors constituting the gate
• Enables semi-automatic characterization
• Possible extensions for stacking
• Possible extensions for multiple clock-cycle settling times
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Gate-Leakage Power(Circuit Level)
• Enough equations and theory to use up the entire FlexSoC seminar series
Chalmers University of Technology
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Gate-Leakage Power(Macro Model)
• Equation-based model considering on- and off-states of the transistors constituting the gate
• Enables semi-automatic characterization
• Complications include leakage paths originating in one gate and ending up in another gate
Chalmers University of Technology
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Separating PowerDissipation Mechanisms
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Leakage Power Increase
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Active vs. Leakage Power
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Separation of Mechanisms(Rise- and Fall-Times)
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Separation of Mechanisms(Supply-Voltage Scaling)
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Mismatch for Methodologies without a Leakage Component
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Mismatch for Methodologies without Leakage or Dynamica Frequency and Supply Scaling
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Complex Gates
• Most circuit-level models are only valid for a single transistor or an inverter
• Macromodels have to be able to account for large components, 32b multipliers etc
• Complexity increases super-linearly with the number of transistors in the component
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Non-Conforming Components
There are classes of components which do not conform to the presented basic models:
• Clock generators
• Memories
• etc
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Clock Generation (DLL)
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Clock Generators (Delay Element)
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Non-Linear Frequency Dependence for Certain Types of Components
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Dynamic Precision
• Different architectures might impose different precision requirements for different components (static during estimation)
• Different operating modes might warrant different need for precision (changes during estimation)
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Conclusions
• Power estimation is not simply about averaging the current through the supplies
• Circuit simulation is too slow
• A lot of research is needed to enable high-level power estimation for future designs: some in mechanism modeling but more importantly in the estimation framework