ch7

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Microprogrammed Control

MICROPROGRAMMED CONTROL

• Control Memory

• Sequencing Microinstructions

• Microprogram Example

• Microinstruction Format

• Design of Control Unit

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COMPARISON OF CONTROL UNIT IMPLEMENTATIONSImplementation of Control Unit

I Opcode Address

Decoder

MappingLogic

Address control word

Control Memory

Control signals specify microoperations

Microprogrammed Control Unit

Control signals of ADD instruction specify sequence of microops:DR ← M[AR]AC ← AC + DR

Control signals of ADD instruction specify sequence of microops: DR ← M[AR]AC ← AC + DR

ADD D1T4: DR ← M[AR]D1T5: AC ← AC + DR, SC ← 0

Hardwired Control Unit

Control signals specify microoperations

15 14 13 12 11 - 0

3 x 8decoder

7 6 5 4 3 2 1 0

Controllogic gates

D0D

T

T

715

0

15 14 . . . . 2 1 04 x 16

decoder

4-bitsequence

counter(SC)

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Microprogrammed Control Implementation of Control Unit

READ ONLY MEMORY (ROM)

2k words(n bits/word)

n data input lines

n data output lines

k address lines

Read

Write

m x n ROM(m=2k)

k address input lines

n data output lines

Random Access Memory (RAM) Read Only Memory (ROM)

ROM Characteristics- Perform read operation only, write operation is not possible- Information stored in a ROM is made permanent during production

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MICROPROGRAMMED CONTROL UNIT

Sequencer: Logic circuit that determines the address of the next microinstruction

Controlword

Next addressgenerator

(sequencer)

Control address register(CAR)

Controlmemory(ROM)

Externalinput

Next-address information

Implementation of Control Unit

Microinstruction

Control Memory

:

Microinstruction

Microprogram

Microoperation codes Next-address information

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MICROINSTRUCTION SEQUENCING

Fetch routine

Indirect routine

Execute routine

Control Memory

:

:

CAR

- Microinstructions are stored in control memory in groups, each group specifies a routine

Sequencing

- Each computer instruction has its own microprogram routine that generates the microoperations needed to execute the instruction

- Address sequencing of control memory is capable of:- Sequencing the microinstructions within the routine- Branching from one routine to another based on the microinstruction

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Sequencing Capabilities Required in a Control Memory- Incrementing of the control address register- Unconditional and conditional branches- A facility for subroutine call and return- A mapping process from the bits of the machine

instruction to an address for control memory

Sequencing

Instruction code

Mappinglogic

Multiplexers

Control memory (ROM)

Subroutineregister(SBR)

Branchlogic

Statusbits

Microoperations


Incrementer

MUXselect

select a statusbit

Branch address

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Sequencing

Instruction code

Mappinglogic

Multiplexers



Branchlogic

Statusbits

Microoperations


MUXselect

select a statusbit

Branch address

Incrementer

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Sequencing

Instruction code

Mappinglogic

Multiplexers



Branchlogic

Statusbits

Microoperations


Incrementer

MUXselect

select a statusbit

Branch address

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Sequencing

Instruction code

Mappinglogic

Multiplexers



Branchlogic

Statusbits

Microoperations


Incrementer

MUXselect

select a statusbit

Branch address

10





Sequencing

Instruction code

Mappinglogic

Multiplexers



Branchlogic

Statusbits

Microoperations


Incrementer

MUXselect

select a statusbit

Branch address

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MICROINSTRUCTION SEQUENCINGSequencing

Instruction code

Mappinglogic

Multiplexers



Branchlogic

Statusbits

Microoperations


Incrementer

MUXselect

select a statusbit

Branch address

Problem 7-5: The system shown above uses a control memory of 1024 words of32 bits each. The microinstruction has three fields as shown in the diagram. Themicrooperation field has 16 bits.a. How many bits are there in the branch address field and the select field?b. If there are 16 status bits in the system, how many bits of the branch logic are

used to select a status bit?c. How many bits are left to select an input for the multiplexers?

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MAPPING OF INSTRUCTIONS

Microinstructionaddress

1 0 1 1 AddressOP-code

Mapping bits 0 x x x x 0 0

0 1 0 1 1 0 0

MachineInstruction

Sequencing

OP-codes of InstructionsAND ADDLDA

000000010010

Address

0 0000 00

0 0001 00

0 0010 00

Mapping bits 0 xxxx 00AND Routine

ADD Routine

LDA Routine

Controlmemory

4-bit opcode

7-bit address (for control memory

of 128 words)

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MAPPING OF INSTRUCTIONS

Microinstruction address (11 bits)

x x x x x xOp-code (6 bits)

0 0 x x x x x x 0 0 0

Sequencing

Problem 7-8: Formulate a mapping procedure that provides eightconsecutive microinstructions for each routine. The operation codehas six bits and the control memory has 2048 words.

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MICROPROGRAM EXAMPLEMicroprogram

Computer Configuration

MUX

AR10 0

PC10 0

Address Memory2048 x 16

MUX

DR15 0

Arithmeticlogic andshift unit

AC15 0

SBR6 0

CAR6 0

Control memory128 x 20

Control unit

AC

DRPC

DR

AC

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MICROINSTRUCTION FORMATMicroprogram

EA is the effective addressSymbol OP-code Description

ADD 0000 AC ← AC + M[EA]BRANCH 0001 if (AC < 0) then (PC ← EA)STORE 0010 M[EA] ← ACEXCHANGE 0011 AC ← M[EA], M[EA] ← AC

Sample machine instructions

Machine instruction format

I Opcode15 14 11 10

Address0

Microinstruction Format

F1 F2 F3 CD BR AD3 3 3 2 2 7

F1, F2, F3: Microoperation fieldsCD: Condition for branching BR: Branch fieldAD: Address fieldMicrooperations Next-address information

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MICROINSTRUCTION FIELDS DESCRIPTION - F1,F2,F3Microprogram

Two simultaneous microoperations:

DR M[AR] with F2 = 100

and PC PC + 1 with F3 = 101

F1 Microoperation Symbol000 None NOP001 AC ← AC + DR ADD010 AC ← 0 CLRAC011 AC ← AC + 1 INCAC100 AC ← DR DRTAC101 AR ← DR(0-10) DRTAR110 AR ← PC PCTAR111 M[AR] ← DR WRITE

F2 Microoperation Symbol000 None NOP001 AC ← AC - DR SUB010 AC ← AC ∨ DR OR011 AC ← AC ∧ DR AND100 DR ← M[AR] READ101 DR ← AC ACTDR110 DR ← DR + 1 INCDR111 DR(0-10) ← PC PCTDR

F3 Microoperation Symbol000 None NOP001 AC ← AC ⊕ DR XOR010 AC ← AC’ COM011 AC ← shl AC SHL100 AC ← shr AC SHR101 PC ← PC + 1 INCPC110 PC ← AR ARTPC111 Reserved

F1 F2 F3 CD BR AD

Microinstruction

Microoperation fields = 000 100 101

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MICROINSTRUCTION FIELDS DESCRIPTION - CD, BR

CD Condition Symbol Comments00 Always = 1 U Unconditional branch01 DR(15) I Indirect address bit10 AC(15) S Sign bit of AC11 AC = 0 Z Zero value in AC

Microprogram

F1 F2 F3 CD BR AD

Microinstruction

BR Symbol Function00 JMP CAR ← AD if condition = 1

CAR ← CAR + 1 if condition = 001 CALL CAR ← AD, SBR ← CAR + 1 if condition = 1

CAR ← CAR + 1 if condition = 010 RET CAR ← SBR (Return from subroutine)11 MAP CAR(2-5) ← DR(11-14), CAR(0,1,6) ← 0

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SYMBOLIC MICROINSTRUCTIONS• Symbols are used in microinstructions as in assembly language• A symbolic microprogram can be translated into its binary equivalent

by a microprogram assembler

Sample Formatfive fields: label: micro-ops CD BR AD

Microprogram

Label: may be empty or may specify a symbolicaddress terminated with a colon

Micro-ops: consists of one, two, or three symbols separated by commas

CD: one of {U, I, S, Z}, where U: Unconditional BranchI: Indirect address bitS: Sign of ACZ: Zero value in AC

BR: one of {JMP, CALL, RET, MAP}

AD: one of {Symbolic address, NEXT, empty}

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SYMBOLIC MICROPROGRAM - FETCH ROUTINE -

Binary microprogram translated by an assembler

1000000 110 000 000 00 00 10000011000001 000 100 101 00 00 10000101000010 101 000 000 00 11 0000000

Binaryaddress F1 F2 F3 CD BR AD

Microprogram

Symbolic microprogram for the fetch routine:ORG 64PCTAR U JMP NEXT READ, INCPC U JMP NEXT DRTAR U MAP

FETCH:

During the fetch routine, read an instruction from memory,map the opcode to microinstruction address, and update PC

AR ← PCDR ← M[AR], PC ← PC + 1AR ← DR(0-10), CAR(2-5) ← DR(11-14), CAR(0,1,6) ← 0

Sequence of microoperations for the fetch routine:

CD Symbol00 U01 I10 S11 Z

BR Symbol00 JMP01 CALL10 RET11 MAP

F1 Symbol000 NOP001 ADD010 CLRAC011 INCAC100 DRTAC101 DRTAR110 PCTAR111 WRITE

F2 Symbol000 NOP001 SUB010 OR011 AND100 READ101 ACTDR110 INCDR111 PCTDR

F3 Symbol000 NOP001 XOR010 COM011 SHL100 SHR101 INCPC110 ARTPC111

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SYMBOLIC MICROPROGRAM• Control Memory: 128 20-bit words• First 64 words: Routines for the 16 machine instructions• Last 64 words: Used for other purpose (e.g., fetch routine and other routines)• Mapping: Opcode XXXX into 0XXXX00, the first address for the 16 routines are

0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60

Microprogram

ORG 0NOPREADADD

ORG 4NOPNOPNOPARTPC

ORG 8NOPACTDRWRITE

ORG 12NOPREADACTDR, DRTACWRITE

ORG 64PCTARREAD, INCPCDRTARREADDRTAR

IUU

SUIU

IUU

IUUU

UUUUU

CALLJMPJMP

JMPJMPCALLJMP

CALLJMPJMP

CALLJMPJMPJMP

JMPJMPMAPJMPRET

INDRCTNEXTFETCH

OVERFETCHINDRCTFETCH

INDRCTNEXTFETCH

INDRCTNEXTNEXTFETCH

NEXTNEXT

NEXT

ADD:

BRANCH:

OVER:

STORE:

EXCHANGE:

FETCH:

INDRCT:

Label Microops CD BR AD

Partial Symbolic Microprogram

Symbol Opcode DescriptionADD 0000 AC ← AC + M[EA]BRANCH 0001 if (AC < 0) then (PC ← EA)STORE 0010 M[EA] ← ACEXCHANGE 0011 AC ← M[EA], M[EA] ← AC

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Microprogrammed Control Microprogram

Address Binary MicroinstructionMicro Routine Decimal Binary F1 F2 F3 CD BR AD

ADD 0 0000000 000 000 000 01 01 10000111 0000001 000 100 000 00 00 00000102 0000010 001 000 000 00 00 10000003 0000011 000 000 000 00 00 1000000

BRANCH 4 0000100 000 000 000 10 00 00001105 0000101 000 000 000 00 00 10000006 0000110 000 000 000 01 01 10000117 0000111 000 000 110 00 00 1000000

STORE 8 0001000 000 000 000 01 01 10000119 0001001 000 101 000 00 00 000101010 0001010 111 000 000 00 00 100000011 0001011 000 000 000 00 00 1000000

EXCHANGE 12 0001100 000 000 000 01 01 100001113 0001101 001 000 000 00 00 000111014 0001110 100 101 000 00 00 000111115 0001111 111 000 000 00 00 1000000

FETCH 64 1000000 110 000 000 00 00 100000165 1000001 000 100 101 00 00 100001066 1000010 101 000 000 00 11 0000000

INDRCT 67 1000011 000 100 000 00 00 100010068 1000100 101 000 000 00 10 0000000

BINARY MICROPROGRAM

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MICROPROGRAM

Problem 7-14: The following is symbolic microprogram for an instruction in the computer defined in Chapter 7.

ORG 40NOP S JMP FETCHNOP Z JMP FETCHNOP I CALL INDIRECTARTPC U JMP FETCH

a. Specify the operation performed when the instruction is executed.b. Convert the four microinstructions into their equivalent binary form.





BR Symbol00 JMP01 CALL10 RET11 MAP

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MICROPROGRAM

Problem 7-16: Write a symbolic microprogram routine for the following instruction in the computer defined in Chapter 7.

Symbol Opcode Symbolic Function DescriptionSUB 0101 AC ← AC – M [EA] Subtract

ORG 20NOP I CALL INDIRECTREAD U JMP NEXTSUB U JMP FETCH

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Microprogrammed ControlDESIGN OF CONTROL UNIT

- DECODING OF MICROOPERATION FIELDS -

Design of Control Unit

3 x 8 decoder

7 6 5 4 3 2 1 0

F1

3 x 8 decoder

7 6 5 4 3 2 1 0

F2

3 x 8 decoder

7 6 5 4 3 2 1 0

F3




FromPC

From

Select 0 1Multiplexers

ARLoadClock

DR

TAR

PCTA

R

DR(0-10)

Arithmeticlogic andshift unit

ANDADD

ACLoad

AC

DRDRTAC F1 Microoperation Symbol101 AR ← DR(0-10) DRTAR110 AR ← PC PCTAR

F1 Microoperation Symbol001 AC ← AC + DR ADD100 AC ← DR DRTAC

F2 Microoperation Symbol011 AC ← AC ∧ DR AND

Problem 7-19: Show how outputs 5 and 6 of decoder F3 in the above figure are to be connected to the program counter PC.

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MICROPROGRAM SEQUENCERDesign of Control Unit

3 2 1 0S1 MUX1

External(MAP)

SBRLoad

Incrementer

CAR

Inputlogic

I0

T

MUX2Select

1ISZ

Test

Clock

Control memory

Microops CD BR AD

L

I1S0

. . .. . .

S1S0 Address Source00 CAR + 101 AD (JMP or CALL)10 SBR (Return)11 MAPBranch

Logic

CD

BR

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MICROPROGRAM SEQUENCERDesign of Control Unit

3 2 1 0S1 MUX1

External(MAP)

SBRLoad

Incrementer

CAR

Inputlogic

I0

T

MUX2Select

1ISZ

Test

Clock

Control memory

Microops CD BR AD

L

I1S0

. . .. . .

S1S0 Address Source00 CAR + 101 AD (JMP or CALL)10 SBR (Return)11 MAP

CD

BR


BR Symbol T Function00 JMP 1 CAR ← AD

0 CAR ← CAR + 101 CALL 1 CAR ← AD, SBR ← CAR+1

0 CAR ← CAR + 110 RET X CAR ← SBR11 MAP X CAR ← External

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MICROPROGRAM SEQUENCER- CONDITION AND BRANCH CONTROL -

Design of Control Unit

S1 = I1S0 = I1I0 + I1’T

L = I1’I0T

InputlogicI0

I1

TMUX2Select

1I

SZ

Test

CD field from Control Memory

From CPU

BR fieldfromControl Memory

L (load SBR with CAR + 1) for subroutine Call

S0S1

for next addressselection

L

BR Input MUX 1 Load SBRField I1I0T Meaning Source of Address S1S0 L

00 000 next CAR+1 0 0 000 001 JMP AD 0 1 001 010 next CAR+1 0 0 001 011 CALL AD and SBR CAR+1 0 1 110 10x RET SBR 1 0 011 11x MAP External 1 1 0

Input LogicS1S0 Address Source00 CAR + 101 AD (JMP or CALL)10 SBR (Return)11 MAP

ch7

Documents

ac ac dr2 control signals

address lines

microprogram routine

routine microinstructions

logic circuit

microinstruction sequencer

x n rom

indirect routine