William Stallings William Stallings Computer Organization

d A hit tand Architecture

Chapter 11CPU StructureCPU Structureand Function

CPU StructureCPU Structure

CPU must:Fetch instructionsInterpret instructionsFetch dataProcess dataProcess dataWrite data

RegistersRegisters

CPU must have some working space (temporary storage)Called registersNumber and function vary between processor d idesignsOne of the major design decisionsTop level of memory hierarchy

User Visible RegistersUser Visible Registers

General PurposeDataAddressCondition Codes

G l P R i t (1)General Purpose Registers (1)

May be true general purposeMay be restrictedMay be used for data or addressingData

Accumulator

AddressingSegment

G l P R i t (2)General Purpose Registers (2)

Make them general purposeIncrease flexibility and programmer optionsIncrease instruction size & complexity

Make them specializedS ll (f t ) i t tiSmaller (faster) instructionsLess flexibility

How Many GP Registers?How Many GP Registers?

Between 8 - 32Fewer = more memory referencesMore does not reduce memory references and takes up processor real estateSee also RISC

How big?How big?

Large enough to hold full addressLarge enough to hold full wordOften possible to combine two data registers

C programmingdouble int a;long int a;

Condition Code RegistersCondition Code Registers

Sets of individual bitse.g. result of last operation was zero

Can be read (implicitly) by programse.g. Jump if zero

( ll ) b bCan not (usually) be set by programs

Control & Status RegistersControl & Status Registers

Program CounterInstruction Decoding RegisterMemory Address RegisterMemory Buffer Register

Revision: what do these all do?

Program Status WordProgram Status WordA set of bitsIncludes Condition CodesSign of last resultSign of last resultZeroCarryCarryEqualOverflowOverflowInterrupt enable/disableSupervisorSupervisor

Supervisor ModeSupervisor Mode

Intel ring zeroKernel modeAllows privileged instructions to executeUsed by operating systemNot available to user programs

Other RegistersOther Registers

May have registers pointing to:Process control blocks (see O/S)Interrupt Vectors (see O/S)

N B CPU design and ope ating s stem designN.B. CPU design and operating system design are closely linked

Example Register OrganizationsOrganizations

Foreground ReadingForeground Reading

Stallings Chapter 11Manufacturer web sites & specs

Instruction CycleInstruction Cycle

RevisionStallings Chapter 3

Indirect CycleIndirect Cycle

May require memory access to fetch operandsIndirect addressing requires more memory accessesCan be thought of as additional instruction

b lsubcycle

Instruction Cycle with IndirectInstruction Cycle with Indirect

Instruction Cycle State DiagramDiagram

Data Flow (Instruction Fetch)Data Flow (Instruction Fetch)

Depends on CPU designIn general:

FetchPC contains address of next instructionAddress moved to MARAddress placed on address busControl unit requests memory readResult placed on data bus copied to MBR then to IRResult placed on data bus, copied to MBR, then to IRMeanwhile PC incremented by 1

Data Flow (Data Fetch)Data Flow (Data Fetch)

IR is examinedIf indirect addressing, indirect cycle is performed

Right most N bits of MBR transferred to MARC t l it t dControl unit requests memory readResult (address of operand) moved to MBR

Data Flow (Fetch Diagram)Data Flow (Fetch Diagram)

Data Flow (Indirect Diagram)Data Flow (Indirect Diagram)

Data Flow (Execute)Data Flow (Execute)

May take many formsDepends on instruction being executedMay include

Memory read/writeInput/OutputRegister transfersALU tiALU operations

Data Flow (Interrupt)Data Flow (Interrupt)

SimplePredictableC t PC d t ll ti ft i t tCurrent PC saved to allow resumption after interruptContents of PC copied to MBRSpecial memory location (e g stack pointer) loaded toSpecial memory location (e.g. stack pointer) loaded to MARMBR written to memoryPC loaded with address of interrupt handling routineNext instruction (first of interrupt handler) can be fetchedfetched

Data Flow (Interrupt Diagram)Data Flow (Interrupt Diagram)

PrefetchPrefetch

Fetch accessing main memoryExecution usually does not access main memoryCan fetch next instruction during execution of current instructionCalled instruction prefetch

Improved PerformanceImproved Performance

But not doubled:Fetch usually shorter than executionP f t h th i t ti ?Prefetch more than one instruction?

Any jump or branch means that prefetched instructions are not the required instructionsq

Add more stages to improve performance

PipeliningPipelining

Fetch instructionDecode instructionCalculate operands (i.e. EAs)Fetch operandsExecute instructionsWrite result

Overlap these operationsp p

Timing of PipelineTiming of Pipeline

Branch in a PipelineBranch in a Pipeline

Dealing with BranchesDealing with Branches

Multiple StreamsPrefetch Branch TargetLoop bufferBranch predictionDelayed branching

Multiple StreamsMultiple Streams

Have two pipelinesPrefetch each branch into a separate pipelineUse appropriate pipeline

Leads to bus & register contentionMultiple branches lead to further pipelines being p p p gneeded

Prefetch Branch TargetPrefetch Branch Target

Target of branch is prefetched in addition to instructions following branchKeep target until branch is executedUsed by IBM 360/91

Loop BufferLoop Buffer

Very fast memoryMaintained by fetch stage of pipelineCheck buffer before fetching from memoryVery good for small loops or jumpsc.f. cacheUsed by CRAY-1y

Branch Prediction (1)Branch Prediction (1)

Predict never takenAssume that jump will not happenAlways fetch next instruction 68020 & VAX 11/780VAX will not prefetch after branch if a page faultVAX will not prefetch after branch if a page fault would result (O/S v CPU design)

Predict always takenPredict always takenAssume that jump will happenAlways fetch target instruction

Branch Prediction (2)Branch Prediction (2)

Predict by OpcodeSome instructions are more likely to result in a jump than thersthan thersCan get up to 75% success

Taken/Not taken switchTaken/Not taken switchBased on previous historyGood for loopsGood for loops

Branch Prediction (3)Branch Prediction (3)

Delayed BranchDo not take jump until you have toRearrange instructions

Branch Prediction State DiagramDiagram

Foreground ReadingForeground Reading

Processor examplesStallings Chapter 11Web pages etc.