cdf drift chamber signal analyzer boardedg.uchicago.edu/~bogdan/fadc/doc/fadc_pres1.pdf ·...
TRANSCRIPT
![Page 1: CDF Drift Chamber Signal Analyzer Boardedg.uchicago.edu/~bogdan/FADC/doc/fadc_pres1.pdf · fadc_pres1.ppt Author: bogdan Created Date: 12/12/2002 1:40:32 PM](https://reader034.vdocuments.mx/reader034/viewer/2022050323/5f7cd2b351163d766c04d0e1/html5/thumbnails/1.jpg)
June 4-8, 2001 Valencia, Spain Mircea Bogdan, RT2001 1
CDF Drift Chamber Signal Analyzer Board
Bill AshmanskasMircea BogdanHenry Frisch
Aseet MukherjeeHarold Sanders
Mel Shochet
![Page 2: CDF Drift Chamber Signal Analyzer Boardedg.uchicago.edu/~bogdan/FADC/doc/fadc_pres1.pdf · fadc_pres1.ppt Author: bogdan Created Date: 12/12/2002 1:40:32 PM](https://reader034.vdocuments.mx/reader034/viewer/2022050323/5f7cd2b351163d766c04d0e1/html5/thumbnails/2.jpg)
June 4-8, 2001 Valencia, Spain Mircea Bogdan, RT2001 2
CDF Drift Chamber Signal Analyzer BoardDrift Chamber Signals – Fe55 pulses
Six-channel scope:® Designed for CDF Central
Calorimeter and COT crates;® Use of limited +5V power;® 4-buffer CDF/VME readout;® Bandwidth: 100MHz @ 3dB;® Input: [-150;+50]mV;® 8-Bit, 500MHz FADC;® Triggered by L1,L2 Accept;® Samples delayed/buffered in a
~5.5 us pipeline;® 132 ns CDF clock markers.
![Page 3: CDF Drift Chamber Signal Analyzer Boardedg.uchicago.edu/~bogdan/FADC/doc/fadc_pres1.pdf · fadc_pres1.ppt Author: bogdan Created Date: 12/12/2002 1:40:32 PM](https://reader034.vdocuments.mx/reader034/viewer/2022050323/5f7cd2b351163d766c04d0e1/html5/thumbnails/3.jpg)
June 4-8, 2001 Valencia, Spain Mircea Bogdan, RT2001 3
CDF Drift Chamber Signal Analyzer BoardBlock Diagram
® 6 A/D Channels;® 6 Data Buffers;® 495.8 MHz ECL
Crystal Oscillator;® Power Block:
+3.3V & +2.5V;® VME Interface with
Altera-EPM7128S.
![Page 4: CDF Drift Chamber Signal Analyzer Boardedg.uchicago.edu/~bogdan/FADC/doc/fadc_pres1.pdf · fadc_pres1.ppt Author: bogdan Created Date: 12/12/2002 1:40:32 PM](https://reader034.vdocuments.mx/reader034/viewer/2022050323/5f7cd2b351163d766c04d0e1/html5/thumbnails/4.jpg)
June 4-8, 2001 Valencia, Spain Mircea Bogdan, RT2001 4
CDF Drift Chamber Signal Analyzer BoardAnalog/Digital Conversion Channel
® Gain = 10;® Offset=-0.5V;® 500MHz FADC;® 2x8-Bit ECL Buses
at 250MHz;® 2x16-Bit TTL Buses
at 125MHz;® 5V/5.2V - 3A
DC/DC converters;® +/- 4.6V linear
power with LDO.
![Page 5: CDF Drift Chamber Signal Analyzer Boardedg.uchicago.edu/~bogdan/FADC/doc/fadc_pres1.pdf · fadc_pres1.ppt Author: bogdan Created Date: 12/12/2002 1:40:32 PM](https://reader034.vdocuments.mx/reader034/viewer/2022050323/5f7cd2b351163d766c04d0e1/html5/thumbnails/5.jpg)
June 4-8, 2001 Valencia, Spain Mircea Bogdan, RT2001 5
CDF Drift Chamber Signal Analyzer BoardData Buffer Channel
® Input: four 8-bit data banks, 2 ns apart, at 125 MHz;® ACEX1K30TC144-1 - splits data into a 64-bit bus at 62.5MHz® APEX 20K200BC356-1 - delays and buffers data for VME readout.
![Page 6: CDF Drift Chamber Signal Analyzer Boardedg.uchicago.edu/~bogdan/FADC/doc/fadc_pres1.pdf · fadc_pres1.ppt Author: bogdan Created Date: 12/12/2002 1:40:32 PM](https://reader034.vdocuments.mx/reader034/viewer/2022050323/5f7cd2b351163d766c04d0e1/html5/thumbnails/6.jpg)
June 4-8, 2001 Valencia, Spain Mircea Bogdan, RT2001 6
CDF Drift Chamber Signal Analyzer BoardTest pulse
Overlay:® Test pulse generated with
LeCroy9211 and sampled with a two-channel prototype board.