cd74hc137, cd74hct137, cd54hc237 ... - moodle.calvino.ge.it
TRANSCRIPT
1
Data sheet acquired from Harris SemiconductorSCHS146F
Features
• Select One of Eight Data Outputs- Active Low for CD74HC137 and CD74HCT137- Active High for ’HC237 and CD74HCT237
• l/O Port or Memory Selector
• Two Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13ns at VCC = 5V,15pF, TA = 25oC (CD74HC237)
• Fanout (Over Temperature Range)- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTLLogic ICs
• HC Types- 2V to 6V Operation- High Noise Immunity: NIL = 30%, NIH = 30%, of VCC
at VCC = 5V
• HCT Types- 4.5V to 5.5V Operation- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Description
The CD74HC137, CD74HCT137, ’HC237, andCD74HCT237 are high speed silicon gate CMOS decoderswell suited to memory address decoding or data routingapplications. Both circuits feature low power consumptionusually associated with CMOS circuitry, yet have speedscomparable to low power Schottky TTL logic.
Both circuits have three binary select inputs (A0, A1 and A2)that can be latched by an active High Latch Enable (LE)signal to isolate the outputs from select-input changes. A“Low” LE makes the output transparent to the input and thecircuit functions as a one-of-eight decoder. Two OutputEnable inputs (OE1 and OE0) are provided to simplifycascading and to facilitate demultiplexing. Thedemultiplexing function is accomplished by using the A0, A1,A2 inputs to select the desired output and using one of theother Output Enable inputs as the data input while holdingthe other Output Enable input in its active state. In theCD74HC137 and CD74HCT137 the selected output is a“Low”; in the ’HC237 and CD74HCT237 the selected output isa “High”.
Ordering Information
PART NUMBERTEMP. RANGE
(oC) PACKAGE
CD54HC237F3A -55 to 125 16 Ld CERDIP
CD74HC137E -55 to 125 16 Ld PDIP
CD74HC137PW -55 to 125 16 Ld TSSOP
CD74HC137PWR -55 to 125 16 Ld TSSOP
CD74HC137PWT -55 to 125 16 Ld TSSOP
CD74HC237E -55 to 125 16 Ld PDIP
CD74HC237M -55 to 125 16 Ld SOIC
CD74HC237MT -55 to 125 16 Ld SOIC
CD74HC237M96 -55 to 125 16 Ld SOIC
CD74HC237NSR -55 to 125 16 Ld SOP
CD74HC237PW -55 to 125 16 Ld TSSOP
CD74HC237PWR -55 to 125 16 Ld TSSOP
CD74HC237PWT -55 to 125 16 Ld TSSOP
CD74HCT137E -55 to 125 16 Ld PDIP
CD74HCT137MT -55 to 125 16 Ld SOIC
CD74HCT137M96 -55 to 125 16 Ld SOIC
CD74HCT237E -55 to 125 16 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96and R denote tape and reel. The suffix T denotes a small-quantityreel of 250.
March 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD74HC137, CD74HCT137,CD54HC237, CD74HC237,
CD74HCT237High-Speed CMOS Logic, 3- to 8-Line
Decoder/Demultiplexer with Address Latches
[ /Title(CD74HC137,CD74HCT137,CD74HC237,CD74HCT237)/Sub-ject(HighSpeed
2
PinoutCD54HC237 (CERDIP)
CD74HC137 (PDIP, TSSOP)CD74HCT137 (PDIP, SOIC)
CD74HC237 (PDIP, SOIC, SOP, TSSOP)CD74HCT237 (PDIP)
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
A1
A3
LE
OE1
OE0
GND
Y7
VCC
Y1
Y2
Y3
Y4
Y5
Y6
Y0
15
14
13
12
10
7
9
11
1Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
237 137
6
2
4
5
A0
A1
A2
LE
OE1
OE0
3-BITLATCH 1 OF 8
DECODER
GND = 8VCC = 16
HC/HCT HC/HCT
’HC137, ’HCT137 TRUTH TABLE
INPUTS OUTPUTS
LE OE0 OE1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H X X X H H H H H H H H
X L X X X X H H H H H H H H
L H L L L L L H H H H H H H
L H L L L H H L H H H H H H
L H L L H L H H L H H H H H
L H L L H H H H H L H H H H
L H L H L L H H H H L H H H
L H L H L H H H H H H L H H
L H L H H L H H H H H H L H
L H L H H H H H H H H H H L
H H L X X X Depends upon the address previously applied while LE was at a logic low.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
’HC237, ’HCT237 TRUTH TABLE
INPUTS OUTPUTS
LE OE0 OE1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H X X X L L L L L L L L
X L X X X X L L L L L L L L
L H L L L L H L L L L L L L
L H L L L H L H L L L L L L
L H L L H L L L H L L L L L
L H L L H H L L L H L L L L
L H L H L L L L L L H L L L
L H L H L H L L L L L H L L
L H L H H L L L L L L L H L
L H L H H H L L L L L L L H
H H L X X X Depends upon the address previously applied while LE was at a logic low.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
3
Functional Block Diagram
A1 LATCH
A2 LATCH
A0
A1
A2
LE
OE1
OE0
LE
LE
LE
LE
p
n
p
n
LE
LE
A0
A0
A1
A0
A2
A2
15
14
13
12
11
10
9
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1
2
3
4
5
6
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
4
Absolute Maximum Ratings Thermal InformationDC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7VDC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mADC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mADC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mADC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating ConditionsTemperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oCSupply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6VHCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCCInput Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance, θJA (see Note 1):E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/WM (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/WNS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/WPW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oCMaximum Storage Temperature Range . . . . . . . . . .-65oC to 150oCMaximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TESTCONDITIONS
VCC(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI (V) IO (mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level InputVoltage
VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level InputVoltage
VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level OutputVoltageCMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level OutputVoltageTTL Loads
- - - - - - - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level OutputVoltageCMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level OutputVoltageTTL Loads
- - - - - - - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input LeakageCurrent
II VCC orGND
- 6 - - ±0.1 - ±1 - ±1 µA
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
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Quiescent DeviceCurrent
ICC VCC orGND
0 6 - - 8 - 80 - 160 µA
HCT TYPES
High Level InputVoltage
VIH - - 4.5 to5.5
2 - - 2 - 2 - V
Low Level InputVoltage
VIL - - 4.5 to5.5
- - 0.8 - 0.8 - 0.8 V
High Level OutputVoltageCMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level OutputVoltageTTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level OutputVoltageCMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level OutputVoltageTTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input LeakageCurrent
II VCC andGND
0 5.5 - - ±0.1 - ±1 - ±1 µA
Quiescent DeviceCurrent
ICC VCC orGND
0 5.5 - - 8 - 80 - 160 µA
Additional QuiescentDevice Current PerInput Pin: 1 Unit Load
∆ICC(Note 2)
VCC-2.1
- 4.5 to5.5
- 100 360 - 450 - 490 µA
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TESTCONDITIONS
VCC(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI (V) IO (mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
All 1.5
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,360µA max at 25oC.
Prerequisite For Switching Specifications
PARAMETER SYMBOLVCC(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
An to LE Setup Time tSU 2 50 - - 65 - 75 - ns
4.5 10 - - 13 - 15 - ns
6 9 - - 11 - 13 - ns
An to LE Hold Time tH 2 30 - - 40 - 45 - ns
4.5 6 - - 8 - 9 - ns
6 5 - - 7 - 8 - ns
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
6
LE Pulse Width tW 2 50 - - 65 - 75 - ns
4.5 10 - - 13 - 15 - ns
6 9 - - 1 - 13 - ns
HCT TYPES
An to LE Setup Time tSU 4.5 10 - - 13 - 15 - ns
An to LE Hold TimetHCD74HCT137 4.5 7 - - 9 - 11 - ns
CD74HCT237 tH 4.5 5 - - 5 - 5 - ns
LE Pulse Width tW 4.5 10 - - 13 - 15 - ns
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOLTEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation DelayCD74HC137, CD74HCT137
tPLH, tPHL CL = 50pF 2 - - 180 - 225 - 270 ns
An to any Y 4.5 - - 36 - 45 - 54 ns
6 - - 31 - 38 - 46 ns
Propagation Delay’HC237, CD74HCT237
tPLH, tPHL CL = 50pF 2 - - 160 - 200 - 240 ns
An to any Y 4.5 - - 32 - 40 - 48 ns
6 - - 27 - 34 - 41 ns
Address to Output
CD74HC137 tPLH, tPHL CL = 15pF 5 5 15 - - - - - ns
’HC237 tPLH, tPHL CL = 15pF 5 - 13 - - - - - ns
OE0 to any Y or Y tPLH, tPHL CL = 50pF 2 - - 145 - 180 - 220 ns
4.5 - - 29 - 36 - 44 ns
6 - - 25 - 31 - 38 ns
OE1 to any Y or Y tTLH, tTHL CL = 50pF 2 - - 145 - 180 - 220 ns
4.5 - - 29 - 36 - 44 ns
6 - - 25 - 31 - 38 ns
LE to any Y or Y tTLH, tTHL CL = 50pF 2 - - 190 - 240 - 285 ns
4.5 - - 38 - 48 - 57 ns
6 - - 32 - 41 - 48 ns
Power DissipationCapacitance, (Notes 3, 4)
CD74HC137 CPD CL = 15pF 5 - 19 - - - - - pF
’HC237 CPD CL = 15pF 5 - 23 - - - - - pF
Output Transition Time tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CI - - - - 10 - 10 - 10 pF
Prerequisite For Switching Specifications (Continued)
PARAMETER SYMBOLVCC(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
7
HCT TYPES
Propagation DelayAn to any Y or YAddress to Output
tPLH, tPHL CL = 50pF 4.5 - - 38 - 48 - 57 ns
tPLH, tPHL CL = 15pF 5 - 16 - - - - - ns
OE0 to any Y (HC137) tPLH, tPHL CL = 50pF 4.5 - - 35 - 44 - 53 ns
OE0 to any Y (HC237) tPLH, tPHL CL = 50pF 4.5 - - 33 - 41 - 60 ns
OE1 to any Y (HC137) tTLH, tTHL CL = 50pF 4.5 - - 37 - 46 - 56 ns
OE1 to any Y (HC237) tTLH, tTHL CL = 50pF 4.5 - - 35 - 44 - 53 ns
LE to any Y (HC137) tTLH, tTHL CL = 50pF 4.5 - - 44 - 55 - 66 ns
LE to any Y (HC237) tTLH, tTHL CL = 50pF 4.5 - - 42 - 53 - 63 ns
Power DissipationCapacitance, (Notes 3, 4)
CD74HC137 CPD CL = 15pF 5 - 19 - - - - - pF
’HC237 CPD CL = 15pF 5 - 23 - - - - - pF
Output Transition Time tTLH, tTHL CL = 50pF 4.5 15 19 22 ns
Input Capacitance CI - - - - 10 - 10 - 10 pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOLTEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC inaccordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES ANDPULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC inaccordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES ANDPULSE WIDTH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATIONDELAY TIMES, COMBINATION LOGIC
CLOCK 90%50%
10% GND
VCC
trCL tfCL
50% 50%
tWL tWH
10%
tWL + tWH =fCL
I
CLOCK 2.7V1.3V
0.3V GND
3V
trCL = 6nstfCL = 6ns
1.3V 1.3V
tWL tWH
0.3V
tWL + tWH =fCL
I
tPHL tPLH
tTHL tTLH
90%50%10%
50%10%INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V1.3V0.3V
1.3V10%INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
8
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,AND PROPAGATION DELAY TIMES FOR EDGETRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,AND PROPAGATION DELAY TIMES FOR EDGETRIGGERED SEQUENTIAL LOGIC CIRCUITS
Test Circuits and Waveforms (Continued)
trCL tfCL
GND
VCC
GND
VCC50%
90%
10%
GND
CLOCKINPUT
DATAINPUT
OUTPUT
SET, RESETOR PRESET
VCC50%
50%
90%
10%50%
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
ICCL50pF
tSU(L)
tH(H)
trCL tfCL
GND
3V
GND
3V
1.3V2.7V
0.3V
GND
CLOCKINPUT
DATAINPUT
OUTPUT
SET, RESETOR PRESET
3V
1.3V
1.3V1.3V
90%
10%1.3V
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
ICCL50pF
tSU(L)
1.3V
tH(H)
1.3V
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
5962-8860601EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8860601EACD54HC237F3A
CD54HC237F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC237F
CD54HC237F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8860601EACD54HC237F3A
CD74HC137E ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC137E
CD74HC137PW ACTIVE TSSOP PW 16 90 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ137
CD74HC137PWR ACTIVE TSSOP PW 16 2000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ137
CD74HC237E ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC237E
CD74HC237EE4 ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC237E
CD74HC237M ACTIVE SOIC D 16 40 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC237M
CD74HC237M96 ACTIVE SOIC D 16 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC237M
CD74HC237M96G4 ACTIVE SOIC D 16 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC237M
CD74HC237ME4 ACTIVE SOIC D 16 40 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC237M
CD74HC237NSR ACTIVE SO NS 16 2000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC237M
CD74HC237PWR ACTIVE TSSOP PW 16 2000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ237
CD74HC237PWT ACTIVE TSSOP PW 16 250 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ237
CD74HCT137E ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT137E
CD74HCT137M96 ACTIVE SOIC D 16 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT137M
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
CD74HCT137MT ACTIVE SOIC D 16 250 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT137M
CD74HCT137MTE4 ACTIVE SOIC D 16 250 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT137M
CD74HCT237E ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT237E
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 3
OTHER QUALIFIED VERSIONS OF CD54HC237, CD74HC237 :
• Catalog: CD74HC237
• Military: CD54HC237
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
CD74HC137PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC237M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC237NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC237PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC237PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT137M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC137PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC237M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HC237NSR SO NS 16 2000 367.0 367.0 38.0
CD74HC237PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC237PWT TSSOP PW 16 250 367.0 367.0 35.0
CD74HCT137M96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X4.55
16X 0.300.19
TYP6.66.2
1.2 MAX
0.150.05
0.25GAGE PLANE
-80
BNOTE 4
4.54.3
A
NOTE 3
5.14.9
0.750.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016ASMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. Reference JEDEC registration MO-153.
SEATINGPLANE
A 20DETAIL ATYPICAL
SCALE 2.500
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EXAMPLE BOARD LAYOUT
0.05 MAXALL AROUND
0.05 MINALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016ASMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLEEXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
8 9
16
15.000
METALSOLDER MASKOPENING
METAL UNDERSOLDER MASK
SOLDER MASKOPENING
EXPOSED METALEXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASKDEFINED
(PREFERRED)
SOLDER MASKDEFINED
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EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016ASMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
8 9
16
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