cbc performance with switched capacitor dc-dc …dmray/cbc_documentation/pwg_feb_2012.pdf · cbc...
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1
CBC performance with switched capacitor DC-DC converter
Mark Raymond, Tracker Upgrade Power Working Group, February 2012.
2
2 powering features included on CBC prototype
LDO regulator (1.2 -> 1.1) feeds analog FE
provides stable voltage railand supply noise rejection
2.5 -> 1.2 DC-DC converter
allows to power CBC using single 2.5 V rail
thanks to Michal Bochenek and Federico Facciofor the design and help with incorporating the layout into the CBC
dataclock
trigger
I2C, reset
7 mm
4 mmam
pli
fiers
& c
om
para
tors
256 deeppipeline
+ 32 deep
buffers
biasgenerator
2.5 -> 1.25 DC-DC converter
LDO
bandgap
SLVS
power
power
TESTDEVICES
pads for test features
pads for test features
CBC power features
3
CBC power features - DC performance
DC-DC switched capacitor converter
converts 2.5 -> ~ 1.2
clearly functioning, high efficiency ~ 90%
study of DC-DC switching effects on noise
follows in next slides
LDO linear regulator
provides clean,regulated rail to analog FE
~ 1.2 Vin, 1.1 Vout
dropout ~ 40 mV for 60 mA load
provides > 30dB supply rejection up to 10 MHz
for further details see: http://www.hep.ph.ic.ac.uk/~dmray/CBC_documentation/CBC_Tracker_Electronics_May_11.pdf
DC-DC & LDO outputs1.25
1.20
1.15
1.10
1.05
Volts
1 us / division
LDO input LDO output
1.11
1.10
1.09
1.08
1.07
1.06
1.05
1.04
LD
O o
utp
ut [V
]
1.201.151.101.05
LDO input voltage [V]
30mA load 60mA load
LDO dropout 40 mV
4
DC-DC
LDO
ban
dg
ap
DC-DC diff. clock (CMOS)
DC-DC 1.2
GND(D)
VDDD
GND(A)
VDDA
VLDOO
VLDOI
+2.5V GND
BGI linked (or not) to BGO
can power CBC from single +2.5V supply1 MHz diff. clock to DC-DC circuitDC-DC 1.2V feeds VDDD (dig. supply) and VLDOI (LDO I/P)4 external capacitors minimum
(actually 5 in this picture)
DC-DC powering option
1uF
100n
100n
100n
100n
maybe don’t need this cap
CBContest
board
+2.5
GNDGND
GNDGND
DC-DC1.2
all GNDsconnectedtogether
5
DC-DC
LDO
ban
dg
ap
DC-DC diff. clock (CMOS)
DC-DC 1.2
GND(D)
VDDD
GND(A)
VDDA
VLDOO
VLDOI
+2.5V GND
BGI linked to BGO
to study effects on analog performance
1uF
100n
100n
100n
100nexternal DC supply
externalDC supply
at least 2 possibilities for adverse effects
1) noise on DC-DC O/P rail could affect analogueperformance via VDDA rail (though LDO should reject)
2) DC-DC circuit noise could couple to front end viaanother path (substrate, GND, ..)
study here concentrates on 2nd path by providinganalogue rail from external clean supply
will provide digital rail either from external supplyor from DC-DC output (when DC-DC operating)
all GNDsconnectedtogether
6
adding external capacitance
GND
GND
GND
individualchannel
capacitors
want to measure noise (from s-curves) dependence on external capacitanceplug-on boards containing arrays of capacitors connect to bonded out channelsacquire s-curve for one of the bonded out channels
7
1000
800
600
400
200
0
no
. o
f e
ven
ts
450440430420410400
comparator threshold VCTH [mV]
fixed trig., 1.2V
c) Cadded = 5.79 pF
1000
800
600
400
200
0
no
. o
f even
ts
440430420410400390
fixed trig., 1.2V
a) Cadded = 1.78 pF
1000
800
600
400
200
0
no.
of
eve
nts
440430420410400390
fixed trig., 1.2V
b) Cadded = 3.78 pF
s-curves:referencemeasurement
measure s-curves for single channel for different externalcapacitances
conditions for measurements on this slide
digital circuitry supplied with external 1.2 V supply
DC-DC not running
CBC triggered at fixed time following a fast reset
=> always triggering same pipeline location
gives cleanest possible measurement as reference
(no reason to expect any effect from random triggering, but just to check)
8
1000
800
600
400
200
0
no
. o
f e
ven
ts
450440430420410400
comparator threshold VCTH [mV]
fixed trig., 1.2V random trig., 1.2V
c) Cadded = 5.79 pF
1000
800
600
400
200
0
no
. o
f even
ts
440430420410400390
fixed trig., 1.2V random trig., 1.2V
a) Cadded = 1.78 pF
1000
800
600
400
200
0
no.
of
eve
nts
440430420410400390
fixed trig., 1.2V random trig., 1.2V
b) Cadded = 3.78 pF
now repeat for random triggering
digital circuitry still supplied with external 1.2V supply
DC-DC still not running
but fast reset removed
pseudo-random trigger, so now triggering locationsthroughout pipeline
no effect on s-curves visible (i.e. no effect on noise)
(as expected)
s-curves: DC supply(random trigger)
9
1000
800
600
400
200
0
no
. o
f e
ven
ts
450440430420410400
comparator threshold VCTH [mV]
fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC
c) Cadded = 5.79 pF
1000
800
600
400
200
0
no
. o
f even
ts
440430420410400390
fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC
a) Cadded = 1.78 pF
1000
800
600
400
200
0
no.
of
eve
nts
440430420410400390
fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC
b) Cadded = 3.78 pF
now feed digital circuitry with DC-DC 1.2 V
DC-DC now running
return to triggering at fixed time following a fast reset
DC-DC clocked at 1 MHzwith fixed phase relationship to fast reset
once again - no significant effect on s-curves
=> DC-DC circuit doesn’t affect intrinsic noise
s-curves: DC-DC running(fixed trigger time)
10
1000
800
600
400
200
0
no. o
f events
450440430420410400
comparator threshold VCTH [mV]
fixed trig., 1.2V random trig., 1.2V
fixed trig., DC-DC random trig., DC-DC
c) Cadded = 5.79 pF
1000
800
600
400
200
0
no. o
f events
440430420410400390
fixed trig., 1.2V
random trig., 1.2V fixed trig., DC-DC
random trig., DC-DC
a) Cadded = 1.78 pF
1000
800
600
400
200
0
no
. of
even
ts
440430420410400390
fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC
random trig., DC-DC
b) Cadded = 3.78 pF
now try pseudo-random triggering again
DC-DC still running
s-curves now distorted for larger capacitance
=> something to do with random triggering when DC-DC circuitoperating
an effect associated with specific pipeline locations?
try to understand what’s going on with a more systematic study
=> look at s-curve dependence on triggered pipeline location
s-curves: DC-DC running(random trigger)
11
500
450
400
350
300
250
200
S-c
urv
e m
id-p
oin
ts [
mV
]
1009080706050403020100trig. pos'n [ 25 ns steps]
20
15
10
5
0
nois
e [m
V rm
s]
100
80
60
40
20
0
no
. of
eve
nts
500450400350300
VCTH [mV]
Cadded = 1.78 pF
s-curve dependence on triggered pipeline loc’n
acquire s-curves with increasing separationbetween fast reset time and trigger position(25 nsec steps)
DC-DC circuit operating
results here for smallest capacitance:
not all s-curves in same position
plotting s-curve mid-point vs vs. triggerposition shows repetitive structure
separation between positive (or negative)
shifts = 40 steps = 1 µsec = DC-DC period
pedestal shift only, no change in shape
=> intrinsic noise unaffected40 steps
12
500
450
400
350
300
250
200
S-c
urv
e m
id-p
oin
ts [
mV
]
1009080706050403020100trig. pos'n [ 25 ns steps]
20
15
10
5
0
no
ise
[mV
rms]
100
80
60
40
20
0
no
. of
eve
nts
500450400350300
VCTH [mV]
Cadded = 3.78 pF
increasing external capacitance
effect becomes much more noticeable
13
500
450
400
350
300
250
200
S-c
urv
e m
id-p
oin
ts [
mV
]
1009080706050403020100trig. pos'n [ 25 ns steps]
20
15
10
5
0
nois
e [m
V rm
s]
Cadded = 5.79 pF
100
80
60
40
20
0
no
. of
eve
nts
500450400350300
VCTH [mV]
for largest external capacitance
s-curves in top plot colour coded to showwhich ones correspond to which point inbottom plot
some distortion visible for most negativelyshifted curves (out of amplifier linear range)
so DC-DC circuit operation somehowaffects channel pedestal
magnitude of effect proportional to externalcapacitance to ground
14
500
450
400
350
300
250
200
S-c
urv
e m
id-p
oin
ts [
mV
]
1009080706050403020100
trig. pos'n [ 25 ns steps]
20
15
10
5
0
no
ise
[mV
rms]
100
80
60
40
20
0
no
. o
f e
ven
ts
500450400350300
VCTH [mV]
Cadded = 5.8 pF
repeat for external DC supplies
just to check
effect goes away completely if DC-DCcircuit not operational
15
what’s going on?
GNDEXT
GNDINT
CEXT
Cf
behaviour most likely due to DC-DC circuit operationcausing difference between internal and external grounds
would result in spurious charge injectionproportional to CEXT
can anything be done to improve situation?
better connection between GNDINT and GNDEXT ?
ultimately limited by bond wires
is present test setup optimal?
have tried to improve following discussions with CERN engineers
start by taking a critical look at CBC test board
vnoise
16
CBC test board copper layout
double-sided pcb~ solid ground on bottom surface connected (PTH) to ground on top surfaceCBC glued on the centre ground areaground brought out from under chip to bond pads
top bottom
17
possible deficiencies
too cautious about keepingbonding area clear - capacitorscould have been positionedcloser to chip
could have put more plated throughholes in
have tried to “make improvements”to existing board to see whetherperformance is affected
top
18
have tried to improve grounding anddecoupling by turning this
into this
this is the final version of the test boardafter all modifications
chip glob-topped to protect bonds
will go through modifications step-by-stepfor clarity - describing changes andshowing resulting effects on s-curves
“improvements”
19
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
reference
first take reference measurement
measure s-curves as before for 3.8 pF added external cap.
look at 3 channels at top, middle and bottom of chip
20
improved ground coupling between CBC and external capacitor board
three lengths of tinned copper braid soldered to ground plane on back of CBC board
connected to ground area on external capacitor board
21
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
reference
effect of improved grounding
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch4
100
80
60
40
20
0
500450400350300
ch60
improved groundingto external caps
some differences - most noticeable for channel 60
22
improved 2.5 V rail decoupling
2.5V decoupled closer to the chip
extra copper piece added adjacent to2.5 V input, soldered to ground
additional 100 nF capacitor solderedas close as possible to bond pad
solder 2.5 V
23
improved 2.5 V rail decoupling - reality
extra copper
pieceextra
capacitor
24
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
reference
effect of improved 2.5 V decoupling
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch4
100
80
60
40
20
0
500450400350300
ch60
improved grounding to external caps
ch124 gets appears to get worse, ch 4 gets better
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
added cap on 2.5V rail
25
extra ground contacts
26
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
extra ground contacts
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
added cap on 2.5V rail
effect of extra ground contacts
not much difference
27
additional shielding
copper tape cover over topof capacitors - solderedround edge
28
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
extra ground contacts
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
added shielding
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
added cap on 2.5V rail
efect of additional shielding
channel 60 now looks a bit strange
29
some more capacitor repositioning
DC-DC output decoupling & floatingcapacitor as close as possible to chip
30
some more capacitor repositioning
31
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
output & floating caps
as close as possible
effect of capacitor repositioning
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
added shielding
some effects on all three channels – not obvious what conclusions to draw
32
conclusions?
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
reference
100
80
60
40
20
0
500450400350300
ch124
100
80
60
40
20
0
500450400350300
ch60
100
80
60
40
20
0
500450400350300
ch4
after everything
no dramatic improvement in behaviour
clearly some effects but no strongindication of a “magic solution”
might be able to do better with new improved board layout?
but seems unlikely that all “undesirable”effects can be made to go away
33
summary
fundamental performance of DC-DC circuit itself is good
high efficiency for 2:1 step down conversion
no significant effect on intrinsic noise
but switching transients appear to couple to internalchip ground causing pedestal shifts
- magnitudes dependent on external capacitance
worth noting: this would likely not be a problem for hybrid pixel chips
low sensor capacitancelow inductance bump-bond coupling between sensor and chip grounds
what next?
more measurements? - I’m open to suggestions
CBC2 will include same DC-DC circuit
bump-bond layout ought to help significantly with performance(better coupling between on and off-chip grounds)
GNDEXT
GNDINT
CEXT
Cf
vnoise