case design guidelines for apple devices...
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4R7
U5902
R3740
R3750
L8112
L3750
L3740
U3750
U3740
FL3751
FL3750
FL3741
FL3740
J5950
L6111_RF
U6102_RF
C5934
U3060
J5900
L8105
L8106
L8107
U3600
U8100 D8258
D8228
D3000
D8100
U0600
LED9000
C1421
C1321
L3000
C3001
C3000
J6190_RF
J6051
J6050
U5903
U3010
U3009
U3000
U3007
U5900
U1600
L8229
R3009
Y0602
L8104
C8124
L8102
L8109
L8100
L8103
L8101
L8110
Y8138
C8165
C8166
L8111
L8225
L8255
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C1414
C1104
C1420
C1427
C1327
C1192
C1314
C1100
C1105
C1320
C1103
C1101
CA185
C1179
C8194
C1301
C1102
C8154
C8155
R5961
R5960
R3744
R3745
R3754
R3755
R3025
R3030
R3031
R3033
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R2205
R0760
R0718
R0717
R0716R
0720
R0715
R0711
R0713
R0714
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R3160
R3742
R3743
R3752
R3753
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R3060
R3173
R3171
R3071
R3070
R3631
R3630
R0708
R0710
R0709
R9000
R3101
R3032
L3620
R8222
R8281
R3751
R3741
R1022
R1420
R10234
R1020
R1021
R9002
R3190
R3066
R3012
C5960
C3756
C3746
C3060
C3110
C3108C3106
C3105
C3103
C3041
C3031
C3030
C5936
C5935
C5932
C5931
C3102
C3050
C1652 C1635
C1634
C1633
C1632
C1631
C1630
C1623
C1620
C1625
C1624
C1622
C1621
C6110_RF
C1325
C1426
C1408
C1424
C1411
C1021
C1023
C1144
C1433
C1407
C1412
C1425
C1413
C1434
C1022
C1333
C1313
C1306C1312
C1197
C1311
C1307
C1326
C1308
C1020
C1334C1324
C1432
C1406
C3767
C3768
C3787
C3788
C3632
C3630
C3631
C3740
C3749
C3750
C3759
C3761
C3764
C3781
C3784
C3763
C3766
C3783
C3786
C3760
C3780
C1318
C3617
C3616
C3754
C3744
C3721
C3711
C3614
C0640
C3620
C3008 C3002
C8142
C8143
C8163
C8164
C1651 C1650
C8131
C3603
C5933
C5930C3755
C3745
C3720
C3710
C8226
C8256
C8100 C8101
C8102
C8103
C8104
C8105
C8107
C8108
C8109 C8110
C8111
C8112
C8113
C8114
C8117
C8118
C8119
C8120
C8121
C8122
C8123
C8195
C8126C8125
C8232
C8233
C8234
C8235
C8262
C8263
C8264
C8265
C8237
J7500
J3700J2200
R5962
R8297 R8296
R6108_RF
R6114_RF
R5934
R5929
R0652
R5931
R5930
R1220
R5990
R6105_RF
R6107_RF
R6109_RF
R6111_RF
R6113_RF
R1200
R1201
R1202
R1208
R1209
R1206
R1205
R1204
R1203
R5991
R0622
R0621R0620
R0608
R0730
R0700
R6112_RF
R0650
R5935
R0651
R3611
R3610
R3613
R3612
R1455R
1456
R1095
R1096
R1083
R1084
R1453
R1454
R1356
R1056
R1055
R1354
R1353
R1054
R1053
R1355
R0642
R0640
R0643
R0703
R0704
R3640
R0701
R0702
R3620
R5933
R5932
R3181
R3180
C3601
C3605
C3606
C3607
C3608
C3610
C3758
C3757
C3748
C3747
C6109
C3104
C8148
C3107
C8152
C3753
C3752
C3751
C3743
C3742
C3741C8144
J5400 J5401 J3011J3010
C5991
C5944
C5943
C5942
C5941
C5940
C3691
C6103_RF
C1422
C1456
C1463
C1095
C1096
C1430C1404
C1405 C1084
C1085
C1454
C1462
C1363
C1330
C1304
C1056
C1058
C1054
C1362
C1354
C1331
C1057
C1305
C1356
C1322
C8292
C1431
C3723
C3722
C3713
C3712
C6102_RF
C6104_RF
C1423
C1435
C1419
C1309
C1335
C1323
C1319
C1409
C0651
C0650
C3602
C3615
C1610
C1611 C1613
C1614
C1615
C6101_RF
C1612
C3192
C3191
C3009
C3053
C3007
C3005
C3070
C1302
C1402
C1403
C1303
C3618
C8147
C8149
C3112
C3101
C8146
C8201
C8251
C8266
C8267
C5783
U5650
U5640
U5610
U5630
U5620
U5600U5670
U5660
L2210
L2200
L2201
L5520L
5530
L2242
L5930
C8217
C8281
C8282
C8215
C8220
C8221
C8223
C8214
C2281C2282C2283C2285C2287 C2284C2286 C2280
C0632
C0633
C0634
C1141
C1177
C1154 C1178
C1153
C1137
C1140
C1165
C1166
C1139
C1138
C1136
C3770
C3771
C3773
C3772
C2241
R0921
R0920
R2285R2286R2287 R2280R2281R2282R2283R2284
R0843 R
0842
R1691
R1690
R9030
R9020
R1305
R1306
R1351
R1452
R1451
R1405
R1406R1352
R9021
R9031
L5570
L5560L5580
R5630
R5641 R5640
R5631
C0961
C0960
C1122C1120
C1126
C1184 C1185
C1123
C1121
C1152
C1151
C1119
C1195
C1125
C1196
C1124
C6111_RF
C6107_RF
C6108_RF
C6190_RF
C6192_RF
C6191_RF
L5701
L5700
L6192_RF
L6191_RF
L6190_RF
R8173
R8203
R8130
R8116
R3601R0610
R0950
R0613
R1654
FL7500
FL0910
FL5750
FL5710
FL5740
R8290
R8291
R2290
R8170
U1400U1300
C8236
C7527
C7526
C2270C2220
C2253C2233
C2271C2221
Q8200
Q8201
Q8203
Q8202
C0933
C0934
C0932
C8172
C8196
R8100
R8219
Q8123
Q8104
U3101FL5990
CA199
DZ5791DZ5792
DZ5750
DZ5710
DZ5740
DZ5760 L5757
D8230
DZ8120
DZ5900
DZ5901
DZ5902
DZ5903
DZ5990
L2212L2222L2232L2202
U2200
Q9010
Q9030
Q9020
C8239
C8238
C5581
C5551
C5561
C5571
C5731
U6101_RF
J6191_RF
U6104_RF
J6000
U3003U3100
D5990
L5540
L5500 L
5510
L5931
C8153
C8145
C8151
C8209
C8136C8135
C8139
C8140
C8141
C1113
C1115
C1316
C0614
C1116
CA195
C0980
CA198
C1118
C1117
C1417
C0935
C1114
C2202
C8134
C1328
C1329
C1416
C1428
C1429
C1317
C8173
C8174
C8170
C8171
C3111
CA193
C1601 C1602
C1600
CA197
CA196C0843 C
0842
C1690
C1691
C0810
C0811
C0812
C0820
C0821
C0951
C0927
C0613
C0606
C0605
C0931C0930
C1145
C0924
C0982
C8206
C8207
C1352
C0953
C0957
C0952
C0950
C0981
C0631
C0608
C0630
C1450
C0609
C0635
C1452
C1461
C1350
C1360
C1460
C1361
C3690
C5990
C0612
C0607
C0928
C0929
C0904
C11A0
C11A1
C11B0
C11B1
C11C0
C11C1
C11D0
C11D1
C11E0
C11E1
C0636
C11F0
C0637
C0621
C0623
C5920C5910
C5900
C5722
C8130
C8162
C8161
C8160
C8159
C8158
C8157
C8156
C8187
C8188
C8189
C8190
C8191
C8192
C8193
C3609
C8167
C8133
C8132
C8168
C3612
R1210
R1211
R0932
R0930
R0931
R0933
R0706R0705
R2242
R2241
R2240
R1260
R0831
R0832
R1655
R0941 R0942
R1207
R0604
R0900
R0940
C3611
C8138
C1150
C1182
C1171
C1172
C1169
C1170
C1149
C1183
C1157 C1160
C1158
C1159
C1193
C1194
C1176
C1175
C1174
C1173
C1164
C1163
C1162
C1161
C0910
C2232
C5553
C5563C5573
C5584C5733
C2230
C7525
C5570
C5560
C5550C5580C5730
C7522
C7523
C5552
C5630
C5640
C7524
C5572
C5562
C2206
C5583
C5661
C5670C5671
C5660C5732
C3604
C3613
C8291
C8290
C8137
C1418
C8169 C8210
CA186
C1198
C1133
CA187
CA188
C1199
CA190
C1605
CA192
C1606
C1604
C1130
C1135C1131
C1132
C1134
CA191
CA189
CA150
CA151CA152
CA153
C1143
C1129
C1142
C1410
C1128
C1310
C1332
C5721
C5750
C5765
C5766
C5711
C5710
C1607
C1608
C1609
C5740
C5741
C8212
C8204
C3006
C3109
C0956
C0909
C0907
C2239
C2246
C2247
C2240
C2248
C2249
C5582
C2250
C2251
C2242
C2243
C2203
C2244
C2245
C0903
C0908
C0955
R8231
R8240
R8232
R8261
R8227
R8239
R8265
R8270
R8262
R8269
R8235
R8257
R1321
R1421
R1320
R8282
R8216
R8218
R8280
FL0911
L5550
L5730
R9001
R8292
R8172
R3120
R8293
R0911
R8196
R5790
R3107
R9010
R9011
R0719
C1147
C1148
C1167C1168
C1156
C1106
CA194
C1180
C1155
C1181
C1108
C1109
C1111
C1415C1190
C1110
C1107C1191C1315
820-3249-BOT MLB
820-3249-TOP MLB
www.witesomtesla.com www.mobile-files.com
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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DRAWING
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2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
PROPRIETARY PROPERTY OF APPLE INC.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
DESCRIPTION OF REVISION
CKAPPD
2 1
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PAGE
THE INFORMATION CONTAINED HEREIN IS THE
C
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Apple Inc.
THE POSESSOR AGREES TO THE FOLLOWING:
DRAWING TITLE
DSIZE
REVISION
DRAWING NUMBER
BRANCH
REV ECN
7
B
3
II NOT TO REPRODUCE OR COPY IT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
IV ALL RIGHTS RESERVEDIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
(JOE)
(TERRY)
(JOE)
(TERRY)
(TERRY)
(AMANDA)
(TERRY)
(TERRY)
(AMANDA)
(AMANDA)
(TERRY)
(AMANDA)
(TERRY)
(TERRY)
(TERRY)
(TERRY)
(AMANDA)
(AMANDA)
(AMANDA)
(SYSTEM DRI)(SYSTEM DRI)
(MATT)
(JOE)
(JOE)
(MARK)
(AMANDA)
(MARK)
(MARK)
(MADHAVI)
(MADHAVI)
(MADHAVI)
(AMANDA)
(AMANDA)
(AMANDA)
(AMANDA)
(AMANDA)
(AMANDA)
(MADHAVI)
(AMANDA)
(MADHAVI)
(AMANDA)
X140 MLB
1 OF 39
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A.0.0
051-9385
A 0001554595
LAST_MODIFIED=Thu Jul 26 10:29:36 2012
NAND16 N/A13 N/A
DDR 2 AND 314 N/A12 N/A
13 N/A11 N/ADDR 0 AND 1
12 N/AN/AAP: MISC & ALIASES10
BOM TABLES4 N/AN/A3
31 PMU: ADRIANA PAGE 3 MADHAVI 12/06/201183
AP: NAND8 N/A6 N/A
CONTENTSPDF DATESYNC MASTERCSA
MLB
DRAWING
DEBUG/MISC.32 MLB 11/09/201190
33 N/A N/A93 TEST/HOLES/FIDUCUALS
34 POWER ALIASES N/A N/A121
35 CONSTRAINTS: MLB RULES MIKE 11/30/20111507 AP: I/Os N/A5 N/A
7 AP: TV,DP,MIPI9 N/AN/A
10 N/A8 N/AAP: DDR
AP: POWER11 N/A9 N/A
ALIASES21 N/A14 N/A
VIDEO: EDP CONNECTOR22 N/A15 N/A
GRAPE: GROUNDHOG,CONN,BOOST30 N/A16 N/A
GRAPE: Z1, Z231 N/A17 N/A
AUDIO: L81 CODEC36 N/A18 N/A
AUDIO: SPEAKER AMP37 N/A19 N/A
SENSOR FLEX CONN54 N/A20 N/A
SENSOR CONN FILTERS 155 N/A21 N/A
SENSOR CONN FILTERS 256 N/A22 N/A
E75 DOCK SUPPORT57 N/A23 N/A
IO FLEX CONN58 N/A24 N/A
TRISTAR59 N/A25 N/A
CONNECTOR: CELLULAR60 N/A26 N/A
61 N/A27 N/AWIFI/BT
75 12/06/201128 MADHAVIPOWER: BATTERY CONNECTOR
82 12/06/201130 MADHAVIPMU: ADRIANA PAGE 2
154 11/30/2011MIKE39 CONSTRAINTS: POWER / GND
CONSTRAINTS: DDR/FMI38 MIKE 11/30/2011153
AP: MAIN6 N/A4 N/A
BLOCK DIAGRAM: SYSTEM2 N/A2 N/A
MIKE152 CONSTRAINTS: DISPLAY/AUDIO37 11/30/2011
PMU: ADRIANA PAGE 181 12/06/201129 MADHAVI
36 CONSTRAINTS: LOW SPEED BUS MIKE 11/30/2011151
CONTENTSCSAPDF DATESYNC MASTER
Table of Contents1 N/A1 N/A
iPad 4th Gen
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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REVISION
BRANCH
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THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
XSP
HP
AMP
AMPSPEAKER
MIC2MIC1
L81MBUS
AUDIO CODEC
ASP
SPI1 SPI
NCI2S4
I2S1
BATTERY
I2S0
I2S3
SPI3
GROUNDHOG
CSA 61
GPSCELLULAR/
GYRO
SENSOR BOARD VGA FLEXSENSOR BOARD
ACCELEROMETER ALS
FF CAMERAVGA FLEX
REAR CAMERAVA5 FLEX
I2S2LPDDR2
PROX SENSOR
SENSOR BOARD
COMPASS
SENSOR BOARD
ISP_I2C1MIPI1C
ISP_I2C0
DISPLAY/
USART
SIM CARD
CSA 31
CSA 13-14 NOT ON
HSIC1
TRISTAR
MIPI0C
EDP
DWI
UART5
CSA 31
CSA 30
CSA 75
CSA 36
I2C2
I2C1
BACKLIGHT
Z2
Z1
TOUCH PANEL
I2C0
FMI0 FMI1
CSA 16
HSIC1_1
BT_I2S
UART3 WIFI/BT
BALIWIFI-ONLY CONFIG
UART2
UART4
HSIC3
DIVERSITY CELLULAR ANT
GPS ANT
WIFI/BT ANT
IPC
CSA 59
USB2.0
UART1
UART6
NAND FLASH
USARTCSA 60
PRIMARY CELLULAR ANT
PMUADRIANA
CSA 81,82
BUTTON FLEX
HOME BUTTON
HALL EFF 1
HALL EFF 2
USB11
BLOCK DIAGRAM: SYSTEMSYNC_MASTER=N/A SYNC_DATE=N/A
051-9385
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CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
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PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
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PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
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MLB_E: LEGACY CELLULAR CONFIGMLB_D: LEGACY CELLULAR CONFIGMLB_C: CELLULAR CONFIGMLB_B: CELLULAR CONFIGMLB_A: WIFI ONLY CONFIGMLB: MLB BOARD ONLY
DEV: DEV BOARD ONLY64GB_PROD: 64 GB CONFIG32GB_PROD: 32GB CONFIG16GB_PROD: 16GB CONFIG
BOM OPTIONS
Power aliases required by this page:
BOM options provided by this page:
SCH AND BOARD P/N
Page Notes
BARCODE LABEL/EEEE CODES
SOC/PMU
MECHANICAL PARTS
NAND
32GB FLASH CONFIGURATIONS
NAND
SDRAM
PMU
SOC
Signal aliases required by this page:
(NONE)
(NONE)
COMMONALTERNATE
AUDIO
GRAPE
MEMORY
16GB FLASH CONFIGURATIONS
64GB FLASH CONFIGURATIONS
128GB FLASH CONFIGURATIONS
EEEE_MLB_C_64GEEEE_F1W91 CRITICALEEEE FOR 639-3743 (MLB C 64G)825-7838
EEEE_MLB_C_32GEEEE_F1WF CRITICAL1 EEEE FOR 639-3742 (MLB C 32G)825-7838
1 CRITICAL825-7838 EEEE_F80REEEE FOR 639-4178 (MLB C 128G) EEEE_MLB_C_128G
EEEE_MLB_C_16GEEEE_F1WG CRITICAL1 EEEE FOR 639-3741 (MLB C 16G)825-7838
825-7838 1 EEEE FOR 639-3263 (MLB B 16G) CRITICALEEEE_DWKG EEEE_MLB_B_16G
825-7838 EEEE FOR 639-3740 (MLB B 64G)1 CRITICALEEEE_F1WC EEEE_MLB_B_64G
825-7838 1 EEEE FOR 639-3739 (MLB B 32G) CRITICALEEEE_F1W7 EEEE_MLB_B_32G
825-7838 1 CRITICALEEEE_F80PEEEE FOR 639-4177 (MLB B 128G) EEEE_MLB_B_128G
825-7838 1 CRITICALEEEE FOR 639-4176 (MLB A 128G) EEEE_F80Q EEEE_MLB_A_128G
EEEE_MLB_A_64GEEEE_F1W8 CRITICAL1 EEEE FOR 639-3738 (MLB A 64G)825-7838
U16001 CRITICALTOSHIBA PPN1.5 128GB 128GB_PROD335S0912
CRITICAL1 U1600 64GB_PROD335S0880 TOSHIBA PPN1.5 64GB
BOM TABLESSYNC_DATE=N/ASYNC_MASTER=N/A
TOSHIBA PPN1.5 16GB335S0878 16GB_PRODU1600 CRITICAL1
BASIC COMMON,ALTERNATE
CRITICAL1 U8100343S0622 IC,PMU,ADRIANA,D2018A1,FCBGA
LPDDR2,533MHZ,ELPIDA,38NMU1400,U1400333S0638 333S0636
LPDDR2,533MHZ,HYNIX,38NM333S0637 U1300,U1400333S0636
CRITICAL2 U1300,U1400333S0636 LPDDR2,533MHZ,512MB,SAMSUNG,35NM
335S0879 TOSHIBA PPN1.5 32GB1 U1600 32GB_PRODCRITICAL
U0600IC,SOC,H5G,FCBGA1089,0.5MM1343S0598 CRITICAL
1 CRITICALSCH,MLB,X140 SCH1051-9385
FENCE,NAND,TOP,MLB,X140806-4195 PD_FENCE_NAND1 CRITICAL
FENCE,AMP,MLB,X140 CRITICAL806-3956 PD_FENCE_AMP1
FENCE,2,BTM,MLB,X1401806-3492 PD_FENCE_BTM2 CRITICAL
FENCE,LARGE,TOP,MLB,X140806-3493 PD_FENCE_LARGE1 CRITICAL
FENCE,1,BTM,MLB,X140806-4196 CRITICAL1 PD_FENCE_BTM1
825-7838 EEEE FOR 639-3737 (MLB A 32G)1 CRITICAL EEEE_MLB_A_32GEEEE_F1WH
825-7838 EEEE FOR 639-3736 (MLB A 16G)1 CRITICAL EEEE_MLB_A_16GEEEE_F1WD
1 CRITICAL820-3249 PCBF,MLB,X140 PCB1
051-9385
A.0.0
4 OF 154
3 OF 39
IN
OUT
IN
IN
OUT
OUT
IN
VDD_ANA_PLL
JTAG_TRST*
CFSB
CPU0_SWITCH
CPU1_SWITCH
DDR0_CKEIN
DDR1_CKEIN
DDR2_CKEIN
DDR3_CKEIN
FAST_SCAN_CLK
FUSE1_FSRC
HOLD_RESET
HSIC_VDD121
HSIC_VDD122
HSIC_VDD123
HSIC_VSS121
HSIC_VSS122
HSIC_VSS123
HSIC1_DATA
HSIC1_STB
HSIC2_DATA
HSIC2_DVDD102
HSIC2_DVSS
HSIC2_STB
HSIC3_DATA
HSIC3_DVDD103
HSIC3_DVSS
HSIC3_STB
JTAG_SEL
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRTCK
RESET*
TESTMODE
TST_CLKOUT
TST_STPCLK
USB_ANALOGTEST
USB_ASW_VDD18
USB_ASW_VSS18
USB_BRICKID
USB_BRICKID_DM_MON
USB_DM
USB_DP
USB_DVDD
USB_ID
USB_REXT
USB_VBUS
USB_VDD330
USB_VSSA0
USB11_DM
USB11_DP
WDOG
XI0
XO0SYM 1 OF 12
SYM 11 OF 12
VSSVSS
BI
BI
BI
BI
BI
BI
OUT
OUT
BI
BI
PP
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TRISTAR
NEEDED IF WE GO TO 9600
NEW TO BALI
<1MA
30MA
BB
8MABCM4330
CHANGE TO USB 3.3V TO AVOID
FAILURE IN CHARGE DETECT CIRCUIT AT 3.0V-5%
MLB OPTION USED FOR FF
PER PINPER PIN 2.7MA11.9MA
CPU_VDD CONTROL
ISSUE FOUND IN H5P:
WLAN
5.4MA
USB 1.1 BASEBAND/TRISTAR
MDM9615NOSTUFF
010051/32W5% MF100K
01005
1/32W1%
MF
100K
25 26 30 39
01005
1/32W5%
MF
7.5K
16V10%1000PF
0201X7R-CERM
01005
1/32W1%
MF
221K
25
MLB
01005
1/32W0%
MF
0.00
CRITICAL
01005
16V5%CERM
22PF
CRITICAL
SM-224.000MHZ-16PF-60PPM
CRITICAL
01005
16V5%CERM
22PF01005
1/32W5%
MF
2201005
1/32W1%
MF
1.00M
201
1%
MF
68.1K1/20W
201
1%1/20WMF
43.2
01005
10%6.3V0.01UF
X5R01005
20%6.3V0.1UF
X5R-CERM01005
0.1UF20%6.3VX5R-CERM
01005
20%X5R-CERM6.3V0.1UF
01005
10%6.3VX5R
0.01UF
01005
10%6.3VX5R
0.01UF
NP0-C0G-CERM16V+/-0.5PF8.2PF
01005
01005
1/32W0%
MF
0.00
01005
10%6.3VX5R
0.01UF
10%6.3V
402CERM
1UF+/-0.5PF8.2PF
01005NP0-C0G-CERM16V
01005
10%6.3VX5R
0.01UF
01005X5R
0.1UF20%4V
10
10 36 39
010051/32W5%
100K
1/32W 010055%
100K
010051/32W5%
100K
10
10
10
OMIT_TABLE
BALI-H5GBGA
OMIT_TABLE
BGABALI-H5G
26 36
26 36
14 36
14 36
25 36
25 36
30
30
NP0-C0G-CERM+/-0.5PF8.2PF16V
01005
01005X5R
0.1UF20%4V
01005X5R
0.1UF20%4V
+/-0.5PF8.2PF
01005NP0-C0G-CERM16V
+/-0.5PF8.2PF
01005NP0-C0G-CERM16V
+/-0.5PF8.2PF
01005NP0-C0G-CERM16V
25 36
25 36
P4MMSM
AP: MAINSYNC_MASTER=N/A SYNC_DATE=N/A
USB11_AP_BBMUX_NUSB11_AP_BBMUX_P
CPU1_SWITCHCPU0_SWITCH
USB_AP_NUSB_AP_P
HSIC1_WLAN_STBHSIC1_WLAN_DATA
HSIC3_BB_STBHSIC3_BB_DATA
AP_HOLD_RESET
AP_FAST_SCAN_CLK
AP_TST_STPCLK
JTAG_AP_TRST_L
AP_TESTMODE
AP_WDOG_RESET_IN
RST_AP_L
=PP1V8_H5
JTAG_AP_TCK
=PP1V8_PLL_H5
TP_JTAG_AP_TDO
AP_WDOG
=PP1V2_HSIC_H5
PP1V8_PL0_F
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3MM
MIN_LINE_WIDTH=0.2MMVOLTAGE=1.8V
MIN_NECK_WIDTH=0.1MM
JTAG_AP_SEL
JTAG_AP_TMSJTAG_AP_TDI
NC_HSIC2_DATANO_TEST=TRUE
NO_TEST=TRUENC_HSIC2_STB
=PP1V8_H5
=PP1V8_H5
NC_USB_IDNO_TEST=TRUE
AP_DDR1_CKEIN_1V2
NC_USB_BRICKIDNO_TEST=TRUE
NC_USB_BRICKID_DM_MONNO_TEST=TRUE
PPVBUS_USB
NC_USB_ANALOGTESTNO_TEST=TRUE
AP_24M_O
USB_REXT0
USB_AP_VBUS0
XTAL_AP_24M_I
NC_JTAG_AP_TRTCKNO_TEST=TRUE
=PP1V0_USB_H5
=PP1V8_VDDIO18_H5
=PP3V3_USB_H5
XTAL_AP_24M_O
=PP1V0_HSIC_H5
TP_AP_TST_CLKOUT
R06081 2
R06421
2
R06401
2
C06401
2
R06431
2
R06521 2
C06511
2
Y0602
2 4
1 3
C06501
2
R06511 2
R06501
2
R06101
2
R06131
2
C06351
2
C06341
2
C06331
2
C06321
2
C06311
2
C06301
2
C06071
2
R06041 2
C06091
2
C06141
2
C06121
2
C06081
2
C06131
2
R06201 2
R06211 2
R06221 2
U0600
A18
N32
N24
L6
F9
AG10
AD5
N27
L31
G16
R33
T33
R31
T28
T25
T31
AN17
AF18
AG19
AM17
R27
R26
AF19
R28
T29
AG18
H17
J17
F16
H16
F17
K16
J16
G17
D18
C19
A19
D32
E32
R25
N26
P32
P31
P29
N33
M33
R30
P27
T30
P28
P26
R29
U18
C18
J33
K33
U0600A1
A2
B2
N21
N23
P1
P8
P10
P12
P14
P16
P18
P20
B4
P22
P30
P33
R2
R6
R9
R11
R13
R15
R17
B9
R19
R21
R23
R32
T5
T6
T8
T10
T12
T14
B12
T16
T22
T24
T32
U1
U2
U4
U9
U11
U13
B15
U15
U17
U21
U23
U33
V8
V10
V12
V14
V16
B32
V19
V21
V23
V30
W3
W9
W11
W13
W15
W17
B33
W20
W22
W24
Y1
Y10
Y12
Y14
Y16
Y18
Y19
C7
Y21
Y23
Y25
Y28
Y32
AA2
AA9
AA11
AA13
AA15
C10
AA17
AA20
AA22
AA24
C13
C33
C16
A3
D3
D5
D8
D11
D14
D17
U19
E10
F1
E22
E24
E25
F2
F5
F22
F24
F25
F30
A31
A11
G3
G18
G21
G22
G26
V18
H4
H9
H10
H11
A14
H12
H13
H14
H21
H22
H28
H33
J2
J9
J11
A17
J13
J15
J21
T18
K3
K8
K10
K12
K14
K22
A32
K26
K30
L1
L4
L9
L11
L13
L15
L17
L19
A33
L21
L33
M2
M3
M8
M10
M12
M14
M16
M18
B1
M20
M22
M28
N3
N9
N11
N13
N15
N17
N19
C06361
2
C06061
2
C06051
2
C06371
2
C06211
2
C06231
2
PP0600 1
6 OF 154
051-9385
A.0.0
4 OF 39
4 5 7 10 34
25 36
34
36
34
39
10
25 36
36
4 5 7 10 34
4 5 7 10 34
29
36
36
34
6 7 9 34
34
36
34
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
IN
IN
IN
OUT
BI
OUT
BI
OUT
BI
OUT
OUT
IN
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
IN
OUT
IN
IN
IN
SWI_DATA
SPI3_SSIN
SPI3_SCLK
SPI3_MOSI
SPI3_MISO
SPI2_SSIN
SPI2_SCLK
SPI2_MOSI
SPI2_MISO
SPI1_SSIN
SPI1_SCLK
SPI1_MOSI
SPI1_MISO
SPI0_SSIN
SPI0_SCLK
SPI0_MOSI
SPI0_MISO
SPDIF
I2S4_MCK
I2S4_LRCK
I2S4_DOUT
I2S4_DIN
I2S4_BCLK
I2S3_MCK
I2S3_LRCK
I2S3_DOUT
I2S3_DIN
I2S3_BCLK
I2S2_MCK
I2S2_LRCK
I2S2_DIN
I2S2_BCLK
I2S1_MCK
I2S1_LRCK
I2S1_DOUT
I2S1_DIN
I2S1_BCLK
I2S0_MCK
I2S0_LRCK
I2S0_DOUT
I2S0_DIN
I2S0_BCLK
I2C2_SDA
I2C2_SCL
I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL
DWI_DO
DWI_DI
DWI_CLK
I2S2_DOUT
SYM 3 OF 12
UART6_TXD
UART6_RXD
UART6_RTSN
UART6_CTSN
UART5_TXD
UART5_RXD
UART4_TXD
UART4_RXD
UART4_RTSN
UART4_CTSN
UART3_TXD
UART3_RXD
UART3_RTSN
UART3_CTSN
UART2_TXD
UART2_RXD
UART2_RTSN
UART2_CTSN
UART1_TXD
UART1_RXD
UART1_RTSN
UART1_CTSN
UART0_TXD
UART0_RXD
TMR32_PWM2
TMR32_PWM1
TMR32_PWM0
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO39
GPIO38
GPIO37
GPIO36
GPIO35
GPIO34
GPIO33
GPIO32
GPIO31
GPIO30
GPIO3
GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO2
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO1
GPIO0
GPIO_VSEL25_SPI3
GPIO_VSEL25_I2C2
GPIO_SVSEL25_FMI
GPIO_SVSEL18_FMI
GPIO_3V1
GPIO_3V0
EHCI_PORT_PWR3
EHCI_PORT_PWR2
EHCI_PORT_PWR1
EHCI_PORT_PWR0
GPIO10
SYM 2 OF 12
ININ
OUT
IN
IN
IN
IN
IN
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
OS CURRENTLY SUPPORTSUSB1.1 FOR DEBUG.
TO SENSOR BOARD:
3.0V
1.8V
WIFI DEBUG
1.8VTO TRISTAR
MDM9600
TO TRISTAR
AND SIZE THESE RESISTORSNEED TO CHARACTERIZE RISE TIME
AD7149 PROX 0101100XTO SENSOR BOARD:
NOT USED
1.8VBT
L81 CODEC XSP1.8V
1.8V IO
AND SW UPDATE
TO BB
GRAPE
VSEL25_SPI3 HIGH => SPI3 3.0VVSEL25_I2C2 HIGH => I2C2 3.0VVSEL18_FMI AND VSEL25_FMI LOW => FMI CHANNEL AT 1.8V
TO BT UARTBCM4330
AP3GDL8 GYRO 1101000X
CT809 ALS 0111001X
TO:TRISTAR 0011010X
TO BB UART
1.8V
1.8V
AKM8975B COMPASS 0001110X
L81 CODEC ASP
ADRIANA PMU 0111100XL19 LEFT 1000000XL19 RIGHT 1000001X
I2C PULL-UPSBUTTON PULLUPS
L19 AMPLIFIERS
USED FOR DEBUG
LIS331DLH ACCEL 0011001X
MF
220K
5%1/20W
201
5%1/20W
220K
MF201
220K
MF201
1/20W5%
NOSTUFF
100K
MF201
5%1/20W
NOSTUFF
1/20W5%
201MF
100K100K
MF201
5%1/20W
100K
MF201
5%1/20W
1/32W
01005MF
33.21%
14 36
14 36
14 36
14 36
18 36
18 36
18 36
18 36
18 36
18 36
18 36
18 36
18 36
10
10
10
100K
MF201
5%1/20W
26 36
5 19 25 30 36
5 19 25 30 36
5 22 36
5 22 36
5 22 36
5 22 36
30 36
30 36
30 36
14
22
26
26
5 26
26 36
20
26
5 30
10
5 32
5
10
10
10
10
10
25 36
25 36
26 36
26 36
25 26 36
25 26 36
14 36
14 36
14 36
14 36
14 36
14 36
25 36
25 36
26 39
28 30
20
22
5 14 36
30
18
5 20 30
OMIT_TABLE
BALI-H5GBGA
OMIT_TABLE
BALI-H5GBGA
19 26
26
26
MF01005
1/32W5%1.00K1.00K
MF01005
5%1/32W
1.00K
MF01005
5%1/32W
1.00K
MF01005
5%1/32W
2.2K
MF01005
5%1/32W
2.2K
MF01005
5%1/32W
14 36
26 36
5 23 30
5 20 30
5 19
22
26
10
100K
MF201
5%1/20W
16 36
16 36
16 36
16 36
18 36
18 36
18 36
18 36
100K
MF201
5%1/20W
100K
MF201
5%1/20W
22
22
22
25 30
16
16
5 16
15
14
NOSTUFF
MF201
5%1/20W
100K
33.2
MF01005
1%1/32W
19
26
19
19
26
5 19
19
19
19
19
100K
MF201
5%1/20W 1/20W
5%
201MF
100K
10
SYNC_MASTER=N/A SYNC_DATE=N/A
AP: I/Os
I2S2_BT_BCLKI2S2_BT_LRCKI2S2_BT_DINI2S2_BT_DOUT
I2S3_CODEC_XSP_BCLKI2S3_CODEC_XSP_LRCKI2S3_CODEC_XSP_DIN
I2S0_CODEC_ASP_BCLKI2S0_CODEC_ASP_LRCKI2S0_CODEC_ASP_DINI2S0_CODEC_ASP_DOUT
I2S0_CODEC_ASP_MCK_R
I2S3_CODEC_XSP_DOUT
GPIO_BOARD_ID_2
GPIO_BOARD_ID_0GPIO_BOARD_ID_1
GPIO_BB_HSIC_HOST_RDY
I2C0_SCL_1V8I2C0_SDA_1V8
I2C1_SDA_1V8
I2C2_SCL_3V0I2C2_SDA_3V0
DWI_AP_CLKDWI_AP_DIDWI_AP_DO
GPIO_BT_WAKEGPIO_ALS_IRQ_L
GPIO_AP_MODEM_WAKE
GPIO_BB_RESET_DET_LGPIO_BB_RADIO_ON_L
GPIO_BB_HSIC_RESUME
GPIO_PMU_KEEPACT
GPIO_BOOT_CONFIG_1GPIO_FORCE_DFUGPIO_DFU_STATUSGPIO_BOOT_CONFIG_2GPIO_BOOT_CONFIG_3
GPIO_BRD_REV0GPIO_BRD_REV1GPIO_BRD_REV2
UART6_AP_RXDUART6_AP_TXD
UART1_BB_CTS_LUART1_BB_RTS_LUART1_BB_RXDUART1_BB_TXD
UART3_BT_CTS_LUART3_BT_RTS_LUART3_BT_RXDUART3_BT_TXD
UART4_WLAN_RXDUART4_WLAN_TXD
UART2_TS_ACC_RXDUART2_TS_ACC_TXD
GPIO_BB_RST_L
UART5_BATTERY_TRXD
GPIO_BTN_VOL_UP_L
GPIO_WLAN_HSIC_HOST_RDY
GPIO_PMU_IRQ_L
GPIO_CODEC_IRQ_L
GPIO_BTN_SRL_L
SPK_IDBB_JTAG_TRST_RF_LBB_JTAG_TDI_RFBB_JTAG_TDO_RF
GPIO_WLAN_HSIC_DEV_RDY
GPIO_BB_HSIC_DEV_RDY
GPIO_BTN_HOME_LGPIO_BTN_ONOFF_L
GPIO_SPKAMP_RST_L
GPIO_PROX_IRQ_LGPIO_BB_GPS_SYNCGPIO_BOOT_CONFIG_0
SPI3_GRAPE_MISOSPI3_GRAPE_MOSISPI3_GRAPE_SCLKSPI3_GRAPE_CS_L
SPI1_CODEC_MISOSPI1_CODEC_MOSISPI1_CODEC_SCLKSPI1_CODEC_CS_L
GPIO_GYRO_IRQ1
GPIO_GYRO_IRQ2GPIO_ACCEL_IRQ1_L
PMU_GPIO_TS_INT
GPIO_GRAPE_FW_DNLD_EN_LGPIO_GRAPE_RST_L
GPIO_GRAPE_IRQ_L
PM_LCDVDD_PWREN
GPIO_WL_HSIC_RESUME
I2S1_SPKAMP_MCK_R
BB_JTAG_TMS_RF
GPIO_SPKAMP_RIGHT_IRQ_L
GPIO_SPKAMP_LEFT_IRQ_L
BB_JTAG_TCK_RF
GPIO_SPKAMP_KEEPALIVE
I2S1_SPKAMP_BCLKI2S1_SPKAMP_LRCKI2S1_SPKAMP_DINI2S1_SPKAMP_DOUT
GPIO_BTN_VOL_DOWN_L
GPIO_ACCEL_IRQ2_L
GPIO_BB_GSM_TXBURSTGPIO_BOARD_ID_3
=PP1V8_S2R_MISC
=PP1V8_ALWAYS
GPIO_BTN_ONOFF_L
NC_UART0_RXDNO_TEST=TRUE
NC_TMR32_PWM2_APNO_TEST=TRUE
NC_UART2_RTSNNO_TEST=TRUE
NC_UART6_RTSNNO_TEST=TRUE
NC_UART6_CTSNNO_TEST=TRUE
NC_UART5_TXDNO_TEST=TRUE
NC_EHCI_PORT_PWR3_APNO_TEST=TRUE
NC_UART4_CTS_LNO_TEST=TRUE
NC_UART0_TXDNO_TEST=TRUE
I2C2_SCL_3V0
I2C1_SCL_1V8
I2C1_SDA_1V8
I2C2_SDA_3V0
I2C0_SCL_1V8
PP3V0_SENSOR_FLT
NC_SWI_APNO_TEST=TRUE
NC_I2S4_MCK NO_TEST=TRUE
NC_I2S4_LRCK NO_TEST=TRUE
NC_I2S4_DIN NO_TEST=TRUE
NC_I2S4_BCLK NO_TEST=TRUE
GPIO_VSEL25_SPI3
GPIO_VSEL25_I2C2
=PP1V8_H5
GPIO_GRAPE_IRQ_L
I2C0_SDA_1V8
=PP1V8_H5
=PP1V8_H5
I2S1_SPKAMP_MCK
NC_I2S2_MCK NO_TEST=TRUE
NC_I2S3_MCK NO_TEST=TRUE
TP_SPI0_SSIN
I2S0_CODEC_ASP_MCK
GPIO_BTN_SRL_L
GPIO_SPKAMP_RST_LGPIO_WLAN_HSIC_HOST_RDYGPIO_BB_RADIO_ON_LGPIO_DFU_STATUSGPIO_FORCE_DFUGPIO_PMU_KEEPACT
GPIO_SPKAMP_KEEPALIVE
=PP1V8_S2R_MISC
NC_UART4_RTC_LNO_TEST=TRUE
NC_I2S4_DOUT NO_TEST=TRUE
NC_AP_GPIO216 NO_TEST=TRUE
GPIO_BTN_HOME_L
I2C1_SCL_1V8
R07081 2
R07091 2
R07101 2
R07151
2
R07141
2
R07131
2
R07111
2
R0700
1 2
R07201
2
U0600
T26
W32
W28
Y33
U29
W27
W29
H20
B19
M29
M32
M26
N31
M27
L24
M24
N30
L23
H30
L29
L26
L25
L28
J29
E29
J25
M30
K32
L32
H25
K31
J32
K28
F31
K29
Y31
V28
V32
V29
AB29
Y29
AA28
AA32
AB28
AB33
AC29
W33
D19
G20
E19
F19
AB27
U0600
AK28
AJ25
AK26
AK27
AK20
AJ19
AJ18
AJ23
AK23
AJ20
AJ22
AJ24
AL25
AM26
AK25
AN26
AK22
F26
E26
J31
F29
E30
H31
J30
H32
G27
E27
AK19
F32
J28
G31
G32
G28
G33
J26
G30
G29
F27
AK21
AK24
AJ21
AK18
AL26
AH25
H19
J19
H27
G25
E31
H29
V33
W31
V27
K18
K19
AM27
AM28
AN27
AN28
Y30
AC27
AC33
AD33
AB32
AC30
AC32
AD32
Y27
AA29
AB31
AC31
J18
K17
AC28
W30
AA30
AA31
R07061
2
R07051
2
R07041
2
R07031
2
R07021
2
R07011
2
R07161
2
R07171
2
R07181
2
R07601
2
R0730
1 2
R07191
2
R07211
2 051-9385
A.0.0
7 OF 154
5 OF 39
5 32 34
34
5 20 30
35
5 22 36
5 22 36
5 22 36
5 22 36
5 19 25 30 36
20 21
4 5 7 10 34
5 16
5 19 25 30 36
4 5 7 10 34
4 5 7 10 34
36
5 20 30
5 19
5 14 36
5 26
5
5 32
5 30
5 19
5 32 34
5 23 30
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
PVDDP_GRP3
PVDDP_GRP2
PVDDP_GRP1
FMI1_WENN
FMI1_WEN
FMI1_REN
FMI1_IO7
FMI1_IO6
FMI1_IO5
FMI1_IO4
FMI1_IO3
FMI1_IO2
FMI1_IO1
FMI1_IO0
FMI1_DQVREF
FMI1_DQSN
FMI1_DQS
FMI1_CLE
FMI1_CEN7
FMI1_CEN6
FMI1_CEN5
FMI1_CEN4
FMI1_CEN3
FMI1_CEN2
FMI1_CEN1
FMI1_CEN0
FMI1_ALE
FMI0_WENN
FMI0_IO4
FMI0_IO3
FMI0_IO2
FMI0_IO1
FMI0_IO0
FMI0_DQVREF
FMI0_DQSN
FMI0_CLE
FMI0_CEN7
FMI0_CEN6
FMI0_CEN5
FMI0_CEN4
FMI0_CEN3
FMI0_CEN2
FMI0_CEN1
FMI0_CEN0
FMI0_ALE
FMI0_IO7
FMI0_IO6
FMI0_IO5
FMI0_WEN
FMI0_REN
FMI0_DQS
PVDDP_GRP4
PVDDP_GRP5
FMI1_VREFFMI0_VREF
SYM 4 OF 12
VSS
VSS
SYM 12 OF 12
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
6 13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
6 13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
1/32W5%
01005MF
100K
13 38
13 38
13 38
13 38
51.1K1/32W1%
01005MF
51.1K1/32W1%
01005MF
01005X5R4V20%0.1UF
01005
4V20%X5R
0.1UF
OMIT_TABLE
BGABALI-H5G
CKPLUS_WAIVE=PDIFPR_BADTERMCKPLUS_WAIVE=PDIFPR_BADTERM
OMIT_TABLE
BGABALI-H5G
4V20%
01005X5R
0.1UF4V20%
01005X5R
0.1UF
4V20%
01005X5R
0.1UF4V20%
01005X5R
0.1UF4V20%
01005X5R
0.1UF
1/32W5%
01005MF
100K
AP: NANDSYNC_DATE=N/ASYNC_MASTER=N/A
FMI_DQVREF_H5FMI_DQVREF_H5
=PP1V8_NAND_H5
=PP1V8_NAND_H5
=PP1V8_VDDIO18_H5
=PP1V8_VDDIO18_H5=PP1V8_NAND_H5
NO_TEST=TRUENC_FMI0_CE4_L
NO_TEST=TRUENC_FMI0_CE6_L
FMI0_CE0_L
NO_TEST=TRUENC_FMI0_CE7_L
FMI1_CE0_L
NO_TEST=TRUE NC_FMI1_CE4_L
NO_TEST=TRUE NC_FMI1_CE5_L
NO_TEST=TRUE NC_FMI1_CE7_LNO_TEST=TRUE NC_FMI1_CE6_L
NO_TEST=TRUE NC_FMI1_CE3_LNO_TEST=TRUE NC_FMI1_CE2_LNO_TEST=TRUE NC_FMI1_CE1_L
NO_TEST=TRUENC_FMI0_CE3_L
=PP1V8_NAND_H5NO_TEST=TRUE NC_FMI1_DQSNNO_TEST=TRUENC_FMI0_DQSN
NO_TEST=TRUENC_FMI0_CE5_L
NO_TEST=TRUENC_FMI0_RE NO_TEST=TRUE NC_FMI1_RE
NO_TEST=TRUENC_FMI0_CE1_L
NO_TEST=TRUENC_FMI0_CE2_L
FMI1_DQSFMI1_RE_LFMI1_WE_LFMI1_CLEFMI1_ALE
FMI1_AD<7>FMI1_AD<6>FMI1_AD<5>FMI1_AD<4>FMI1_AD<3>FMI1_AD<2>FMI1_AD<1>FMI1_AD<0>
FMI1_CE0_L
FMI0_CLE
FMI0_DQS
FMI0_WE_LFMI0_RE_L
FMI0_ALE
FMI0_AD<7>FMI0_AD<6>FMI0_AD<5>FMI0_AD<4>FMI0_AD<3>FMI0_AD<2>FMI0_AD<1>FMI0_AD<0>
FMI0_CE0_L
R08311
2
R08321
2
R08421
2
R08431
2
C08421
2
C08431
2
U0600
AJ28
AN29
AM30
AL28
AL27
AJ32
AJ31
AM31
AL30
AH29
AL31
AL32
AG27
AM29
AK33
AJ30
AK31
AH28
AJ29
AN30
AH27
AK30
AG28
AK32
AK29
AJ33
AF29
AF30
AE29
AD30
AF27
AE27
AF28
AE28
AH31
AF32
AF33
AD27
AE33
AH33
AG33
AG30
AD31
AE31
AG29
AD29
AF31
AD28
AG32
AG31
AF26
AB26
P25
G19
K24
U0600AB8
AB10
AB12
AB14
AB16
AB18
AB19
AB21
AB23
AB25
AB30
AC1
AC3
AC9
AC11
AC13
AC15
AC17
AC20
AC22
AC24
AD8
AD10
AD12
AD14
AD16
AD18
AD19
AD21
AD23
AD25
AE4
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE17
AE22
AE30
AE32
A6
AF3
AF16
AG2
AG16
AG17
AG25
AH5
AH10
AH15
AH16
AH17
AH30
AH32
P24
AJ17
AJ27
AK2
AK8
AK14
AK17
AH1
AL3
AL7
AL10
AL13
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL1
AL29
AM1
AM2
AM6
AM9
AM12
AM15
AM32
AM33
AN1
AN2
AL33
T20
AN11
AN14
AN32
AN33
AN3
AN31
AN6
C1
C08201
2
C08211
2
C08101
2
C08111
2
C08121
2
051-9385
A.0.0
8 OF 154
6 OF 39
6 6
6 9 34
6 9 34
4 6 7 9 34
4 6 7 9 34 6 9 34
6 13 38
6 13 38
6 9 34
IN
OUT
OUT
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
MIPI_VSS
ISP0_FLASH
ISP0_PRE_FLASH
ISP0_SCL
ISP0_SDA
ISP1_FLASH
ISP1_PRE_FLASH
ISP1_SCL
ISP1_SDA
MIPI_VDD10
MIPI_VSYNC
MIPI0C_DNCLK
MIPI0C_DNDATA0
MIPI0C_DNDATA1
MIPI0C_DNDATA2
MIPI0C_DNDATA3
MIPI0C_DPCLK
MIPI0C_DPDATA0
MIPI0C_DPDATA1
MIPI0C_DPDATA2
MIPI0C_DPDATA3
MIPI0D_VDD10_PLL
MIPI0D_VDD18
MIPI0D_VREG_0P4V
MIPI1C_DNCLK
MIPI1C_DNDATA0
MIPI1C_DNDATA1
MIPI1C_DPCLK
MIPI1C_DPDATA0
MIPI1C_DPDATA1
MIPI1D_VDD10_PLL
MIPI1D_VDD18
MIPI1D_VREG_0P4V
SENSOR0_CLK
SENSOR0_RST
SENSOR1_CLK
SENSOR1_RST
SYM 5 OF 12
EDP_PAD_TX3P
EDP_PAD_TX3N
EDP_PAD_TX2P
EDP_PAD_TX2N
EDP_PAD_TX1P
EDP_PAD_TX1N
EDP_PAD_TX0P
EDP_PAD_TX0N
EDP_PAD_R_BIAS
EDP_PAD_DVSS
EDP_PAD_DVDD
EDP_PAD_DC_TP
EDP_PAD_AVSSX
EDP_PAD_AVSSP0
EDP_PAD_AVSS3
EDP_PAD_AVSS2
EDP_PAD_AVSS1
EDP_PAD_AVSS0
EDP_PAD_AVSS_AUX
EDP_PAD_AVDDX
EDP_PAD_AVDDP0
EDP_PAD_AVDD3
EDP_PAD_AVDD2
EDP_PAD_AVDD1
EDP_PAD_AVDD0
EDP_PAD_AVDD_AUX
EDP_PAD_AUXP
EDP_PAD_AUXN
EDP_HPD
DP_PAD_TX3P
DP_PAD_TX3N
DP_PAD_TX2P
DP_PAD_TX2N
DP_PAD_TX1P
DP_PAD_TX1N
DP_PAD_TX0P
DP_PAD_TX0N
DP_PAD_R_BIAS
DP_PAD_DVSS
DP_PAD_DVDD
DP_PAD_DC_TP
DP_PAD_AVSSX
DP_PAD_AVSSP0
DP_PAD_AVSS3
DP_PAD_AVSS2
DP_PAD_AVSS1
DP_PAD_AVSS0
DP_PAD_AVSS_AUX
DP_PAD_AVDDX
DP_PAD_AVDDP0
DP_PAD_AVDD3
DP_PAD_AVDD2
DP_PAD_AVDD1
DP_PAD_AVDD0
DP_PAD_AVDD_AUX
DP_PAD_AUXP
DP_PAD_AUXN
DP_HPD
DAC_VREF DAC_OUT3
DAC_OUT2
DAC_OUT1
DAC_IREF
DAC_AVSS18D
DAC_AVSS18A
DAC_AVDD18D
DAC_AVDD18A
DAC_COMP
SYM 6 OF 12
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TABLE_ALT_ITEM
SOCHOT1_L PULL-UP ON CSA 90
3.3MA
3.3MA
15MA65MA
2MA
40MA
PER PIN
65MA
22MA
15MA
10MA PER PIN
16MA
22MA
PER PIN 15MA
NOTE: 0.6V ANALOG REF
FRONT FACING CAM
15MA
16MA
10MA
SHUTDOWN IS ACTIVE LOW
SHUTDOWN IS ACTIVE HIGH
REAR FACING CAM
NOTE: 0.6V ANALOG REF
56PF5%6.3VNP0-C0G01005
4V20%0.1UF
X5R0100556PF
5%6.3VNP0-C0G01005
0
MF
5%1/20W
20156PF5%6.3VNP0-C0G01005
0.22UF
402
20%6.3VX5R
0.22UF
402
20%6.3VX5R
0.22UF20%6.3V
402X5R
0.01UF6.3VX5R10%
01005
0.01UF6.3VX5R10%
01005
4V20%0.1UF
X5R01005
25VCER0201
+/-0.1PF%8.2PF
0.1UF6.3VX5R201
10%
240-OHM-0.2A-0.8-OHM
0201
NOSTUFF
0.1UF6.3V
NOSTUFF
X5R201
10%
6.34K1%1/20W
NOSTUFF
201MF
0.1UF6.3V
NOSTUFF
X5R201
10%
15 37
MF
5%1/32W
1.00K
01005MF
5%1/32W
1.00K
01005
22 36
22 36
22 36
22 36
1.00K
MF
5%1/32W
01005
1.00K
MF
5%1/32W
01005
010050%
1/32W
0.00MF
0.00MF0%
1/32W 01005
0.1UF6.3VX5R201
10%
0.1UF6.3VX5R201
10%0.1UF6.3VX5R201
10%1UF
CERM402
6.3V10%
0201
2.2NF10%10VX5R-CERM
10VX5R-CERM10%2.2NF
0201
56PF5%6.3VNP0-C0G01005
1UF
CERM402
6.3V10%
0.01UF6.3VX5R
10%
01005
80-OHM-0.2A-0.4-OHM
0201-1
0.01UF6.3V
NOSTUFF
X5R10%
01005
4.99K
MF
1%1/32W
01005
15 37
15 37
15 37
15 37
15 37
15 37
4.99K
MF
1%1/32W
01005
15 37
15 37
15 37
15 37
0.01UF6.3V
NOSTUFF
X5R10%
01005
BALI-H5GBGA
OMIT_TABLE
BALI-H5GBGA
OMIT_TABLE
22
22 36
22
22 36
22
21 37
21 37
21 37
21 37
21 37
21 37
21 37
21 37
21 37
21 37
16VNP0-C0G-CERM01005
8.2PF+/-0.5PF
16VNP0-C0G-CERM01005
8.2PF+/-0.5PF
16VNP0-C0G-CERM+/-0.5PF8.2PF
01005
100K
MF
5%1/32W
NOSTUFF
01005
100K
MF
5%1/32W
01005
SYNC_MASTER=N/A SYNC_DATE=N/A
AP: TV,DP,MIPI
FL0910155S0725 155S0359 ? RDAR://PROBLEM/11104943
=PP1V0_MIPI_H5
=PP1V8_MIPI_H5
EDP_AUX_PEDP_AUX_N
=PP1V8_VDDIO18_H5
MIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWRPP0V4_MIPI0D
VOLTAGE=0.4V
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3MM
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.1MMPP0V4_MIPI1D
VOLTAGE=0.4VMIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
VOLTAGE=1.8VMIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.1MM
PP1V8_EDP_AVDD_AUX
EDP_HPD
ISP0_CAM_RF_I2C_SDA
EDP_DATA_P<0>EDP_DATA_N<0>
EDP_DATA_P<1>EDP_DATA_N<1>
EDP_DATA_P<2>EDP_DATA_N<2>
EDP_DATA_P<3>
ISP1_CAM_FF_CLK
MIPI1C_CAM_FF_CLK_PMIPI1C_CAM_FF_CLK_N
MIPI1C_CAM_FF_DATA_N<0>MIPI1C_CAM_FF_DATA_P<0>
MIPI0C_CAM_RF_CLK_P
MIPI0C_CAM_RF_DATA_N<1>MIPI0C_CAM_RF_DATA_P<1>
MIPI0C_CAM_RF_DATA_N<0>MIPI0C_CAM_RF_DATA_P<0>
SOCHOT0_L
SOCHOT1_L
=PP1V8_H5
SOCHOT0_LSOCHOT1_L
ISP0_CAM_RF_CLK_R
NC_MIPI1C_CAM_FF_DATA_P<1>NO_TEST=TRUE
NC_DAC_AP_OUT3NO_TEST=TRUE
=PP1V0_MIPI_PLL_H5
NC_MIPI1C_CAM_FF_DATA_N<1>NO_TEST=TRUE
NC_MIPI0C_CAM_RF_DATA_P<3> NO_TEST=TRUE
NC_MIPI0C_CAM_RF_DATA_P<2> NO_TEST=TRUE
NC_MIPI0C_CAM_RF_DATA_N<3> NO_TEST=TRUE
NC_MIPI0C_CAM_RF_DATA_N<2> NO_TEST=TRUE
DAC_AP_COMP
NC_DAC_AP_OUT2NO_TEST=TRUE
TP_DP_AP_ANALOG_TEST
NC_DP_DATA_N<2>NO_TEST=TRUE
NC_DP_DATA_P<2>NO_TEST=TRUE
NC_DP_DATA_N<3>NO_TEST=TRUE
NC_DP_DATA_P<3>NO_TEST=TRUE
DP_R_BIAS
NC_MIPI_VSYNC_H5 NO_TEST=TRUE
NC_DP_DATA_N<1>NO_TEST=TRUE
NC_DP_DATA_P<1>NO_TEST=TRUE
NC_DP_DATA_N<0>NO_TEST=TRUE
NC_DP_DATA_P<0>NO_TEST=TRUE
NC_DP_AUX_NNO_TEST=TRUE
VOLTAGE=1.0V
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3MM
MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MM
PP1V0_MIPI_PLL_F
NC_DAC_AP_OUT1NO_TEST=TRUE
NC_DP_HPDNO_TEST=TRUE
NC_DP_AUX_PNO_TEST=TRUE
=PP1V8_VDDIO18_H5
=PP1V0_DP_PAD_DVDD_H5
=PP1V8_EDP_H5
DAC_AP_COMP_FTR
DAC_AP_IREF
=PP1V8_VDDIO18_H5
=PP1V8_H5
ISP0_CAM_RF_RST_L
ISP0_CAM_RF_CLK
ISP1_CAM_FF_I2C_SCL
=PP1V8_DP_H5
=PP1V0_EDP_PAD_DVDD_H5
ISP0_CAM_RF_SHUTDOWN
ISP1_CAM_FF_CLK_RISP1_CAM_FF_SHUTDOWN_L
ISP1_CAM_FF_I2C_SDA
ISP0_CAM_RF_I2C_SCL
NO_TEST=TRUE NC_ISP0_CAM_RF_FLASH
TP_EDP_AP_ANALOG_TEST
EDP_DATA_N<3>
AP_EDP_R_BIAS
DAC_AP_VREF
MIPI0C_CAM_RF_CLK_N
C09241
2
C09271
2C09301
2
R09111 2
C09311
2
C09321
2
C09331
2
C09341
2
C09531
2
C09521
2
C09511
2
C09101
2
C09091
2
FL0911
1 2
C09561
2
R09501
2
C09551
2
R09331
2
R09321
2
R09311
2
R09301
2
R09001 2
R09401 2
C09071
2
C09031
2
C09081
2
C09351
2C09611
2
C09601
2
C09821
2
C09801
2
C09811
2
FL0910
1 2
C09501
2
R09211
2
R09201
2
C09571
2
U0600 M25
M31
AA27
U28
N25
L30
AA33
U30
AN20
AN22
AN21
AN19
AN18
AM20
AM22
AM21
AM19
AM18
AH21
AH19
AH20
AN24
AN23
AN25
AM24
AM23
AM25
AH22
AH24
AH23
AF20
AF21
AF22
AF23
AF24
AG20
AG21
AG22
AG23
AG24
U27
V31
U32
U31
T27
U0600
H24
H23
G24
G23
K23
J24
F33
E33
D33J23
B18
A25
A26
E21
E20
B20
A20
D22
D21
C23
F21
F20
D20
C20
B22
B21
A23
F23
C24
A24
E23
D23
D24
B23
B24
C21
C22
A21
A22
E18
C29
C30
C28
C27
D26
D25
D30
D29
B31
A28
A27
B26
B25
B30
B29
C32
F28
C31
D31
E28
A29
A30
D27
D28
B27
B28
C25
C26
C09291
2
C09281
2
C09041
2
R09421
2
R09411
2
051-9385
A.0.0
9 OF 154
7 OF 39
34
34
4 6 7 9 34
39
7
7 32
4 5 7 10 34
7
7 32
36
34 39
4 6 7 9 34
34
34
4 6 7 9 34
4 5 7 10 34
34
34
36
39
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DDR1_VREF_DQ
DDR1_VDD_CKE
DDR1_RREF
DDR1_PDQS3
DDR1_PDQS2
DDR1_PDQS1
DDR1_PDQS0
DDR1_NDQS3
DDR1_NDQS2
DDR1_NDQS1
DDR1_NDQS0
DDR1_DQ9
DDR1_DQ8
DDR1_DQ7
DDR1_DQ6
DDR1_DQ5
DDR1_DQ4
DDR1_DQ31
DDR1_DQ30
DDR1_DQ3
DDR1_DQ29
DDR1_DQ28
DDR1_DQ27
DDR1_DQ26
DDR1_DQ25
DDR1_DQ24
DDR1_DQ23
DDR1_DQ22
DDR1_DQ21
DDR1_DQ20
DDR1_DQ2
DDR1_DQ19
DDR1_DQ18
DDR1_DQ17
DDR1_DQ16
DDR1_DQ15
DDR1_DQ14
DDR1_DQ13
DDR1_DQ12
DDR1_DQ11
DDR1_DQ10
DDR1_DQ1
DDR1_DQ0
DDR1_DM3
DDR1_DM2
DDR1_DM1
DDR1_DM0
DDR1_CSN1
DDR1_CSN0
DDR1_CKE1
DDR1_CKE0
DDR1_CKB
DDR1_CK
DDR1_CA9
DDR1_CA8
DDR1_CA7
DDR1_CA6
DDR1_CA5
DDR1_CA4
DDR1_CA3
DDR1_CA2
DDR1_CA1
DDR1_CA0
DDR0_VREF_DQ
DDR0_VDD_CKE
DDR0_RREF
DDR0_PDQS3
DDR0_PDQS2
DDR0_PDQS1
DDR0_PDQS0
DDR0_NDQS3
DDR0_NDQS2
DDR0_NDQS1
DDR0_NDQS0
DDR0_DQ9
DDR0_DQ8
DDR0_DQ7
DDR0_DQ6
DDR0_DQ5
DDR0_DQ4
DDR0_DQ31
DDR0_DQ30
DDR0_DQ3
DDR0_DQ29
DDR0_DQ28
DDR0_DQ27
DDR0_DQ26
DDR0_DQ25
DDR0_DQ24
DDR0_DQ23
DDR0_DQ22
DDR0_DQ21
DDR0_DQ20
DDR0_DQ2
DDR0_DQ19
DDR0_DQ18
DDR0_DQ17
DDR0_DQ16
DDR0_DQ15
DDR0_DQ13
DDR0_DQ12
DDR0_DQ10
DDR0_DQ1
DDR0_DQ0
DDR0_DM3
DDR0_DM2
DDR0_DM1
DDR0_DM0
DDR0_CSN1
DDR0_CSN0
DDR0_CKE1
DDR0_CKE0
DDR0_CKB
DDR0_CK
DDR0_CA9
DDR0_CA8
DDR0_CA7
DDR0_CA6
DDR0_CA5
DDR0_CA4
DDR0_CA3
DDR0_CA2
DDR0_CA1
DDR0_CA0
DDR0_DQ14
DDR0_DQ11
SYM 7 OF 12
DDR2_CA0
DDR2_CA1
DDR2_CA2
DDR2_CA3
DDR2_CA8
DDR2_CA9
DDR2_CK
DDR2_CKB
DDR2_CKE0
DDR2_CKE1
DDR2_CSN1
DDR2_DM1
DDR2_DM2
DDR2_DM3
DDR2_DQ1
DDR2_DQ14
DDR2_DQ31
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DQ8
DDR2_NDQS1
DDR2_NDQS2
DDR2_NDQS3
DDR2_PDQS3
DDR2_RREF
DDR2_VREF_DQ
DDR3_CA0
DDR3_CA1
DDR3_CA2
DDR3_CA3
DDR3_CA7
DDR3_CA8
DDR3_CA9
DDR3_CK
DDR3_CKB
DDR3_CKE0
DDR3_CKE1
DDR3_CSN0
DDR3_CSN1
DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DQ0
DDR3_DQ1
DDR3_DQ10
DDR3_DQ11
DDR3_DQ13
DDR3_DQ15
DDR3_DQ17
DDR3_DQ18
DDR3_DQ19
DDR3_DQ20
DDR3_DQ21
DDR3_DQ22
DDR3_DQ23
DDR3_DQ24
DDR3_DQ25
DDR3_DQ27
DDR3_DQ28
DDR3_DQ29
DDR3_DQ3
DDR3_DQ30
DDR3_DQ31
DDR3_DQ4
DDR3_DQ5
DDR3_NDQS0
DDR3_PDQS3
DDR3_RREF
DDR3_DM3
DDR3_PDQS0DDR2_PDQS0
DDR2_NDQS0
DDR2_PDQS1
DDR2_PDQS2
DDR3_CA4
DDR2_DQ12
DDR2_VDD_CKE
DDR2_CSN0
DDR2_DQ13
DDR2_DQ15
DDR2_DQ16
DDR2_DQ17
DDR2_DQ18
DDR2_DQ19
DDR2_DQ20
DDR2_DQ21
DDR2_DQ22
DDR2_DQ0
DDR2_DQ2
DDR2_DQ4
DDR2_DQ3
DDR2_CA7
DDR2_CA6
DDR2_CA5
DDR2_CA4
DDR2_DQ30
DDR2_DQ11
DDR2_DQ10
DDR2_DQ9
DDR3_DQ26
DDR3_CA5
DDR3_DQ12
DDR3_DQ14
DDR3_DQ16
DDR3_DQ2
DDR3_CA6
DDR2_DQ29
DDR2_DQ27
DDR2_DQ26
DDR2_DQ25
DDR2_DQ24
DDR2_DQ23
DDR2_DQ28
DDR2_DM0
DDR3_PDQS1
DDR3_PDQS2
DDR3_DQ9
DDR3_DQ8
DDR3_DQ7
DDR3_DQ6
DDR3_VDD_CKE
DDR3_VREF_DQ
DDR3_NDQS3
DDR3_NDQS2
DDR3_NDQS1
SYM 8 OF 12
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
11 38
11 38
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11 38
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11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
11 38
11 38
11 38
11 38
11 38
0.01UF
X5R01005
10%6.3V
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
4.7K
MF01005
1%1/32W
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
4.7K
MF01005
1%1/32W
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
0.01UF
X5R01005
10%6.3V
11 38
11 38
11 38
11 38
11 38
11 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
4.7K
MF01005
1%1/32W
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
4.7K
MF01005
1%1/32W
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
12 38
0.22UF
X5R0201
20%6.3V
0.22UF
X5R0201
20%6.3V
0.22UF
X5R0201
20%6.3V
0.22UF
X5R0201
20%6.3V
BALI-H5GBGA
OMIT_TABLE
BALI-H5GBGA
OMIT_TABLE
0.01UF
X5R01005
10%6.3V
4.7K
MF01005
1%1/32W
4.7K
MF01005
1%1/32W
0.01UF
X5R01005
10%6.3V
4.7K
MF01005
1%1/32W
4.7K
MF01005
1%1/32W
240
MF201
1%1/20W
240
MF201
1%1/20W
240
MF201
1%1/20W
240
MF201
1%1/20W
0.01UF
X5R01005
10%6.3V
0.01UF
X5R01005
10%6.3V
0.01UF
X5R01005
10%6.3V
0.01UF
X5R01005
10%6.3V
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
11 38
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11 38
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11 38
11 38
SYNC_MASTER=N/A SYNC_DATE=N/A
AP: DDR
=PP1V2_S2R_H5PPVREF_DDR1_DQ_H5
=PP1V2_VDDIOD_H5
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
PPVREF_DDR3_DQ_H5
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
PPVREF_DDR2_DQ_H5
=PP1V2_VDDIOD_H5=PP1V2_VDDIOD_H5
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
PPVREF_DDR1_DQ_H5
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
PPVREF_DDR0_DQ_H5
=PP1V2_VDDIOD_H5
H5G_DDR1_ZQ
PPVREF_DDR0_DQ_H5
H5G_DDR0_ZQ H5G_DDR2_ZQ
PPVREF_DDR2_DQ_H5
H5G_DDR3_ZQ
=PP1V2_S2R_H5PPVREF_DDR3_DQ_H5
NC_DDR0_CKE<1> NO_TEST=TRUE
NC_DDR0_CSN<1> NO_TEST=TRUE
=PP1V2_S2R_H5 =PP1V2_S2R_H5
NC_DDR2_CSN<1>NO_TEST=TRUE
NC_DDR2_CKE<1>NO_TEST=TRUE
NC_DDR1_CSN<1>NO_TEST=TRUE
NC_DDR1_CKE<1>NO_TEST=TRUE
NC_DDR3_CSN<1>NO_TEST=TRUE
NC_DDR3_CKE<1>NO_TEST=TRUE
DDR0_DQ<24>DDR0_DQ<23>DDR0_DQ<22>DDR0_DQ<21>DDR0_DQ<20>DDR0_DQ<19>DDR0_DQ<18>DDR0_DQ<17>DDR0_DQ<16>DDR0_DQ<15>DDR0_DQ<14>DDR0_DQ<13>DDR0_DQ<12>DDR0_DQ<11>DDR0_DQ<10>DDR0_DQ<9>DDR0_DQ<8>DDR0_DQ<7>DDR0_DQ<6>DDR0_DQ<5>
DDR0_DQ<3>DDR0_DQ<4>
DDR0_DQ<2>DDR0_DQ<1>DDR0_DQ<0>
DDR3_CSN<0>
DDR3_CKE<0>DDR3_CK_NDDR3_CK_P
DDR3_CA<7>DDR3_CA<6>DDR3_CA<5>DDR3_CA<4>
DDR3_DM<3>DDR3_DM<2>DDR3_DM<1>DDR3_DM<0>
DDR3_CA<8>DDR3_CA<9>
DDR3_DQS_P<2>DDR3_DQS_N<2>DDR3_DQS_P<3>DDR3_DQS_N<3>
DDR3_DQS_P<0>DDR3_DQS_N<0>DDR3_DQS_P<1>DDR3_DQS_N<1>
DDR3_DQ<20>DDR3_DQ<19>DDR3_DQ<18>DDR3_DQ<17>DDR3_DQ<16>
DDR3_DQ<27>DDR3_DQ<26>DDR3_DQ<25>DDR3_DQ<24>DDR3_DQ<23>DDR3_DQ<22>DDR3_DQ<21>
DDR3_DQ<31>DDR3_DQ<30>DDR3_DQ<29>DDR3_DQ<28>
DDR3_CA<0>DDR3_CA<1>DDR3_CA<2>DDR3_CA<3>
DDR3_DQ<0>DDR3_DQ<1>DDR3_DQ<2>DDR3_DQ<3>DDR3_DQ<4>DDR3_DQ<5>DDR3_DQ<6>
DDR3_DQ<13>DDR3_DQ<12>DDR3_DQ<11>DDR3_DQ<10>DDR3_DQ<9>DDR3_DQ<8>DDR3_DQ<7>
DDR3_DQ<15>DDR3_DQ<14>
DDR1_CSN<0>
DDR1_DQS_N<1>DDR1_DQS_P<1>DDR1_DQS_N<0>DDR1_DQS_P<0>
DDR1_DQS_N<3>DDR1_DQS_P<3>DDR1_DQS_N<2>DDR1_DQS_P<2>
DDR1_CA<9>DDR1_CA<8>
DDR1_CK_PDDR1_CK_NDDR1_CKE<0>
DDR1_DM<0>DDR1_DM<1>DDR1_DM<2>DDR1_DM<3>
DDR1_CA<4>DDR1_CA<5>DDR1_CA<6>DDR1_CA<7>
DDR1_CA<3>DDR1_CA<2>DDR1_CA<1>
DDR1_DQ<28>DDR1_DQ<29>DDR1_DQ<30>DDR1_DQ<31>
DDR1_CA<0>
DDR1_DQ<21>DDR1_DQ<22>DDR1_DQ<23>DDR1_DQ<24>DDR1_DQ<25>DDR1_DQ<26>DDR1_DQ<27>
DDR1_DQ<14>DDR1_DQ<15>DDR1_DQ<16>DDR1_DQ<17>DDR1_DQ<18>DDR1_DQ<19>DDR1_DQ<20>
DDR1_DQ<7>DDR1_DQ<8>DDR1_DQ<9>DDR1_DQ<10>DDR1_DQ<11>DDR1_DQ<12>DDR1_DQ<13>
DDR1_DQ<6>DDR1_DQ<5>DDR1_DQ<4>DDR1_DQ<3>DDR1_DQ<2>DDR1_DQ<1>DDR1_DQ<0>
DDR2_CSN<0>
DDR2_CKE<0>
DDR2_CK_PDDR2_CK_N
DDR2_DQS_P<3>DDR2_DQS_N<3>
DDR2_DQS_N<2>DDR2_DQS_P<2>DDR2_DQS_N<1>
DDR2_DQS_N<0>DDR2_DQS_P<1>
DDR2_DQS_P<0>
DDR2_DM<3>
DDR2_DM<1>DDR2_DM<2>
DDR2_DM<0>
DDR2_CA<9>
DDR2_CA<7>DDR2_CA<8>
DDR2_CA<6>DDR2_CA<5>DDR2_CA<4>
DDR2_CA<2>DDR2_CA<3>
DDR2_CA<1>DDR2_CA<0>
DDR2_DQ<31>DDR2_DQ<30>DDR2_DQ<29>
DDR2_DQ<27>DDR2_DQ<28>
DDR2_DQ<26>DDR2_DQ<25>DDR2_DQ<24>
DDR2_DQ<22>DDR2_DQ<23>
DDR2_DQ<21>DDR2_DQ<20>DDR2_DQ<19>
DDR2_DQ<17>DDR2_DQ<18>
DDR2_DQ<16>DDR2_DQ<15>DDR2_DQ<14>DDR2_DQ<13>DDR2_DQ<12>DDR2_DQ<11>
DDR2_DQ<9>DDR2_DQ<10>
DDR2_DQ<8>DDR2_DQ<7>DDR2_DQ<6>DDR2_DQ<5>DDR2_DQ<4>DDR2_DQ<3>DDR2_DQ<2>DDR2_DQ<1>DDR2_DQ<0>
DDR0_CSN<0>
DDR0_CK_NDDR0_CKE<0>
DDR0_CK_P
DDR0_DQS_P<3>DDR0_DQS_N<2>
DDR0_DQS_N<1>DDR0_DQS_P<2>
DDR0_DQS_P<1>DDR0_DQS_N<0>DDR0_DQS_P<0>
DDR0_DM<3>DDR0_DM<2>DDR0_DM<1>DDR0_DM<0>
DDR0_CA<9>DDR0_CA<8>DDR0_CA<7>DDR0_CA<6>DDR0_CA<5>DDR0_CA<4>DDR0_CA<3>DDR0_CA<2>DDR0_CA<1>DDR0_CA<0>
DDR0_DQ<31>DDR0_DQ<30>DDR0_DQ<29>DDR0_DQ<28>DDR0_DQ<27>DDR0_DQ<26>DDR0_DQ<25>
DDR0_DQS_N<3>
C10561
2
R10551
2
R10561
2
C10541
2
R10531
2
R10541
2
C10841
2
R10831
2
R10841
2
C10961
2
R10951
2
R10961
2
R10201
2
R10211
2
R10221
2
R102341
2
C10571
2
C10581
2
C10951
2
C10851
2
C10201
2
C10211
2
C10221
2
C10231
2
U0600
G5
G6
H5
H6
J5
M5
M6
N6
P5
P6
P4
N4
J1
K1
K6
J6
E12
E9
C14
D6
B14
B13
B8
C8
B7
B6
C6
D7
B17
C17
B16
E17
D13
D16
E16
C15
D15
E6
B5
C5
E5
C4
D4
C12
B3
C3
D12
B11
C11
B10
C9
D9
A12
A8
A15
A5
A13
A7
A16
A4
M4
H15
D10
E15
F15
F14
E14
F13
E8
F8
F7
E7
F6
F11
F12
A10
A9
F10
E13
L5
N5
G4
R5
H2
H3
P3
R3
T2
R4
T3
T4
C2
D2
E2
E4
J3
E3
F3
F4
G2
U3
V2
V3
U5
V4
V5
J4
U6
V6
K2
L2
K4
K5
N2
P2
H1
M1
E1
R1
G1
N1
D1
T1
E11
H8
L3
U0600
AH6
AG6
AH7
AG7
AH8
AH11
AG11
AG12
AH12
AG13
AH14
AH13
AN10
AN9
AG9
AG8
AD4
AG4
AB6
AK4
AB2
AB3
AG5
AH2
AJ2
AG3
AH3
AJ3
W2
W4
Y2
Y3
AC2
Y4
AA3
AA4
AA5
AK3
AL2
AM3
AM4
AL4
AL5
AC4
AK5
AJ5
AD2
AD3
AE2
AE3
AF2
AF4
AB1
AF1
W1
AJ1
AA1
AG1
V1
AK1
AH9
Y8
AB4
W5
W6
Y5
Y6
AA6
AD6
AE5
AE6
AF6
AF5
AH4
AJ4
AD1
AE1
AC6
AC5
AK11
AG14
AJ8
AG15
AL8
AL9
AK12
AJ12
AM13
AK13
AJ13
AJ14
AM5
AL6
AK6
AJ6
AK9
AM7
AK7
AJ7
AM8
AM14
AL14
AJ15
AK15
AL15
AJ16
AJ9
AK16
AM16
AM10
AJ10
AK10
AL11
AM11
AL12
AN8
AN12
AN5
AN15
AN7
AN13
AN4
AN16
AB5
AE8
AJ11
051-9385
A.0.0
10 OF 154
8 OF 39
8 34
8
8 9 34
8 8
8 9 34 8 9 34
8 8
8 9 34
8 8
8 34
8
8 34 8 34
VDD VDD
SYM 10 OF 12
SYM 9 OF 12
VDD_ANA_TMPSADC1
VDD_ANA_TMPSADC0
VDD_ANA1
VDD_ANA0
VDDIOD3
VDDIOD2
VDDIOD0
VDDIOD
VDDIO30_GRP3
VDDIO30_GRP2
VDDIO30_GRP1
VDDIO18_GRP6
VDDIO18_GRP5
VDDIO18_GRP4
VDDIO18_GRP3
VDDIO18_GRP2
VDDIO18_GRP1
VDD_SRAM
VDD_CPU1
VDD_CPU0
VDD_CPUB
VDDIOD1
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
FAST SCAN CLK
12MA
12MA
10MA
35MA
18MA
45MA
45MA
52MA
GPIO_3V0
FMI0-3 (1.8V)
9500MA MAX2MA
TEMP SENSORANALOG
45MA
5MA
5MA
2MAI2C2
SPI3
USB11
FMI1-3 (1.8V)
6.3V20%
603X5R
10UF 10UF
X5R603
20%6.3V
0.22UF20%
6.3VX5R
0201
0.22UF20%
6.3V
0201X5R
0.22UF
X5R0201
20%6.3V
10UF
X5R603
20%6.3V
0.22UF
X5R0201
20%6.3V
4.3UF
X5R-CERM0610
20%4V
56PF5%6.3VNP0-C0G01005
0.22UF
X5R0201
20%6.3V
0.22UF
X5R0201
20%6.3V
0.22UF
X5R0201
20%6.3V
0.22UF
X5R0201
20%6.3V
4.3UF
X5R-CERM20%4V
0610
4.3UF
X5R-CERM20%4V
0610
4.3UF
X5R-CERM0610
20%4V
4.3UF
X5R-CERM0610
20%4V
10UF
X5R603
20%6.3V
0.22UF
X5R0201
20%6.3V
0.22UF
X5R0201
20%6.3V
0.22UF
0201
20%X5R
6.3V
0.22UF20%
6.3V
0201X5R
10UF
X5R603
20%6.3V
4.3UF
X5R-CERM0610
20%4V
4.3UF
0610
20%4V
X5R-CERM
4.3UF
X5R-CERM0610
20%4V
4.3UF
X5R-CERM0610
20%4V
0610
4V4.3UF
20%X5R-CERM
4V20%
0610
4.3UF
X5R-CERM
10UF
X5R603
20%6.3V
10UF
X5R603
20%6.3V
10UF
X5R603
20%6.3V
10UF
X5R
20%6.3V
603
0.22UF20%
6.3V
0201X5R
1UF
CERM402
10%6.3V
1UF
CERM402
10%6.3V
1UF
CERM402
10%6.3V
1UF
CERM402
10%6.3V
1UF
CERM402
10%6.3V
1UF
CERM402
10%6.3V
0.1UF
X5R-CERM20%
6.3V
01005
0.1UF
X5R-CERM20%
6.3V
01005
0.1UF20%
6.3VX5R-CERM
01005
0.1UF20%
6.3VX5R-CERM
01005
0.1UF20%
6.3VX5R-CERM
01005
0.1UF20%
6.3VX5R-CERM
01005
0.1UF20%
6.3VX5R-CERM
01005
0.1UF20%
6.3VX5R-CERM
01005
4.3UF
X5R-CERM0610
20%4V
0.22UF
X5R0201
20%6.3V
0.22UF
X5R0201
20%6.3V
10UF
CERM-X5R0402-1
20%6.3V 6.3V
CERM-X5R0402-1
10UF20%
6.3VCERM-X5R0402-1
10UF20%
6.3V10%
402CERM
1UF4V20%X5R-CERM0610
4.3UF
402CERM6.3V
1UF10%
4V20%
0204X7S
0.47UF
CRITICAL
0.22UF
X5R0201
20%6.3V
0.22UF
X5R0201
20%6.3V
0.1UF
X5R-CERM20%
6.3V
01005
0.1UF
X5R-CERM20%
6.3V
01005
4.3UF
X5R-CERM0610
20%4V
4.3UF
X5R-CERM0610
20%4V
0.1UF
X5R-CERM
20%6.3V
01005
0.1UF
X5R-CERM
20%6.3V
01005
1UF
X5R0201
20%6.3V
4.3UF
X5R-CERM0610
20%4V
4.3UF
X5R-CERM0610
20%4V
20%6.3VX5R
0201
1UFBALI-H5GBGA
OMIT_TABLE
BALI-H5GBGA
OMIT_TABLE
1UF
X5R0201
20%6.3V 6.3V
20%
0201X5R
1UF 1UF
X5R0201
20%6.3V
20%6.3VX5R
0201
1UF20%
6.3VX5R
0201
1UF20%
6.3VX5R
0201
1UF
1UF
0201
20%6.3VX5R
1UF
X5R0201
6.3V20%
CERM-X5R-1201
20%4V
0.47UF 0.47UF20%4V
CERM-X5R-1201
1UF
X5R0201
20%6.3V
1UF
X5R0201
20%6.3V
1UF
X5R0201
20%6.3V
1UF
X5R0201
20%6.3V
20%6.3VX5R
0201
1UF20%
6.3VX5R
0201
1UF20%
6.3VX5R
0201
1UF20%
6.3VX5R
0201
1UF
1UF
X5R0201
20%6.3V
1UF
X5R0201
20%6.3V
0.47UF
CERM-X5R-1201
20%4V
201
20%4V
0.47UF
CERM-X5R-1
0.47UF
CERM-X5R-1201
20%4V
0.47UF
CERM-X5R-1201
20%4V
0.47UF
CERM-X5R-1201
20%4V
0.47UF
CERM-X5R-1201
20%4V
0.47UF
CERM-X5R-1201
20%4V
0.47UF
CERM-X5R-120%4V
201201CERM-X5R-1
4V20%
0.47UF0.47UF
201
20%4V
CERM-X5R-1
1UF
X5R0201
20%6.3V
1UF
X5R0201
20%6.3V
0.47UF
CERM-X5R-1201
20%4V
0.47UF
CERM-X5R-1201
20%4V
0.22UF
X5R0201
20%6.3V
0.22UF
X5R0201
20%6.3V
0.22UF
X5R0201
20%6.3V
0.22UF
X5R0201
20%6.3V
16VNP0-C0G-CERM
01005
8.2PF+/-0.5PF
16VNP0-C0G-CERM
01005
8.2PF+/-0.5PF
16VNP0-C0G-CERM
01005
8.2PF+/-0.5PF
16VNP0-C0G-CERM
01005
8.2PF+/-0.5PF
16VNP0-C0G-CERM
01005
8.2PF+/-0.5PF
16VNP0-C0G-CERM
01005
8.2PF+/-0.5PF
16VNP0-C0G-CERM
01005
8.2PF+/-0.5PF
16VNP0-C0G-CERM
01005
8.2PF+/-0.5PF
16VNP0-C0G-CERM
01005
8.2PF+/-0.5PF
16VNP0-C0G-CERM
01005
8.2PF+/-0.5PF
16VNP0-C0G-CERM01005
8.2PF+/-0.5PF
0.22UF20%
6.3VX5R
0201
20%6.3V
0.22UF
0201X5R
0.22UF20%
6.3V
0201X5R
20%6.3V
0201X5R
0.22UF
AP: POWERSYNC_DATE=N/ASYNC_MASTER=N/A
138S0702 138S0657 QTY 21 RDAR://PROBLEM/8837828
C1106,C1107,C1108,C1109,C1110,C1111,C1147,C1148,C1155,C1156,C1167,C1168,C1180,C1181,C1190,C1191,C1315,C1321,C1415,C1421,CA194
=PPVDD_SOC_H5
=PPVDD_SOC_H5
=PPVDD_CPU0_H5
=PPVDD_CPUB_H5
=PP1V8_NAND_H5
=PP3V0_VDDIO30_H5
=PP1V8_VDDIO18_H5
=PP1V8_VDDIO18_H5
=PP3V0_VDDIO30_H5
=PP1V2_VDDIOD_H5
=PPVDD_SRAM_H5
=PPVDD_CPU1_H5
C1135 1
2
C11341
2
C11331
2
C11321
2
C11311
2
C11301
2
C11291
2
C11281
2
C1100 1
2
C1101 1
2
C1142 1
2
C1192 1
2
C11971
2
C1191 1
2
C11451
2
C11991
2
C11981
2
CA1921
2
CA1911
2
C1147 1
2
C1148 1
2
C1181 1
2
C1180 1
2
C1179 1
2
CA1881
2
CA1871
2
CA1861
2
CA185 1
2
C1111 1
2
C1110 1
2
C1109 1
2
C1108 1
2
C1107 1
2
C1106 1
2
C1103 1
2
C1102 1
2
C1105 1
2
C1104 1
2
C11151
2
C11141
2
C11131
2
C11181
2
C11171
2
C11161
2
C1153 1
2
C1154 1
2
C1136 1
2
C1137 1
2
C1138 1
2
C1139 1
2
C1140 1
2
C1141 1
2
C1190 1
2
C11431
2
C11441
2
CA1931
2
CA1971
2
CA1961
2
CA1951
2
CA1941
2
CA1981
2
CA1991
2
CA1901
2
CA1891
2
C1178 1
2
C1177 1
2
C1167 1
2
C1168 1
2
C1166 1
2
C1165 1
2
C1157 1
2
C1156 1
2
C1155 1
2
C1161 1
2
U0600J8
J10
L8
AD11
AD13
AD15
AD17
AE16
AE18
AF17
U20
R18
R24
L10
L12
L14
L16
L18
L20
L22
M9
M11
J12
M13
M15
M17
M19
M21
M23
N8
N10
N12
N14
J14
N16
N18
N20
N22
P9
P11
P15
P17
P19
P21
J22
P23
R8
R10
R12
R14
R16
R20
R22
T9
T11
K9
T13
T15
T17
T21
T23
U8
U10
U12
U14
U16
K11
U22
U24
V9
V11
V13
V15
V17
V25
W8
W10
K13
W12
W14
W16
T19
W26
Y9
Y11
Y13
Y15
Y17
K15
Y26
AA8
AA10
AA12
AA14
AA16
AA18
AA26
AB9
AB11
K21
AB13
AB15
AB17
AC8
AC10
AC12
AC14
AC16
AC18
AD9
U0600
AE20
AE24
W18
P13
AA21
AB20
AB22
AC19
AC21
AD20
AE19
AE21
AA23
AB24
AC23
AC25
AD22
AD24
AE23
AE25
V20
V22
V24
Y20
Y22
Y24
AA19
AA25
W19
W21
W23
W25
H18
H26
J27
K27
L27
N29
U25
U26
V26
AF25
AH18
N28
F18
K25
J20
K20
AG26
AH26
AJ26
AC26
AD26
AE26
G7
G8
J7
K7
L7
M7
N7
P7
R7
T7
U7
V7
G9
W7
Y7
AA7
AB7
AC7
AD7
AE7
AF7
AF8
AF9
G10
AF10
AF11
AF12
AF13
AF14
AF15
G11
G12
G13
G14
G15
H7
C1158 1
2
C1159 1
2
C1160 1
2
C1162 1
2
C1163 1
2
C1164 1
2
C1149 1
2
C1150 1
2
C1151 1
2
C1152 1
2
C1169 1
2
C1170 1
2
C1171 1
2
C1172 1
2
C1173 1
2
C1174 1
2
C1175 1
2
C1176 1
2
C1182 1
2
C1183 1
2
C1184 1
2
C1185 1
2
C1126 1
2
C1125 1
2
C1124 1
2
C1123 1
2
C1122 1
2
C1121 1
2
C1120 1
2
C1119 1
2
C1193 1
2
C1194 1
2
C1195 1
2
C1196 1
2
CA1531
2
CA1521
2
CA1511
2
CA1501
2
C11B0 1
2
C11B1 1
2
C11C0 1
2
C11C1 1
2
C11D1 1
2
C11D0 1
2
C11E1 1
2
C11E0 1
2
C11A1 1
2
C11A0 1
2
C11F01
2
051-9385
A.0.0
11 OF 154
9 OF 39
9 34
9 34
34
34
6 34
9 34
4 6 7 9 34
4 6 7 9 34
9 34
8 34
34
34
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTIN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
011 DVTEVT010
CURRENT SETTING --->
X140 AP BB_26 (MLB E)
X140 DEV BB_42
X140 AP WLAN (MLB A)
0010 SPI0 W/TEST
BOARD_ID[2]
BOARD_ID[1]
BOARD_ID[3]
X140 DEV BB_26
X140 DEV BB_26A
X140 AP BB_26A (MLB D)
X140 AP BB_42 (MLB C)
X140 DEV BB_41
X140 AP BB_41 (MLB B)
BOARD ID
0101
0100
0010
0011
1011
1010
1110
1111
0000
0001
000
BRD_REV[2-0]
PROTO
3. READ
2. ENABLE PU AND DISABLE PD
S/W READ FLOW
1. SET GPIO AS INPUT
FOR REFERENCE
1110
3. READ
1101 FMI0/1 4/4 CS
3. READ
BOOT_CONFIG[2]
BOOT_CONFIG[3]
BOOT_CONFIG[1]
BOOT_CONFIG[0]
0001 SPI1
FMI0/1 2/2 CS1100
1101
0100 FMI0 2CS
BOOT_CONFIG[3:0]
1111 RESERVED
1100 FMI0/1 2/2 CS
STUFF FOR FORM FACTOR BOARD
FMI0/1 4/4 CS
FMI0/1 4/4 CS WITH TEST
S/W READ FLOW
JTAG
1110 FMI0/1 4/4 CS W/TEST
1010 FMI1 4CS W/TEST
1000 FMI1 2 CS0111 RESERVED
0011 SPI1 W/TEST
1001 FMI1 4 CS
0110 FMI0 4CS W/TEST
0000 SPI0
2. DISABLE PU AND ENABLE PD
S/W READ FLOW
1. SET GPIO AS INPUT
X140 DEV WLAN
BOARD_ID[3-0]
BOOT CONFIG ID
BOOT_CONFIG[3-0]
2. DISABLE PU AND ENABLE PD
1. SET GPIO AS INPUTCURRENT SETTING --->
PROTO 2001
0101 FMI0 4CS
BOARD_ID[0]
BOARD REVISION
01005
1/32W5%
MF
10K
MLB_B&MLB_D
4
4 36 39
1/32W5%
01005MF
10K1/32W5%
01005MF
10K
NOSTUFF
1/32W5%
01005MF
10K
1/32W5%
01005MF
10K
DEV
1/32W5%
01005MF
10K
MLB_C&MLB_E
1/32W5%
01005MF
100K
SHORT-01005
NOSTUFF
SHORT-01005
NOSTUFF
SHORT-01005
NOSTUFF
5
5
5
5
5
5
5
5
5
5
4
4
4
4
30 25
MLB_D&MLB_E
1/32W5%
01005MF
10K
5
NOSTUFF
1/32W5%
01005MF
10K
5%
100
MF01005
1/32W
5%
100
MF01005
1/32W
NOSTUFF
10K5%
MF01005
1/32W
NOSTUFF
10K
MF01005
5%1/32W
10K
MF01005
5%1/32W
SYNC_MASTER=N/A SYNC_DATE=N/A
AP: MISC & ALIASES
GPIO_BOARD_ID_3
=PP1V8_H5
GPIO_BOARD_ID_2
GPIO_BOARD_ID_1
GPIO_BRD_REV0GPIO_BRD_REV1GPIO_BRD_REV2
PMU_USB_BRICKID
JTAG_AP_SEL
GPIO_BOOT_CONFIG_1
GPIO_BOOT_CONFIG_2
AP_TST_STPCLK
AP_FAST_SCAN_CLK
AP_HOLD_RESET
AP_TESTMODE
JTAG_AP_TRST_L
=PP1V8_H5
GPIO_BOOT_CONFIG_3
GPIO_BOOT_CONFIG_0
USB_BRICKID MAKE_BASE=TRUE
GPIO_BOARD_ID_0
R12051
2
R12021
2 R12101 2
R12111 2
R12071
2
R12081
2
R12091
2
R12011
2
R12001
2
R12031
2
R12061
2
R12041
2
R12601 2
XW1200
12
XW1201
12
XW1202
12
R12201
2
051-9385
A.0.0
12 OF 154
10 OF 39
4 5 7 10 34
4 5 7 10 34
CK_1
DQ13_2
DQ14_2
DQ2_2
DQ1_2
DQ0_2
CKB_2
CKE_2
DQ21_1
DQ12_1
DQ11_1
DQ10_1
DQ0_1
DQ1_1
DQ2_1
DQ3_1
DQ4_1
DQ5_1
CSB_1
CKE_1
CKB_1
CA9_1
CA8_1
CA7_1
CA6_1
CA5_1
CA4_1
CA3_1
CA2_1
CA1_1
CA0_1
DQSB2_1
DQS2_1
DQ20_1
DQ19_1
DQ22_1
DQ23_1
DQ18_1
DQ16_1
DQ17_1
DQ15_1
DQ14_1
DQ13_1
DQ9_1
DQ7_1
DQ8_1
DQ6_1
DQ24_1
DQ31_1
DQ30_1
DQ31_2
DQ29_2
DQ30_2
DQ28_2
DQ26_2
DQ27_2
DQ25_2
DQ24_2
DQ23_2
DQ21_2
DQ22_2
DQ20_2
DQ19_2
DQ18_2
DQ17_2
DQ16_2
DQ15_2
DQ12_2
DQ11_2
DQ10_2
DQ8_2
DQ9_2
DQ6_2
DQ7_2
DQ5_2
DQ4_2
DQ3_2
DQSB3_2
DQS3_2
CA7_2
CA8_2
CA9_2
CK_2
DQS1_2
VREFCA_1 VREFCA_2
VREFDQ_1 VREFDQ_2
2_QZ1_QZ
DQSB3_1
DQSB2_2
DQSB1_2DQSB1_1
DQSB0_2DQSB0_1
DQS3_1
DQS2_2
DQS1_1
DQS0_2DQS0_1
DQ29_1
DQ28_1
DQ27_1
DQ26_1
DQ25_1
CA6_2
CA5_2
CA4_2
CA3_2
CA2_2
CA1_2
CA0_2
DM0_1
DM1_1
DM2_1
DM3_1
CSB_2
DM0_2
DM1_2
DM2_2
DM3_2
DDR_1
DDR_2
SYM 1 OF 2
VDD1_3
VDD1_1 VSS55
VSS51
VSS6
VSS49
VSS4
VSS3
VDDQ33
VDDCA1
VDDCA2
VSS46
VDD1_0
VDD1_8
VDD1_5
VDD1_6
VDD1_7
VSS52
VSS0
VSS2
VSS7
VSS9
VSS10
VSS13
VSS18
VSS20
VSS32
VSS33
VSS34
VSS42
VSS43
VSS44
VSS29
VSS28
VSS27
VSS26
VSS25
VSS23
VSS22
VSS47
VSS53
VSS48
VSS50
VSS1
VSS12
VDD1_11
VDD2_3
VDD2_2
VDD1_2
VDD2_6
VDD2_7
VDD2_13
VDD2_14
VDD2_16
VDDQ27
VDDQ32
VDDQ31
VDDQ
VDDQ6
VDDQ23
VDDQ30
VDDQ22
VDDQ16
VDDQ34
VDDQ17
VDDQ21
VDDQ19
VDDQ24
VDDQ20
VDDQ28
VDDCA3
VDDCA4
VDDCA5
VDDCA6
VDDCA7
VDDCA8
VDD2_1
VDDQ26
VDDQ25
VSS24
VDD2_9
VDD2_8
VDDQ1
VDD1_9
VDD1_10
VDDCA9
VDDCA10
VDDQ29
VDDQ3
VDD1_4
VDD2_5
VDD2_4
VDD2_15
VSS41
VSS40
VSS39
VSS54
VSS36
VSS35
VDD2_10
VDD2_11
VDD2_12
VSS45
VDD2
VDDQ
VDDCA
VDD1
VSS
SYM 2 OF 2
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
X5R
20%10UF6.3V
603
X5R
20%
0201
6.3V
0.22UF
10%
X5R
0.01UF6.3V
01005
X5R
20%0.22UF
0201
6.3V
6.3V5%
01005NP0-C0G
56PF
X5R
20%0.22UF
0201
6.3V
10%10V
0.01UF
0201X5R-CERM
X5R
20%0.22UF
0201
6.3V
X5R
20%0.22UF
0201
6.3V
10%6.3V
402CERM
1UF
X5R
20%0.22UF
0201
6.3V
10%
X5R
0.01UF
01005
6.3V
X5R
20%0.22UF
0201
6.3V
10%
X5R
0.01UF6.3V
01005
NP0-C0G01005
6.3V
56PF5%
10%
X5R
0.01UF6.3V
01005
X5R
0.22UF20%
0201
6.3V
10%6.3V
1UF
CERM402
X5R
20%0.22UF
0201
6.3V
X5R
20%0.22UF
0201
6.3V
10%6.3V
402CERM
1UF
10%
X5R
0.01UF6.3V
01005
20%4.3UF
0610
4VX5R-CERM
20%
0610X5R-CERM
4V
4.3UF
X5R
20%6.3V
10UF
603
X5R
10UF20%
6.3V
603
6.3V5%
01005NP0-C0G
56PF
10%
402
6.3V
1UF
CERM
X5R
20%0.22UF
0201
6.3V
5%56PF
01005NP0-C0G
6.3V
X5R
20%6.3V
10UF
603
201
2401%1/20WMF
10%
X5R
0.01UF6.3V
0100501005MF1/32W1%10K
10%
X5R
0.01UF6.3V
01005X5R
20%0.22UF
0201
6.3V01005MF1/32W1%10K
201MF1/20W1%240
10%
X5R
0.01UF6.3V
01005
01005MF1/32W1%10K
10%
X5R
0.01UF6.3V
0100501005MF1/32W1%10K
10%6.3V
402
1UF
CERM
10%
X5R
0.01UF6.3V
01005
10%
X5R
0.01UF6.3V
01005
01005MF1/32W1%4.7K
01005MF1/32W1%4.7K
01005MF1/32W1%4.7K
10%
X5R
0.01UF6.3V
01005
10%
X5R
0.01UF6.3V
0100501005MF1/32W1%4.7K
X5R
20%6.3V
0.22UF
0201
OMIT_TABLE
BGAXXXMB
H4G-DRAM
OMIT_TABLE
XXXMBH4G-DRAM
BGA
10%6.3V
1UF
CERM402
SYNC_MASTER=N/A
DDR 0 AND 1SYNC_DATE=N/A
NET_SPACING_TYPE=PWRMIN_LINE_WIDTH=0.3MM
VOLTAGE=0.6V
PPVREF_DDR1_DQ
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
=PP1V2_VDDQ_DDR
NET_SPACING_TYPE=PWR
VOLTAGE=0.6V
MIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2MM
PPVREF_DDR0_DQ
=PP1V2_VDDQ_DDR
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.3MM
VOLTAGE=0.6V
PPVREF_DDR1_CA
=PP1V2_S2R_DDR
VOLTAGE=0.6V
NET_SPACING_TYPE=PWRMIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
PPVREF_DDR0_CA
=PP1V2_S2R_DDR
=PP1V2_S2R_DDR
DDR1_DQ<8>
DDR0_DQ<11>DDR1_DQ<12>DDR1_DQ<13>
DDR1_DM<2>
DDR1_CA<7>
DDR1_CA<5>
=PP1V8_S2R_DDR
DDR1_DM<1>
DDR0_DQ<14>
DDR0_DQ<2>
DDR0_DQ<13>
=PP1V2_VDDQ_DDR
=PP1V2_S2R_DDR
DDR0_DQ<8>DDR0_DQ<9>DDR0_DQ<10>
DDR1_CK_P
DDR0_DQ<5>DDR0_DQ<6>
DDR0_CK_NDDR0_CKE<0>
DDR1_DQ<29>
DDR1_DQ<4>DDR1_DQ<3>DDR1_DQ<2>
DDR1_DQ<9>DDR1_DQ<10>DDR1_DQ<11>
DDR1_CSN<0>
DDR1_CKE<0>DDR1_CK_N
DDR1_CA<9>DDR1_CA<8>
DDR1_CA<6>
DDR1_CA<4>DDR1_CA<3>DDR1_CA<2>DDR1_CA<1>DDR1_CA<0>
DDR1_DQS_N<3>DDR1_DQS_P<3>
DDR1_DQ<28>DDR1_DQ<27>
DDR1_DQ<30>DDR1_DQ<31>
DDR1_DQ<26>
DDR1_DQ<24>DDR1_DQ<25>
DDR1_DQ<7>DDR1_DQ<6>DDR1_DQ<5>
DDR1_DQ<1>
DDR1_DQ<15>DDR1_DQ<0>
DDR1_DQ<14>
DDR1_DQ<16>
DDR1_DQ<23>DDR1_DQ<22>
DDR0_DQ<23>
DDR0_DQ<21>DDR0_DQ<22>
DDR0_DQ<20>
DDR0_DQ<18>DDR0_DQ<19>
DDR0_DQ<17>DDR0_DQ<16>DDR0_DQ<31>
DDR0_DQ<29>DDR0_DQ<30>
DDR0_DQ<28>DDR0_DQ<27>DDR0_DQ<26>DDR0_DQ<25>DDR0_DQ<24>DDR0_DQ<7>
DDR0_DQ<4>DDR0_DQ<3>
DDR0_DQ<0>DDR0_DQ<1>
DDR0_DQ<15>
DDR0_DQ<12>
DDR0_DQS_N<2>DDR0_DQS_P<2>
DDR0_CA<7>DDR0_CA<8>DDR0_CA<9>
DDR0_CK_P
DDR0_DQS_P<0>
PPVREF_DDR0_CAPPVREF_DDR0_DQ
DDR0_DQS_N<3>
DDR0_DQS_N<0>DDR1_DQS_N<0>
DDR0_DQS_N<1>DDR1_DQS_N<1>
DDR1_DQS_P<2>
DDR0_DQS_P<3>
DDR1_DQS_P<0>
DDR0_DQS_P<1>DDR1_DQS_P<1>
DDR1_DQ<21>DDR1_DQ<20>DDR1_DQ<19>DDR1_DQ<18>DDR1_DQ<17>
DDR0_CA<6>DDR0_CA<5>DDR0_CA<4>DDR0_CA<3>DDR0_CA<2>DDR0_CA<1>DDR0_CA<0>
DDR1_DM<0>DDR1_DM<3>
DDR0_CSN<0>
DDR0_DM<1>DDR0_DM<0>DDR0_DM<3>DDR0_DM<2>
PPVREF_DDR1_DQPPVREF_DDR1_CA
DDR1_DQS_N<2>
DDR1_ZQ DDR0_ZQ
C1305 1
2
C1304 1
2
C1309 1
2
C13081
2
C1303 1
2
C13071
2
C1302 1
2
C1301 1
2
C1306 1
2
C1322 1
2
C13131
2
C1319 1
2
C1312 1
2
C1318 1
2
C1326 1
2
C1311 1
2
C13171
2
C1325 1
2
C13241
2
C1331 1
2
C1335 1
2
C1330 1
2
C13341
2
C1329 1
2
C13331
2
C1310 1
2
C1316 1
2
C1315 1
2
C1321 1
2
C1314 1
2
C1320 1
2
C13231
2
C1328 1
2
C1332 1
2
C1327 1
2
R13211
2
C13601
2
R13051
2
C13501
2
R13061
2
R13201
2
C13611
2
R13511
2
C13521
2
R13521
2
C13621
2
C13541
2
R13531
2
R13541
2
R13551
2
C13631
2
C13561
2
R13561
2
U1300T15 G16
U15 G17
U14 H17
V14 H18
T13 J16
T9 N16
U9 N17
U8 P17
V8 P18
T7 R16
U12 K17
U11 L17
V13 J18
U13 J17
C12 K3
B10 M2
B16 G4
D7 T2
C15 G3
B8 P5
C8 P4
D8 P3
E8 P2
B7 R4
C7 R3
B18 B2
C18 C2
D18 D3
E18 D2
D15 G2
B17 E4
D17 E3
E17 E2
E16 F2
B6 T5
B5 U5
C5 U4
D5 U2
B4 V5
C4 V4
B14 H5
B3 V3
C3 V2
C14 H4
D14 H3
E14 H2
B13 J3
C13 J2
C9 N4
D9 N3
D13 J4
D10 M4
C16 F4
D6 T3
D12 K4
C10 M3
D16 F3
C6 T4
U10 M17
D11 L4
U7 R17
U1300A2
B1
W17
U19
B11
F17
L2
M16
T10
U18
V17
V6
E11
W5
W16
W19
W18
V19
A3
T19
E19
L5
M18
U17
T18
V10
V16
V18
F18
T8
H16
K16
L16
P16
T11
T12
T14
V7
E1
U1
J5
K2
N2
R5
A8
A10
A14
A13
C17
C19
H1
E10
E15
B12
U3
W3
M1
P1
A17
D4
A16
A1
D19
E12
E13
F16
A4
G18
J1
K18
K5
L18
L3
M5
N18
N5
A6
R18
R2
T1
T17
U16
U6
B15
V11
V12
V15
T6
V9
W1
W4
A18
B19
C1
E7
G5
T16
V1
W2
A19
B9
C11
D1
051-9385
A.0.0
13 OF 154
11 OF 39
11 38 39
11 12 34
11 38 39
11 12 34
11 38 39
11 12 34
11 38 39
11 12 34
11 12 34
8 38
8 38
8 38
8 38
8 38
8 38
8 38
12 34
8 38
8 38
8 38
8 38
11 12 34
11 12 34
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
11 38 39
11 38 39
8 38
8 38 8 38
8 38 8 38
8 38
8 38
8 38
8 38 8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
11 38 39
11 38 39
8 38
38 38
CK_1
DQ13_2
DQ14_2
DQ2_2
DQ1_2
DQ0_2
CKB_2
CKE_2
DQ21_1
DQ12_1
DQ11_1
DQ10_1
DQ0_1
DQ1_1
DQ2_1
DQ3_1
DQ4_1
DQ5_1
CSB_1
CKE_1
CKB_1
CA9_1
CA8_1
CA7_1
CA6_1
CA5_1
CA4_1
CA3_1
CA2_1
CA1_1
CA0_1
DQSB2_1
DQS2_1
DQ20_1
DQ19_1
DQ22_1
DQ23_1
DQ18_1
DQ16_1
DQ17_1
DQ15_1
DQ14_1
DQ13_1
DQ9_1
DQ7_1
DQ8_1
DQ6_1
DQ24_1
DQ31_1
DQ30_1
DQ31_2
DQ29_2
DQ30_2
DQ28_2
DQ26_2
DQ27_2
DQ25_2
DQ24_2
DQ23_2
DQ21_2
DQ22_2
DQ20_2
DQ19_2
DQ18_2
DQ17_2
DQ16_2
DQ15_2
DQ12_2
DQ11_2
DQ10_2
DQ8_2
DQ9_2
DQ6_2
DQ7_2
DQ5_2
DQ4_2
DQ3_2
DQSB3_2
DQS3_2
CA7_2
CA8_2
CA9_2
CK_2
DQS1_2
VREFCA_1 VREFCA_2
VREFDQ_1 VREFDQ_2
2_QZ1_QZ
DQSB3_1
DQSB2_2
DQSB1_2DQSB1_1
DQSB0_2DQSB0_1
DQS3_1
DQS2_2
DQS1_1
DQS0_2DQS0_1
DQ29_1
DQ28_1
DQ27_1
DQ26_1
DQ25_1
CA6_2
CA5_2
CA4_2
CA3_2
CA2_2
CA1_2
CA0_2
DM0_1
DM1_1
DM2_1
DM3_1
CSB_2
DM0_2
DM1_2
DM2_2
DM3_2
DDR_1
DDR_2
SYM 1 OF 2VDD1_3
VDD1_1 VSS55
VSS51
VSS6
VSS49
VSS4
VSS3
VDDQ33
VDDCA1
VDDCA2
VSS46
VDD1_0
VDD1_8
VDD1_5
VDD1_6
VDD1_7
VSS52
VSS0
VSS2
VSS7
VSS9
VSS10
VSS13
VSS18
VSS20
VSS32
VSS33
VSS34
VSS42
VSS43
VSS44
VSS29
VSS28
VSS27
VSS26
VSS25
VSS23
VSS22
VSS47
VSS53
VSS48
VSS50
VSS1
VSS12
VDD1_11
VDD2_3
VDD2_2
VDD1_2
VDD2_6
VDD2_7
VDD2_13
VDD2_14
VDD2_16
VDDQ27
VDDQ32
VDDQ31
VDDQ
VDDQ6
VDDQ23
VDDQ30
VDDQ22
VDDQ16
VDDQ34
VDDQ17
VDDQ21
VDDQ19
VDDQ24
VDDQ20
VDDQ28
VDDCA3
VDDCA4
VDDCA5
VDDCA6
VDDCA7
VDDCA8
VDD2_1
VDDQ26
VDDQ25
VSS24
VDD2_9
VDD2_8
VDDQ1
VDD1_9
VDD1_10
VDDCA9
VDDCA10
VDDQ29
VDDQ3
VDD1_4
VDD2_5
VDD2_4
VDD2_15
VSS41
VSS40
VSS39
VSS54
VSS36
VSS35
VDD2_10
VDD2_11
VDD2_12
VSS45
VDD2
VDDQ
VDDCA
VDD1
VSS
SYM 2 OF 2
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
6.3V
402CERM
1UF10%
6.3V
1UF
CERM402
10%
20%0.22UF
0201
6.3VX5R
20%0.22UF
0201
6.3VX5R
20%
0201
6.3V
0.22UF
X5R
20%6.3V
603
10UF
X5R
6.3VNP0-C0G
56PF5%
01005
6.3V
01005
0.01UF
X5R
10%
6.3V
01005
0.01UF
X5R
10%
20%0.22UF
0201
6.3VX5R
X5R-CERM0201
0.01UF10V10%
6.3V
01005
0.01UF
X5R
10%
6.3VCERM
1UF
402
10%
20%0.22UF
0201
6.3VX5R
6.3V
1UF
CERM402
10%
20%0.22UF
0201
6.3VX5R
20%
X5R-CERM
4.3UF4V
0610
6.3V
01005
0.01UF
X5R
10%6.3V
1UF
402CERM
10%
6.3V
01005
5%56PF
NP0-C0G
6.3V
1UF
CERM402
10%
6.3V
01005
5%
NP0-C0G
56PF20%
0.22UF
0201
6.3VX5R
20%0.22UF
0201
6.3VX5R
20%0.22UF
0201
6.3VX5R
20%
0610
4V
4.3UF
X5R-CERM20%
6.3V
10UF
603X5R
20%0.22UF
0201
6.3VX5R
20%6.3V
10UF
603X5R
6.3V5%
56PF
01005NP0-C0G
20%6.3V
10UF
603X5R
MF1/20W1%240
201
01005
6.3V
0.01UF
X5R
10%
01005
6.3V
0.01UF
X5R
10%
01005MF1/32W1%10K
6.3V
01005
0.01UF
X5R
10%
01005MF1/32W1%10K
2401%1/20WMF201
01005
6.3V
0.01UF
X5R
10%
01005
6.3V
0.01UF
X5R
10%
01005MF1/32W1%10K
01005MF1/32W1%10K
20%0.22UF
0201
6.3VX5R
01005
6.3V
0.01UF
X5R
10%
01005
6.3V
0.01UF
X5R
10%
01005
6.3V
0.01UF
X5R
10%
01005MF1/32W1%4.7K
01005MF1/32W1%4.7K
01005MF1/32W1%4.7K
01005
6.3V
0.01UF
X5R
10%
0.22UF20%
0201
6.3VX5R
01005MF1/32W1%4.7K
BGAXXXMB
H4G-DRAM
OMIT_TABLE
BGA
H4G-DRAMXXXMB
OMIT_TABLE
20%0.22UF
0201
6.3VX5R
SYNC_MASTER=N/A SYNC_DATE=N/A
DDR 2 AND 3
DDR2_CK_PDDR2_CK_N
PPVREF_DDR3_DQVOLTAGE=0.6V
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MMNET_SPACING_TYPE=PWR
=PP1V2_VDDQ_DDR
PPVREF_DDR2_DQ
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MMNET_SPACING_TYPE=PWR
=PP1V2_VDDQ_DDR
PPVREF_DDR3_CA
MIN_NECK_WIDTH=0.2MMVOLTAGE=0.6V
MIN_LINE_WIDTH=0.3MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
=PP1V2_S2R_DDR
NET_SPACING_TYPE=PWR
PPVREF_DDR2_CA
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.3MM
VOLTAGE=0.6V
=PP1V2_S2R_DDR
DDR3_ZQ DDR2_ZQ
=PP1V2_S2R_DDR
DDR3_DQ<11>
DDR3_CKE<0>
DDR3_CK_P
DDR3_CA<7>
DDR3_CA<1>DDR3_CA<0>
=PP1V2_S2R_DDR
=PP1V2_VDDQ_DDR
=PP1V8_S2R_DDR
DDR2_DM<2>DDR2_DM<3>DDR2_DM<0>DDR2_DM<1>
DDR2_CSN<0>
DDR3_DM<2>DDR3_DM<3>DDR3_DM<0>DDR3_DM<1>
DDR2_CA<0>DDR2_CA<1>DDR2_CA<2>DDR2_CA<3>DDR2_CA<4>DDR2_CA<5>DDR2_CA<6>
DDR3_DQ<17>DDR3_DQ<18>DDR3_DQ<19>DDR3_DQ<20>DDR3_DQ<21>
DDR3_DQS_P<1> DDR2_DQS_P<1>
DDR3_DQS_P<0>
DDR2_DQS_P<3>
DDR3_DQS_P<2>
DDR3_DQS_N<1> DDR2_DQS_N<1>
DDR3_DQS_N<0> DDR2_DQS_N<0>
DDR2_DQS_N<3>
DDR3_DQS_N<2>
PPVREF_DDR2_DQPPVREF_DDR3_DQPPVREF_DDR2_CAPPVREF_DDR3_CA
DDR2_DQS_P<0>
DDR2_CA<9>DDR2_CA<8>DDR2_CA<7>
DDR2_DQS_P<2>DDR2_DQS_N<2>
DDR2_DQ<11>DDR2_DQ<12>DDR2_DQ<13>
DDR2_DQ<15>DDR2_DQ<14>
DDR2_DQ<1>DDR2_DQ<0>
DDR2_DQ<2>DDR2_DQ<3>DDR2_DQ<4>
DDR2_DQ<7>DDR2_DQ<24>DDR2_DQ<25>DDR2_DQ<26>DDR2_DQ<27>DDR2_DQ<28>
DDR2_DQ<30>DDR2_DQ<29>
DDR2_DQ<31>DDR2_DQ<16>DDR2_DQ<17>
DDR2_DQ<19>DDR2_DQ<18>
DDR2_DQ<20>
DDR2_DQ<22>DDR2_DQ<21>
DDR2_DQ<23>DDR3_DQ<22>DDR3_DQ<23>
DDR3_DQ<16>
DDR3_DQ<14>
DDR3_DQ<0>DDR3_DQ<15>
DDR3_DQ<1>
DDR3_DQ<5>DDR3_DQ<6>DDR3_DQ<7>
DDR3_DQ<25>DDR3_DQ<24>
DDR3_DQ<26>
DDR3_DQ<31>DDR3_DQ<30>
DDR3_DQ<27>DDR3_DQ<28>
DDR3_DQS_P<3>DDR3_DQS_N<3>
DDR3_CA<2>
DDR3_CA<4>DDR3_CA<5>
DDR3_CA<9>
DDR3_CK_N
DDR3_CSN<0>
DDR3_DQ<13>DDR3_DQ<12>
DDR3_DQ<10>DDR3_DQ<9>DDR3_DQ<8>
DDR3_DQ<2>DDR3_DQ<3>DDR3_DQ<4>
DDR3_DQ<29>
DDR2_CKE<0>
DDR2_DQ<8>DDR2_DQ<9>DDR2_DQ<10>
DDR2_DQ<6>DDR2_DQ<5>
DDR3_CA<8>
DDR3_CA<6>
DDR3_CA<3> C1405 1
2
C1409 1
2
C14131
2
C1404 1
2
C14081
2
C1412 1
2
C1411 1
2
C1403 1
2
C1402 1
2
C1406 1
2
C14071
2
C1410 1
2
C1401 1
2
C1419 1
2
C1422 1
2
C1431 1
2
C1426 1
2
C1418 1
2
C14171
2
C1425 1
2
C1416 1
2
C14241
2
C1421 1
2
C1430 1
2
C1429 1
2
C1428 1
2
C1435 1
2
C14341
2
C14331
2
C1432 1
2
C1415 1
2
C1414 1
2
C1420 1
2
C14231
2
C1427 1
2
R14211
2
C14601
2
C14501
2
R14051
2
R14061
2
R14201
2
C14611
2
C14521
2
R14511
2
R14521
2
C14621
2
C14541
2
C14631
2
R14531
2
R14541
2
R14551
2
C14561
2
R14561
2
U1400T15 G16
U15 G17
U14 H17
V14 H18
T13 J16
T9 N16
U9 N17
U8 P17
V8 P18
T7 R16
U12 K17
U11 L17
V13 J18
U13 J17
C12 K3
B10 M2
B16 G4
D7 T2
C15 G3
B8 P5
C8 P4
D8 P3
E8 P2
B7 R4
C7 R3
B18 B2
C18 C2
D18 D3
E18 D2
D15 G2
B17 E4
D17 E3
E17 E2
E16 F2
B6 T5
B5 U5
C5 U4
D5 U2
B4 V5
C4 V4
B14 H5
B3 V3
C3 V2
C14 H4
D14 H3
E14 H2
B13 J3
C13 J2
C9 N4
D9 N3
D13 J4
D10 M4
C16 F4
D6 T3
D12 K4
C10 M3
D16 F3
C6 T4
U10 M17
D11 L4
U7 R17
U1400A2
B1
W17
U19
B11
F17
L2
M16
T10
U18
V17
V6
E11
W5
W16
W19
W18
V19
A3
T19
E19
L5
M18
U17
T18
V10
V16
V18
F18
T8
H16
K16
L16
P16
T11
T12
T14
V7
E1
U1
J5
K2
N2
R5
A8
A10
A14
A13
C17
C19
H1
E10
E15
B12
U3
W3
M1
P1
A17
D4
A16
A1D19
E12
E13
F16
A4
G18
J1
K18
K5
L18
L3
M5
N18
N5
A6
R18
R2
T1
T17
U16
U6
B15
V11
V12
V15
T6
V9
W1
W4
A18
B19
C1
E7
G5
T16
V1
W2
A19
B9
C11
D1
051-9385
A.0.0
14 OF 154
12 OF 39
8 38
8 38
12 38 39
11 12 34
12 38 39
11 12 34
12 38 39
11 12 34
12 38 39
11 12 34
38 38
11 12 34
8 38
8 38
8 38
8 38
8 38
8 38
11 12 34
11 12 34
11 34
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38 8 38
8 38
8 38
8 38
8 38 8 38
8 38 8 38
8 38
8 38
12 38 39 12 38 39
12 38 39 12 38 39
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
TP
TP
TP
TP
TP
TP
TP
IN
IN
IN
IN
IN
IN
IN
IO0-1
IO7-1
IO6-1
IO3-1
IO4-1
IO5-1
IO1-1
IO2-1
IO7-0
IO5-0
IO6-0
IO4-0
IO2-0
IO3-0
IO1-0
IO0-0
VCC
CLE1
CE1*
CLE0
CE0*
WE0*
ALE0
RE0
RE0*
DQS0*
R/B0*
DQS0
ALE1
WE1*
RE1
RE1*
DQS1
DQS1*
R/B1*
ZQ
VREF
VSSQVSS
VCCQVDDI
TMSC
TCKC
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
TP
TP
TP
TP
NC
NC
NC
NC
TP
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
DO NOT PLACE IN NAND SINGLE PCS SHIELD CAN AREA
TEST POINTS
NP0-C0G25V
0201
27PF5%
27PF25VNP0-C0G0201
5%25VNP0-C0G0201
27PF5%
6.3V20%
0402-1CERM-X5R
10UF
20%0.22UF6.3V
0201X5R
20%6.3V
0402-1CERM-X5R
10UF
0201
6.3V20%
X5R
0.22UF
5%27PF
0201NP0-C0G25V
5%27PF
0201NP0-C0G25V
6.3V20%
0402-1CERM-X5R
10UF
6.3VX5R0201
0.22UF20%
27PF
NP0-C0G25V
0201
5%
0.22UF
X5R
20%6.3V
0201
5%27PF
0201NP0-C0G25V
100K
MF01005
5%1/32W
6 38
6 13 38
6 13 38
6 13 38
6 13 38
6 13 38
6 38
OMIT_TABLE
LGA-12X17
XXNM-XGBX8-MLC-PPN1.5-ODP
6 13 38
6 13 38
6 13 38
6 13 38
6 13 38
1/20W1%
201MF
243
10UF
CERM-X5R0402-1
20%6.3V
6.3V20%
0201X5R
1UF
10UF
CERM-X5R0402-1
6.3V20%
10UF
CERM-X5R0402-1
20%6.3V
6.3V20%
0201X5R
1UF
X5R0201
6.3V0.22UF20%
0201
6.3V20%
X5R
0.22UF
6 13 38
6 38
6 38
6 38
6 38
6 38
6 38
6 38
6 13 38
6 38
6 38
6 38
6 38
6 38
6 38
6 38
4V20%
01005X5R
0.1UF
4V20%
01005X5R
0.1UF
1/32W1%
01005MF
51.1K
1/32W1%
01005MF
51.1K
25VNP0-C0G0201
27PF5%
NP0-C0G
5%
0201
25V27PF
5%27PF
0201NP0-C0G25V
10UF
CERM-X5R0402-1
20%6.3V
X5R0201
6.3V0.22UF20%
10UF
CERM-X5R0402-1
6.3V20%
CERM-X5R20%
0402-1
6.3V10UF
0201
6.3V20%
X5R
0.22UF0.22UF
X5R6.3V
0201
20%
SYNC_DATE=N/A
NANDSYNC_MASTER=N/A
=PP1V8_NAND=PP3V3_NAND
FMI1_AD<7>
FMI0_RE_L
FMI1_AD<6>FMI1_AD<5>FMI1_AD<4>FMI1_AD<3>FMI1_AD<2>FMI1_AD<1>FMI1_AD<0>
FMI0_AD<7>FMI0_AD<6>FMI0_AD<5>FMI0_AD<4>FMI0_AD<3>FMI0_AD<2>FMI0_AD<1>FMI0_AD<0>
FMI1_DQS
FMI1_RE_L
FMI1_WE_LFMI1_ALEFMI1_CLEFMI1_CE0_L
FMI0_DQS
FMI0_WE_LFMI0_ALEFMI0_CLEFMI0_CE0_L
TP_FMI_TCKC_U1600
TP_FMI_TMSC_U1600FMI_ZQ_U1600
NAND_SLOT0_RDYBSY_L
FMI_DQVREF_NAND
=PP1V8_NAND
=PP1V8_NAND
FMI1_DQS
FMI0_RE_L
FMI0_ALEFMI0_AD<0>
FMI0_CLE
FMI1_WE_L
FMI0_DQS
FMI1_RE_LFMI1_CLEFMI1_ALE
FMI0_WE_L
FMI1_AD<0>
PPVDDI_NAND_U1600VOLTAGE=1.2VMIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3MM
TP16001
TP16011
TP16021
TP16031
TP16051
TP16061
TP16071
TP16081
TP16091
TP16111
R16551
2
U1600C1
D2
A5
C5
A3
C3
H4
F4
M4
K4
G3
G1
H2
J1
J3
L1
K2
N3
L5
N5
K6
L7
J5
J7
H6
G7
E5
E7
B4
C7
D4
D6
OA0
OB0
B6
F2
M6
N1
N7
OC8
OD8
OE0
OF8
G0
OA8
OB8
G5
B2
F6
L3
A7
M2
OC0
OD0
OE8
OF0
G8
E3
E1
A1
R16541
2
C16021
2
C16501
2
C16011
2
C16001
2
C16511
2
C16061
2
C16051
2
C16901
2
C16911
2
R16901
2
R16911
2
TP16131
TP16151
C16071
2
C16081
2
C16091
2
C16121
2
C16221
2
C16111
2
C16101
2
C16211
2
C16201
2
C16321
2
C16311
2
C16301
2
C16151
2
C16251
2
C16141
2
C16241
2
C16341
2
C16351
2
C16131
2
C16231
2
C16331
2
C16041
2
C16521
2
051-9385
A.0.0
16 OF 154
13 OF 39
13 34 34
13 34
13 34
6 13 38
6 13 38
6 13 38
6 13 38
6 13 38
6 13 38
6 13 38
6 13 38
6 13 38
6 13 38
6 13 38
6 13 38
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
WIFI ALIASES
SYNC_MASTER=N/A SYNC_DATE=N/A
ALIASES
GPIO_WLAN_HSIC_DEV_RDY MAKE_BASE=TRUE
GPIO_BT_WAKE MAKE_BASE=TRUE
MAKE_BASE=TRUEVDDIO_WLAN_BT_1V8
UART3_BT_RTS_L MAKE_BASE=TRUE
PMU_GPIO_CLK_32K_WLAN MAKE_BASE=TRUE
I2S2_BT_BCLK MAKE_BASE=TRUE
I2S2_BT_LRCK MAKE_BASE=TRUE
UART4_WLAN_RXD MAKE_BASE=TRUE
I2S2_BT_DIN MAKE_BASE=TRUE
BT_PCM_INBT_PCM_OUT
UART3_BT_RXD MAKE_BASE=TRUE
PP_WL_BT_VDDIO_AP
HSIC1_WLAN_STB MAKE_BASE=TRUE
GPIO_WLAN_HSIC_HOST_RDY MAKE_BASE=TRUE
PMU_GPIO_WLAN_REG_ON MAKE_BASE=TRUE
DEV_HSIC3_RDY
50_HSIC_WLAN_STROBE
PMU_GPIO_BT_HOST_WAKE MAKE_BASE=TRUE
BT_UART_CTS_L
BT_PCM_SYNC
BT_PCM_CLK
BT_UART_RXD
BT_REG_ON
I2S2_BT_DOUT MAKE_BASE=TRUE
PMU_GPIO_BT_REG_ON MAKE_BASE=TRUE
PMU_GPIO_WLAN_HOST_WAKE MAKE_BASE=TRUE
UART3_BT_TXD MAKE_BASE=TRUE
BT_WAKE
WLAN_REG_ONHOST_WAKE_WLAN
HOST_WAKE_BT
UART3_BT_CTS_L MAKE_BASE=TRUE
50_HSIC_WLAN_DATAHSIC1_WLAN_DATA MAKE_BASE=TRUE
UART4_WLAN_TXD MAKE_BASE=TRUE WLAN_UART_RXDGPIO_WL_HSIC_RESUME MAKE_BASE=TRUE WLAN_HSIC3_RESUME
WLAN_UART_TXD
CLK32K_AP
BT_UART_RTS_L
BT_UART_TXD
AP_HSIC3_RDY
051-9385
A.0.0
21 OF 154
14 OF 39
5 36
5
34
5 36
30 36
5 36
5 36
5 36
5 36
27
27
5 36
27
4 36
5 36
30
27
27
30
27
27
27
27
27
5 36
30
30
5 36
27
27
27
27
5 36
27 4 36
5 36 27
5 27
27
27
27
27
27
2 3
OUT
IN
IN
IN
IN
IN
IN
SYM_VER-2
IN
SYM_VER-2
SYM_VER-2
SYM_VER-2
IN
SYM_VER-2
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
NC
NC
NC
IN
NC
NC
NC
NC
NC
NC
CAP
ON S
D
VDD
GND
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
518S0827
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION
EDP CONNECTOR
LAYOUT NOTE:
7 37
CERM50V+/-0.25PF
402-1
8.2PF
CERM50V+/-0.25PF
402-1
8.2PF
NOSTUFF16V
+/-0.1PF
01005NP0-C0G
1.2PF
NOSTUFF16V
+/-0.1PF
01005NP0-C0G
1.2PF
NOSTUFF16V
+/-0.1PF
01005NP0-C0G
1.2PF
NOSTUFF16V
+/-0.1PF
01005NP0-C0G
1.2PF
NOSTUFF16V
+/-0.1PF
01005NP0-C0G
1.2PF
NOSTUFF16V
+/-0.1PF
01005NP0-C0G
1.2PF
CRITICAL
F-RT-SM502250-8051-B
NOSTUFF16V
+/-0.1PF
01005NP0-C0G
1.2PF
NOSTUFF16V
+/-0.1PF
01005NP0-C0G
1.2PF
5%
MF1/20W
0
201
5%1/20W
201
0
MF
5%
201MF
1/20W
0
0201
16V10%
X7R-CERM
1000PF
0201
25V+/-0.1PF%
CER
8.2PF
CRITICAL
0402A
FERR-120-OHM-1.5A
5%82PF
0201NP0-C0G-CERM25V
5%
NOSTUFF
1/20W
201MF
47K
CERM6.3V10%
402
1UF6.3V10%
201X5R
0.1UF
1/32W1%
01005MF
100K
30 37
30 37
30 37
30 37
30 37
30 37
CERM50V10%
0402
820PF5%CERM50V
0402
100PF
CERM50V10%
0402
820PF5%
CERM50V
0402
100PF
CRITICAL
0402
FERR-240-OHM-25%-300MA
CRITICAL
0402
FERR-240-OHM-25%-300MA
1/32W1%
01005MF
100K
90-OHM-50MA
CRITICAL
TCM0605-1
30 37
1/32W1%
01005MF
100K
12-OHM-100MA-8.5GHZ
CRITICAL
TCM0806-4SM
12-OHM-100MA-8.5GHZ
CRITICAL
TCM0806-4SM
12-OHM-100MA-8.5GHZ
CRITICAL
TCM0806-4SM
6.3V 10%201 X5R
0.1UF
6.3V 10%201 X5R
0.1UF
201 6.3V 10% X5R
0.1UF
201 6.3V 10% X5R
0.1UF
6.3V 10%201 X5R
0.1UF
30 37 6.3V 10%201 X5R
0.1UF
10%6.3V201 X5R
0.1UF
0.1UF
6.3V 10%201 X5R
10%
0.1UFX5R201 6.3V
CRITICAL
12-OHM-100MA-8.5GHZTCM0806-4SM
0.1UF
X5R201 10%6.3V
6.3V10%
201X5R
0.1UF
30 37
5
7 37
7 37
5%1/20W
201MF
100K
7 37
30 37
7 37
7 37
7 37
7 37
7 37
7 37
7 37
01005
1.00M
01005
1.00M
30 37
01005
1.00M
01005
1.00M
01005
1.00M
01005
1.00M
01005
1.00M
01005
1.00M
30 37
CRITICAL
TDFNSLG5AP302
6.3V10%
201X5R
0.1UF
50V10%
0402X7R
3900PF
RDAR://PROBLEM/9017591L2202,L2212,L2222,L2232155S0559155S0625
RDAR://PROBLEM/8616060, RADAR://PROBLEM/9015335L2242,L5500,L5510,L5520,L5530,L5540,L5930,L5931
155S0583155S0667
VIDEO: EDP CONNECTORSYNC_MASTER=N/A SYNC_DATE=N/A
J2200_36_GND
J2200_43_GND
J2200_43_GND
J2200_36_GND
J2200_29_GND
J2200_29_GND
LED_IO_2_B
LED_IO_6_B
CONN_EDP_DATA_EMI_P<3>
=PPLED_REG_A
=PPLED_REG_B
PP3V3_S0_LCD_FERR
CONN_EDP_AUX_EMI_P
CONN_EDP_AUX_EMI_NEDP_AUX_EMI_N
EDP_AUX_EMI_P
CONN_EDP_DATA_EMI_P<0>
CONN_EDP_DATA_EMI_N<0>
CONN_EDP_DATA_EMI_P<1>
CONN_EDP_DATA_EMI_N<1>
EDP_DATA_EMI_N<0>
EDP_DATA_EMI_P<0>
EDP_DATA_EMI_N<1>
EDP_DATA_EMI_P<1>
CONN_EDP_DATA_EMI_N<3>
CONN_EDP_DATA_EMI_P<2>
CONN_EDP_DATA_EMI_N<2>
CONN_EDP_DATA_EMI_P<3>
CONN_EDP_DATA_EMI_N<1>
CONN_EDP_DATA_EMI_P<0>
CONN_EDP_DATA_EMI_P<1>
CONN_EDP_DATA_EMI_P<2>CONN_EDP_DATA_EMI_N<3>CONN_EDP_DATA_EMI_P<3>
CONN_EDP_DATA_EMI_N<1>CONN_EDP_DATA_EMI_P<1>CONN_EDP_DATA_EMI_N<2>
CONN_EDP_AUX_EMI_PCONN_EDP_AUX_EMI_N
CONN_EDP_DATA_EMI_P<0>CONN_EDP_DATA_EMI_N<0>
PPVCC_MAIN
CONN_EDP_DATA_EMI_N<0>
LCD_RAMP
NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMVOLTAGE=20.4V
MAX_NECK_LENGTH=3 MM
PPLED_BACK_REG_A
PPLED_BACK_REG_B
NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMVOLTAGE=20.4V
MAX_NECK_LENGTH=3 MM
PP3V3_LCDVDD_SW_FMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 MMVOLTAGE=3.3V
LED_IO_1_ALED_IO_3_A
EDP_DATA_P<1>
EDP_DATA_N<1>
EDP_DATA_P<0>
LED_IO_5_A
EDP_DATA_N<0>
EDP_AUX_P
EDP_AUX_N
PM_LCDVDD_PWREN
LED_IO_4_B
LED_IO_2_ALED_IO_4_ALED_IO_6_ALED_IO_1_BLED_IO_3_BLED_IO_5_B
EDP_HPD
CONN_EDP_DATA_EMI_P<2>
CONN_EDP_DATA_EMI_N<2>EDP_DATA_EMI_N<2>
EDP_DATA_EMI_P<2>
EDP_DATA_N<2>
EDP_DATA_P<2>
CONN_EDP_DATA_EMI_N<3>EDP_DATA_EMI_N<3>
EDP_DATA_EMI_P<3>
EDP_DATA_N<3>
EDP_DATA_P<3>
=PP3V3_LCD
PP3V3_S0_LCD_FERRMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 MMVOLTAGE=3.3V
R22421
2
J2200
1
1011
1213
1415
1617
1819
2
2021
2223
2425
2627
2829
3
3031
3233
3435
3637
3839
4
4041
4243
4445
4647
4849
5
5051
52
53
54
55
67
89
C22061
2
C22321
2
L2201
1 2
C22301
2
R22901
2
C22021
2
C22031
2
C22701
2
C22531
2
C22201
2
C22331
2
L2210
1 2
L2200
1 2
R22401
2
L2242
1 4
R22411
2
L2212
1
2 3
4
L2222
1
2 3
4
L2232
1
2 3
4
C22501 2
C22511 2
C22421 2
C22431 2
C22441 2
C22451 2
C22461 2
C22471 2
C22481 2
L2202
1
2 3
4C22491 2
C22391
2
R22051
2
R22811 2
R2280
1 2
R22831 2
R22821 2
R22841 2
R22861 2
R22851 2
R22871 2
U2200
37
8
52
1
C22401
2
C22411
2
C22711
2
C22211
2
C2287
1 2
C2286
1 2
C2285
1 2
C2284
1 2
C2283
1 2
C2282
1 2
C2281
1 2
C2280
1 2
R22951 2
R22961 2
R22971 2
051-9385
A.0.0
22 OF 154
15 OF 39
15 39
15 39
15 39
15 39
15 39
15 39
15 37
34
34
15 39
15 37
15 37 37
37
15 37
15 37
15 37
15 37
37
37
37
37
15 37
15 37
15 37
15 37
15 37
15 37
15 37
15 37
15 37
15 37
15 37
15 37
15 37
15 37 15 37
15 37
15 37
25 29 30 34 39
15 37
39
39
39
15 37
15 37 37
37
15 37 37
37
34
15 39
CTRL
PGND
THRML
L
VIN
DO
FB
SW
PAD GND
VSTM26
VSTM25
VSTM24
VSTM23
MUX19
MUX17
BON_L0
BON_L1
BON_L2
BON_L3
BON_L4
BON_L5
MUX0
MUX1
MUX2
MUX3
MUX4
MUX5
MUX6
MUX7
MUX8
MUX9
MUX10
MUX11
MUX12
MUX13
MUX16
MUX15
MUX18
MUX20
MUX21
MUX22
MUX23
NC
VSTM1
VSTM0
VSTM6
VSTM5
VSTM4
VSTM3
VSTM2
VSTM8
VSTM11
VSTM10
VSTM7
VSTM16
VSTM15
VSTM14
VSTM13
VSTM12
VSTM21
VSTM20
VSTM19
VSTM18
VSTM17
VSTM22
VSTM27
VSTM31
VSTM30
VSTM29
VSTM28
VSTM32
VSTM36
VSTM35
VSTM34
VSTM33
VSTM37
VSTM42
VSTM41
VSTM40
VSTM39
VSTM38
VSTM47
VSTM45
VSTM44
VSTM43
A_AD_R2
A_AD_R1
A_AD_R0
MUX14
VSTM46
GND
VSTM9
VDDHVCC_DIG
OUT
OUT
OUT
OUT
VCCA
1B1
1B2
2A2
1A1
2A1
1A2
2DIR
2OE*
1DIR
1OE*
2B2
2B1
GND
VCCB
IN
IN
IN
IN
IN
NCOE*
OUT
IN
OUT
VCC
OE
A
NC
Y
GND
IN
IN
NCNCNCNC
NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC
NCNCNCNCNCNCNCNC
NCNC
NC
A
DIR
VCCB
GND
B
VCCA
INOUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
CONNECTORS TO GRAPE FLEXTO Z2
LOAD CURRENT ~ 153UA
MIN_NECK_MIDTH SHOULD BE 0.4MMBOOST CONVERTOR
P/N 518S0828
MATES WITH RIGHTMOST GRAPE FLEX TAIL
MATES WITH LEFTMOST GRAPE FLEX TAIL
TO Z1/Z2
APN:311S0485
(A -> B)
1UF
X5R603-1
25V10%
VLF
4.7UH-700MA-280MOHM
CRITICAL
TPS61045QFN-1
CRITICAL
SM
X5R402
0.1UF25V10%
402X5R
0.1UF25V10%
0.1UF
X5R402
25V10%
X5R6.3V
0.1UF
201
10%
GROUNDHOGBGA
OMITCRITICAL
X5R-X7R-CERM0201
470PF10%16V
402X5R
0.1UF25V10%
MF
0
1/20W5%
201
01/20WMF
NOSTUFF
5%
201
502250-8037-B
CRITICAL
F-RT-SM
502250-8037-B
CRITICAL
F-RT-SM
10K1/20WMF
5%
201
MF-LF1/16W
1%1M
402
1/20WMF
10K5%
201
17
16 17
17
16 17
MF
3.3K
1/20W5%
201
0.1UF6.3VX5R201
10%
SN74AVCH4T245RSV
PQFP1CRITICAL
X5R6.3V
0.1UF
201
10%10K
1/20WMF
5%
201
1/20WMF
10K5%
201
5
5 16 36
5 16 36
5 16 36
17
0.1UF
X5R6.3V
201
10%
SN74LVC1G125DRYR-MLLP
CRITICAL
5 16 36
16 17
17
X5R6.3V
0.1UF
201
10%
LLPSN74LVC1G126DRYR-M
CRITICAL
16 17
16 17
BGASN74LVC1T45YZPR
0.1UF
X5R6.3V
201
10%
0
1/20WMF
NOSTUFF
5%
201
17 5
MF
71.5K1/20W1%
201
603
6.3VX5R
2.2UF10%
25VNPO-C0G
0201
33PF5%
B0520WSXG
SOD-323
CRITICAL
X5R402
0.1UF
25V10%
0.1
1%
MF1/20W
201
SYNC_MASTER=N/A SYNC_DATE=N/A
GRAPE: GROUNDHOG,CONN,BOOST
U30031343S0525 IC,ASIC,GROUNDHOG B0,120B BGA CRITICAL
311S0485311S0523 U3007
311S0532311S0525 U3010
311S0524 311S0533 U3009
MT_PANEL_IN<8>
MT_PANEL_IN<1>MT_PANEL_IN<2>
MT_PANEL_IN<3>MT_PANEL_IN<4>
MT_PANEL_IN<5>MT_PANEL_IN<6>
MT_PANEL_IN<7>MT_PANEL_IN<9>MT_PANEL_IN<11>
MT_PANEL_IN<12>MT_PANEL_IN<13>
MT_PANEL_IN<14>MT_PANEL_IN<15>
MT_PANEL_IN<16>MT_PANEL_IN<17>
MT_PANEL_IN<18>MT_PANEL_IN<19>
MT_PANEL_IN<20>MT_PANEL_IN<21>MT_PANEL_IN<23>
MT_PANEL_IN<24>MT_PANEL_IN<26>
MT_PANEL_IN<27>MT_PANEL_IN<28>
MT_PANEL_IN<29>
MT_PANEL_OUT<39>MT_PANEL_OUT<38>
MT_PANEL_OUT<37>MT_PANEL_OUT<36>
MT_PANEL_IN<0>AG_SHLD_TST_FLEX
GRAPE_MOSIGPIO_GRAPE_RST_L MAKE_BASE=TRUE
RST_GRAPE_Z2_L
SPI3_GRAPE_CS_L MAKE_BASE=TRUE
SPI3_GRAPE_MISO MAKE_BASE=TRUE
VR_BOOST_L
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.2MM
=PP3V0_GRAPE
AG_SHLD_TST_FLEX
Z1_BON_L<5>
Z1_BON_L<3>Z1_BON_L<4>
Z1_BON_L<2>Z1_BON_L<1>Z1_BON_L<0>
Z1_B_ADR<2>Z1_B_ADR<1>Z1_B_ADR<0>
MT_PANEL_OUT<37>MT_PANEL_OUT<36>
MT_PANEL_OUT<39>MT_PANEL_OUT<38>
MT_PANEL_OUT<31>MT_PANEL_OUT<30>MT_PANEL_OUT<29>
MT_PANEL_OUT<26>MT_PANEL_OUT<25>
MT_PANEL_OUT<22>
MT_PANEL_OUT<20>MT_PANEL_OUT<21>
MT_PANEL_OUT<16>
MT_PANEL_OUT<28>
MT_PANEL_OUT<32>
MT_PANEL_OUT<17>
MT_PANEL_OUT<19>
MT_PANEL_OUT<24>
MT_PANEL_OUT<33>MT_PANEL_OUT<34>
MT_PANEL_OUT<23>
MT_PANEL_OUT<11>
MT_PANEL_OUT<15>
MT_PANEL_OUT<1>
MT_PANEL_OUT<8>MT_PANEL_OUT<7>
MT_PANEL_OUT<9>
MT_PANEL_OUT<5>MT_PANEL_OUT<4>
MT_PANEL_OUT<14>
MT_PANEL_OUT<6>
MT_PANEL_OUT<13>
MT_PANEL_OUT<0>
MT_PANEL_OUT<2>
MT_PANEL_OUT<10>
MT_PANEL_OUT<3>
PP18V_GRAPE
MUX_IN<4>
=PP3V0_GRAPE_MARIO1
MUX_IN<8>MUX_IN<7>
MUX_IN<9>
MUX_IN<1>
MUX_IN<11>MUX_IN<10>
MUX_IN<5>
MUX_IN<18>
MUX_IN<12>
MUX_IN<6>
MUX_IN<3>
MUX_IN<14>MUX_IN<15>
MUX_IN<17>
MUX_IN<2>
MUX_IN<0>
MT_PANEL_OUT<24>MT_PANEL_OUT<26>
MT_PANEL_OUT<33>MT_PANEL_OUT<32>
MT_PANEL_OUT<31>MT_PANEL_OUT<30>
MT_PANEL_OUT<29>MT_PANEL_OUT<28>
MT_PANEL_OUT<27>MT_PANEL_OUT<25>MT_PANEL_OUT<23>
MT_PANEL_OUT<22>MT_PANEL_OUT<21>
MT_PANEL_OUT<20>MT_PANEL_OUT<19>MT_PANEL_OUT<17>MT_PANEL_OUT<15>
MT_PANEL_OUT<14>MT_PANEL_OUT<13>
MT_PANEL_OUT<12>MT_PANEL_OUT<11>
MT_PANEL_OUT<10>MT_PANEL_OUT<9>
MT_PANEL_OUT<8>MT_PANEL_OUT<7>
MT_PANEL_OUT<6>MT_PANEL_OUT<5>
MT_PANEL_OUT<4>MT_PANEL_OUT<3>
MT_PANEL_OUT<2>MT_PANEL_OUT<1>
MT_PANEL_OUT<0>
MT_PANEL_OUT<34>MT_PANEL_OUT<35>
AG_SHLD_TST
MUX_IN<19>
MT_PANEL_OUT<18>MT_PANEL_OUT<16>
PM_BOOST_EN
MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.2MM
AGND_U3000
MUX_IN<16>
GRAPE_SCLKGRAPE_CS_L
=PP3V0_GRAPE
MT_PANEL_OUT<35>
MT_PANEL_OUT<18>
RST_GRAPE_Z1_L
GRAPE_MISO
MUX_IN<13>MT_PANEL_OUT<12>
SPI3_GRAPE_MOSI MAKE_BASE=TRUE
SPI3_GRAPE_SCLK MAKE_BASE=TRUE
MT_PANEL_IN<25>
NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMVOLTAGE=18V
PP18V_GRAPE
VR_BOOST_FBK
PP18V_R_GRAPENET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.6MMVOLTAGE=18V
=PP3V0_GRAPE=PP3V0_GRAPE
DIR_U3007GPIO_GRAPE_FW_DNLD_EN_L
Z2_H_CS_L
Z1_CS_OE
Z1_SCLK
Z1_MISO
SPI3_GRAPE_SCLKSPI3_GRAPE_CS_L
SPI3_GRAPE_MOSI
=PP3V0_GRAPE=PP3V0_GRAPE
Z1_CS_OE
Z1_MOSISPI3_GRAPE_MISO
Z1_CS_L
Z1_CS_OE
Z2_H_CS_L
=PP1V8_MISC
MT_PANEL_OUT<27>
GPIO_GRAPE_IRQ_L GPIO_GRAPE_IRQ_3V0_L
=PP3V0_GRAPE
MT_PANEL_IN<22>
MT_PANEL_IN<10>
MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.2MM
VR_BOOST_SW
C30001
2
R30091
2
R30121
2
C3008 1
2
D3000A K
C30091 2
L3000
1 2
U3000
53
4
6
1
7
8
9
2
XW3000
1
2
C30011
2
R30661 2
C3005 1
2
C3007 1
2
C3053 1
2
C30061
2
U3003
A10B9
A9
C7
A7
B7B8
A8
C8
C9
D7
G7
G8
E3
E5
E6
E7
F6
F7
G5
G6
B1
C1
I5
J8
J9
K8
J10I10
H10
F11C11
E10
E1
A11B4
A5
A2
F2
H1
J1
J2
J3
K4
H5
C6
D3
F5
F8
F9
G3
G4
G9
H3
H4
H7
H8
D4
H9
J6
K7
D5
D6
D8
D9
E4
E8
F4
A6
B6
E9
F3
A1
B2
H2
I2
K1
K2I3
K3
J4
I4
K6
H6
C2
K5
J5I7
K9
I8
K10
I6
J7
K11I9
D1
J11
I11
H11
G11
G10
F10
C10D10E11
D11
D2
B11
B10
C4
A4
B5
C5A3
B3
E2
F1
G1
G2
I1
C30021
2
C30701
2
R30701 2
R30711
2
J3010
1
1011
1213
1415
1617
1819
2
2021
2223
2425
2627
2829
3
3031
3233
3435
3637
38
39
4
40
41
56
78
9
J3011
1
1011
1213
1415
1617
1819
2
2021
2223
2425
2627
2829
3
3031
3233
3435
3637
38
39
4
40
41
56
78
9
R30251
2
R30331
2
R30321
2
C30311
2
U3007
6
7
15
14
4
1
8
9
13
12
5
16
10
11
3 2
C30301
2
R30311
2
R30301
2
C30411
2
U3009
2
3
1
6
4
C30501
2U3010
2
3
1
6
4
U3060
C1 C2
B2
B1
A1 A2
C30601
2
R30601 2
051-9385
A.0.0
30 OF 154
16 OF 39
5
5
17
17 17
17 17
17 17
17
17
17 17
17 17
17 17
17 17
17 17
17
17 17
17 17
17 17
16 16
16 16
17 16
17
5
17
5 16 36
5 16 36
16 17 34
16
17
17
17
17
17
17
17
17
17
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
17
34
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
16
16
16 16
16 16
16 16
16
16
16 16
16 16
16
16
16 16
16 16
16 16
16 16
16 16
16 16
16 16
16 16
16 16
17
17
16
16
17
39
17
17
17
16 17 34
16
16
17
17
17
16
5 16 36
5 16 36
17
16
16 17 34 16 17 34
16 17 34 16 17 34
34
16
16 17 34
17
17
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
OUT
IN
IN
IN
IN51
RESET*
VDDDIGVDDIO
V18
MOSI
VDDANA
IN25
BON_L0
BON_L1
BON_L2
BON_L3
BON_L4
BON_L5
B_ADR0
B_ADR1
B_ADR2
CS*
DONE
GNDANAGNDDIG GNDIO
GO
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IN17
IN18
IN19
IN20
IN21
IN22
IN23
IN24
IN27
IN28
IN29
IN30
IN31
IN32
IN33
IN34
IN35
IN36
IN37
IN38
IN39
IN40
IN41
IN42
IN43
IN44
IN45
IN46
IN47
IN48
IN49
IN50
IN52
IN53
IN54
IN55
IN56
IN57
IN58
IN59
IN60
IN61
MISO
PCLK
SCLK
STMIN
STMOUT
TM
IN26
IN62
IN63
NCNCNCNCNCNCNCNCNCNCNCNCNCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NC
NCNC
NCNC
VDDANA VDDCORE
TM0
TM1
RESET*
LFOO
A_CS*
A_SDI
IN7_0
H_SCLK
VDDLDO
JTAG_TDI
JTAG_TCK
IN9_1
IN9_0
IN8_1
IN8_0
IN7_1
IN6_1
IN6_0
IN5_1
IN4_1
IN4_0
IN3_1
IN3_0
IN2_1
IN2_0
IN11_1
IN11_0
IN10_1
IN10_0
IN1_1
IN1_0
IN0_1
IN0_0
H_SDO
H_SDI
H_CS*
GPIO7
GPIO6
FLOO
BOOT_CFG1
BOOT_CFG0
BON_L5
BON_L4
BON_L3
BON_L2
BON_L1
BON_L0
B_ADR1
ARMTAPMD*A_SDO
A_SCLK
GPIO1
GPIO0
GPIO2
GPIO3
VDDIO
GPIO5
CLKIN
CLKOUT
EXTFLLIN
JTAG_TDO
JTAG_TMS
GPIO4
IN5_0
B_ADR2
B_ADR0
GND
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
FLOAT
BON_L4
Z2 - PRODUCT STRAP OPTIONS
VDDANA AND VDDCOREARE EACH GENERATED WITHIN
J2
FLOAT
BON_L5
LOW
ALL OTHER STRAPS
DEFAULT
LOW
X
BON_L3
FLOAT J2
X K48
MODE
CRITICAL ERROR
INTERNAL PU
MIN_NECK_MIDTH SHOULD BE 0.4MM
FLOAT FLOAT K94
Z2 AND BYPASSED OUTSIDE
MODE
DEPENDENT 1
SLAVE
AUTONOMOUS
DEPENDENT 2
K48 USES DEPENDENT 2 MODE
CFG0CFG1
0 0
0
1
1
1
0
1
ARM9 MCU (Z2 BASED)ZEPHYR 1+ ASIC
MF1/20W5%0
201
1/20W
201
5%
MF
0
201MF
1/20W5%0
0402-1
6.3V20%10UF
CERM-X5R
402
6.3VX5R-CERM1
4.7UF20%
16
16
16
16
16
16
16
16
16 17
16 17
16 17
16
30 36
01005
1005%1/32WMF
01005
1005%1/32WMF
16 17
16 17
16
16 17
100K
MF
5%1/20W
201
X5R4V
402
20%2.2UF
X5R6.3V
201
10%0.1UF
0.1UF6.3VX5R201
10%
402
6.3VX5R-CERM1
4.7UF20%
1/20W
201
4.7
MF
5%
10UF20%6.3VCERM-X5R0402-1
BCM5973BGA
CRITICAL
201
0.1UF6.3V10%
X5R
0.1UF10%6.3VX5R201
201
6.3VX5R
10%0.1UF
1/20W
201
5%100K
MF
0.1UF
X5R6.3V10%
201
201
10%
X5R6.3V
0.1UF
20%10UF
CERM-X5R6.3V
0402-1
20%4VX5R402
2.2UF
BCM5974CKFBGHFBGA
CRITICAL
Z1_GO
201MF
100K
1/20W5%
1/20W1%
MF201
1.00
GRAPE: Z1, Z2SYNC_DATE=N/ASYNC_MASTER=N/A
Z1_PCLK
NC_BON_L1 NO_TEST=TRUE
AG_SHLD_TSTNC_BON_L3 NO_TEST=TRUE
GPIO_GRAPE_IRQ_3V0_LPM_BOOST_EN
NET_SPACING_TYPE=PWR
VOLTAGE=1.8V
Z2_3V3_1V8_INMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
Z1_CS_OE_R
U3101_TM1
MT_PANEL_IN<10>
=PP3V0_GRAPE
HOST_REFCLK
Z2_A_CS_L
MT_PANEL_IN<26>
Z1_PCLK
MUX_IN<19>MUX_IN<18>MUX_IN<17>MUX_IN<16>MUX_IN<15>MUX_IN<14>MUX_IN<13>MUX_IN<12>
MUX_IN<10>MUX_IN<9>MUX_IN<8>MUX_IN<7>MUX_IN<6>MUX_IN<5>MUX_IN<4>MUX_IN<3>
MUX_IN<1>
MT_PANEL_IN<29>MT_PANEL_IN<28>MT_PANEL_IN<27>
MT_PANEL_IN<24>MT_PANEL_IN<23>MT_PANEL_IN<22>MT_PANEL_IN<21>
MT_PANEL_IN<18>MT_PANEL_IN<17>
MT_PANEL_IN<15>MT_PANEL_IN<14>MT_PANEL_IN<13>MT_PANEL_IN<12>MT_PANEL_IN<11>
MT_PANEL_IN<9>MT_PANEL_IN<8>MT_PANEL_IN<7>
MT_PANEL_IN<4>MT_PANEL_IN<3>
Z1_DONE
Z1_B_ADR<2>Z1_B_ADR<1>Z1_B_ADR<0>
Z1_BON_L<5>Z1_BON_L<4>Z1_BON_L<3>Z1_BON_L<2>Z1_BON_L<1>Z1_BON_L<0>
MT_PANEL_IN<25>
NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.6MMVOLTAGE=1.8V
Z1_1V8_OUT
MT_PANEL_IN<1>
MT_PANEL_IN<16>
RST_GRAPE_Z1_L
U3100_TM
BOOT_CFG0_RBOOT_CFG1_R
=PP3V0_GRAPE
RST_GRAPE_Z2_L
Z1_CS_OE
Z1_SCLKZ1_MISOZ1_MOSI
Z2_H_CS_L
PMU_GPIO_CLK_32K_GRAPEMAKE_BASE=TRUE
Z1_MOSIZ1_MISOZ1_CS_LZ1_SCLK
MUX_IN<11>
MUX_IN<0>
MT_PANEL_IN<19>
MT_PANEL_IN<2>
MUX_IN<2>
Z1_1V8_OUT
MT_PANEL_IN<0>
Z1_STMIN
Z1_GOMT_PANEL_IN<5>MT_PANEL_IN<6>
GRAPE_CS_LGRAPE_MOSIGRAPE_MISOGRAPE_SCLK
TP_U3101_TCK
NC_BON_L5 NO_TEST=TRUE
Z1_DONE
TP_U3101_TDITP_U3101_TDOTP_U3101_TMS
TP_Z2_A_SCLKTP_Z2_A_SDITP_Z2_A_SDO
TP_U3101_TM0
=PP3V0_GRAPE_Z2
MT_PANEL_IN<20>
=PP3V0_GRAPE
VOLTAGE=1.8VMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.1MMNET_SPACING_TYPE=PWR
Z2_VDDANA
VOLTAGE=1.8VMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.1MMNET_SPACING_TYPE=PWR
Z2_VDDCORE
=PP3V0_GRAPE_Z1
NET_SPACING_TYPE=PWR
MT_3V3_INT
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.2MMVOLTAGE=3.0V
C31061
2
C31051
2
C31081
2
R31071
2
C31091
2
C31101
2
C31111
2
C31121
2
U3101
F1
G1
F2
G4E6
F9
F8
G9
J8
H9
J9
H7
J7
H5
F6
D3
E5
E4
G7
G5
C3
H8
C4
D6
D7
D8
C9
D9
G2
D1
J2
J3
H4
J6
G3
F3
F4
H6
H1
J1
H3
J4
A9
B9
B2
C1
B1
A1
A7
A8
B8
C8
B7
C7
A6
B6
C6
C5
B5
A5
A4
B4
A3
B3
C2
A2
G6
E8
E9
F7
F5
D5
E7
D4
D2
E1
G8
H2
J5
E2
E3
R31601
2
R31901 2
R31711
2
R31731
2
R3120
1 2
C31911
2
C31071
2
R31801
2
R31811
2
R31551
2
C31011
2
C31021
2
C31031
2
C31041
2
R31011 2
C31921
2
U3100
A5
B5
A6
A2
A1
A3
A4
B4
B3
B10
B7
B1
B2
C12
D3
D11
F7
H7
L3
L4
L5
L6
L7
B12
L8
L9
L10
L11
B13
C2
C3
C6
C7
C8
C11
C4
B11
A8
H2
G2
E1
E2
J2
G1
F2
J7
K2
N4
M5
N5
D7
M6
N3
M3
L1
K1
L2
N6
M2
M4
M1
C1
N2
N1
N13
N12
M10
M13
N8
M12
K13
L13
F1
L12
M11
N11
M8
N9
M9
N10
K12
J13
F12
J1
G13
J12
E12
E13
H13
N7
D13
D12
H12
F13
D2
C13
E7
M7
G12
D1
K7
H1
B9
B8
A12
A7
A11
A13
A10
A9
B6
G6
G7
G8
K4
K10
C10
C5
C9
051-9385
A.0.0
31 OF 154
17 OF 39
17
17
16
16
16 17 34
16
17
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
17
16
16
16
16
16
16
16
16
16
16
17
16
16
16
16 17 34
16
16
16
16
16
17
16
17 16
16
17
34
16
16 17 34
34
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
BI
BI
OUT
IN
IN
IN
IN
OUT
OUT
SYM 2 OF 2
DMIC1_SCLK
DMIC2_SD
MCLK
GND13
GND0
TSTI2
TSTI1
TSTI0
GND18
GND17
GND16
GND15
GND14
GND12
GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
RESET*
WAKE*
INT*
CDOUT
CDIN
CCLK
XSP_SDOUT
XSP_SDIN_DAC2_MUTE
XSP_LRCK_FSYNC
XSP_SCLK
ASP_SDOUT
ASP_SDIN
ASP_LRCK
ASP_SCLK
DMIC2_SCLK
DMIC1_SD
CS*
MBUS_REF
SYM 1 OF 2
FLYP
MIC4_BIAS_FILT
AIN3+
AIN1-
FLYN
GNDA
MIC1_BIAS
MIC2_BIAS_FILT_IN
MIC2_BIAS_FILT
MIC2_BIAS
AIN2+
AIN2M
MIC2_BIAS_IN
AIN3-
MIC3_BIAS
MIC3_BIAS_FILT
AIN4+
AIN4-
MIC4_BIAS
GNDP
GNDD
GNDHS
+VCP_FILT
FILT-
FILT+
LINEOUT_REF
LINEOUTB
LINEOUTA
HPDETECT
HS4_REF
HS3_REF
HS4
HS3
HPOUTB
HPOUTA
DN
DP
AOUT2-AOUT2+
AOUT1_M
AOUT1+
GNDCP
-VCP_FILT
VA
VCP1
VD
VP0
VL
VP1
VPROG_CP
VPROG_MB
SPEAKER_VQ
AIN1+
MIC1_BIAS_FILT
GNDHS
FLYC
VCP0
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
PLACE R3630 & R3631 CLOSE TO U3600
MIKEY BUS FILTER
DIGITAL MIC
TO HEADPHONE JACK
TO THE HP CONNECTORPLACE L3600 TO 3605 CLOSE
X5R-CERM1402
20%6.3V4.7UF
NOSTUFF
SHORT-8L-0.25MM-SM
4.7UF
X5R-CERM1402
20%6.3V
CRITICAL
4.7UF
X5R-CERM1402
20%6.3V
CRITICAL
MF 010055%1/32W2222
MF010055%1/32W
22
22
5 36
5 36
22MF010055%1/32W
22MF010055%1/32W
5 36
5 36
5 36
5 36
5 36
5 36
5 36
5 36
5 36
5 36
5 36
5
30
30
SHORT-8L-0.25MM-SM
NOSTUFF
SHORT-8L-0.25MM-SM
NOSTUFF
0.01UF
X5R-CERM020110%10V
0.01UF
X5R-CERM020110%10V
4.7UF
X5R-CERM1402
20%6.3V
CRITICAL
2.21K
MF201
1%1/20W
X5R0201-MUR
20%6.3V
CRITICAL
1.0UF
NOSTUFF
1.00K
MF01005
5%1/32W
18 25
2.2UF
X5R402
10%6.3V
NOSTUFFCRITICAL
25 37
25 37
12
MF201
5%1/20W
12
MF201
5%1/20W
SIGNAL_MODEL=EMPTY
100PF
NP0-CERM0201
5%25V
0201
100PF
NP0-CERM
5%25V
NOSTUFF
SIGNAL_MODEL=EMPTY
100PF
NP0-CERM0201
5%25V
18 25
MF201
5%1/20W
0
NOSTUFF
22
22
22
22
22
22
0.01UF
X5R01005
10%6.3V
0.01UF
X5R01005
10%6.3V
X5R0201-MUR
1.0UF20%6.3V
4.7UF
X5R-CERM1402
20%6.3V
CRITICAL1.00
1%1/20WMF201
201
1%
MF
1.00
1/20W
MF1/20W1%255K
201
201
5%1/20WMF
0
NOSTUFF
CS42L81-CWZR-A1
CRITICAL
WLCSP
CRITICAL
WLCSPCS42L81-CWZR-A1
0.1UF
X5R-CERM0201
10%16V
16V10%
0201X5R-CERM
0.1UF
X5R-CERM0402
10V
CRITICAL
4.7UF20%
16V0.1UF
X5R-CERM0201
10%
4V20%
01005X5R
0.1UF4V20%
01005X5R
0.1UF
0201-MUR
1.0UF
X5R20%6.3V
CRITICAL
X5R-CERM16.3V20%
402
4.7UF
4.7UF
X5R-CERM1402
20%6.3V
CRITICAL
4.7UF
20%6.3V
CRITICAL
402X5R-CERM1
20
240-OHM-0.2A-0.8-OHM
0201
4700PF
X7R201
10%10V
NOSTUFFMF
01005
5%1/32W
3.3K
AUDIO: L81 CODECSYNC_DATE=N/ASYNC_MASTER=N/A
=PPVCC_MAIN_AUDIO
MIKEY_TS_NMIKEY_TS_P
L81_MBUS_NL81_MBUS_P
VOLTAGE=1.7V
MIN_NECK_WIDTH=0.2 MMPP1V7_VA_VCP_RMIN_LINE_WIDTH=0.6 MM
L81_MIC2_BIAS
0.30MM0.15MM
L81_NVCP
GND_AUDIO_CODEC
0.30MM0.15MM
L81_PVCP
NO_TEST=TRUENC_MIC1_BIAS
L81_MBUS_P
CODEC_HP_DET_R CONN_HP_HEADSET_DET
MIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.15MM
HP_LEFT_FILT
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.15MM
HP_RIGHT_FILT
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM
HP_HS3_FILT
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MM
HP_HS4_FILT
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.15MMMIN_NECK_WIDTH=0.1MM
HP_HS3_REF_FILT
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.15MMMIN_NECK_WIDTH=0.1MM
HP_HS4_REF_FILT
MAKE_BASE=TRUE
L81_MBUS_REF
L81_MBUS_REF
PMU_GPIO_CODEC_RST_LPMU_GPIO_CODEC_HS_INT_LGPIO_CODEC_IRQ_L
I2S0_CODEC_ASP_MCK_R
SPI1_CODEC_MISOSPI1_CODEC_MOSI
I2S3_CODEC_XSP_DINI2S3_CODEC_XSP_DOUTI2S3_CODEC_XSP_LRCKI2S3_CODEC_XSP_BCLK
I2S0_CODEC_ASP_DINI2S0_CODEC_ASP_DOUTI2S0_CODEC_ASP_LRCKI2S0_CODEC_ASP_BCLK
DMIC1_FF_SD
L81_MIC2_BIAS_IN
MIN_LINE_WIDTH=0.3MML81_FLYP
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.15MM
L81_FLYC
MIC1_BIAS_FILT
MIC4_BIAS_FILTMIC3_BIAS_FILT
AIN4NAIN4PAIN3NAIN3PAIN1NAIN1P
AIN4P
MIC4_BIAS_FILTAIN4N
MIC3_BIAS_FILT
AIN3PAIN3N
MIC1_BIAS_FILT
AIN1PAIN1N
HP_MIC_P
L81_MIC2_BIAS_FILT_INL82_MIC2_BIAS_FILT
CODEC_HP_RIGHT
MIN_LINE_WIDTH=0.15MMMIN_NECK_WIDTH=0.1MM
CODEC_HP_HS3_REF
MIN_LINE_WIDTH=0.15MMMIN_NECK_WIDTH=0.1MM
CODEC_HP_HS4_REF
CODEC_HP_HS4
NO_TEST=TRUENC_RIGHT_CH_OUT_P
CODEC_HP_DET
NO_TEST=TRUENC_DMIC2_SCLK
L81_AIN2_N
L81_DMIC1_FF_SCLK
NO_TEST=TRUENC_CODEC_LINE_OUT_R
L81_AIN2_P
NO_TEST=TRUENC_MIC4_BIAS
NO_TEST=TRUENC_RIGHT_CH_OUT_N
CODEC_HP_HS3_REF HP_MIC_N
CODEC_HP_HS4_REF
GND_AUDIO_CODEC
L81_SPEAKER_VQ
NO_TEST=TRUENC_MIC3_BIAS
L81_FILT
I2S0_CODEC_ASP_SDOUT
CODEC_HP_DET
=PP1V8_AUDIO
NO_TEST=TRUENC_CODEC_LINE_OUT_L
L81_DMIC1_FF_SD
I2S3_CODEC_XSP_SDOUT
L81_MBUS_N
NO_TEST=TRUENC_LEFT_CH_OUT_P
CODEC_HP_LEFT
NO_TEST=TRUENC_LEFT_CH_OUT_N
GND_AUDIO_CODEC
SPI1_CODEC_SCLKSPI1_CODEC_CS_L
CODEC_MIC_BIAS_FILTMAKE_BASE=TRUE
CODEC_AINMAKE_BASE=TRUE
DMIC1_FF_SCLK
GND_AUDIO_CODEC
CODEC_HP_HS3
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.15MM
L81_FLYN
PP_VPROG_CP_RVOLTAGE=4.7VMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM
=PP1V7_VA_VCP
=PP1V8_AUDIO
PP_VPROG_MB_RVOLTAGE=4.7VMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM
LDO10
U3600
B3
A3
A2
A1
A6
B8
A7
C5
B2
B1
B6
B7
C6
D3
F6
F7
F8
G5
G6
G7
H5
H7
J5
D5
D6
D7
D8
E5
E6
E7
F5
B9
K5
C8
C9
C4
C7
D4B10
B5
B4
A5
A4
U3600
E4
E3
D1
C1
C2
C3
E2
D2
F9
F10
D9
D10
K4
J4
F1
E1
J10
K10
H10
G2
J9
A10
J2
K2
E10
H8
J8
K8
J1
K7
K1
J7
H6
K6
J6
K9
H2
H3
G4
F3
K3
J3
H4
G3
F4
F2
H9
C10
G1
G8
G9
A9
A8
E8
E9
G10
H1
C36141
2
C36131
2
C36091
2
C3604 1
2
C36151
2
C36021
2
C36031
2 C36011
2
C3605
12
C3606
12
L3620
1 2
C36201
2
R36201 2
C36101
2
XW3600
1 2
C3607
1 2
C3608
1 2
R3612 1 2
R3613 1 2
R3610 1 2
R3611 1 2
XW3602
12
XW3603
12
C3616
1 2
C3617
1 2
C3612
1 2
R36011 2
C3611 1
2
R36401
2
C3618 1
2
R36301 2
R36311 2
C36301
2
C36311
2
C36321
2
R36141 2
C36911
2
C36901
2
C36981
2
C36991
2
R36991 2
R369812
R36971
2
R36961 2
051-9385
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36 OF 154
18 OF 39
19 34
18 37
18 37
18 39
18 37
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
37
18
18
18
37
37
18 37
18
18 39
36
18
18 34
18 37
18 39
18 39
19 34
18 34
29 39
FILT+
SCL
VP
SDA
VA
ADO
VBST
SW
GNDA
IREF+
OUT+
OUT-
ISENSE+
ISENSE-
VSENSE+
VSENSE-
LDO_FILT
GNDP
INT*
RESET*
ALIVE
MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT
VER1
FILT+
SCL
VP
SDA
VA
ADO
VBST
SW
GNDA
IREF+
OUT+
OUT-
ISENSE+
ISENSE-
VSENSE+
VSENSE-
LDO_FILT
GNDP
INT*
RESET*
ALIVE
MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT
VER1
OUT
TABLE_5_ITEM
TABLE_5_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)LEFT SPEAKER AMP
I2C ADDRESS: 1000001X
SPEAKER CONNECTOR
RIGHT SPEAKER AMP
I2C ADDRESS: 1000000X
APN 518S0672
PLACE XWS CLOSE TO CONNECTOR
4.7UF
20%6.3V 402
X5R-CERM1
X5R-CERM120%4026.3V
4.7UF
NOSTUFF
0.01UF
X5R-CERM0201
10%10V
0.1UF
X5R201
10%6.3V
OMIT_TABLECRITICAL
220-OHM-2.0A
0603
OMIT_TABLE
220-OHM-2.0A
0603
CRITICAL
1%
MF
CRITICAL
1/4W
0805
0.100
OMIT_TABLE
10
MF201
5%1/20W
44.2K
MF201
1%1/20W
4.7UF
X5R-CERM1402
20%6.3V
0.1UF
X5R201
10%6.3V
OMIT_TABLE
220-OHM-2.0A
0603
CRITICAL
OMIT_TABLE
220-OHM-2.0A
0603
CRITICAL
4.7UF
X5R-CERM1402
20%6.3V
MF
1%
CRITICAL
1/4W
0805
0.100
44.2K
MF201
1%1/20W
WLCSP
CRITICAL
CS35L19B-CWZR
22UF
0603-1X5R-CERM
CRITICAL
10V20%
10%0.1UF
X5R-CERM0201
16V
4.7UF
X5R-CERM0402
20%10V
CRITICAL
4.7UF
X5R-CERM0402
20%10V
CRITICAL
4.7UF
0402
20%10V
CRITICAL
X5R-CERM
CRITICAL
CS35L19B-CWZRWLCSP
22UF
0603-1X5R-CERM
CRITICAL
10V20%
0.1UF
X5R-CERM0201
10%16V
4.7UF
X5R-CERM0402
20%10V
CRITICAL
4.7UF
X5R-CERM0402
20%10V
CRITICAL
4.7UF
X5R-CERM0402
20%10V
CRITICAL 100PF
NP0-C0G01005
5%16V
NOSTUFFCRITICAL
100PF
NP0-C0G01005
5%16V
NOSTUFFCRITICAL
100PF
01005
5%16V
NOSTUFFCRITICAL
NP0-C0G
NOSTUFF
100PF
NP0-C0G01005
5%16V
CRITICAL
SMSIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTYSM
SIGNAL_MODEL=EMPTYSM
SIGNAL_MODEL=EMPTYSM
78171-6006M-RT-SM
CRITICAL
5
22UF
0603-1X5R-CERM
CRITICAL
10V20%
22UF
0603-1X5R-CERM
CRITICAL
10V20%
0.1UF
X5R-CERM0201
10%16V
0.1UF
X5R-CERM0201
10%16V
CRITICAL
TFA302610A-SM
2.2UH-20%-3.3A-0.115OHM
CRITICAL
TFA302610A-SM
2.2UH-20%-3.3A-0.115OHM
NOSTUFF
25V5%
0201NP0-C0G-CERM
18PF
+/-0.1PF%8.2PF
CER25V
0201
+/-0.1PF%8.2PF
CER25V
0201
NOSTUFF
3.9PF
NP0-C0G-CERM0201
+/-0.1PF25V
NOSTUFF
3.9PF
NP0-C0G-CERM0201
+/-0.1PF25V
+/-0.1PF%8.2PF
CER25V
0201
NOSTUFF
18PF
NP0-C0G-CERM0201
5%25V
NOSTUFF
18PF
NP0-C0G-CERM0201
5%25V
+/-0.1PF%8.2PF
CER25V
0201
NOSTUFF
3.9PF
NP0-C0G-CERM0201
+/-0.1PF25V
OMIT_TABLE
5%10
MF201
1/20W
OMIT_TABLE
10
MF201
5%1/20W
OMIT_TABLE
10
MF201
5%1/20W
NOSTUFF
0.01UF
X5R-CERM0201
10%10V
10K
MF201
5%1/20W
10K
MF201
5%1/20W
10K
MF201
5%1/20W
NOSTUFF
NP0-CERM0201
5%25V
100PF
NOSTUFF
100PF
NP0-CERM0201
5%25V
NOSTUFF
100PF
NP0-CERM0201
5%25V
NOSTUFF
NP0-CERM0201
5%25V
100PF
10K
MF
5%1/20W
201
NOSTUFF
3.9PF
NP0-C0G-CERM0201
+/-0.1PF25V
NOSTUFF
25V5%
0201NP0-C0G-CERM
18PF
27PF
NP0-C0G01005
5%16V
27PF
NP0-C0G01005
5%16V
27PF
NP0-C0G01005
5%16V
27PF
NP0-C0G01005
5%16V
RES,MF,1/10W,0OHM,5,0603,SMD,LF FL3740,FL3741,FL3750,FL37514113S0022 ? ?
RES,MF,1/20W,0.0OHM,5,0201,SMD R3742,R3743,R3752,R37534117S0002 ? ?
AUDIO: SPEAKER AMPSYNC_DATE=N/ASYNC_MASTER=N/A
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM
SPKR_R_N
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM
SPKR_L_N
SPKR_L_FLR
MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM
GPIO_SPKAMP_KEEPALIVE
=PPVCC_MAIN_AUDIO
GPIO_SPKAMP_LEFT_IRQ_L
SPKR_L_VSENSE_N_FILTI2C0_SCL_1V8
SPK_ID
=PP1V7_VA_VCP
GPIO_SPKAMP_RIGHT_IRQ_L
GPIO_SPKAMP_RST_L
I2C0_SDA_1V8
L19_R_VBOOST=PPVCC_MAIN_AUDIO
I2S1_SPKAMP_BCLK
I2S1_SPKAMP_MCK_R
GPIO_SPKAMP_RST_L
SPKR_L_CONN_N
SPKR_L_VSENSE_N
SPKR_R_VSENSE_P_FILTSPKR_R_VSENSE_N_FILT
SPKR_L_VSENSE_P
SPKR_R_VSENSE_N
SPKR_R_VSENSE_PSPKR_R_SES_PSPKR_R_SES_N
SPKR_R_FLR
MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM
SPKR_R_P
SPKR_R_CONN_P
SPKR_L_CONN_P
SPKR_R_CONN_N
SPKR_R_VSENSE_N
L19_L_SWITCH
I2C0_SDA_1V8
L19_R_SWITCH
I2S1_SPKAMP_DOUT
I2S1_SPKAMP_LRCK
I2S1_SPKAMP_BCLK
I2S1_SPKAMP_MCK_R
GPIO_SPKAMP_KEEPALIVE
SPKR_L_VSENSE_P
SPKR_L_VSENSE_N
SPKR_R_VSENSE_P
L19_L_FILT
I2C0_SCL_1V8
SPKR_R_CONN_N
SPKR_R_CONN_P
PP1V7_VA_VCP
L19_L_IREF
L19_L_LDO_FILT
I2S1_SPKAMP_DIN
I2S1_SPKAMP_LRCK
L19_R_LDO_FILTL19_R_FILT
I2S1_SPKAMP_DIN
L19_R_IREF
L19_L_VBOOST
I2S1_SPKAMP_DOUT
SPKR_L_SES_PSPKR_L_SES_N
=PP1V7_VA_VCP
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM
SPKR_L_P
SPKR_L_CONN_P
SPKR_L_CONN_N
SPKR_L_VSENSE_P_FILT
C3747
1 2
C3748
1 2
C3760
1 2
C37461
2
FL3741
1 2
FL3740
1 2
R37401 2
R37431
2
R37411
2
C3757
1 2
C37561
2
FL3751
1 2
FL3750
1 2
C3758
1 2
R37501 2
R37511
2
U3740
C7
D7
F2
B5
B6
C6
E4
F3
F4
A3
B3
B4
C3
C4
D3
D4
A7
B7
F1
E1
C5
F6
E7
C2
D2
A6
D6
E6
D5
F7
E5
A2
B2
F5
A1
B1
C1
D1
A4
A5
E3
E2
C37451
2
C37441
2
C37431
2
C37421
2
C37411
2
U3750
C7
D7
F2
B5
B6
C6
E4
F3
F4A3
B3
B4
C3
C4
D3
D4
A7
B7
F1
E1
C5
F6
E7
C2
D2
A6
D6
E6
D5
F7
E5
A2
B2
F5
A1
B1
C1
D1
A4
A5
E3
E2
C37551
2
C37541
2
C37531
2
C37521
2
C37511
2
C37721
2
C3773 1
2
C3771 1
2
C37701
2
XW3774
1 2
XW3775
1 2
XW3776
1 2
XW3777
1 2
J3700
7
8
1
2
3
4
5
6
C37101
2
C37201
2
C37211
2
C37111
2
L3750
1 2
L3740
1 2
C37841
2
C37491
2
C37591
2
C37861
2
C37631
2
C37401
2
C37611
2
C37811
2
C37501
2
C37831
2
R37421
2
R37521
2
R37531
2
C3780
1 2
R37441 2
R37551 2
R37541 2
C3768 1
2
C3787 1
2
C3788 1
2
C3767 1
2
R37451 2
C37661
2C37641
2
C37121
2
C37221
2
C37231
2
C37131
2
051-9385
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19 OF 39
37
37
37
5 19
18 19
34
5
37
5 19 25 30 36
18 19 34
5
5 19
5 19 25 30 36
18 19
34
5 19
5 19
5 19
19 37
19 37
37
37
19 37
19 37
19 37
37
37
37
37
19 37
19 37
19 37
19 37
5 19 25 30 36
5 19
5 19
5 19
5 19
5 19
19 37
19 37
19 37
5 19 25 30 36
19 37
19 37
29 34 39
5 19
5 19
5 19
5 19
37
37
18 19 34
37
19 37
19 37
37
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
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B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
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D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
APN: 518S0828
APN: 518S0828
F-RT-SM502250-8037-B
CRITICAL
F-RT-SM
CRITICAL
502250-8037-B
SENSOR FLEX CONNSYNC_DATE=N/ASYNC_MASTER=N/A
CONN_ACCEL_IRQ1_LCONN_HP_HEADSET_DETCONN_HP_RIGHT_FILT1CONN_HP_HS3_REF_MIC2CONN_HP_HS4_REF_MIC1
MIPI1C_CAM_FF_CLK_F_N
CONN_HP_HS4_FILT1
CONN_PROX_IRQ_L
PP2V8_CAM_FLT
MIPI0C_CAM_RF_DATA_F_N<0>
CONN_I2C2_SCL_3V0CONN_ISP0_CAM_RF_SHUTDOWN
CONN_ISP0_CAM_RF_RST_L
CONN_I2C1_SDA_1V8
MIPI1C_CAM_FF_CLK_F_P
CONN_GYRO_IRQ2
CONN_GYRO_IRQ1CONN_HP_LEFT_FILT1
CONN_DMIC1_FF_SCLK
CONN_ALS_IRQ_L
CONN_ISP0_CAM_RF_I2C_SDA
CONN_ISP1_CAM_FF_I2C_SCL
MIPI1C_CAM_FF_DATA_F_N<0>
CONN_I2C1_SCL_1V8
CONN_I2C2_SDA_3V0
CONN_DMIC1_FF_SDCONN_ISP0_CAM_RF_I2C_SCLCONN_HALL_IRQ
PP3V0_S2R_HALL_FLT
PP3V0_SENSOR_FLTPP1V8_SENSOR_FLT
CONN_ISP0_CAM_RF_CLK
MIPI0C_CAM_RF_DATA_F_P<0>MIPI0C_CAM_RF_DATA_F_N<1>
MIPI0C_CAM_RF_DATA_F_P<1>
CONN_ISP1_CAM_FF_SHUTDOWN_L
CONN_ISP1_CAM_FF_I2C_SDACONN_ISP1_CAM_FF_CLK
MIPI0C_CAM_RF_CLK_F_NMIPI0C_CAM_RF_CLK_F_P
MIPI1C_CAM_FF_DATA_F_P<0>
GPIO_BTN_SRL_LGPIO_BTN_ONOFF_L
GPIO_BTN_VOL_UP_LGPIO_BTN_VOL_DOWN_L
CONN_ACCEL_IRQ2_L
CONN_HP_HS3_FILT1
J5400
1
1011
1213
1415
1617
1819
2
2021
2223
2425
2627
2829
3
3031
3233
3435
3637
38
39
4
40
41
56
78
9
J5401
1
1011
1213
1415
1617
1819
2
2021
2223
2425
2627
2829
3
3031
3233
3435
3637
38
39
4
40
41
56
78
9
54 OF 154
A.0.0
051-9385
20 OF 39
22
18
22
22
22
21 37
22
22
21
21 37
22 36
22
22
22 36
21 37
22
22
22
22
22
22 36
22 36
21 37
22 36
22 36
22
22 36
22 21
5 21
21
22 36
21 37
21 37 21 37
22
22 36
22 36
21 37 21 37
21 37
5 30 5 30
5 5
22
22
SYM_VER-1
SYM_VER-1
SYM_VER-1
BI
BI
BI
BI
BI
IN
IN
BI
BI
IN
IN
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
SYM_VER-1
SYM_VER-1
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
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D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
DCR 0.31
DCR 0.31
DCR 0.31
90-OHM-50MATCM0605-1
CRITICAL
TCM0605-190-OHM-50MA
CRITICAL
TCM0605-190-OHM-50MA
CRITICAL
0201
25VCER
+/-0.1PF%8.2PF
0201
25VCER
+/-0.1PF%8.2PF
0201
25VCER
+/-0.1PF%8.2PF
0201
25V+/-0.1PF%
CER
8.2PF
5%
MF1/20W
0
201
NOSTUFF
7 37
7 37
7 37
20 37
7 37
7 37
7 37
7 37
7 37
7 37
7 37
20 37
20 37
20 37
20 37
20 37
20 37
20 37
20 37
20 37
5%
0
1/20WMF201
NOSTUFF
5%
MF1/20W
0
201
NOSTUFF
5%
MF1/20W
0
201
NOSTUFF
5%
MF1/20W
0
201
NOSTUFF
5%
MF1/20W
0
201
NOSTUFF
5%
0
1/20WMF201
NOSTUFF
5%
0
1/20WMF201
NOSTUFF
5%
0
1/20WMF201
NOSTUFF
5%
NOSTUFF
201MF
1/20W
0
0201X7R-CERM
1000PF10%16V
1UF
402
10VX5R10%5%
82PF
0201NP0-C0G-CERM25V
0201X7R-CERM
1000PF10%16V
0201X7R-CERM
1000PF10%16V
0201X7R-CERM
1000PF10%16V
1UF
402
10VX5R10%5%
82PF
0201NP0-C0G-CERM25V
402
1UF10VX5R10%5%
82PF
0201NP0-C0G-CERM25V
6.3V0.1UF
X5R201
10%
402
1UF10VX5R
10%5%82PF
0201NP0-C0G-CERM25V
0201
240-OHM-0.2A-0.8-OHM
0402
240-OHM-25%-400MA
240-OHM-25%-400MA
0402
0402
240-OHM-25%-400MA
TCM0605-190-OHM-50MA
CRITICAL
TCM0605-190-OHM-50MA
CRITICAL
SENSOR CONN FILTERS 1SYNC_DATE=N/ASYNC_MASTER=N/A
MIPI0C_CAM_RF_DATA_P<1>
MIPI0C_CAM_RF_DATA_N<1>
MIPI0C_CAM_RF_DATA_F_P<1>
MIPI0C_CAM_RF_DATA_F_N<1>
MIPI0C_CAM_RF_DATA_P<0>
MIPI0C_CAM_RF_DATA_N<0>
MIPI0C_CAM_RF_DATA_F_P<0>
MIPI0C_CAM_RF_DATA_F_N<0>
MIPI0C_CAM_RF_CLK_P
MIPI0C_CAM_RF_CLK_N
MIPI0C_CAM_RF_CLK_F_P
MIPI0C_CAM_RF_CLK_F_N
MIPI1C_CAM_FF_CLK_N
MIPI1C_CAM_FF_CLK_P
MIPI1C_CAM_FF_CLK_F_N
MIPI1C_CAM_FF_CLK_F_P
MIPI1C_CAM_FF_DATA_F_P<0>MIPI1C_CAM_FF_DATA_P<0>
MIPI1C_CAM_FF_DATA_F_N<0>MIPI1C_CAM_FF_DATA_N<0>
VOLTAGE=3.0V
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM
PP3V0_SENSOR_FLT
PP1V8_SENSOR_FLT
MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.8V
MIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
=PP3V0_SENSOR
=PP3V0_S2R_HALL
=PP1V8_SENSOR
=PP2V8_CAM
PP3V0_S2R_HALL_FLT
VOLTAGE=3.0V
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
VOLTAGE=2.8V
PP2V8_CAM_FLT
C55521
2
C55511
2
C55501
2
C55831
2
C55621
2
C55721
2
C55611
2
C55601
2
C55711
2
C55701
2
C55821
2
C55811
2
C55801
2
L5550
1 2
L5560
1 2
L5570
1 2
L5580
1 2
L5500
1
2 3
4
L5510
1
2 3
4
L5530
1
2 3
4
L5540
1
2 3
4
L5520
1
2 3
4
C55531
2
C55631
2
C55731
2
C55841
2
R55411 2
R55401 2
R55311 2
R55211 2
R55111 2
R55011 2
R55301 2
R55201 2
R55101 2
R55001 2
051-9385
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55 OF 154
21 OF 39
5 20
20
34
23 34
34
34
20
20
IN1
IN2
IN4
IN3
OUT1
OUT2
OUT3
OUT4
GND
IN
IN1
IN2
IN4
IN3
OUT1
OUT2
OUT3
OUT4
GND
IN1
IN2
IN4
IN3
OUT1
OUT2
OUT3
OUT4
GND
IN
BI
OUT
OUT
OUT
IN
IN
BI
IN
OUT
OUT
BI
OUT
IN
BI
OUT
BI
IN
BI
NCNC
IN
OUT
IN
OUT
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
BI
IN
IN
NCNC
IN1
IN2
IN4
IN3
OUT1
OUT2
OUT3
OUT4
GND
OUT
OUT
OUTIN1
IN2
IN4
IN3
OUT1
OUT2
OUT3
OUT4
GND
OUT
IN
IN
IN1
IN2
IN4
IN3
OUT1
OUT2
OUT3
OUT4
GND
OUT
IN
NC
IN
NC NC
NC
IN
IN
OUT
IN IN1
IN2
IN4
IN3
OUT1
OUT2
OUT3
OUT4
GND
IN1
IN2
IN4
IN3
OUT1
OUT2
OUT3
OUT4
GND
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
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D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
AND RECHARACTERIZATION
PLACE IT NEAR U0600
PLACE IT NEAR U0600
22 OHM
22 OHM
DO NOT STUFF WITHOUTAUDIO TEM APPROVAL
800MHZ-100MA-27PF0603
22
5%
402
1/16WMF-LF
16V10%1000PF
0201X7R-CERM
NOSTUFFMF-LF
22
1/16W5%
402
7 36
800MHZ-100MA-27PF0603
0603800MHZ-100MA-27PF
20
20 36
20
20 36
30
7
7 36
7 36
20
20 36
20 36
20 36
5
5 36
5 36
20 36
20 36
5 36
5 36
20
20
20
20
18
18
7
5
20
20
20
20
5
5
5
5
20 36
20
20 36
20 36
7 36
7 36
7 0603-1
CRITICAL
800MHZ-100MA-27PF
18
18
18
0603-1
CRITICAL
800MHZ-100MA-27PF
18
18
18
0603800MHZ-100MA-27PF
20
20
20
20
20
20
NOSTUFF
25V5%NP0-C0G
27PF
0201
22
5%
402
1/16WMF-LF
16V10%1000PF
0201X7R-CERM
NOSTUFF402
1/16W
22
MF-LF
5%
7 36
800MHZ-100MA-27PF0603
800MHZ-100MA-27PF0603
SENSOR CONN FILTERS 2SYNC_DATE=N/ASYNC_MASTER=N/A
U5600,U5610,U5620,U5630,U5640,U5650,U5660,U5670155S0373 RADAR:8376668155S0643 ?
HP_HS4_REF_FILTHP_HS3_REF_FILT
HP_HS4_FILTHP_HS3_FILT
CONN_I2C2_SDA_3V0ISP1_CAM_FF_SHUTDOWN_L
ISP0_CAM_RF_I2C_SDA
CONN_HP_HS4_REF_MIC1CONN_HP_HS3_REF_MIC2
I2C1_SCL_1V8DMIC1_FF_SD
I2C2_SDA_3V0
CONN_I2C1_SCL_1V8
CONN_ISP1_CAM_FF_SHUTDOWN_L
CONN_ALS_IRQ_LCONN_I2C1_SDA_1V8
CONN_ISP0_CAM_RF_SHUTDOWN
CONN_ISP0_CAM_RF_I2C_SDACONN_ISP0_CAM_RF_RST_LCONN_ISP0_CAM_RF_I2C_SCL
CONN_HALL_IRQ
CONN_PROX_IRQ_LCONN_ISP1_CAM_FF_I2C_SDACONN_ISP1_CAM_FF_CLK
GPIO_ALS_IRQ_LI2C1_SDA_1V8
I2C2_SCL_3V0ISP0_CAM_RF_SHUTDOWN
DMIC1_FF_SCLK
ISP0_CAM_RF_RST_LISP0_CAM_RF_I2C_SCL
PMU_GPIO_HALL_IRQ
ISP0_CAM_RF_C ISP0_CAM_RF_FILT
GPIO_PROX_IRQ_LISP1_CAM_FF_I2C_SCL
ISP1_CAM_FF_I2C_SDAISP1_CAM_FF_FILT
ISP0_CAM_RF_CLK
ISP1_CAM_FF_CLK
GPIO_ACCEL_IRQ2_L
GPIO_ACCEL_IRQ1_LGPIO_GYRO_IRQ2
GPIO_GYRO_IRQ1
CONN_ACCEL_IRQ1_LCONN_GYRO_IRQ2CONN_ACCEL_IRQ2_LCONN_GYRO_IRQ1
ISP1_CAM_FF_C
CONN_I2C2_SCL_3V0
CONN_ISP0_CAM_RF_CLK
CONN_HP_RIGHT_FILT1 HP_RIGHT_FILT
HP_LEFT_FILT
CONN_HP_HS4_FILT1CONN_HP_HS3_FILT1CONN_HP_LEFT_FILT1
CONN_ISP1_CAM_FF_I2C_SCL
CONN_DMIC1_FF_SD
CONN_DMIC1_FF_SCLK
U56409
10
1
2
3
4
5
6
7
8
U5620
9
10
1
2
3
4
5
6
7
8
R56311 2
C56301
2
R56301 2
U5630
9
10
1
2
3
4
5
6
7
8
U5650
9
10
1
2
3
4
5
6
7
8
U5610
9
10
1
2
3
4
5
6
7
8
R56411 2
C56401
2
R56401 2
U5600
9
10
1
2
3
4
5
6
7
8
U5660
9
10
1
2
3
4
5
6
7
8
U5670
9
10
1
2
3
4
5
6
7
8
C56201
2
56 OF 154
A.0.0
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36 36
36 36
OUTIN
OUTIN
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
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A
NOTICE OF PROPRIETARY PROPERTY:
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D
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
USED TO BE C5733 8.2PF CAP
SIGNAL FROM FLOATING
SIGNAL FROM FLOATING
USING PADS TO KEEP THIS UNUSED
USING PADS TO KEEP THIS UNUSED
WHEN HALL2 WAS USED
WHEN HALL2 WAS USEDUSED TO BE C5741 27PF CAPUSED TO BE C5740 27PF CAP
WHEN HALL2 WAS USED
SIGNAL FROM FLOATINGUSING PADS TO KEEP THIS UNUSED
0.055 OHM DCR
0.055 OHM DCR
50V10%
402X7R
0.01UF5%
0201
25VNP0-C0G
27PF040227V-100PF
0603
FERR-70-OHM-4A
5%100K
MF201
1/20W16V+/-0.5PF
01005NP0-C0G-CERM
8.2PF5%
0201
25V27PF
NP0-C0G
0201
FERR-22-OHM-1A-0.065-OHM
0201
FERR-22-OHM-1A-0.065-OHM
0201-114.2V-6PF
0201-114.2V-6PF
5 30
25V
0201CER
8.2PF+/-0.1PF%
0201
120-OHM-200MA
25V
0201CER
8.2PF+/-0.1PF%0201
6.8V-100PF
24
201
05%1/20WMF0201
X7R-CERM
NOSTUFF
16V10%1000PF
NOSTUFF
10V10%
402X5R
1UF5%82PF
0201NP0-C0G-CERM25V
NOSTUFF0201
NOSTUFF
240-OHM-0.2A-0.8-OHM
30
201
01/20WMF
5%
0201
NOSTUFF
120-OHM-200MA
201
05%1/20WMF0201
NOSTUFF
6.8V-100PF
24
RDAR://PROBLEM/9625601155S0320 L5700,L5701155S0513
377S0116 377S0108 RDAR://PROBLEM/8370432DZ5760
155S0657 FL5710,FL5750155S0537
L5757155S0397155S0741 RDAR://PROBLEM/11238851
E75 DOCK SUPPORTSYNC_DATE=N/ASYNC_MASTER=N/A
MAX_NECK_LENGTH=3 MM
VOLTAGE=3.0VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWR
PP3V0_S2R_HALL2_FLT
CONN_HALL2_IRQ
=PP3V0_S2R_HALL
MIN_NECK_WIDTH=0.2MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
VOLTAGE=6.0VMIN_LINE_WIDTH=0.6MM
CONN_E75_PPVBUS_USB
E75_ACC_POUT_ID1
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.6MMVOLTAGE=3.3V
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.2MM
CONN_E75_ACC_POUT_ID2E75_ACC_POUT_ID2
PPVBUS_USB_EMI
DISCRETE_BTN_HOME_L GPIO_BTN_HOME_L
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMVOLTAGE=3.3V
MAX_NECK_LENGTH=3 MM
CONN_E75_ACC_POUT_ID1
PMU_GPIO_HALL2_IRQ
C57831
2
C57501
2
DZ5760
1
2
L5757
1 2
R57901
2
C57221
2
C57211
2
L5700
1 2
L5701
1 2
DZ5792
A
C
DZ5791
A
C
C57111
2
FL5710
1 2
C57101
2
DZ5710
1
2
C57331
2
C57321
2
C57311
2
C57301
2
L5730
1 2
R57411
2
FL5740
1 2
C57401
2
DZ5740
1
2
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23 OF 39
24 21 34
24
25
24 25
34 39
24
NCBI
BI
BI
BI
OUT
NC
OUT
NC
OUT
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
PN 516S0542 (PLUG - MALE)
IO FLEX CONNECTOR
518S0692
.
16V+/-0.5PF
01005NP0-C0G-CERM
8.2PF
16V+/-0.5PF
01005NP0-C0G-CERM
8.2PF
16V+/-0.5PF
01005NP0-C0G-CERM
8.2PF
CRITICAL
M-ST-SMCPB6450-0101F
25 36
25 36
25 36
25 36
25
23
CRITICAL
F-RT-SMFF18-6A-R11AD-B-3H
23
SYNC_MASTER=N/A SYNC_DATE=N/A
IO FLEX CONN
PP3V0_S2R_HALL2_FLT
CONN_E75_ACC_POUT_ID1
CONN_E75_ACC_POUT_ID2
CONN_E75_PPVBUS_USBCONN_E75_PPVBUS_USB
CONN_E75_DPAIR1_PCONN_E75_DPAIR1_N
CONN_E75_DPAIR2_NCONN_E75_DPAIR2_P
CONN_E75_ACC_DET_L
DISCRETE_BTN_HOME_LCONN_HALL2_IRQ
C59001
2
C59101
2
C59201
2
J5900
51
52
53
54
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
35 36
37 38
39
4
40
41 42
43 44
45 46
47 48
49
5
50
6
7 8
9
J5950
1
2
3
4
5
6
051-9385
A.0.0
58 OF 154
24 OF 39
23
23
23
23 24 23 24
BI
BI
BI
VCC
GND
SELOE*
D+
D-
Y+
Y-
M+
M- BI
BIBI
BI
IN
SYM_VER-1
OUT
IN
OUT
NC
BYPASS
SCL
INT
SDA
SWITCH_EN
HOST_RESET
OVP_SW_EN*
CON_DET_L
DN2
DP2
DN1
DP1
ACC2
ACC1
P_IN
VDD_1V8
VDD_3V0
ACC_PWR
JTAG_DIO
UART2_RX
JTAG_CLK
UART1_RX
UART2_TX
UART0_RX
UART1_TX
USB0_DN
UART0_TX
BRICK_ID
USB0_DP
USB1_DN
USB1_DP
DIG_DN
DVSS
DVSS
DVSS
DIG_DP
SYM_VER-1
OUT
BI
BI
IN
OUT
IN
IN
BI
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_5_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
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12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_ALT_ITEM
BB DEBUG UART(T’S OFF TO H5G UART1)
ACCESSORY USB
BASEBAND USB MUX BYPASS
TRISTAR BASEBAND USB MUX(NEEDED FOR MDM9600 BB)
DEFAULT =>
SEL
0
1
M+
Y+
D+
Y-
M-
D-
NOTE: ISOLATE SELECT SIGNAL FROMPMU ON MLB_B AND MLB_C SO THE MUXIS PERMANENTLY POINTED TO THE DOCK
ACCESSORY UART
AP DEBUG UART
PLACE NEAR U5900
TO BB USB
24 36
24 36
24 36
8.2PF
NP0-C0G-CERM01005
+/-0.5PF16V
DSF01S30SCSM-201
CRITICAL
8.2PF
NP0-C0G-CERM01005
+/-0.5PF16V
TQFNPI3USB102ZLE
MLB_D&MLB_E
0.1UF
X5R201
10%6.3V
MLB_D&MLB_E
10K
MF201
5%1/20W
MLB_D&MLB_E
1/20W5%
201MF
10K
MLB_D&MLB_E
25 26 36
25 26 36 4 36
4 36
30
1/32W0%
01005MF
0.00
MLB_D&MLB_E
201
0
1/20WMF
5%
MLB_B&MLB_C
201
0
1/20WMF
5%
MLB_B&MLB_C
1/20W5%
201MF
100K
MLB_A
1/20W5%
201MF
100K
MLB_A
90-OHM-50MATCM0605-1
CRITICAL
29
4 26 30 39
25
1.0UF
X5R0201-MUR
20%6.3V
0.00
MF01005
0%1/32W
MF
0.00
01005
0%1/32W
220K
MF
01005
5%1/32W
220K
MF
01005
5%1/32W
74LVC1G32SOT891
0.1UF
X5R201
10%6.3V
0.1UF
X5R201
10%6.3V
0.1UF
X5R201
10%6.3V
THS7383IYKARWCSP
OMIT_TABLE
1UF
X5R0402
10%25V
90-OHM-50MATCM0605-1
CRITICAL
0201-MUR
1.0UF
X5R20%6.3V
0.1UF
X5R201
10%6.3V
01005
120-OHM-210MA
16V+/-0.5PF
01005NP0-C0G-CERM
8.2PF
ESD0P2RF-02LSTSSLP-2-1
CRITICAL
ESD0P2RF-02LSTSSLP-2-1
CRITICAL
ESD0P2RF-02LSTSSLP-2-1
CRITICAL
ESD0P2RF-02LSTSSLP-2-1
CRITICAL
0.00
MF01005
0%1/32W
18
ESD0P2RF-02LSTSSLP-2-1
CRITICAL
0.00
MF01005
0%1/32W
22
MF01005
5%1/32W
8.2PF
NP0-C0G-CERM01005
+/-0.5PF16V
8.2PF
NP0-C0G-CERM01005
+/-0.5PF16V
8.2PF
NP0-C0G-CERM01005
+/-0.5PF16V
8.2PF
NP0-C0G-CERM01005
+/-0.5PF16V
4 36
4 36
10K
MF01005
5%1/32W
100K
MF01005
5%1/32W
24
30
25
4
24 36
343S0614 IC,ASIC,TRISTAR,CBTL1608,A1,WLCSP36 CRITICALU59001
SYNC_MASTER=N/A
TRISTARSYNC_DATE=N/A
FL5990155S0773 155S0453 ? RDAR://PROBLEM/10882925
CONN_E75_DPAIR2_P
UART1_BB_TXDUART1_BB_RXD
JTAG_AP_TCK_TS_R
JTAG_AP_TCK
JTAG_AP_TMS_TS_R
JTAG_AP_TMS
UART2_TS_ACC_TXD
USB_AP_NUSB_AP_P
USB_BRICKID
USB_TS_BBMUX_NUSB_TS_BBMUX_P
UART6_AP_TXDUART6_AP_RXD
UART2_TS_ACC_RXD
USB_BBMUX_BB_PUSB_TS_BBMUX_P
USB_BBMUX_BB_NUSB_TS_BBMUX_N
USB_TS_BBMUX_NUSB_TS_BBMUX_P
USB_BBMUX_BB_NUSB_BBMUX_BB_P
USB11_AP_BBMUX_NUSB11_AP_BBMUX_P
TS_BBMUX_EN_L PMU_GPIO_BBUSBTODOCK_ENPMU_GPIO_BBUSBTODOCK_EN_R
=PP3V2_S2R_USBMUX
CONN_E75_DPAIR2_N
OVP_SW_EN_L
RST_AP_LTS_HOST_RESET
L81_MBUS_REF
CONN_E75_ACC_DET_L
PMU_RESET_INTS_HOST_RESET
AP_WDOG_RESET_INPMU_RESET_IN_R
TS_HOST_RESET_R
=PP1V8_S2R_USBMUX
MIKEY_TS_PMIKEY_TS_N E75_ACC_POUT_ID1
E75_ACC_POUT_ID2
I2C0_SDA_1V8
PMU_GPIO_TS_INTI2C0_SCL_1V8
PMU_E75_ACC_DET_R_L
=PP1V8_S2R_USBMUX
PMU_E75_ACC_DET_L
BYPASS_U5900
PPVCC_MAIN
PPVBUS_PROT
TS_E75_DPAIR2_N
TS_E75_DPAIR1_PTS_E75_DPAIR1_N
TS_E75_DPAIR2_P
=PP3V0_S2R_TRISTAR TRISTAR=PP3V3_ACC
CONN_E75_DPAIR1_P
CONN_E75_DPAIR1_N
L5931
1
2 3
4
C59331
2
R59301 2
R59311 2
R593212
R593312
U5903
2
1
3
6
4
C59321
2
C59351
2
C59311
2
U5900
C5
E5
D5
C2
E6
E3
C4
C3
B2
B4
A2
A4
A6
C1
F5
B6
C6A5
B5
D6
F6
D4
D3
E4
E1
E2
F1
F2
D1
D2
B3
A3
B1
A1
F3
F4
C59341
2
L5930
1
2 3
4
C59301
2
C59361
2
FL5990
1 2
C59901
2
DZ5900
1
2DZ5901
1
2
DZ5903
1
2DZ5902
1
2
R59291 2
DZ5990
1
2
R59341 2
R59351 2
C59401
2
C59421
2C59411
2
C59431
2
R59901 2
R59911
2
C59911
2
D5990
A
K
C59441
2
U5902
6
7
3
4
5
8 10
9
2
1
C59601
2
R59611
2
R59601
2
R59621 2
R59651 2
R59661 2
R59711
2
R59701
2
051-9385
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25 OF 39
5
5 26 36
5 26 36
4 36
4 36
5 36
10
25 36
25 36
5 36
5 36
5 36
25 26 36 25 36
25 26 36 25 36
25 36
25 36
34
25 34
18 37
18 37 23
23
5 19 30 36
5 30
5 19 30 36
25 34
30
15 29 30 34 39
29
36
36
36
36
34
34
BI
BI
BI
BI
BI
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
IN
IN
IN
IN
OUT
IN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
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B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
DEBUG
998-3732
.
CELLULAR/GPS HOTBAR PADS
25 36
25 36
5
4 26 36
4 26 36
5
4 25 30 39
30
5
5 39
5
5 36
5 36
5
5
30
30
5 25 36
5 25 36
5 36
5 36
HOT-BAR-PADSHB-SM
OMIT
MM4829-2702F-ST-SM
NOSTUFF
MM4829-2702F-ST-SM
NOSTUFF
27
5
5
5
5
5 36
SYNC_DATE=N/ASYNC_MASTER=N/A
CONNECTOR: CELLULAR
=BATT_POS_F_3G
HSIC3_BB_STB
HSIC3_BB_DATA
USB_BBMUX_BB_PUSB_BBMUX_BB_N
GPIO_AP_MODEM_WAKE
HSIC3_BB_STB
HSIC3_BB_DATA
GPIO_BB_RADIO_ON_LRST_AP_L
PMU_GPIO_BB_PMU_RST_LGPIO_BB_GSM_TXBURSTGPIO_BB_RST_LGPIO_BB_RESET_DET_L
GPIO_BB_HSIC_HOST_RDYGPIO_BB_HSIC_RESUME
BB_JTAG_TDI_RF
GPIO_BB_GPS_SYNCPMU_GPIO_BB_HOST_WAKE
BB_VBUS_DET
UART1_BB_RXDUART1_BB_TXDUART1_BB_CTS_LUART1_BB_RTS_L
WLAN_TX_BLANK
BB_JTAG_TMS_RF
BB_JTAG_TRST_RF_L
BB_JTAG_TDO_RF
BB_JTAG_TCK_RF
GPIO_BB_HSIC_DEV_RDY
J6000
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
42
5
6
7
8
9
J6050
234
1
J6051
234
1
051-9385
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26 OF 39
34
4 26 36
4 26 36
IN
OUTYA
B
NCGND
VCC
IN
IN
IN
OUT
IN
BI
BI
OUT
IN
OUT
IN
IN
IN
OUT
OUT
IN
PP
PP
PP
PP
PP
PP
PP
OUT
OUT
RF_SW_CTRL_3
WLAN_HSIC_STROBE
WLAN_HSIC_DATA
SR_VLX
JTAG_SEL
BT_REG_ON
VIN_1P2LDO
CLK32K_AP
GPIO_6
VDDIO_1P8V
WL_REG_ON
BATT_VCC
VBATT_RF_VCC
VBATT_RF_VCC
2G_ANT
5G_ANT
HOST_WAKE_BT
BT_WAKE
BT_UART_RXD
BT_UART_RTS*
BT_UART_TXD
BT_UART_CTS*
BT_PCM_CLK
BT_PCM_SYNC
BT_PCM_OUT
BT_PCM_IN
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_12
THRML_PADGND
NC
NC
OUT
GND
INHI
LO
COM
GND
PP
PP
PP
PP
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
CHANGE LIST07FEB2012 MUSHTAQ COPIED FROM N41, ADDED J2 ANT MATCH/CONN C6107 FROM 20PF TO 8.2PF, C6108 FROM 10PF TO 4.7PF U6104 FROM SOSHIN TO MURATA LFD212G45DS5D355
13FEB2012 AMANDA CHANGED OMIT TO OMIT_TABLE AND UPDATED BOM OPTION TABLES TO ALTERNATE TABLES
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN
WLAN/BT
PULL DOWN RESISTORS
GPIO6 SDIO_DATA<1> SDIO_DATA<2> MODE DEFAULT ARM STATE
1 0 1 HSIC OUT OF RESET
NO LONGER NEEDED BASED
0 X X SDIO IN RESET
1 1 1 BOOTLESS HSIC IN RESET
1 X 0 GSPI IN RESET
CONDUCTED TEST PORT
32K INTERFACE TO AP
ON AND GATE REMOVAL
REMOVED BOM TABLE FOR C6111_RF (NOW ALWAYS NOSTUFF)
ANTENNA CONNECTOR
6.3V20%
0201X5R
0.22UF
1/32W5%
01005MF
10K
1/32W1%
01005MF
1.00M
14 27
26
SOT89174AUP1G08GF
14 27
SHORT-01005
6.3V20%
402X5R-CERM1
4.7UF
CRITICAL
0603
2.5UH-30%-0.7A-0.24OHM
14
14 27
1/32W5%
01005MF
10K
SHORT-0402
6.3V20%
0402-1CERM-X5R
10UF16V5%
01005NP0-C0G
27PF
1/32W5%
01005MF
10K
14
14
14
14
14
14
14
14
14 27
14
14
14 27
6.3V10%
01005X5R
0.01UF16V5%
01005NP0-C0G
27PF1/32W0%
01005MF
0.00
NOSTUFF
1/32W5%
01005MF
10K
1/32W5%
01005MF
10K
14 27
SMP4MM
P4MM SM
SMP4MM
SMP4MM
SMP4MM
SMP4MM
P4MM SM
14 27
27
OMIT_TABLE
LGALBEE5ZHTWC501
NOSTUFF
25V+/-0.1PF
201COG-CERM
0.2PF
1/32W0%
01005MF
0.00
+/-0.25PF%
8.2PF
NP0-C0G0201
25V
CRITICAL
NOSTUFF
02015.6NH-3%-0.35A
NOSTUFF
02015.6NH-3%-0.35A
MM8030-2600RK0
CRITICAL
F-ST-SM
CRITICAL
0402
50VNP0-CERM
0.2PF+/-0.05PF
04025.6NH+/-0.3NH
NOSTUFF
CRITICAL
F-ST-SMMM4829-2702
CRITICAL
25V+/-0.1PF
0201COG-CERM
4.7PF
8.2PF
NP0-C0G0201
+/-0.25PF%25V
CRITICAL
SMDPX205850DT-9038A1SJ
CRITICAL
P4MM SM
P4MM SM
P4MM SM
P4MM SM
CRITICAL
3.9PF
NP0-CERM50V
+/-0.1PF
0402
1 U6101_RFWIFI MODULE - MURATA339S0171 CRITICAL
WIFI MODULE - USIU6101_RF339S0171339S0175
311S0548 311S0398 U6102_RF
WIFI/BTSYNC_DATE=N/ASYNC_MASTER=N/A
AGG_CHANNEL
AP_HSIC3_RDYWLAN_HSIC3_RESUME
WLAN_REG_ON_RC
HSIC_DEVICE_RDY
PP_WL_BT_VDDIO_AP
WLAN_REG_ON
50_HSIC_WLAN_STROBE50_HSIC_WLAN_DATA
WLAN_BUCK_OUT
WLAN_SR_VLX1
WLAN_TX_BLANK
BT_REG_ON
WLAN_REG_ON
=BATT_VCC
BT_PCM_OUTBT_PCM_IN
BT_PCM_SYNCBT_PCM_CLK
BT_UART_RTS_LBT_UART_CTS_L
BT_UART_TXDBT_UART_RXD
BT_WAKE
HOST_WAKE_BT
WLAN_UART_RXDWLAN_UART_TXDHSIC_DEVICE_RDY
50_WLAN_A50_WLAN_G
AGG_CHANNEL
AGG_CHANNEL
GPIO_6
DEV_HSIC3_RDY
CLK32K_AP
PP_WLAN_VDDIO_1V8VOLTAGE=1.8V
WIFI_50S50_OHM
RF_CAL
BATT_VCC_WLAN
WLAN_CLK32K
JTAG_SEL
HOST_WAKE_WLAN
WLAN_REG_ON
HOST_WAKE_WLAN
AP_HSIC3_RDY
DEV_HSIC3_RDY
WLAN_UART_RXD
WLAN_UART_TXD
HSIC_DEVICE_RDY
50_HSIC_WLAN_STROBE
50_HSIC_WLAN_DATA
PP_WL_BT_VDDIO_APVOLTAGE=1.8V
RF_CAL_MATCHWIFI_50S50_OHM
50_WLAN_G_1
50_WLAN_A_DIPLX
50_OHMWIFI_50S
RF_ANT_MATCH1
50_OHMWIFI_50SRF_ANT
C6110_RF1
2
R6113_RF1
2
R6112_RF1 2
U6102_RF
2
1
36
4
XW6101_RF
1 2
C61091
2
L6111_RF
1 2
R6107_RF1
2
XW6102_RF
1 2
C6101_RF1
2
C6102_RF1
2
R6111_RF1
2
C6103_RF1
2
C6104_RF1
2
R6108_RF1 2
R6105_RF1
2
R6109_RF1
2
PP6101_RF1
PP6102_RF1
PP6103_RF1
PP6104_RF1
PP6105_RF1
PP6106_RF1
PP6107_RF1
U6101_RF
42
52
27
3
4
2
5
30
36
35
38
37
39
32
17
18
33
41
43
44
45
48
49
50
51
19
20
21
22 1
16
23
26
9
8
13
10
12
7
11
6
34
14
40
28
53
54
55
56
57
58
59
60
46
47
15
29
31
24
25
C6111_RF1
2
R6114_RF1 2
C6192_RF
1 2
L6192_RF
1
2
L6191_RF
1
2
J6191_RF
34
12
C6191_RF1
2
L6190_RF
1
2
J6190_RF
2 3 4
1
C6108_RF
1 2
C6107_RF
1 2
U6104_RF
5
246
1
3
PP6109_RF1
PP6110_RF1
PP6111_RF1
PP6112_RF1
C6193_RF1 2
051-9385
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27 OF 39
5
27
14
27
14 27
14 27
34
38
38
27
27
14 27
14
39
39
14 27
14 27
14 27
14 27
14 27
14 27
27
14 27
14 27
14 27
38
38
BI
BI
A
A
A
A
HDQ
THERM
PACK_NEG
PACK_POS
SENSE
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
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12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TABLE_ALT_ITEM
HAS TP7502
APN:516S0926
NOTE: REMOVED R7541NPO-C0G
33PF25V
0201
5%
X7R-CERM
1000PF10%16V
0201NPO-C0G
33PF25V
0201
5%
240-OHM-0.2A-0.8-OHM
02015 30
25VNP0-C0G-CERM0201
82PF5%
30
NOSTUFFTP-P55
NOSTUFFTP-P55
NOSTUFFTP-P55
NOSTUFFTP-P55
CRITICAL
BATT-J2F-RT-SMTH
0402C0G-CERM
33PF50V5%
0402C0G-CERM
4.7PF+/-0.1PF50V
SYNC_MASTER=MADHAVI SYNC_DATE=12/06/2011
POWER: BATTERY CONNECTOR
?155S0644 155S0274
FL7500,L3620,L5550,L5730
RDAR://PROBLEM/11282371
=BATT_POS_CONN
BATT_SNS
NET_SPACING_TYPE=ANLGMIN_LINE_WIDTH=0.25MMMIN_NECK_WIDTH=0.20MM
BATT_SWI_CONN
BATTERY_NTCNET_SPACING_TYPE=ANLG
UART5_BATTERY_TRXD
C75221
2
C75241
2
C75231
2
FL7500
1 2
C75251
2
TP75001
TP75011
TP75021
TP75031
J7500
1
2
3
4
5
6
7
8
C75261
2
C75271
2
051-9385
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34
29
S
D
GNCNC
VLDO6
VLDO5
VLDO4
VLDO3
VLDO2
VLDO1
BUCK5_FB
VLDO8
VLDO7
WDIG_SW
CPU1V8_SW
CPU1V8_SW
CPU1V2_SW
CPU1V2_SW
BUCK5_LX0
BUCK4_FB
VPUMP
VBUCK3
BUCK3_LX0
BUCK3_FB
BUCK2_LX3
BUCK2_LX2
BUCK2_LX1
BUCK2_LX0
BUCK2_FB
BUCK0C_LX0
BUCK0C_FB
BUCK0B_LX1
BUCK0B_LX0
BUCK0B_FB
BUCK0A_LX0
BUCK0A_FB
BUCK5_BYP
BUCK4_LX0
VBUCK4
ON_BUF
VLDO16
VLDO12
VLDO11
VLDO10
VLDO9
BUCK0A_LX1
CHG_LX
IBAT_S
IBAT
VBAT
ACT_DIO
VCENTER
VBUS
VBUS_OVP_OFF
VDD_BUCK0A
VDD_BUCK0B
VDD_BUCK0C
VDD_BUCK2_01
VDD_BUCK2_23
VDD_BUCK4
VDD_BUCK3
VDD_BUCK5
VCC_MAIN_S
VDD_LDO1_6
VDD_LDO3_5_8
VDD_LDO2
VDD_LDO4_7
VDD_LDO10
VDD_LDO9
VDD_LDO16
VDD_LDO11
VDD_LDO12
XTAL1
XTAL2
VCC_MAIN
SWITCH POWER
XTAL
BUCK
SYM 2 OF 3
USB/BAT
VCC-MAIN
LDO
LDO INPUT
S
G
D
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
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8 7 6 5 4 3
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B
A
NOTICE OF PROPRIETARY PROPERTY:
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12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
LAYOUT NOTE: PLACE
1 CAP PER PIN N5 N14
TOTAL CAPS = ~400UFVCC_MAIN BYPASS
AT EACH VDD INPUT
ADDITIONAL DISTRIBUTED12UF (NO DERATING)R
DSON=0.0136@VGS=-2.5V
VGS MAX
IMAX
RDS(ON)
CHANNEL
MOSFET
27 MOHM @-4.5V
FDMC6676BZ
P-TYPE
+/- 25V
6.9 A
ADDITIONAL DISTRIBUTED64UF (NO DERATING)
R3173- PLACE NEAR PMUID=12.0A
ADDITIONAL DISTRIBUTED
ADDITIONAL DISTRIBUTED98UF (NO DERATING)
ADDITIONAL DISTRIBUTED27UF (NO DERATING)
32UF (NO DERATING)
(RON=0.05 OHM MAX)
(5MA; 1.8V)
(650MA; 1.1V)
(200MA; 2.5-3.55V)
(250MA; 1.7-3.0V)
(300MA; 1.2-3.0V)
(150MA; 0.6-1.3V)
(15MA; 2.0-3.55V)
(50MA; 1.2-3.1V)
(150MA; 2.5-3.6V)
(50MA; 2.5-3.3V)
(100MA; 1.65-1.805V; BUCK3)
(150MA; 1.2-3.1V)
LDO BYPASSUSB REVERSE VOLTAGE PROTECTION
LAYOUT NOTE: PLACERIGHT AT THE PIN
RIGHT AT THE PIN
(PP3V3_OUT)
(300MA; 1.7-3.0V)
(100MA; 1.8-3.3V)
R8196, C8196 CAN BEANYWHERE BET.TRISTAR
LAYOUT NOTE:
AND PMU
NOTE: FOR NO BATTERY SITUATION
ESR MAX=70MOHM
PLACE ONE 10UF CAP
(RON=0.2 OHM MAX)
(RON=0.05 OHM MAX)
ESR MAX=70MOHM
DCR=32MOHM MAX
R3172- PLACE NEAR BMUC3172- PLACE NEAR PMU
LAYOUT NOTE -
NOTE: 10V ZENER
22UF
603X5R-CERM-1
20%6.3V
CRITICAL
402MF
1/16W1%
0.5
CRITICAL
32.768K-20PPM-12.5PF
2012-1
5%25V
CRITICAL
18PF
NP0-C0G201
CERM
1UF
402
6.3V10%
CERM
1UF6.3V
402
10%
2.2UF6.3V
402
CRITICAL
X5R
10%
0402CERM-X5R
6.3V
10UF20%
CRITICAL
2.2UF
402
6.3V
CRITICAL
X5R
10%1UF6.3V
402
CRITICAL
X5R
10%
6.3V
4.7UF
X5R-CERM1402
20%
CRITICAL
CRITICAL
603
6.3V20%22UF
X5R-CERM-1
2.2UF
402
6.3V
CRITICAL
X5R
10%
402
2.2UF6.3V
CRITICAL
X5R
10%
402
20%6.3V
X5R-CERM1
4.7UF
CRITICAL
0201
6.3V
0.22UF20%
X5R
CRITICAL
22UF20%6.3V
603X5R-CERM-1
CRITICAL
20%
603
22UF6.3VX5R-CERM-1
LLP
CRITICAL
BZT52C10LP
MLP3.3X3.3FDMC6676BZ
CRITICAL
MF
1%1/20W
220K
201
470K1%
MF1/20W
NOSTUFF
201
1.0UH-20%-2.74A-59MOHM
PSB32251E-SM
CRITICALOMIT_TABLE
603X5R-CERM-16.3V20%22UF
CRITICALNOSTUFF
6.3V
22UF
X5R-CERM-1603
CRITICAL
20%
CRITICAL
603
22UF20%6.3VX5R-CERM-1
CRITICAL
20%6.3V
603
22UF
X5R-CERM-1
CRITICAL
603
22UF6.3V20%
X5R-CERM-1
CRITICAL
22UF
603
6.3V20%
X5R-CERM-1
CRITICAL
20%
603
6.3V
22UF
X5R-CERM-1
CRITICAL
20%
CERM-X5R0402
10UF6.3V
CRITICAL
20%6.3V
0402
10UF
CERM-X5RCERM-X5R
10UF
0402
6.3V20%
CRITICAL
0402CERM-X5R6.3V20%
CRITICAL
10UF
PSB32251E-SM
1.0UH-20%-2.74A-59MOHMOMIT_TABLE
CRITICAL
0402
20%10UF
CERM-X5R6.3V
CRITICAL
CRITICAL
10UF20%6.3VCERM-X5R0402
CERM-X5R0402
10UF
CRITICAL
20%6.3V
603
6.3V20%10UF
CRITICAL
X5R22UF
X5R-CERM-1
CRITICAL
6.3V20%
603
4.7UF
X5R-CERM1402
6.3V20%
CRITICAL
402X5R-CERM1
6.3V
4.7UF20%
CRITICAL
X5R-CERM1
20%6.3V
402
4.7UF
CRITICAL
402
4.7UF6.3V20%
X5R-CERM1
CRITICAL
0201X5R-CERM
0.01UF10V10%
402
2.2UF6.3V
CRITICAL
X5R
10%
25V
0402X7R
0.022UF10%
NOSTUFF1%
4.7K
201MF
1/20W
CERM402
6.3V
1UF10%
CRITICAL
35V
4.7UF
0603X5R-CERM
10%
5%
MF
NOSTUFF
4.7K
1/20W
201
CRITICAL
20%6.3V
10UF
CERM-X5R0402
CRITICAL
603
6.3V20%22UF
X5R-CERM-1
0402
6.3V20%10UF
CRITICAL
CERM-X5R
0402CERM-X5R
10UF6.3V20%
CRITICAL
0402
CRITICAL
20%6.3V
10UF
CERM-X5R
0402
CRITICAL
10UF20%6.3VCERM-X5R
NOSTUFF
0402
CRITICAL
20%6.3V
10UF
CERM-X5R
NOSTUFF
NOSTUFF
SM
CRITICAL
PSB32251E-SM
1.0UH-20%-2.74A-59MOHMOMIT_TABLE
SM
NOSTUFF
1.0UH-20%-2.74A-59MOHM
CRITICAL
PSB32251E-SM
OMIT_TABLE
PSB32251E-SM
1.0UH-20%-2.74A-59MOHMOMIT_TABLE
CRITICAL
0201
25VCER
8.2PF+/-0.1PF%5%
82PF
0201NP0-C0G-CERM25V
0201
20%1UF6.3V
CRITICAL
X5R
CRITICAL
0402CERM-X5R6.3V20%10UF
6.3V
603
20%22UF
CRITICAL
X5R-CERM-1
CRITICAL
22UF20%6.3V
603X5R-CERM-1
SM
NOSTUFF
CRITICAL
PSB25201E-SM
1.0UH-20%-2.3A-64MOHMOMIT_TABLE
CRITICAL
1.0UH-20%-3.9A-0.035OHM
PILE32251E-SMCRITICAL
1.0UH-20%-3.9A-0.035OHM
PILE32251E-SM
X5R-CERM-1
CRITICAL
22UF6.3V20%
603
NOSTUFF
CRITICAL
20%22UF6.3V
603X5R-CERM-1
SM
NOSTUFF
CRITICAL
1.0UH-20%-3.9A-0.035OHM
PILE32251E-SM
SM
NOSTUFF
CRITICAL
603
22UF20%6.3VX5R-CERM-1
CRITICAL
20%22UF
603
6.3VX5R-CERM-1
CRITICAL
22UF20%6.3V
603X5R-CERM-1
SM
NOSTUFF
1.0UH-20%-2.74A-59MOHM
PSB32251E-SM
CRITICALOMIT_TABLE
2.2UH-20%-3.3A-0.064OHM
PIME051E-SM
CRITICAL
SM
NOSTUFF
CERM402
6.3V
1UF10%
CERM
1UF6.3V
402
10%
CERM
1UF6.3V
402
10%
0201
1UF20%6.3VX5R
4991/20W1%
MF201
OMIT_TABLE
FCBGAD2018
5%25V
18PF
201
CRITICAL
NP0-C0G
CERM-X5R
10UF
CRITICAL
0402
6.3V20%
CRITICAL
20%6.3V
603
22UF
X5R-CERM-1
10UF20%6.3VCERM-X5R0402
CRITICAL
CERM-X5R0402
6.3V20%10UF
CRITICAL
6.3V
0402CERM-X5R
20%
CRITICAL
10UF
CRITICAL
PIME101E-SM
2.2UH-20%-4A-32MOHM
CERM-X5R
20%6.3V
0402
CRITICAL
10UF
CRITICAL
10UF20%6.3V
0402CERM-X5R
0402
20%6.3V
10UF
CERM-X5R
CRITICAL
20%6.3V
603
10UF
CRITICAL
X5R
CRITICAL
20%
603
10UF6.3VX5R
CRITICAL
6.3VTANT-1
150UF
B15G
20%
PLACEMENT_NOTE=PLACE NEAR L8225.1
150UF
TANT-1B15G
6.3V20%
CRITICAL
PMEG4030ERSOD-123W
CRITICAL
25V
0402X7R
0.022UF
NOSTUFF
10%
5%
MF1/20W
0
201
NOSTUFF
SHORT-0201
4.7UF35V
CRITICAL
X5R-CERM
10%
0603
CRITICAL
2.2UF25V
805X5R-CERM
10%
CRITICAL
20%22UF6.3V
603X5R-CERM-1
FDMC6683MLP3.3X3.3
CRITICAL
6.3VCERM-X5R0402-1
20%10UF
CRITICAL
0402-1CERM-X5R6.3V20%10UF
CRITICAL
20%
0402-1CERM-X5R6.3V
10UF
NOSTUFFCRITICAL
0402-1
10UF20%6.3VCERM-X5R
NOSTUFFCRITICAL
RDAR://PROBLEM/8376462L8111152S1292152S1452 ?
RDAR://PROBLEM/9936684197S0399 ? Y8138197S0392
?128S0279128S0339 C8165,C8166 RDAR://PROBLEM/8967213
138S0676 138S0654 ??
C8100,C8101,C8102,C8103,C8104,C8105,C8107,C8108,C8109,C8110,C8111,C8112,C8113,C8114,C8117,C8118,C8119,C8120,C8121,C8222,C8123,C8195
L8100,L8101,L8102,L8103,L8109,L8110152S1637 6 IND,1.0UH,20%,59MO,2.74A CRITICAL
1152S1638 L8104 CRITICALIND,1.0UH,20%,64MO,2.3A
SYNC_MASTER=MADHAVI SYNC_DATE=12/06/2011
PMU: ADRIANA PAGE 1
PPVCC_MAIN
NET_SPACING_TYPE=CRYSTAL PMU_XTAL
OVP_SW_EN_L_R
MIN_LINE_WIDTH=0.60MM
NET_SPACING_TYPE=PWR
VOLTAGE=6.0VMAX_NECK_LENGTH=3 MM
PPVBUS_PROTMIN_NECK_WIDTH=0.20MM
PP1V8
TP_PP1V8_GRAPE
PP1V2
PP1V1_CPU1_FET
PP1V1_CPU0_FET
PP1V8_S2R
PP3V0_GRAPE
PP3V0_S2R_HALL
PP2V8_CAM
NET_SPACING_TYPE=PWRMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM
BUCK5_FB
PP1V2_S2R
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=PWRDIDT=TRUE
BUCK2_LX2
PP1V2_SOC
MIN_LINE_WIDTH=0.6 MM
BUCK2_LX1
DIDT=TRUEMIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=PWR
DIDT=TRUENET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
BUCK2_LX0
PPVCC_MAIN
OVP_SW_EN_L
PPVCC_MAIN
PP3V0_S2R_HALL
OVP_SW_EN_L
BATT_SNS_R
PPVCC_MAIN_CPU0 PPVCC_MAIN_SOC
PP1V1_CPUB
PP2V8_CAMPP3V0_S2R_TRISTARPP3V0_IO
PP1V8_ALWAYS
LDO10
PP3V0_SENSOR
PP1V1_SRAM
NET_SPACING_TYPE=PWR
VOLTAGE=4.6VMAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.30MMMIN_NECK_WIDTH=0.20MM
BATT_POS_RC
NET_SPACING_TYPE=ANLGMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.20MMVBUS_PROT_G
PPVBUS_USB_DCIN
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=PWR
BUCK0A_LX1
DIDT=TRUE
MIN_NECK_WIDTH=0.20 MMNET_SPACING_TYPE=PWRMIN_LINE_WIDTH=0.25 MM
BUCK0B_FB
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=PWRDIDT=TRUE
BUCK0B_LX0
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=PWR
BUCK0B_LX1
NET_SPACING_TYPE=PWRMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM
BUCK0C_FB
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=PWRDIDT=TRUE
BUCK0C_LX0
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=PWR
BUCK3_LX0
NET_SPACING_TYPE=PWR
VOLTAGE=4.6V
MIN_NECK_WIDTH=0.20MM
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.30MMPMU_VPUMP
NET_SPACING_TYPE=PWRMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM
BUCK4_FB
PP3V0_S2R_TRISTAR
NET_SPACING_TYPE=PWR
PPVBUS_USBMIN_LINE_WIDTH=0.60MMMIN_NECK_WIDTH=0.25MM
MAX_NECK_LENGTH=3 MMVOLTAGE=6V VOLTAGE=6V
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.60MMPMU_VCENTER
PP1V2_S2R
PP3V3_ACC
PP1V7_VA_VCP
PP3V0_IOLDO10
PP1V0PP1V1_SRAMPP1V8_ALWAYS
NET_SPACING_TYPE=PWRMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM
BUCK2_FB
NET_SPACING_TYPE=CRYSTALPMU_EXTAL
PPBATT_VCC
PP3V2_S2R_USBMUX
LDO5
LDO5PP3V3_ACCPP1V0
PP3V2_S2R_USBMUXPP1V7_VA_VCP
PP3V0_GRAPE
PPVCC_MAIN
PPVCC_MAIN_CPU0
PPVCC_MAIN_CPU1
PPVCC_MAIN_SOC
NET_SPACING_TYPE=SWITCHNODEDIDT=TRUE
MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
SW_CHGA
PP3V0_SENSOR
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=PWRDIDT=TRUE
BUCK5_LX0
PP3V3_OUT
PP1V8_S2R
PP1V8_S2R
PPVCC_MAIN
PP1V2_S2R
BATT_SNS
PPBATT_VCC
MIN_LINE_WIDTH=0.2 MMMIN_NECK_WIDTH=0.1 MM
ACT_DIO
NET_SPACING_TYPE=ANLG
BUCK4_LX0MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=PWRDIDT=TRUE
NET_SPACING_TYPE=PWRMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM
BUCK3_FB
PPVCC_MAIN_CPU1
BUCK0A_FBNET_SPACING_TYPE=PWRMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.6 MM
BUCK0A_LX0MIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=PWRDIDT=TRUE
C81011
2
C81031
2
C81051
2
C81081
2
C81101
2
C81121
2
C81141
2
L8100
1 2 C81001
2
C81021
2
XW81001 2
L8101
1 2
XW81011 2
L8102
1 2
L8103
1 2
C81641
2
C81631
2
C81311
2
C81301
2
C81041
2
C81071
2
XW81021 2
L8104
1 2
L8105
1 2
L8106
1 2
C81091
2
XW81031 2
L8107
1 2
XW81041 2
C81111
2
C81131
2
XW81051 2
L8110
1 2
L8111
1 2
XW81061 2
C81411
2
C81391
2
C81401
2
C81381
2
R81731
2
U8100
M18
E11
A9
B9
A11
B11
E6
A5
B5
A7
B7
F5
E1
E2
E15
A13
B13
A15
B15
A17
B17
A19
B19
H5
G1
G2
D4
A3
B3
A23
B23
E18
A21
B21
F22
F23
G22
G23
H22
H23
J22
J23
L1
L2
J1
J2
P15
P16
P17
P18
M17
M16
M14
K2
M2
E20
E21
H21
J19
J20
J21
K20
K21
E19
K19
F19
F20
F21
G19
G20
G21
H19
H20
L23
N15
N16
N17
N18
L20
E22
E23
K22
K23
A10
B10
A6
B6
D1
D2
A14
B14
A18
B18
H1
H2
A2
B2
A22
B22
N6
N2
N5
N14
N9
N4
N7
N3
N11
P9
P6
M1
P5
P14
P4
N8
P2
P8
P10
P3
M6
P11
K3
K1
N1
P1
C81431
2
C81621
2
C81611
2
C81601
2
C81591
2
L8112
1 2
C81581
2
C81571
2
C81561
2
C81551
2
C81541
2
C8165 1
2
C8166 1
2
D8100
A
K
C81721
2
R81721 2
XW8114
12
C81251
2C8124 1
2
Q8104
5
4
1 2 3
C81711
2
C81701
2
C81731
2
C81741
2
R81001
2
Y81381 2
C8142 1
2
C81361
2
C81351
2
C8147 1
2
C8144 1
2
C8145 1
2
C8146 1
2
C8152 1
2
C8153 1
2
C8149 1
2
C8168 1
2
C8169 1
2
C81951
2DZ8120
AK
Q8123
5
4
123
R81301
2
R81161
2
L8109
1 2
C81201
2
C81211
2
C81221
2
C81231
2
C81191
2
C81181
2
C81171
2
C81931
2
C81921
2
C81911
2
C81901
2
C81891
2
C81881
2
C81871
2
C81941
2
C8133 1
2
C8132 1
2
C8167 1
2
C8148 1
2
C81371
2
C8151 1
2
C81961
2
R81961 2
C81341
2
C81261
2
R81701 2
C81801
2
C81811
2
C81831
2
C81821
2
C81841
2
C81851
2
29 OF 39
051-9385
A.0.0
81 OF 154
15 25 29 30 34 39
36
25
32 34 39
34 39
30 39
30 39
29 34 39
29 34 39
29 34 39
29 34 39
39
29 34 39
39
34 39
39
39
15 25 29 30 34 39
25 29
15 25 29 30 34 39
29 34 39
25 29
29 34 29 34
34 39
29 34 39
29 34
29 34 39
29 34 39
18 29 39
29 34 39
29 34 39
39
34
39
39
39
39
39
39
39
39
29 34
4
29 34 39
29 34 39
19 29 34 39
29 34 39
18 29 39
29 34 39
29 34 39
29 34 39
39
36
29 32 34 39
29 34 39
29 39
29 39
29 34 39
29 34 39
29 34 39
19 29 34 39
29 34 39
15 25 29 30 34 39
29 34
29 34
29 34 29 34 39
39
34 39
29 34 39
29 34 39
15 25 29 30 34 39
29 34 39
28
29 32 34 39
39
39
29 34
39
39
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NCNCNCNCNCNCNCNCNCNC
G
S
D
G
S
D
IN
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
G
S
D
G
S
D
IN
IN
IN
IN
OUT
OUT
IN
BI
IN
IN
OUT
GPIO16
GPIO17
AMUX_A3
AMUX_AY
AMUX_B0
AMUX_B1
WLED_LXA
ACC_ID
BRICK_ID
ADC_IN7
TDEV4
FW_DPHP_DET
GPIO14
GPIO15
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
ADC_REF
VDD_RTC
VDD_REF_A
VDD_REF
BUTTON1
ACC_DET
BUTTON3
AMUX_A0
AMUX_A1
AMUX_A2
AMUX_B2
AMUX_B3
AMUX_BY
BUTTON2
CPUA_EN
CPUA_SW_G
CPUA_SW_S
CPUB_EN
CPUB_SW_G
CPUB_SW_S
DPHP
DWI_CK
DWI_DI
DWI_DO
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
IREF
KEEPACT
LCM_FB
LCM2_EN
IRQ*
RESET*
RESET_IN
SDA
SHDN
TBAT
TCAL
TDEV1
TDEV2
TDEV3
TDEV5
TDEV6
TDEV7
TDEV8
VDD_BOOST_LCM
VDD_LCM_SW
VLCM1
VLCM2
VLCM3
VOUT_WLED_A
VOUT_WLED_B
VREF
WLED1_A
WLED1_B
WLED2_A
WLED2_B
WLED3_A
WLED3_B
WLED4_A
WLED4_B
WLED5_A
WLED5_B
WLED6_A
WLED6_B
ADC_IN31
WLED_LXB
BOOST_LCM_LX
VDD_LCM
SCL
ANALOG
DIGITAL
REFERENCES
INPUT
INPUT
GPIO
TEMPERATURE
WDOG
RESET
ANALOG MUX
I2C & DWI
LCM/GRAPE
LED BACKLIGHT
SYM 1 OF 3
IN
IN
IN
IN
IN
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
(NOTE: 2MHZ)(INTERNAL PULL-DOWN)
(INTERNAL PULLDOWN; TE ENABLE)
CLOSE TO PMU
(1.8_S2R;NO PD REQ’D PER BB TEAM)
(INTERNAL PD)
PLACE XW AND CAP
(TEMP6 BOTTOM SIDE NEAR BRIDGE FLEX)
(TEMP5 - TOP SIDE NEAR NAND)
BB_VBUS_DET STUFFING OPTIONSELECTING GPIO OPTION BY DEFAULTREMOVE STUFFING RES AND WIRE DIRECTLY FOR PRODUCTION
PLACEMENT NOTE: PLACE NEAR PIN K24
(INTERNAL PULL-DOWN)
(INTERNAL PULL-DOWN)
(1.8_S2R;NO PD REQ’D PER BB TEAM)
(INTERNAL PU TO PP1V8_S2R)
(INTERNAL PULL-DOWN)
(TEMP3 - BOTTOM SIDE NEAR I/O FLEX CONN)
CLOSE TO PMU
(1.8_S2R PUSH-PULL)
(PPLED_OUT_B)
RESISTOR FOR TEMP CALIBRATION
CLOSE TO PMU
PLACE XW AND CAP
PLACE XW AND CAP
DCR=106MOHM MAX
DCR=106MOHM MAX
CLOSE TO PMU
PLACE XW AND CAP (PULLUP INSIDE H5G)
USED BY Z2
(INTERNAL PULL-DOWN)
CLOSE TO PMU
(TEMP1 - BOTTOM SIDE NEAR H5G)
(TEMP2 - BOTTOM SIDE NEAR PMU)
(TEMP4 - BOTTOM SIDE NEAR WIFI)
DWI NAMING RELATIVE TO AP
(INTERNAL PD; CAN’T BE USED FOR 32K CLK OUTPUT)
(INTERNAL PD)
(PPLED_OUT_A)
PLACEMENT NOTE: PLACE NEAR PIN K4
(2.5V ALWAYS ON PU IN BMU)
NEED RADAR TO STOP GENERATING 32K CLOCK
LOCATION DESCRIPTIONS ARE FROM J2SENSOR LOCATIONS TBD
PLACE XW AND CAP
PLACE XW AND CAP
I2C ADDRESS: 0111100X (0X78)
CLOSE TO PMU
10KOHM-1%-0.31MA
0201
CRITICAL
NOSTUFFSM
01005
5%100PF
6.3VCERM
15 37
15 37
15 37
15 37
SOD-323
CRITICAL
PMEG4010BEA
201
10%0.1UF
X5R6.3V
201
1/20W
1.00
MF
1%
201
1/20W
1.00
MF
1%
1/20W1%
MF
1.00
201
1/20W1%
1.00
MF201
1%1/20WMF
1.00
2011.00
1/20WMF
1%
201 1.00
1/20WMF
1%
2011.00
1/20WMF
1%
201
15 37
15 37
15 37
15 37
15 37
CRITICAL
SOD-323
PMEG4010BEA
15 37
15 37
15 37
14 36
10KOHM-1%-0.31MA
0201
CRITICAL
CERM
5%6.3V
01005
100PF
NOSTUFFSM
10KOHM-1%-0.31MA
0201
CRITICAL
01005
100PF5%
CERM6.3V
NOSTUFFSM
CRITICAL
4.7UH-3.2A
PIME051E-SM
14
0603-1
10UF20%10VX5R
CRITICAL
CRITICAL
35V10%4.7UF
0603X5R-CERM
CRITICAL
PIME051E-SM
4.7UH-3.2A
0603-1
10UF20%
X5R10V
CRITICAL
14
SOD882
PMEG2005AEL
CRITICALNOSTUFF
17 36
CRITICAL
10%4.7UF
0603X5R-CERM35V
10%
X5R-CERM0603
35V
4.7UF
CRITICAL CRITICAL
35V10%4.7UF
X5R-CERM0603
CRITICAL
35V10%4.7UF
0603X5R-CERM
CRITICAL
35V10%4.7UF
0603X5R-CERM
CRITICAL
35V10%4.7UF
0603X5R-CERM
CRITICAL
X5R-CERM0603
4.7UF10%35V
402
1UF10V10%
X5R
NOSTUFF
01005
0.01UF
X5R6.3V10%
BGACSD58874W1015
CSD58874W1015BGA
402
10%10VX5R
1UF
NOSTUFF
10%
X5R-CERM6.3V
01005
1000PF
5 25
SMNOSTUFF
SMNOSTUFF
01005
0%
MF1/32W
0.00
01005
0%
MF1/32W
0.00
NOSTUFF
26
23
25
MF1/20W1%
6.34K
201
26
5 28
14
14
26
18
22
18
2.2UH-1.05A-0.195OHM
VLS201612E-SM
CRITICALNOSTUFF
20%10UF
0603X5R-CERM25V
NOSTUFF
402
10V20%
X5R-CERM
2.2UF
NOSTUFF
CSD58874W1015BGA
CSD58874W1015BGA
201
1/20W5%
MF
0
201
1/20W
0
MF
5%
0.22UF20%
0201X5R6.3V
NOSTUFF
16V10%
X5R-CERM
0.1UF
0201
16V10%
0201X5R-CERM
0.1UF
NOSTUFF
MF
5%
201
1/20W
1M
NOSTUFF
201MF1/20W5%1M
NOSTUFF
28
5
32
200K1/20W
201MF
1%
25
4 25 26 39
5
5 19 25 36
5 19 25 36
5 36
5 36
5 36
PLACEMENT_NOTE=PLACE NEAR U8100.K16
X7R50V10%
402
0.01UF
PLACEMENT_NOTE=PLACE NEAR U8100.K16
402
10%0.01UF
X7R50V
PLACEMENT_NOTE=PLACE NEAR U8100.K1710%
402X7R50V
0.01UF
PLACEMENT_NOTE=PLACE NEAR U8100.K17
402
10%
X7R50V
0.01UF
D2018FCBGA
OMIT_TABLE
0.1UF10%6.3VX5R2010.01UF
01005X5R6.3V10%
X5R01005
0.01UF10%6.3V
5 23
5 20
5 20
25
10
100PF
CERM01005
6.3V5%
10KOHM-1%-0.31MA
0201
CRITICAL
SMNOSTUFF
10KOHM-1%-0.31MA
0201
CRITICAL
CERM01005
6.3V5%
100PF
SMNOSTUFF
CRITICAL
3.92K
1/16W4020.1%
MF
100PF6.3VCERM
5%
01005
402
10%
CERM6.3V
1UF
1.00
1/20W
201
1%
MF
MF
1.00
1/20W1%
201
1/20W
201
1.00
MF
1%
1/20WMF
1%
201
1.00
10KOHM-1%-0.31MA
0201
CRITICAL
NOSTUFFSM
100PF5%
01005
6.3VCERM
?107S0208107S0150
R8216,R8218,R8222,R8280,R8281,R8282
RDAR://PROBLEM/8380367
SYNC_DATE=12/06/2011
PMU: ADRIANA PAGE 2SYNC_MASTER=MADHAVI
DWI_AP_CLKDWI_AP_DODWI_AP_DI
MIN_NECK_WIDTH=0.25 MMNET_SPACING_TYPE=SWITCHNODEDIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
WLED_LX_A
PPLED_OUT_A
PP1V1_CPU0
PMU_GPIO_BB_VBUS_DET
MAKE_BASE=TRUEVOLTAGE=6.0V
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
PP6V0_LCM_VBOOSTTP_LCM2_EN
VLCM3
PPVCC_MAIN
BOARD_TEMP5_P
PMU_ACC_ID
BOARD_TEMP7_P
PPLED_OUT_B
VLCM3
PMU_GPIO_BB_VBUS_DET
BB_VBUS_DET
BOARD_TEMP6_P
PMU_GPIO_TS_INT
I2C0_SCL_1V8
PMU_GPIO_WLAN_REG_ONPMU_GPIO_BT_REG_ON
GPIO_BTN_HOME_L
BOARD_TEMP8_N
CPU0_SW_SMIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MMMAX_NECK_LENGTH=3 MM
PP6V0_LCM_HIMAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MMVOLTAGE=6.0VMAKE_BASE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.4 MM
NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 MM
LCM_LX
GPIO_BTN_ONOFF_L
LED_IO2_B_R
LED_IO5_B_R
BOARD_TEMP3_N
BOARD_TEMP7_N
PP1V1_CPU1
CPU1_SW_SMIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MMMAX_NECK_LENGTH=3 MM
PPLED_OUT_A
CPU0_SW_G_R
LED_IO_1_A
LED_IO_2_A
LED_IO_3_A
LED_IO_4_A
LED_IO_5_A
LED_IO_6_A
LED_IO_1_B
LED_IO_2_B
LED_IO_3_B
LED_IO_4_B
LED_IO_5_B
PMU_GPIO_BT_HOST_WAKEPMU_GPIO_WLAN_HOST_WAKEPMU_GPIO_BB_HOST_WAKE
GPIO_PMU_KEEPACT
PMU_RESET_INRST_AP_LGPIO_PMU_IRQ_L
I2C0_SDA_1V8
=PPVCC_MAIN_LED
=PPVCC_MAIN_LED
NC_PMU_DP_HPDNO_TEST=TRUE
NC_VLCM1NO_TEST=TRUE
NC_FW_ZENER_PWRNO_TEST=TRUE
LED_IO6_B_R
LED_IO3_B_R
CPU1_SW_G_R
PP1V1_CPU1_FET
CPU1_SW_S
BOARD_TEMP4_N
PPLED_OUT_B
BOARD_TEMP5_N
CPU0_SWITCH
CPU1_SWITCH
PMU_IREFNET_SPACING_TYPE=ANLG
PMU_VREFNET_SPACING_TYPE=ANLG
PMU_VDD_RTCNET_SPACING_TYPE=ANLG
LED_IO4_B_RCPU1_SW_G
PMU_SHDWNNET_SPACING_TYPE=ANLG
PP1V1_CPU0_FET
NC_VLCM2NO_TEST=TRUE
CPU0_SW_GCPU0_SW_S
LED_IO1_B_R
WLED_LX_B
MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
NET_SPACING_TYPE=SWITCHNODEDIDT=TRUE
LED_IO2_A_R
PMU_E75_ACC_DET_L
BATTERY_NTC
NO_TEST=TRUENC_PMU_GPIO16PMU_GPIO_HALL_IRQ
PMU_GPIO_HALL2_IRQ
LED_IO5_A_RLED_IO6_A_R
LED_IO3_A_R
LED_IO_6_B
BOARD_TEMP6_P
BOARD_TEMP8_P
PMU_TCAL NET_SPACING_TYPE=ANLG
LED_IO1_A_R
MIN_NECK_WIDTH=0.1MM
PMU_ADC_REF
MIN_LINE_WIDTH=0.1MMNET_SPACING_TYPE=ANLG
NET_SPACING_TYPE=ANLGPMU_VDD_REF
PMU_GPIO_BB_PMU_RST_LUART5_BATTERY_TRXD
PMU_GPIO_CLK_32K_WLANPMU_GPIO_CLK_32K_GRAPE
PMU_GPIO_CODEC_RST_L
PMU_GPIO_CODEC_HS_INT_L
BOARD_TEMP4_PBOARD_TEMP3_PBOARD_TEMP2BOARD_TEMP1
PMU_GPIO_BBUSBTODOCK_EN
BOARD_TEMP5_P
GPIO_BTN_SRL_LBOARD_TEMP6_N
PMU_USB_BRICKID PMU_USB_BRICKID_RADC_IN7
LED_IO4_A_R
C82101
2
R82031
2
C82041
2
C82091
2
C82121
2
D8230
A K
C82381
2
L8229
1 2
C82371
2
C8236 1
2
Q8200
A1
B1
C1
A2
B2
C2
Q8201
A1
B1
C1
A2
B2
C2
R82921 2
R82931 2
C82901
2
C82911
2
R82901
2
R82911
2
C8266 1
2
C8201 1
2
C8267 1
2
C8251 1
2
U8100
C1
M8
L5
L4
M10
C21
C22
E17
E14
C23
D21
D22
D19
E13
D23
P20
M21
C3
D3
E3
M23
J5
J4
L22
J3
K4
E4
A1
B1
C2
M19
D5
C13
C14
C15
C16
C17
C18
C19
C20
C5
C6
C7
C8
C9
C10
C11
C12
M7
H4
E10
F3
M20
F4
G4
E7
E9
H3
L21
M22
L19
K15
K14
M13
M5
M4
L3
M3
P19
N13
N19
K18
M15
N10
P13
P12
N12
K16
K17
P7
K5
K10
K6
M11
K7
K11
K8
K12
M9
M12
K9
K13
N21
P21
N23
P23
C82071
2
C82061
2C8282 1
2
R8282
1
2
XW82821 2
R8281
1
2C8281 1
2
XW82811 2
R8219
1
2
C8220 1
2
R82271 2
R82321 2
R82311 2
R82351 2
R8280
1 2
XW82031 2
C8223 1
2
R8218
1
2
XW82021 2
C8217 1
2
D8228
A K
R82391 2
R82401 2
R82571 2
R82611 2
R82621 2
R82651 2
R82691 2
R82701 2
D8258
A K
R8222
1
2C8221 1
2
XW82011 2
R8216
1
2
C8215 1
2
XW82001 2
L8225
1 2
C8226 1
2
C82321
2
L8255
1 2
C8256 1
2
C82331
2
C82341
2
C82351
2
C82651
2
C82641
2
C82631
2
C82621
2
C82921
2
Q8203
A1
B1
C1
A2
B2
C2
Q8202
A1
B1
C1
A2
B2
C2
C82391
2
C82141
2
XW82901 2
XW82911 2
R82971 2
R82961 2
R82991 2
82 OF 154
30 OF 39
051-9385
A.0.0
30 34 39
34 39
30
39
30
15 25 29 34 39
30 37
37
30 34 39
30
30
30 37
37
30
39
39
37
37
37
37
34 39
30
30 34 39
30 34
30 34
37
37
29 39
30
37
30 34 39
37
4
4
37
29 39
30
37
37
37
37
37
30 37
37
37
37
37
32 37
32 37
30 37
37
37
SYM 3 OF 3
VSS_LCM
VSS_WLED
VSS_WLED
VSS
VSS
VSS/VSS_BUCK0A2
VSS/VSS_BUCK0B4
VSS/VSSA_BUCK0C
VSS/VSSA_BUCK2
VSS/VSSA_BUCK3
VSS/VSSA_BUCK4
VSS/VSSA_BUCK5
VSS/VSS_BUCK0A0B
VSS/VSSA_BUCK0B
VSS/VSSA_BUCK0A
VSS/VSS_BUCK0C3
VSS/VSS_BUCK2_01
VSS/VSS_BUCK25
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
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D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
ADD A VIA PER PIN FOR ALL VSS_* AND VSSA_* PINS
OMIT_TABLE
FCBGAD2018
PMU: ADRIANA PAGE 3SYNC_DATE=12/06/2011SYNC_MASTER=MADHAVI
U8100
C4
D20
F14
F15
F16
F17
G3
G5
G7
G8
G9
G10
F6
G11
G12
G13
G14
G15
G16
G17
G18
H7
H8
F7
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
F8
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
F9
J16
J17
J18
A8
B8
A12
B12
A4
B4
F10 F1
F2
A16
B16
A20
B20
E12
E8
G6
E16
F11
H6
E5
F18
F12
F13
N20
N22
P22
83 OF 154
A.0.0
051-9385
31 OF 39
G
SYM_VER_1
D
S
G
SYM_VER_1
D
S
G
SYM_VER_1
D
S
IN
OUT
OUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
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REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
SOCHOT TO PMU TDEV1/TDEV2
DEBUG RESET ACCESS
1/20W5%
201MF
100K1/20W5%
201MF
100K
CRITICAL
DFNDMN26D0UFB4
1/32W1%
01005MF
10K
1/32W1%
01005MF
10K
1/32W1%
01005MF
470
1/32W1%
01005MF
470
CRITICAL
DFNDMN26D0UFB4
CRITICAL
DFNDMN26D0UFB4
7
30
30 37
30 37
NOSTUFF
1/20W1%
201MF
1.5K
NOSTUFF
0603RED-50MCD-20MA
NOSTUFF
1/20W5%
201MF
300
5
NOSTUFF
1/20W5%
201MF
300
SYNC_MASTER=MLB SYNC_DATE=11/09/2011
DEBUG/MISC.
GPIO_FORCE_DFU
BOARD_TEMP2
BOARD_TEMP1
PMU_SHDWN
SOCHOT1_L
SOCHOT1_TDEV1
PP1V8
SOCHOT1
=PP1V8_S2R_MISC
PP1V8
SOCHOT1_TDEV2
PPBATT_VCC
PWR_ON_LED
R90021
2
LED9000A
K
R90001
2 R90011
2
R90111
2
R90101
2
Q9010
3
1
2
R90211
2
R90311
2
R90201 2
R90301 2
Q9020
3
1
2
Q9030
3
1
2
051-9385
A.0.0
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32 OF 39
29 32 34 39
5 34
29 32 34 39
29 34 39
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
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D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
PLATING SIZE: 1.4MM X 0.7MMDRILL SIZE: 1.1MM X 0.4MM
PLATED THROUGH HOLES
SL-1.1X0.4-1.4X0.7
TH-NSP
TH-NSP
SL-1.1X0.4-1.4X0.7
TH-NSP
SL-1.1X0.4-1.4X0.7
TH-NSP
SL-1.1X0.4-1.4X0.7
TH-NSP
SL-1.1X0.4-1.4X0.7
SL-1.1X0.4-1.4X0.7
TH-NSP
SL-1.1X0.4-1.4X0.7
TH-NSP
TH-NSP
SL-1.1X0.4-1.4X0.7
SL-1.1X0.4-1.4X0.7
TH-NSP
SL-1.1X0.4-1.4X0.7
TH-NSP
FID0P5SM1P0SQ-NSP
FID0P5SM1P0SQ-NSP
FID0P5SM1P0SQ-NSP
FID0P5SM1P0SQ-NSP
FID0P5SM1P0SQ-NSP
FID0P5SM1P0SQ-NSP
TEST/HOLES/FIDUCUALSSYNC_DATE=N/ASYNC_MASTER=N/A
SL42101
SL42121
SL42131
SL42141
SL42151
SL42161
SL42011
SL42041
SL42051
SL42061
FID4200
1
FID4201
1
FID4202
1
FID4203
1
FID4204
1
FID4205
1
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Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
BUCK3
BUCK3_SW
BACKLIGHT BOOST
CELLULAR RADIO
WLAN
BUCK0A
USB POWER INPUTLDO1
LDO6
BUCK4
CPU1V2_SWBUCK4_SW
LDO8
LDO9
LDO4
LDO7
BUCK5
BUCK0C
POWER CONNECTIONS
BUCK0B
BUCK2
CPU1V8_SW
LDO16
LDO11
CHARGER MAIN
LDO12
LDO3 (NO LONGER NEEDED)
LDO2
BATTERY
I927
SYNC_MASTER=N/A SYNC_DATE=N/A
POWER ALIASES
MIN_LINE_WIDTH=0.2MM
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.1MMNET_SPACING_TYPE=PWR
VOLTAGE=1.8V
PP1V8MAKE_BASE=TRUE
=PP1V8_S2R_MISC
VOLTAGE=4.7V
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6 MM
MAX_NECK_LENGTH=3 MM
PPVCC_MAIN =PPVCC_MAIN_AUDIO
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM
NET_SPACING_TYPE=PWR
MAKE_BASE=TRUE
PP1V7_VA_VCPVOLTAGE=1.7V
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
MAKE_BASE=TRUE
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6 MMVOLTAGE=3.0V
PP3V0_GRAPE
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
MAKE_BASE=TRUE
PP1V0
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0VMIN_LINE_WIDTH=0.6 MM
=PP1V0_HSIC_H5
=PP3V2_S2R_USBMUX
=PP3V0_SENSOR
PPVBUS_USB_DCIN
MIN_LINE_WIDTH=0.6 MMVOLTAGE=6VMAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.15 MM
=BATT_POS_CONN
MAKE_BASE=TRUE
PP3V3_ACCVOLTAGE=3.3VMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
PP3V0_IOVOLTAGE=3.0VMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
MAKE_BASE=TRUE
NET_SPACING_TYPE=PWR
=PPVDD_SOC_H5
MAKE_BASE=TRUE
NET_SPACING_TYPE=PWR
PP1V2_S2R
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMVOLTAGE=1.2V
=PP1V8_S2R_USBMUX
=PP1V8_S2R_DDR
=PP1V2_S2R_DDR
=PP1V8_ALWAYS
MAKE_BASE=TRUE
PP3V3_OUT
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 MMNET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6 MMVOLTAGE=3.3V
=PP3V3_LCD
=PP3V3_USB_H5
=PP3V3_NAND
MAKE_BASE=TRUE
PP1V1_CPU1VOLTAGE=1.1VMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM
MAKE_BASE=TRUE
PP1V1_CPU0VOLTAGE=1.1V
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
=PPVCC_MAIN_LED
=PPVDD_SRAM_H5MAKE_BASE=TRUE
PP1V1_SRAM
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMVOLTAGE=1.1V
=PPVDD_CPU0_H5
MAKE_BASE=TRUE
PP1V2_SOC
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMVOLTAGE=1.2V
VDDIO_WLAN_BT_1V8
=PPVDD_CPU1_H5
NET_SPACING_TYPE=PWR
MAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MM
VOLTAGE=20.4VMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM
PPLED_OUT_A
=PP1V0_DP_PAD_DVDD_H5
=PPLED_REG_A
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
VOLTAGE=20.4VMAKE_BASE=TRUE
PPLED_OUT_B =PPLED_REG_B
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM
MAKE_BASE=TRUE
PP1V8_ALWAYS
=PP1V2_S2R_H5
=PP1V7_VA_VCP
=PP3V3_ACC
=PP3V0_S2R_TRISTARMAKE_BASE=TRUE
PP3V0_S2R_TRISTARVOLTAGE=3.0VMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
MAKE_BASE=TRUE
PP3V0_SENSORVOLTAGE=3.0V
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6 MM
=PP3V0_S2R_HALLMAKE_BASE=TRUE
PP3V0_S2R_HALL
MAX_NECK_LENGTH=3 MM
VOLTAGE=3.0V
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM
NET_SPACING_TYPE=PWR
=PP3V0_VDDIO30_H5
=PP1V2_HSIC_H5
=PP1V0_MIPI_PLL_H5
=PP3V0_GRAPE_MARIO1
=PP3V0_GRAPE_Z2
=PP3V0_GRAPE_Z1
=PP3V0_GRAPE
=PP1V2_VDDIOD_H5=PP1V2_VDDQ_DDR
MIN_NECK_WIDTH=0.1 MM
MAKE_BASE=TRUE
PP1V2
MIN_LINE_WIDTH=0.6 MMVOLTAGE=1.2V
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
MAKE_BASE=TRUE
PP3V2_S2R_USBMUX
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMVOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
PP2V8_CAMMAKE_BASE=TRUE
NET_SPACING_TYPE=PWR
VOLTAGE=2.8V
=PP2V8_CAM
PPVCC_MAIN_CPU0
PPVCC_MAIN_CPU1
PPVCC_MAIN_SOC
=PP1V8_SENSOR=PP1V8_AUDIO
=PP1V8_VDDIO18_H5
=PP1V8_MIPI_H5=PP1V8_DP_H5
=PP1V8_H5
=PP1V8_EDP_H5=PP1V8_NAND_H5=PP1V8_NAND
=PP1V8_MISC
=PPVDD_CPUB_H5MAKE_BASE=TRUE
PP1V1_CPUB
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.1V
NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
PPVBUS_USB_EMI
=PP1V0_MIPI_H5
=PP1V0_USB_H5
=PP1V0_EDP_PAD_DVDD_H5
=BATT_POS_F_3G
=BATT_VCC
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
PPBATT_VCCVOLTAGE=4.2V
=PP1V8_PLL_H5
MIN_NECK_WIDTH=0.15 MMNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM
PP1V8_S2RVOLTAGE=1.8VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
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LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_BOARD_INFO
VERSIONALLEGRO
(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
DEFAULT/BGA SPACING RULES
0.140 MM ~ 5.5 MIL
REGULAR SPACING RULES
PHYSICAL CONSTRAINTS
MISC
MLB CONSTRAINTS
BGA AREA PHYSICAL RULES
NOTES:
0.089 MM ~ 3.5 MIL
0.125 MM ~ 5 MIL
0.114 MM ~ 4.5 MIL
0.18 MM ~ 7 MIL
0.3 MM ~ 12 MIL
0.075 MM ~ 3 MIL
0.102 MM ~ 4 MIL
0.2 MM ~ 8 MIL
0.33 MM ~ 13 MIL
0.4 MM ~ 16 MIL
1.0 MM = 39.37 MIL
0.25 MM ~ 10 MIL
0.15 MM ~ 6 MIL
TCF VERSION (USING SPACING RULE)
ASSIGNING RULE TO NC NET
SPACING CONSTRAINTS
0.104 - 11/30/2011
SINGLE-ENDED PHYSICAL RULES
POWER/GND SPACING RULES
POWER
WIFI PHYSICAL RULES
45 OHMS
90 OHMS
DDR 45 OHMS
DDR 90 OHMS
DIFFERENTIAL PAIR PHYSICAL RULES
MISC PHYSICAL RULES
SINGLE-ENDED PHYSICAL RULES
DIFFERENTIAL PAIR PHYSICAL RULES
I1
ISL4 3.0 MMDDR_45_OHM_SE 0.053 MMY 0.053 MM
3.0 MMDDR_45_OHM_SE * N 0.055 MM0.055 MM
3.0 MMYDDR_45_OHM_SE ISL5,ISL6 0.072 MM0.072 MM
YISL2 3.0 MM0.055 MM0.055 MMDDR_45_OHM_SE
TOP,BOTTOM 3.0 MM0.105 MM 0.105 MMYDDR_45_OHM_SE
YDDR_45_OHM_SE 3.0 MM0.065 MM0.065 MMISL3
Y =STANDARD0.052 MM 0.105 MM 0.105 MMISL5,ISL690_OHM_DIFF 0.052 MM
0.170 MMTOP,BOTTOM =STANDARDY 0.170 MM0.090 MM0.090 MMDDR_90_OHM_DIFF
0.190 MM0.190 MMISL3 YDDR_90_OHM_DIFF 0.062 MM =STANDARD0.062 MM
0.190 MMISL4 0.190 MM0.051 MMDDR_90_OHM_DIFF 0.051 MMY =STANDARD
ISL5,ISL6 0.180 MM0.180 MMY =STANDARDDDR_90_OHM_DIFF 0.066 MM 0.066 MM
DDR_90_OHM_DIFF 0.180 MMN* 0.056 MM 0.180 MM0.056 MM =STANDARD
WIFI_50S TOP,BOTTOM Y 0.245 MM 0.2 MM =STANDARD
WIFI_50S N* =STANDARD=STANDARD=STANDARD
* =STANDARD0.10 MMWIFI_PWR100 0.050 MMY
WIFI_PWR1000 =STANDARD* Y 0.100 MM1.00 MM
CONSTRAINTS: MLB RULESSYNC_DATE=11/30/2011SYNC_MASTER=MIKE
DDR_90_OHM_DIFF ISL2 0.190 MM0.190 MMY 0.062 MM =STANDARD0.062 MM
3.0 MMY 0.065 MMISL3,ISL845_OHM_SE 0.055 MM
3.0 MMY 0.105 MM45_OHM_SE TOP,BOTTOM 0.055 MM
0.059 MMISL6 3.0 MMY45_OHM_SE 0.055 MM
=STANDARDTOP,BOTTOM Y 0.170 MM0.090 MM 0.170 MM90_OHM_DIFF 0.090 MM
0.190 MM0.062 MM =STANDARDISL2,ISL9 0.190 MMY90_OHM_DIFF 0.062 MM
0.052 MM 0.190 MM0.062 MM90_OHM_DIFF YISL3,ISL8 =STANDARD 0.190 MM
Y 0.08 MM1:1_DIFFPAIR * 0.08 MM=STANDARD =STANDARD=STANDARD
10 MMY*SPEAKER 0.5 MM 0.20 MM 0.10 MM 0.10 MM
0.09 MM* Y 10 MMAUDIO_DIFF 0.1 MM 0.10 MM0.10 MM
0.09 MM0.1 MM 0.08 MM10 MM* 0.08 MMLED Y
0.09 MM0.1 MM 0.08 MMTEMP_SENSE 10 MMY 0.08 MM*
BGA_P4_SPABGA_P4**
3.0 MM0.20 MM*PWR Y 0.6MM
3.0 MM0.075 MMY* 0.6MMGND_PH
3.0 MM0.20 MMY* 0.6MMPWR_PMU
* ?0.5 MM0P5MM_SPACING
* ?4:1_SPACING 0.200 MM
*3:1_SPACING ?0.150 MM
*2.5:1_SPACING ?0.125 MM
?2:1_SPACING * 0.100 MM
* ?1.5:1_SPACING 0.075 MM
?*0P08_SPACING 0.080 MM
0.20 MM0P2_SPACING ?*
0.1 MMGND_P1SPACING *
*SWITCHNODE 0.2 MM
** SWITCHNODESWITCHNODE
5:1_SPACING * ?0.250 MM
BGA_P4_SPA 0.200 MM ?*
0 MM=45_OHM_SEDEFAULT Y 0 MM* 3.0 MM=45_OHM_SE
=DEFAULT* =DEFAULTY =DEFAULT 12.7 MM =DEFAULTSTANDARD
0.053 MMY 0.055 MM 3.0 MM45_OHM_SE ISL4,ISL7
0.104 MM* ?TCF_VERSION
0.190 MM0.190 MM0.051 MM =STANDARDISL4,ISL7 Y90_OHM_DIFF 0.051 MM
3.0 MM0.072 MMY45_OHM_SE ISL5 0.055 MM
Y 3.0 MM45_OHM_SE 0.055 MMISL2,ISL9 0.055 MM
=STANDARDYBGA_PHY * 0.060 MM 0.076 MM 0.075 MM0.060 MM
16.2MMNO_TYPE,BGA,BGA06-06,BGA_P4TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,BOTTOM
BGA BGA_PHY*
* BGA_SPA* BGA
CLK BGA* BGA_SPA
GND_P1SPACINGGND **
3:1_SPACING**ANLG
PWR_P1SPACING 0.1 MM*
MM 46.0GNICAPS_MM46P0 ?*
1:1_SPACING * ?0.050 MM
*STANDARD ?=DEFAULT
* ?BGA_SPA =DEFAULT
0.100 MM* ?DEFAULT
NC_UART5_TXDTCF_VERSION
051-9385
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PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
SPACING
ELECTRICAL_CONSTRAINT_SET
HSIC
USB
ELECTRICAL_CONSTRAINT_SET PHYSICAL
NET_TYPE
SPACING
ELECTRICAL_CONSTRAINT_SET SPACING
NET_TYPE
Clock Signal Constraints
ELECTRICAL_CONSTRAINT_SET
SPI
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
ELECTRICAL_CONSTRAINT_SET SPACING
I2C
PHYSICAL
NET_TYPE
JTAG
SPACING
NET_TYPE
UART
PHYSICAL
SPACINGPHYSICAL
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
DWI
NET_TYPE
PHYSICAL
SPACING
NET_TYPE
I2S
NET_TYPE
SPACING
NET_TYPE
XTAL
ELECTRICAL_CONSTRAINT_SET
SPACINGPHYSICAL
PHYSICAL
ELECTRICAL_CONSTRAINT_SET
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL
SPACING
PHYSICAL
I1
I100
I101
I102
I103
I124
I125
I13
I130
I131
I14
I140
I141
I142
I143
I144
I145
I148
I149
I15
I150
I151
I152
I153
I156
I157
I158
I159
I16
I161
I162
I173
I174
I175
I176
I177
I178
I179
I180
I181
I182
I183
I184
I185
I186
I187
I188
I189
I190
I191
I192
I193
I194
I195
I196
I197
I198
I199
I2
I20
I226
I227
I228
I229
I230
I231
I232
I233
I234
I235
I236
I237
I240
I241
I242
I243
I244
I245
I246
I247
I256
I257
I258
I259
I260
I261
I262
I263
I264
I265
I266
I267
I268
I269
I270
I271
I3
I4
I5
I6
I61
I62
I63
I88
I89
I90
I92
I93
I94
I96
I98
I99
SYNC_DATE=11/30/2011SYNC_MASTER=MIKE
CONSTRAINTS: LOW SPEED BUS
* 4:1_SPACINGUSB **CLK * 3:1_SPACING
USB_90D * 90_OHM_DIFF
SPI * 2:1_SPACING*
* 3:1_SPACING*I2S
*UART_50S 45_OHM_SE
* 45_OHM_SEI2S_50S
* 5:1_SPACINGCRYSTAL *
2:1_SPACING*I2SI2S
SPI_50S 45_OHM_SE*
**DWI 2:1_SPACING
UART 3:1_SPACING**
TRAUTRAU 2:1_SPACING*
* 45_OHM_SEHSIC
2:1_SPACING*JTAG *
I2C ** 1.5:1_SPACING
* 45_OHM_SECLK_50S
4:1_SPACING**HSIC
** 2:1_SPACINGHSIC_RDY
* 45_OHM_SEI2C_50S
TS_E75_DPAIR2_NUSBUSB_90D
TS_E75_DPAIR2_PUSBUSB_90D
TS_E75_DPAIR1_NUSBUSB_90D
TS_E75_DPAIR1_PUSBUSB_90D
CONN_E75_DPAIR2_NUSBUSB_90D
CONN_E75_DPAIR2_PUSB_90D USB
CONN_E75_DPAIR1_NUSB_90D USB
CONN_E75_DPAIR1_PUSBUSB_90D
USB11_AP_BBMUX_PUSB_90D USB
USB_TS_BBMUX_NUSBUSB_90D
USB_TS_BBMUX_PUSB_90D USB
I2S0_CODEC_ASP_DINI2SI2S_50S
UART6_AP_TXDUARTUART_50S
UART2_TS_ACC_RXDUARTUART_50SUART2_TS_ACC_TXDUARTUART_50S
JTAG_AP_TCKJTAG
SPI1_CODEC_CS_LSPISPI_50S
SPI3_GRAPE_MOSISPISPI_50S
I2S3_CODEC_XSP_BCLKI2SI2S_50S
I2S2_BT_BCLKI2SI2S_50S
I2S2_BT_DINI2SI2S_50S
CONN_ISP1_CAM_FF_I2C_SCLI2C_50S I2C
UART3_BT_CTS_LUARTUART_50S
ISP0_CAM_RF_CCLKCLK_50S
ISP1_CAM_FF_CLK_RCLKCLK_50S
XTAL_AP_24M_OCRYSTALAP_24M_OCRYSTALPMU_XTALCRYSTALPMU_EXTALCRYSTAL
ISP1_CAM_FF_FILTCLKCLK_50S
ISP0_CAM_RF_CLKCLKCLK_50S
SPI3_GRAPE_MISOSPISPI_50S
JTAG_AP_TMSJTAG
UART1_BB_RXDUARTUART_50S
SPI2_IPC_MISOSPISPI_50S
SPI3_GRAPE_CS_LSPISPI_50S
UART3_BT_RTS_LUARTUART_50S
I2S2_BT_LRCKI2SI2S_50S
I2S2_BT_DOUTI2SI2S_50S
I2S0_CODEC_ASP_LRCKI2SI2S_50S
I2S3_CODEC_XSP_DINI2SI2S_50S
I2S0_CODEC_ASP_BCLKI2SI2S_50S
I2S0_CODEC_ASP_DOUTI2SI2S_50S
SPI3_GRAPE_SCLKSPISPI_50S
ISP0_CAM_RF_CLK_RCLKCLK_50S
JTAG_AP_TDIJTAG
I2S0_CODEC_ASP_SDOUTI2SI2S_50S
I2S0_CODEC_XSP_SDOUTI2SI2S_50S
DWI_AP_DIDWI
SPI2_IPC_SCLKSPISPI_50S
DWI_AP_DODWI
SPI2_IPC_MOSISPISPI_50S
I2S0_CODEC_ASP_MCK_RI2SI2S_50S
I2S0_CODEC_ASP_MCK_RI2SI2S_50S
UART1_BB_TXDUARTUART_50S
SPI1_CODEC_SCLKSPISPI_50S
SPI1_CODEC_MOSISPISPI_50S
SPI1_CODEC_MISOSPISPI_50S
GPIO_BB_HSIC_RESUMESPISPI_50S
UART3_BT_RXDUARTUART_50S
UART1_BB_CTS_LUARTUART_50S
UART4_WLAN_RXDUARTUART_50SUART4_WLAN_TXDUARTUART_50S
UART6_AP_RXDUARTUART_50S
CONN_I2C2_SCL_3V0I2C_50S I2C
ISP1_CAM_FF_I2C_SDAI2CI2C_50S
I2C0_SCL_1V8I2C_50S I2C
I2C1_SDA_1V8I2CI2C_50S
CONN_I2C1_SCL_1V8I2C_50S I2C
CONN_ISP0_CAM_RF_I2C_SDAI2C_50S I2C
DWI_AP_CLKDWI
I2S3_CODEC_XSP_DOUTI2S_50S I2S
I2S3_CODEC_XSP_LRCKI2SI2S_50S
I2S0_CODEC_ASP_MCKI2SI2S_50S
XTAL_AP_24M_ICRYSTAL
UART1_BB_RTS_LUARTUART_50S
UART3_BT_TXDUARTUART_50S
I2C1_SCL_1V8I2CI2C_50SI2C0_SDA_1V8I2CI2C_50S
I2C2_SCL_3V0I2CI2C_50S
ISP0_CAM_RF_I2C_SDAI2CI2C_50SISP1_CAM_FF_I2C_SCLI2C_50S I2C
CONN_I2C1_SDA_1V8I2CI2C_50S
CONN_I2C2_SDA_3V0I2C_50S I2CCONN_ISP0_CAM_RF_I2C_SCLI2C_50S I2C
CONN_ISP1_CAM_FF_I2C_SDAI2C_50S I2C
ISP0_CAM_RF_FILTCLKCLK_50S
ISP1_CAM_FF_CCLKCLK_50S
ISP1_CAM_FF_CLKCLKCLK_50SCONN_ISP1_CAM_FF_CLKCLKCLK_50S
CONN_ISP0_CAM_RF_CLKCLKCLK_50S
I2S0_CODEC_ASP_MCKI2SI2S_50S
ISP0_CAM_RF_I2C_SCLI2CI2C_50S
PMU_GPIO_CLK_32K_WLANCLKCLK_50S
PMU_GPIO_CLK_32K_GRAPECLKCLK_50S
HSIC3_BB_DATAHSICHSIC
HSIC1_WLAN_DATAHSICHSIC
HSIC3_BB_STBHSICHSIC
HSIC1_WLAN_STBHSICHSICGPIO_BB_HSIC_DEV_RDYHSIC HSIC_RDYGPIO_BB_HSIC_HOST_RDYHSIC HSIC_RDYGPIO_WLAN_HSIC_HOST_RDYHSIC HSIC_RDYGPIO_WLAN_HSIC_HOST_RDYHSIC HSIC_RDYGPIO_WLAN_HSIC_DEV_RDYHSIC HSIC_RDY
I2C2_SDA_3V0I2CI2C_50S
USB_AP_NUSB_90D USB
USB_AP_PUSB_90D USB
USB_BBMUX_BB_NUSB_90D USB
USB_BBMUX_BB_PUSBUSB_90D
USB11_AP_BBMUX_NUSBUSB_90D
JTAG_AP_TRST_LRST
TP_JTAG_AP_TDOJTAG
051-9385
A.0.0
151 OF 154
36 OF 39
25
25
25
25
24 25
24 25
24 25
24 25
4 25
25
25
5 18
5 25
5 25
5 25
4 25
5 18
5 16
5 18
5 14
5 14
20 22
5 14
22
7
4
4
29
29
22
7 22
5 16
4 25
5 25 26
5 16
5 14
5 14
5 14
5 18
5 18
5 18
5 18
5 16
7
4
18
5 30
5 30
5 18 36
5 18 36
5 25 26
5 18
5 18
5 18
5 26
5 14
5 26
5 14
5 14
5 25
20 22
7 22
5 19 25 30
5 22
20 22
20 22
5 30
5 18
5 18
5 36
4
5 26
5 14
5 22
5 19 25 30
5 22
7 22
7 22
20 22
20 22
20 22
20 22
22
22
7 22
20 22
20 22
5 36
7 22
14 30
17 30
4 26
4 14
4 26
4 14
5 26
5 26
5 14 36
5 14 36
5 14
5 22
4 25
4 25
25 26
25 26
4 25
4 10 39
4
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
BACKLIGHT
ELECTRICAL_CONSTRAINT_SET
.
TEMP SENSORS
PHYSICAL
NET_TYPE
SPACING
SPACING
NET_TYPE
PHYSICALELECTRICAL_CONSTRAINT_SET
SPACING
MIPI
PHYSICALELECTRICAL_CONSTRAINT_SET
SPACINGPHYSICAL
NET_TYPE
NET_TYPE
SPACINGPHYSICALELECTRICAL_CONSTRAINT_SET
EMBEDDED DISPLAYPORT
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
AUDIO/SPEAKER
I311
I312
I315
I316
I342
I343
I345
I346
I347
I348
I354
I356
I394
I395
I414
I415
I435
I436
I437
I438
I439
I440
I441
I442
I443
I444
I445
I446
I447
I448
I449
I450
I451
I452
I453
I454
I455
I456
I457
I458
I459
I460
I461
I462
I463
I464
I465
I482
I483
I484
I485
I486
I487
I488
I489
I490
I491
I492
I493
I494
I495
I496
I497
I498
I499
I500
I501
I502
I503
I504
I505
I518
I519
I520
I521
I558
I560
I564
I565
I569
I570
I572
I574
I576
I577
I578
I579
I580
I581
I582
I583
I584
I585
I586
I587
I588
I589
I590
I591
I592
I593
I594
I595
I596
I597
I598
I599
I600
I601
I602
I603
I604
I605
I606
I607
I608
I609
I610
I611
90_OHM_DIFF*MIPI_90D
3:1_SPACING**BOARD_TEMP
3:1_SPACINGAUDIO **
90_OHM_DIFFEDP_90D *
EDP ** 4:1_SPACING
45_OHM_SEEDP_50S *
* 4:1_SPACING*MIPI0C
4:1_SPACING*MIPI1C *
* DELDEL
3:1_SPACING**LEDB
** 3:1_SPACINGLEDA
*BOARD_TEMP TEMP_SENSE
CONSTRAINTS: DISPLAY/AUDIOSYNC_MASTER=MIKE SYNC_DATE=11/30/2011
BOARD_TEMP1BOARD_TEMP
BOARD_TEMP8_NBOARD_TEMP BOARD_TEMP
BOARD_TEMP BOARD_TEMP BOARD_TEMP5_P
BOARD_TEMPBOARD_TEMP BOARD_TEMP6_NBOARD_TEMP BOARD_TEMP BOARD_TEMP6_P
BOARD_TEMP4_PBOARD_TEMPBOARD_TEMP
AUDIOAUDIO_DIFF SPKR_L_VSENSE_P_FILT
EDP_90D EDP CONN_EDP_DATA_EMI_N<3>
EDP_90D EDP CONN_EDP_DATA_EMI_N<2>
EDP_90D EDP CONN_EDP_DATA_EMI_P<3>
EDP_90D EDP CONN_EDP_DATA_EMI_P<1>EDP_90D EDP CONN_EDP_DATA_EMI_N<0>EDP_90D EDP CONN_EDP_DATA_EMI_P<0>
EDP_90D EDP CONN_EDP_AUX_EMI_P
EDP_90D EDP CONN_EDP_AUX_EMI_N
EDP_90D EDP EDP_DATA_EMI_N<3>
EDP_90D EDP EDP_DATA_EMI_P<0>EDP_90D EDP EDP_AUX_EMI_N
EDP_90D EDP EDP_DATA_N<3>EDP_90D EDP EDP_DATA_P<3>EDP_90D EDP EDP_DATA_N<2>EDP_90D EDP EDP_DATA_P<2>
EDP_90D EDP EDP_DATA_P<1>
EDP_90D EDP EDP_DATA_N<1>
EDP_90D EDP EDP_DATA_P<0>
EDP_90D EDP EDP_DATA_N<0>
EDP_50S EDP EDP_HPDEDP_90D EDP EDP_AUX_NEDP_90D EDP EDP_AUX_P
MIPI1C_CAM_FF_DATA_N<0>MIPI1CMIPI_90D
BOARD_TEMP BOARD_TEMP2
LED_IO_1_BLED LEDB
LED_IO_6_BLEDBLED
LED_IO_5_BLEDBLED
LED_IO_3_BLEDBLED
LED_IO_3_ALEDALED
LED_IO_2_BLED LEDB
LED_IO_2_ALED LEDA
LED_IO_1_ALED LEDA
LED_IO6_A_RLEDALED
LED_IO5_B_RLEDBLED
LED_IO3_A_RLEDALED
LED_IO2_A_RLEDALEDLED_IO2_B_RLEDBLED
LED_IO1_B_RLEDBLED
LED_IO1_A_RLEDALED
BOARD_TEMP4_NBOARD_TEMP BOARD_TEMP
BOARD_TEMP3_PBOARD_TEMPBOARD_TEMP
MIPI0C_CAM_RF_CLK_PMIPI0CMIPI_90D
MIPI0C_CAM_RF_DATA_N<1>MIPI0CMIPI_90D
MIPI0C_CAM_RF_CLK_NMIPI0CMIPI_90DMIPI0C_CAM_RF_DATA_P<0>MIPI0CMIPI_90DMIPI0C_CAM_RF_DATA_N<0>MIPI0CMIPI_90DMIPI0C_CAM_RF_DATA_P<1>MIPI0CMIPI_90D
MIPI0C_CAM_RF_CLK_F_PMIPI0CMIPI_90D
MIPI0C_CAM_RF_DATA_F_N<1>MIPI0CMIPI_90D
MIPI1CMIPI_90D MIPI1C_CAM_FF_CLK_F_P
MIPI1C MIPI1C_CAM_FF_DATA_F_N<0>MIPI_90D
MIPI0C_CAM_RF_DATA_F_P<0>MIPI0CMIPI_90DMIPI0C_CAM_RF_DATA_F_N<0>MIPI0CMIPI_90D
MIPI1C MIPI1C_CAM_FF_CLK_PMIPI_90D
MIPI0C_CAM_RF_DATA_F_P<1>MIPI0CMIPI_90D
MIPI1CMIPI_90D MIPI1C_CAM_FF_DATA_F_P<0>
AUDIO SPKR_L_SES_NAUDIO_DIFF
MIPI1C_CAM_FF_DATA_P<0>MIPI1CMIPI_90D
MIPI0CMIPI_90D MIPI0C_CAM_RF_CLK_F_N
USB_90D USB L81_MBUS_N
USB_90D USB MIKEY_TS_P
AUDIO SPKR_L_SES_PAUDIO_DIFF
SPKR_L_VSENSE_N_FILTAUDIO_DIFF AUDIO
EDP_90D EDP EDP_DATA_EMI_P<1>EDP_DATA_EMI_N<1>EDP_90D EDP
EDP_DATA_EMI_P<2>EDP_90D EDP
EDP_90D EDP_DATA_EMI_N<2>EDP
EDPEDP_90D EDP_DATA_EMI_P<3>MIPI1C_CAM_FF_CLK_NMIPI1CMIPI_90D
MIPI1CMIPI_90D MIPI1C_CAM_FF_CLK_F_N
EDP_90D EDP EDP_AUX_EMI_P
EDP_90D EDP EDP_DATA_EMI_N<0>
LED_IO_6_ALEDALED
LED_IO_5_ALEDALED
LED_IO_4_ALEDALEDLED_IO_4_BLEDBLED
EDP_90D EDP CONN_EDP_DATA_EMI_N<1>
EDP_90D EDP CONN_EDP_DATA_EMI_P<2>
BOARD_TEMP8_PBOARD_TEMPBOARD_TEMP
BOARD_TEMP7_NBOARD_TEMPBOARD_TEMP
BOARD_TEMP7_PBOARD_TEMPBOARD_TEMP
BOARD_TEMP5_NBOARD_TEMP BOARD_TEMP
BOARD_TEMP BOARD_TEMP3_NBOARD_TEMP
AUDIO_DIFF L81_AIN2_NAUDIO
USB_90D USB L81_MBUS_P
USB_90D USB MIKEY_TS_N
AUDIO SPKR_R_SES_PAUDIO_DIFF
AUDIO SPKR_R_SES_NAUDIO_DIFF
SPKR_R_VSENSE_N_FILTAUDIOAUDIO_DIFF
SPKR_L_VSENSE_PAUDIOAUDIO_DIFF
SPKR_L_VSENSE_NAUDIO_DIFF AUDIO
SPKR_R_CONN_NSPEAKER AUDIO
SPEAKER AUDIO SPKR_R_FLRSPEAKER AUDIO SPKR_L_FLR
SPKR_R_NSPEAKER AUDIO
SPKR_R_PAUDIOSPEAKER
SPKR_R_VSENSE_NAUDIOAUDIO_DIFF
SPKR_R_VSENSE_P_FILTAUDIOAUDIO_DIFF
AUDIO SPKR_R_VSENSE_PAUDIO_DIFF
SPKR_L_CONN_NAUDIOSPEAKER
L81_AIN2_PAUDIOAUDIO_DIFF
AUDIO_DIFF AUDIO HP_MIC_NAUDIOAUDIO_DIFF HP_MIC_P
SPKR_L_PAUDIOSPEAKERSPKR_L_NAUDIOSPEAKER
SPKR_L_CONN_PAUDIOSPEAKER
SPKR_R_CONN_PSPEAKER AUDIO
LED_IO3_B_RLED LEDB
LED_IO4_A_RLEDALEDLED_IO4_B_RLEDBLED
LED LED_IO5_A_RLEDA
LED_IO6_B_RLED LEDB
051-9385
A.0.0
152 OF 154
37 OF 39
30 32
30
30
30
30
30
19
15
15
15
15
15
15
15
15
15
15
15
7 15
7 15
7 15
7 15
7 15
7 15
7 15
7 15
7 15
7 15
7 15
7 21
30 32
15 30
15 30
15 30
15 30
15 30
15 30
15 30
15 30
30
30
30
30
30
30
30
30
30
7 21
7 21
7 21
7 21
7 21
7 21
20 21
20 21
20 21
20 21
20 21
20 21
7 21
20 21
20 21
19
7 21
20 21
18
18 25
19
19
15
15
15
15
15 7 21
20 21
15
15
15 30
15 30
15 30
15 30
15
15
30
30
30
30
30
18
18
18 25
19
19
19
19
19
19
19
19
19
19
19
19
19
19
18
18
18
19
19
19
19
30
30
30
30
30
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
WIFI
ELECTRICAL_CONSTRAINT_SET
ELECTRICAL_CONSTRAINT_SET
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACINGPHYSICAL
SPACING
NET_TYPE
DDR VREF
DDR
PHYSICAL
ELECTRICAL_CONSTRAINT_SET PHYSICAL
NET_TYPE
SPACING SPACING
NET_TYPE
PHYSICAL
NAND
I120
I121
I122
I123
I124
I125
I126
I128
I131
I133
I135
I136
I137
I138
I139
I140
I141
I142
I143
I144
I146
I148
I149
I150
I151
I152
I154
I156
I160
I166
I167
I168
I169
I170
I171
I172
I173
I174
I175
I176
I177
I178
I179
I180
I181
I182
I183
I184
I185
I186
I188
I189
I190
I191
I192
I193
I194
I195
I196
I197
I198
I199
I200
I201
I202
I203
I204
I205
I206
I208
I209
I210
I211
I212
I213
I214
I215
I216
I217
I218
I219
I220
I221
I222
I223
I224
I225
I226
I228
I229
I230
I231
I232
I233
I234
I235
I236
I237
I238
I239
I240
I241
I242
I243
I244
I245
I246
I247
I248
I249
I250
I251
I37
I38
I39
I41
I43
I44
I47
I48
I68
I69
I70
I71
I72
I73
I74
I75
I76
I77
I78
45_OHM_SENAND_50S *
DDR ** 3:1_SPACING
5:1_SPACINGVREF **
DDR_50S * DDR_45_OHM_SE
*DDR_90D DDR_90_OHM_DIFF
*WIFI_PWR100 WIFI_PWR100**NAND1 2:1_SPACING
* S05_IFIWS05_IFIW
WIFI_PWR1000 * WIFI_PWR1000
CONSTRAINTS: DDR/FMISYNC_DATE=11/30/2011SYNC_MASTER=MIKE
NAND0 2:1_SPACING**
DDR DDR0_ZQDDR_50S
DDR DDR0_CSN<2..0>DDR_50S
DDRDDR_50S DDR0_CKE<1..0>DDR DDR0_CK_NDDR_90D
DDR DDR0_CK_PDDR_90D
NAND_50S FMI0_AD<0>NAND0
NAND0NAND_50S FMI0_AD<3>FMI0_AD<4>NAND_50S NAND0
NAND_50S NAND1 FMI1_RE_L
NAND_50S TP_FMI1_CE5_LNAND1
NAND_50S FMI1_CLENAND1
NAND_50S TP_FMI0_CE1_LNAND0
NAND0 FMI0_AD<7>NAND_50S
FMI0_CE0_LNAND_50S NAND0
FMI0_ALENAND0NAND_50S
FMI0_AD<6>NAND_50S NAND0
NAND_50S NAND0 FMI0_DQS
NAND_50S TP_FMI1_CE2_LNAND1
FMI1_CE0_LNAND1NAND_50S
TP_FMI1_CE7_LNAND1NAND_50S
NAND_50S TP_FMI1_CE6_LNAND1
FMI0_CLENAND_50S NAND0
NAND1 FMI1_AD<4>NAND_50S
NAND_50S NAND1 FMI1_AD<5>NAND_50S NAND1 FMI1_AD<6>
NAND1 FMI1_ALENAND_50S
NAND_50S NAND1 FMI1_AD<7>
TP_FMI0_CE6_LNAND0NAND_50S
NAND0 TP_FMI0_CE2_LNAND_50S
TP_FMI0_CE7_LNAND0NAND_50S
FMI0_AD<5>NAND_50S NAND0
NAND_50S FMI1_WE_LNAND1
NAND_50S FMI1_AD<3>NAND1
FMI1_AD<2>NAND1NAND_50S
NAND1 FMI1_AD<1>NAND_50S
FMI1_AD<0>NAND_50S NAND1
NAND0NAND_50S FMI0_WE_L
NAND_50S NAND0 FMI0_RE_L
DDRDDR_50S DDR0_DQ<31..24>
DDR0_DQS_N<3>DDRDDR_90D
DDR DDR0_DQ<15..8>DDR_50S
DDRDDR_90D DDR1_CK_P
DDRDDR_50S DDR2_CA<9..0>
DDR DDR1_DQ<15..8>DDR_50S
DDR DDR1_DQS_P<0>DDR_90D
DDR DDR1_DQS_N<0>DDR_90D
DDR DDR1_DQS_N<2>DDR_90D
DDR DDR1_DQS_N<3>DDR_90D
DDR DDR0_DQS_P<3>DDR_90D
DDRDDR_50S DDR1_DM<3..0>
DDRDDR_50S DDR2_DM<3..0>
DDR DDR2_DQS_P<0>DDR_90D
DDR DDR2_DQS_N<0>DDR_90D
DDR DDR1_DQS_P<1>DDR_90D
DDRDDR_90D DDR2_CK_P
DDR DDR3_ZQDDR_50S
DDR DDR2_DQS_N<1>DDR_90D
DDR DDR2_DQS_P<1>DDR_90D
DDR DDR2_DQ<15..8>DDR_50S
DDRDDR_50S DDR2_DQ<7..0>DDRDDR_50S DDR2_ZQ
DDR DDR2_DQ<31..24>DDR_50S
DDR DDR3_DQS_P<0>DDR_90D
DDR DDR3_CKE<1..0>DDR_50S
DDR DDR3_CK_NDDR_90D
DDR DDR3_CK_PDDR_90D
DDR DDR3_DQS_N<0>DDR_90D
DDR DDR2_DQS_N<2>DDR_90D
DDR DDR2_DQ<23..16>DDR_50S
DDR DDR2_DQS_P<3>DDR_90D
DDR DDR2_DQS_P<2>DDR_90D
DDR DDR3_DQS_N<2>DDR_90DPPVREF_DDR2_CAPPVREF_DDR2_DQ
PPVREF_DDR3_DQPPVREF_DDR3_CA
PPVREF_DDR1_CAPPVREF_DDR1_DQ
PPVREF_DDR0_DQPPVREF_DDR0_CA
DDRDDR_90D DDR0_DQS_P<2>
DDR DDR1_DQS_P<2>DDR_90D
DDR DDR2_CSN<2..0>DDR_50S
DDR DDR2_DQS_N<3>DDR_90D
DDR DDR3_CA<9..0>DDR_50S
DDR DDR3_DM<3..0>DDR_50S
DDR DDR3_CSN<2..0>DDR_50S
DDR DDR3_DQ<7..0>DDR_50S
DDR DDR3_DQS_P<1>DDR_90D
DDRDDR_50S DDR3_DQ<15..8>
DDR DDR3_DQS_N<1>DDR_90D
DDR DDR3_DQS_P<2>DDR_90D
DDRDDR_50S DDR3_DQ<23..16>
DDRDDR_50S DDR3_DQ<31..24>DDR DDR3_DQS_P<3>DDR_90D
DDR DDR3_DQS_N<3>DDR_90D
DDR DDR0_DM<3..0>DDR_50S
DDR DDR0_CA<9..0>DDR_50S
DDR DDR0_DQS_P<0>DDR_90D
DDRDDR_50S DDR1_CA<9..0>
DDRDDR_50S DDR1_DQ<7..0>
DDR DDR2_CKE<1..0>DDR_50S
DDR DDR1_DQS_P<3>DDR_90D
DDR DDR1_DQ<31..24>DDR_50S
DDR DDR1_ZQDDR_50S
DDR DDR1_CSN<2..0>DDR_50S
DDR DDR0_DQS_N<0>DDR_90D
DDR DDR0_DQ<7..0>DDR_50S
DDRDDR_90D DDR0_DQS_N<2>
DDRDDR_50S DDR0_DQ<23..16>DDR DDR0_DQS_N<1>DDR_90D
DDR DDR0_DQS_P<1>DDR_90D
DDR DDR2_CK_NDDR_90D
DDR DDR1_DQ<23..16>DDR_50S
DDR DDR1_DQS_N<1>DDR_90D
DDRDDR_90D DDR1_CK_N
NAND_50S FMI0_AD<1>NAND0
NAND0NAND_50S FMI0_AD<2>
TP_FMI0_CE3_LNAND0NAND_50STP_FMI0_CE4_LNAND0NAND_50S
NAND_50S TP_FMI0_CE5_LNAND0
NAND_50S NAND1 FMI1_DQS
DDRDDR_50S DDR1_CKE<1..0>
NAND1NAND_50S TP_FMI1_CE4_L
WIFI_50S 50_WLAN_G
WIFI_50S 50_WIFI_ANT_FD_1
WIFI_50S 50_WIFI_ANT_FD
WIFI_50S 50_WIFI_ANT_FD_2WIFI_50S 50_WLAN_A_DIPLX
WIFI_50S 50_WLAN_A
WIFI_50S 50_WLAN_G_1
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Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.
124578
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NOTICE OF PROPRIETARY PROPERTY:
PAGE
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
DSIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
RST
ELECTRICAL_CONSTRAINT_SET PHYSICAL
NET_TYPE
GND
SPACING
SPACING
NET_TYPE
PHYSICALELECTRICAL_CONSTRAINT_SET
PWR
VOLTAGE SPACING
NET_TYPE
PHYSICAL
I1
I10
I11
I12
I13
I14
I15
I16
I165
I166
I167
I168
I169
I17
I170
I171
I172
I173
I174
I175
I176
I177
I178
I179
I18
I181
I182
I183
I19
I199
I2
I20
I200
I203
I207
I21
I217
I22
I221
I222
I223
I224
I225
I226
I227
I23
I24
I25
I26
I28
I29
I3
I30
I31
I32
I33
I34
I35
I36
I37
I38
I39
I4
I40
I41
I42
I43
I44
I45
I46
I47
I49
I5
I50
I51
I52
I53
I54
I55
I56
I57
I58
I59
I6
I60
I61
I64
I67
I68
I69
I7
I70
I71
I72
I73
I74
I75
I76
I8
I9
PP_PWR PWR_PMU*
* 4:1_SPACING*RST
* GND_PHGND*PWR * 3:1_SPACING
CONSTRAINTS: POWER / GNDSYNC_DATE=11/30/2011SYNC_MASTER=MIKE
PPVREF_DDR3_CAPWRPP_PWR0.6V
DAC_AP_VREFPWRPP_PWR
PP_PWR4.6V BATT_POS_RCPWR
PWR PP_WLAN_VDDIO_1V81.8V PP_PWR
BATT_VCC_WLAN4.6V PP_PWR PWR
PWRPP_PWR3.55V LDO10
LDO53.2V PWRPP_PWR
PP_PWR PWR PP1V21.2V
PWRPP_PWR5.25V PP5V25_VLCM1
PWRPP_PWR BUCK0A_LX11.1V
1.1V PWRPP_PWR BUCK0A_LX0
PPLED_BACK_REG_A20.4V PP_PWR PWR
PWRPP_PWR3.3V PP3V3_S0_LCD_FERR
PPVREF_DDR0_DQPWRPP_PWR0.6V
PPVREF_DDR2_DQPP_PWR0.6V PWR
PPVBUS_USB_EMIPWR6V PP_PWR
PPVREF_DDR0_CAPWRPP_PWR0.6V
PPVREF_DDR3_DQPWRPP_PWR0.6V
PP_PWR PPVREF_DDR2_CA0.6V PWR
PPVREF_DDR1_DQPP_PWR0.6V PWR
PPVREF_DDR1_CAPP_PWR0.6V PWR
PP_PWR PWR1.8V PP1V8_PL0_F
PP_PWR PWR1.1V PP1V1_CPU1
PWR6.0V PP_PWR PP6V0_LCM_VBOOST
PP_PWR PWR PP1V8_ALWAYS1.8V
PWR3.0V PP_PWR PP3V0_SENSOR
PP_PWR PWR PP3V2_S2R_USBMUX3.0V
PP_PWR PWR3.0V PP3V0_S2R_HALLPP_PWR3.3V PWR PP3V3_ACC
PP_PWR1.7V PWR PP1V7_VA_VCPPP_PWR PWR3.0V PP3V0_GRAPE
PP_PWR1.1V PWR BUCK5_FB
PP_PWR PWR1.2V PP1V2_S2R
PP_PWR1.8V PWR BUCK3_FB
1.1V PWRPP_PWR PP1V1_CPUB
PWRPP_PWR1.1V BUCK0C_LX0PP_PWR PWR1.1V PP1V1_CPU1_FET
1.1V PP_PWR PWR BUCK0B_LX1
1.1V PP_PWR PWR BUCK0B_FB
1.1V PWRPP_PWR BUCK0B_LX0PP1V1_CPU0_FET1.1V PWRPP_PWR
PWR1.1V PP_PWR BUCK0A_FB
PWRPP_PWR1.2V BUCK2_LX0
PWRPP_PWR1.2V BUCK2_LX1
PWRPP_PWR1.2V PP1V2_SOCBUCK3_LX0PP_PWR1.8V PWR
BUCK4_LX0PP_PWR1.2V PWRBUCK4_FBPP_PWR PWR1.2V
PP_PWR PWR3.3V PP3V3_OUT
PWR PP2V8_CAMPP_PWR2.8V
PP_PWR PWR1.0V PP1V0
PWR PP1V8PP_PWR1.8V
PP_PWR1.8V PWR PP1V8_GRAPE
PP_PWR1.8V PP1V8_DP_AVDD_AUXPWR
20.4V PP_PWR PWR PPLED_OUT_APP_PWR PWR20.4V PPLED_OUT_B
PWRPP_PWR6.0V LCM_LX
PWRPP_PWR1.1V BUCK5_LX0
PP_PWR PWR PP1V1_SRAM1.1V
PP_PWR PWR DSP_SW
PWRPP_PWR4.7V PPVCC_MAINPWRPWR5004.2V PPBATT_VCC
1.8V PP_PWR PWR PP1V8_EDP_AVDD_AUX
PP3V3_LCDVDD_SW_FPP_PWR3.3V PWR
PP_PWR PWR3.0V PP3V0_IO
RST RST_PMU_IN
PP_PWR6.0V PP6V0_LCM_HIPWR
RST RST_WLAN_L
RST SIMCRD_RST
PP_PWR PWR1.2V BUCK2_FB
PP_PWR PWR1.0V PP1V0_MIPI_PLL_F
PWRPP_PWR1.1V PP1V1_CPU0
PP1V8_S2RPP_PWR PWR1.8V
1.1V PWRPP_PWR BUCK0C_FB
RST UD881_RST
RST UD882_RST
GRAPE RST_GRAPE_L
RST RST_L63_L
RST RST_DET_LRST RST_BT_LRST RST_BB_PMU_LRST GPIO_BB_RST_LRST RST_AP_LRST RST_AP_1V8_LRST JTAG_AP_TRST_LRST GSM_TXBURST_INDRST DEBUG_RST_LRST DBG_RSTRST BB_TRST_L
VOLTAGE=0V GNDGND GND_SPKR_AMP2
VOLTAGE=0V GNDGND AGND_U3000
VOLTAGE=0V GNDGND GND_AUDIO_CODEC
VOLTAGE=0V GNDGND GND_SPKR_AMP1
PPLED_BACK_REG_BPWR500 PWR20.4V
PP_PWR PWR1.2V BUCK2_LX2
PP3V2_S2R_USBMUXPP_PWR PWR3.0V
GNDGNDGNDVOLTAGE=0V
J2200_36_GNDVOLTAGE=0V GND GNDJ2200_29_GNDVOLTAGE=0V GNDGND
J2200_43_GNDVOLTAGE=0V GND GND
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11 38
11 38
4
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30 34
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30
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15 25 29 30 34
29 32 34
7
15
29 34
30
29
7
30 34
29 34
29
5 26
4 25 26 30
4 10 36
16
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15
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