EC2303-COMPUTER ARCHITECTURE AND ORGANIZATION

EC2303-COMPUTER ARCHITECTURE AND ORGANIZATION

SHANMUGANATHAN ENGINEERING COLLEGE(An ISO 9001:2008 Certified Institution)ARASAMPATTI 622507

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK(2 marks & 16 marks)

SUBJECT CODE:EC2303

SUBJECT NAME:COMPUTER ARCHITECTURE AND ORGANIZATION

YEAR / SEM :

III / V

PREPARED BY

B. MEENAKUMARI M.E., M.I.S.T.E.,AP/ECEV.SARANYA M.E., M.I.S.T.E.,AP/ECE

UNIT I INTRODUCTIONPART A

1. Name the functional units of a computer.The functional units of a computer are Input unit Output unit Control unit Memory unit Arithmetic and logic unit

2. What do you mean by Von-Neumann bottleneck?Because of the stored program architecture of Von-Neumann machine, the processor performance is tightly bound to the memory performance that is, since we need to access memory at least once per cycle to read an instruction the processor can only operate as fast as the memory. This is sometimes known as Von-Neumann bottleneck or memory wall.

3. What is meant by the stored-program concept? Discuss.According to stored-program concept memory can contain the program (Source code), the corresponding complied machine code, editor program and even the compiler that generated the machine code.

4. State and explain the performance equation.The average number of basic steps needed to execute one machine instruction is S, where each basic step is completed in one clock cycle. If the clock cycle rate is R cycles per second, the program execution time is given byT = (N*S)/RThis is often referred to as the basic performance equation.

5. What is a register?A group of flip flops connected together forms a register. A register is used solely for storing and shifting data which is in the form of 1s and/or 0s, entered from an external source.

6. Define priority encoder.A priority encoder is an encoder circuit that includes the priority function. In priority encoder, if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence.

7. What are the factors to be considered in selecting a number representation to be used in a computer? The number of types to be represented: for example, integers, real, float etc. The range of values likely to be encountered. The precision of the numbers, which refer to the maximum accuracy of the representation. The cost of the hardware required to store and process the numbers.

8. What is VLSI?VLSI stands for Very Large Scale Integration. It allows manufactures to fabricate a CPU, main memory or even all the electronic circuits of a computer, on a single IC.9. What is a data selector or multiplexer? And why it is called as data detector? Multiplexer is a digital switch. Particularly, it has 2n input lines and n selection lines , whose bit combinations determine which input line is selected and routed onto available only single output line. Hence multiplexer is a selector of one out of several data sources available at its input lines, to connect it to output line. Simply it is a many to one device and also called data selector.

10. Differentiate direct and indirect addressing modeIn direct addressing mode the address of the location of the operand is given explicitly as a part of the instruction. On the other hand , in indirect addressing mode, the effective address of the operand is the contents of a register or the main memory location. Whose address is given explicitly in the instruction.

11. Define underflow and overflow.Underflow: In a single precision, if the number requires an exponent less than -126 or in a double precision, if the number requires an exponent less than -1022 to represent its normalized form the underflow occurs.Overflow: In a single precision, if the number requires an exponent greater than +126 or in a double precision, if the number requires an exponent greater than +1023 to represent its normalized form the overflow occurs.

12. What are the various ways of representing the signed integers in the system.The ways to represent the signed integers in the system are: Sign-magnitude representation 1s complement 2s complement

13. Define IEEE floating point single and double precision standard.The 32-bit standard representation (single-precision representation) occupies a single 32-bit word. The 32-bits are divided into 3-fields as shown below: (Field 1) sign 1-bit (Field 2) exponent 8-bits (Field 3) mantissa 23-bitsThe 64-bit standard representation (double-precision representation) occupies two 32-bit words. The 32-bits are divided into 3-fields as shown below: (Field 1) sign 1-bit (Field 2) exponent 8-bits (Field 3) mantissa 52-bits

14. State the drawbacks of relative addressing.The main drawbacks of relative addressing are Need of extra logic circuits Extra time required to compute addresses

15. What is little-endian and big endian?When the lower byte addresses are used for the less significant bytes (the rightmost byte) of the word, addressing is called little-endian.When the lower byte addresses are used for the most significant bytes (the leftmost byte) of the word, addressing is called big endian.PART B

1. Explain the architecture of basic computer with neat diagram. 2. Define addressing mode. Classify addressing modes and explain each type with example. 3. i) What is a priority encoder? Design a 16-bit priority encoder using 2 8-bit priority encoder.ii) Design a 4-bit bidirectional shift register with parallel load and explain. 4. i) explain the 4-bit register level magnitude comparator with neat diagram. ii) Name and explain various special register in typical computer. 5. i) How does one detect and correct errors during data transmission. ii) Draw and explain different types of data representations. 6. i) Explain zero, one, two and three addressing instruction with example. ii) Explain the various instruction types.

UNIT IIDATA PATH DESIGNPART A

1. Define co-processor.Complicated arithmetic operations like exponentiation and trigonometric functions are costly to implement in CPU hardware, while software implementations of these operations are slow. In order to implement these special functions with low cost and fast hardware we have to use auxiliary processors called arithmetic co-processors are simply co-processors.

2. What are the two approaches to reduce the delay in address?The two approaches to reduce the delay in address are Carry look-ahead : it reduces the delay of adders from increasing linearly with the word size to increase as the logarithm of the word size Carry select adder: it divides the words to be added into blocks and forms two sums for each block in parallel (one with a carry in of zero and the other with a carry in of one). The carry output from the previous block controls a multiplexer that selects the appropriate sum.

3. What are two techniques to speed up the multiplication operation?The two techniques to speed up the multiplication operation are Bit Pair Recoding of Multipliers Array Multiplier

4. Write down the equations for carry generate and propogate.Pi = Ai BiGi = Ai Bi

5. What is a carry look ahead adder?The method of speeding up the addition process by eliminating inter-stage carry delay is called look-ahead carry addition and the circuit that performs such addition is called carry look-ahead adder.

6. What is a datapath?A processor consists of datapath( data processing) and control unit.The datapath performs all arithmetic and logic operations. Modern computers communicate and operate with binary numbers which use only the digits 0 and 1. The most common data type are fixed point and floating point numbers.

7. Discuss the role of booths algorithm in the design of fast multipliers.To speed up the multiplication process in the booths algorithm a technique called bit pair recoding is used. It is also called modified booths algorithm. It halves the maximum no of summands. In this technique, the booth recoded multiplier bits are grouped in pairs. Then each pair is represented by its equivalent single bit multiplier reducing total no of multiplier bits to half.

8. Discuss the principle behind the booths multiplier.Booths algorithm generates a 2n-bit product and treats both positive and negative numbers uniformly. This algorithm suggests that we can reduce the number of operations required for multiplication by representing multiplier as a difference between two numbers.

9. Write a rule for addition in floating point operation.

Step 1: select the number with a smaller exponent and shift its mantissa right , a number of steps equal to the difference in exponents (e2 e1 )Step 2: set the exponent of the result equal to the larger exponent.Step 3: perform addition/subtraction on the mantissas and determine the sign of the result/Step 4: normalize the result, if necessary

10. What is Von Neumann rounding?Von Neumann rounding is the simplest method of truncation If the bits to be removed are all 0s , they are simply removed, with no changes to the retained bits. However, if any of the bits to be removed are 1, the least significant bit of the retained bit is set to 1.11. When does imprecise exception arise?An imprecise exception is usually a catastrophic failure, where the processor cannot continue processing or allow a particular program or task to continue. It may arise because of two possibilities: The pipeline already may have already completed instructions that are later in program order than the instruction causing the exception. The pipeline may have not yet completed some instruction that is earlier in program order than the instruction causing the exception.

12. Why floating point is more difficult to represent and process than integer?In floating point numbers we have to represent any number in three fields sign, exponent and mantissa. The IEEE 754 standard gives the format for these fields and according to format the numbers are to be represented. in case of any process we have to consider mantissa and exponent separately. Therefore, floating point numbers are more difficult to represent and process than integer.

13. What is the purpose of guard bits used in floating point operation?The guard bits are the extra bits used in the intermediate calculations. The operand are used with the guard bits for calculations and then final result of calculation is truncated to create 24-bit number that approximates the longer final result. Hence, through these guard bits we can get maximum accuracy in the final result.14. What do you mean by end-around carry correction?In binary subtraction using 1s complement method, the carry is generated after addition of two numbers (minuend + 1s complement of subtrahend) is called end-around carry. It is necessary to add this carry in the addition to get the correct result. Such a correction is called end-around carry correction.

15. What is combinational multiplier or array multiplier?The multiplier which uses n shifts and adds operations to multiply n-bit binary number is called combinational multiplier or array multiplier.

PART B

1. Briefly explain the adder and subtractor circuits. 2. Explain in detail the principle of carry look-ahead adder. 3. Explain an algorithm to multiply two positive numbers. Also discuss the realization of a multiplier to implement the same. 4. Explain the Robertsons algorithm for 2complement multiplier and fraction with neat block diagram. 5. Describe in detail Booths multiplication algorithm and its hardware implementation.6. Explain non-restoring division algorithm with the help of suitable example. 7. Describe how the floating-point numbers are represented and used in digital arithmetic operations. Give an example.8. How different arithmetic and logic functions are realized and integrated in an ALU? Explain.9. Describe the basic structure of a pipeline processor and explain how it is carried out in a floating point adder.

UNIT IIICONTROL DESIGNPART A

1. What is the drawback of assigning one bit position to each control signal?Assigning individual bits to each control signal results in long micro instruction because the number of required signals is usually large. Moreover, only a few bits are set to 1 in any given microinstruction, which means the available bit spaces poorly used.

2. What is called static and dynamic branch prediction?The branch prediction decision is always the same every time a given instruction is executed. Any approach that has this characteristic is called static branch prediction. Another approach in which the prediction decision may change depending on execution history is called dynamic branch prediction.

3. Compare any two methods to design the hardwired controller.State Table Method: It is the standard algorithmic approach to sequential circuit design.Delay Element Method: It is a heuristic method based on the use of clocked delay elements for control signal timing.

4. What is the use of microassembler?A Microassembler is used to translate microprograms into executable programs that can be stored in the control memory.

5. Difference between Hardwired and Microprogrammed control unit.AttributeHardwired control Microprogrammed control

SpeedFastSlow

Control functionsImplemented in hardwareImplemented in software

FlexibilityNot flexible, to accommodate new system specifications or new instructionsMore flexible, to accommodate new system specification or new instructions redesign is required

Ability to handle large/complex instruction setsSomewhat difficultEasier

Ability to support operating systems and diagnostic featuresVery difficult (unless anticipated during design)Easy

6. What are the design methods for control units? State table method Delay-element method Sequence counter PLA

7. What is pipeline control?The term pipelining refers to the temporal overlapping of processing. Pipelines are nothing more than assembly lines in computing that can be used either for instruction processing or for performing any complex operation. To achieve pipelining, one must subdivide the input task into a sequence of subtask, each of which can be executed by a specialized hardware stage that operates concurrently with other stages in the pipeline.

8. What factors determine the length of the microinstruction? The maximum number of simultaneous micro-operations that must be specified, i.e., the degree of parallelism required at the micro-operation level. The way in which the control information is encoded. The way in which the address of the next instruction is specified.

9. What is superscalar and superscalar processor?Processors reach performance levels greater than one instruction per cycle by fetching, decoding executing several instructions concurrently. This mode of operation is called superscalar. A processor capable of parallel instruction execution and having performance level greater than one instruction per cycle is known as superscalar processor. 10. What is data hazard in pipelining? What are the solutions?When either the source or the destination operands of an instruction are not available at the time excepted in the pipeline and as a result pipeline is stalled, we say such a situation is a data hazard. The easiest way to handle data hazards is to stall the pipeline. The second simple hardware technique which can handle data hazard is called forwarding or register by passing.

11. What is structural hazard? The hazard that exist because of conflicts due to insufficient resources when even with all possible combination, it may not be possible to overlap the operation is called structural hazard.12. What is the ideal speed-up expected in a pipelined architecture with k stages? The speed-up factor of a k-stage pipeline over an equivalent non-pipelined processor is defined as It can be noticed that maximum speedup is Sk k as n . However, this maximum speed is very difficult to achieve because of data dependencies between successive task (instructions), program branches, interrupts and other factors. = If we assume that Tn = kTp, we have

13. Define pipelining.Pipelining is a technique of decomposing a sequential process into sub operations with each sub process being executed in a special dedicated segment that operates concurrently with all other segments.

14. What are the address-sequencing capabilities required in a control memory?Each microinstruction should explicitly or implicitly specify the next microinstruction to be used. Such address sequencing capabilities are required in a control memory.

15. What is a deadlock?A deadlock is a situation that can arise when two units, A and B, use a shared resource. Suppose that unit B cannot complete its task until unit A completes its task. At the same time, unit B has been assigned a resource that unit A needs. If this happens, neither unit can complete its task. Unit A is waiting for the resource it needs, which is being held by unit B. at the same time unit B is waiting for unit A to finish before it can release that resource.

PART B

1. Draw the diagram of the single bus organization of the data path inside a processor. Explain the above regarding execution.2. Explain the operation of Hardwired Control unit.3. With a neat diagram explain the basic organization of a microprogrammed control unit.4. Describe various factors that reduce the performance of pipelined CPU and the mechanisms used to overcome it.5. What do you mean by hazard? Explain the different types of hazards with the way and means of solving them.6. i) Describe the characteristics of super-scalar processing.ii) Write short notes on nanoprogramming.

UNIT IVMEMORY ORGANIZATIONPART A

1. What are asynchronous DRAMs?In asynchronous DRAMs, the timing of the memory is controlled asynchronously. A specialized memory controller circuit provides the necessary control signals RAS & CAS that govern the timing. The processor must take into account the delay in the response of the memory. Such memories are asynchronous DRAMs.

2. Define the terms: Spatial locality & Temporal locality.Locality of reference manifests itself in two ways: Temporal and spatial. The temporal means that a recently executed instruction is likely to be executed again very soon. The spatial means that instructions stored nearby to the recently executed instruction are also likely to be executed soon.

3. What is DRO and NDRO?In some memories reading the memory destroy the stored information. Such phenomenon is called Destructive Read Out (DRO). Memories in which reading does not affect the stored data have Non Destructive Read Out (NDRO).

4. Compare SRAM with DRAM.

Static RAM Dynamic RAM

Contains less memory cells per unit area.Contains more memory cells per unit area.

Less access time hence faster memories.More access time.

It has no. of flip-flops. Each flip-flop stores one bit.Stores data as a charge on the capacitor. Consists of MOSFET and Capacitor for each cell.

Refreshing circuitry is not required.Refreshing circuitry is required to maintain the charge on the capacitor after every few milliseconds. Extra hardware is required to control refreshing. This makes system design complicated.

Less cost.More cost.

5. What is meant by internal and external fragmentation? Unusable space within a partially filled page frame is called internal fragmentation and unusable space between occupied regions is called external fragmentation.

6. Define random access memory.The memory in which it is possible to access any memory location at random is called random access memory.

7. What are the advantages of using virtual memory? Virtual memory removes the programming burdens of a small, limited amount of main memory. It allows efficient and safe sharing of memory among multiple programs.

8. What is trace cache?It is an instruction cache in a microprocessor that stores dynamic instruction sequences after they have been fetched and executed in order to follow the instructions in subsequent times without needing to return to the regular cache or the memory for the same instruction sequence. An advantage of the trace cache is it reduces the required fetch bandwidth on the processing pipeline.9. Give the features of a ROM cell. It can hold one bit data. It can hold data even if power is turned off. We cant write data in ROM cell; it is read-only.

10. Compare SDRAM with DDR SDRAM.The standard SDRAM performs its operation on the rising edge of the clock signal. On the other hand, the DDR SDRAMs is same as that for standard SDRAM. However, since the transfer data on both the edges of the clock signal, their bandwidth is effectively double for long burst transfer.

11. What is mapping function?Usually, the cache memory can store a reasonable number of blocks at any given time, but this number is small compared to the total number of blocks in the main memory. The correspondence between the main memory blocks and those in the cache is specified by a mapping function.

12. Define locality of reference. What are its types?The program may contain the simple loop, nested loops, or a few procedures that repeatedly called each other. The point is that main instructions in localized area of the program are executed repeatedly during some time period and the remainder of the program is accessed relatively infrequently. This is referred to as locality of reference.

13. What is virtual memory?In the modern computers, the operating system moves program and data automatically between the main memory and secondary storage. Techniques that automatically swaps program and data blocks between main memory and secondary storage device are called virtual memory. The addresses that processor issues to access either instruction or data are called virtual or logical addresses.

14. What is TLB (Transition Look-aside Buffer)?To support demand paging and virtual memory processor has to access page table which is kept in the main memory. To avoid the less access time and degradation of performance, a small portion of the page table is accommodated in the memory management unit. This portion is called TLB (Transition Look-aside Buffer).

15. What is data stripping?In a RAID system, a single large file is stored in several separate disk units by breaking the file up into the number of smaller pieces and storing these pieces on different disks. This is called data stripping.

PART B

1. Explain in detail about the basic memory concepts?2. Draw the neat sketch of memory hierarchy and explain the need of cache memory.3. Write a note on Random Access Memories (RAM) and also explain in detail the internal organization of memory chip.4. i) Write a short note on synchronous DRAM.ii) What is a virtual memory?5. Write notes on RAID disk arrays.6. Describe in detail magnetic tape memories and disk memories.7. Why do we use cache memory and explain the different types of mapping functions with the necessary block diagrams.8. i) Describe in detail about associative memory.ii) Discuss the concept of memory interleaving and give its advantages.

UNIT VSYSTEM ORGANIZATIONPART A

1. What is called a bus master?The device that is allowed to initiate data transfers on the bus at any given time is called the bus master.

2. Draw the simple structure of an interface.

3. How do you handle simultaneous and multiple interrupts. It has to recognize the device requesting an interrupt. It has to obtain the starting address of interrupt service routine corresponds to interrupt request. Because each interrupt request has its own interrupt service routine. It has to allow the device to interrupt while another interrupt is being serviced. It has to take decision that which interrupt to be serviced first when there are simultaneous interrupt requests from two different devices.

4. What are the limitations of programmed I/O? The limitations of programmed I/O are: Programmed I/O requires that all I/O operations be executed under the direct control of the CPU. In programmed I/O, I/O device does not have direct access to main memory. Data transfer speed is low

5. Difference between memory mapped I/O and I/O mapped I/O.Memory mapped I/OI/O mapped I/O

Memory and I/O share the entire address range of processor.Processor provides separate address range for memory and I/O devices.

Usually, processor provides more address lines for accessing memory. Therefore more decoding is required control circuitsUsually, processor provides less address lines for accessing I/O. Therefore less decoding is required control circuits

Memory control signals are used to control read and write I/O operationsI/O control signals are used to control read and write I/O operations

6. What is an interrupt?An interrupt is an event that causes the execution of one program to be suspended and another program to be executed.

7. What are the possible data transfer modes available with pheripherals? Serial data transfer Parallel data transfer Interrupt driven data transfer Programmed I/O data transfer DMA controlled data transfer

8. Compare RISC and CISC architecture.CharacteristicsCISCRISC

Instruction sizeVariesFixed

Instruction length1,2,3,or 4 bytes4 bytes

Instruction decodingSerial (slow) to decodeEasy(quick) to decode

Addressing modesSupports complex addressing modes Complex addressing modes are synthesized in software

Instruction execution speedSlowMedium

9. What is meant by a multiple bus? Where it is organized?The need of high speed shared bus is impractical to satisfy with a single bus. Thus, most computer systems use the multiple buses. These busses have the hierarchical structure.

10. What is CISC and RISC?CISC is an acronym for complex instruction set computers or computing. It is based on the concept of using very large instruction set having simple as well as complex instructions and making instruction set more flexible to keep program length as small as possible.RISC refers to reduced instruction set computers or computing. RISC microprocessors are very different from CISC microprocessors. RISC use concept of keeping the instruction set as simple as possible to allow microprocessors program to be a written using a simple instruction.

11. Define parallel processing. Parallel processing is a term used to denote a large class of techniques that are used to provide simultaneous data processing tasks for the purpose of increasing the computational speed of the computer system. Instead of processing each instruction sequentially as in a conventional computer, a parallel processing system is able to perform concurrent data processing to achieve faster execution time.

12. What is plug and play technology?The plug and play technology means that a new device, such as an additional speaker or mouse or printer etc., can be connected at any time while the system is operating.

13. How does the processor handle an interrupt request? Processor identifies source of interrupt Processor obtains memory address of the interrupt handler PC and other processor status information are saved PC is loaded with address of interrupt handler and program control is transferred to interrupt handler

14. What is meant by bus arbitration?Bus arbitration is the process by which the next device to become the bus master is selected and bus mastership is transferred to it. The selection of bus master is usually done on the priority basis.

15. What is an non-maskable interrupt? What is the action performed on the receipt of a NMI?The interrupts which cannot be masked under software control are called Non Maskable Interrupts. Following actions performed on receipt of a NMI: Processor obtains memory address of interrupt handler of NMI PC and other processor status information are saved PC is loaded with address of interrupt handler of NMI and program control is transferred to interrupt handler

PART B

1. Explain various bus arbitration mechanisms in DMA transfer.2. Discuss the data transfer mechanisms of PCI bus.3. Describe the various mechanisms for accessing I/O devices.4. i) Comparison between programmed I/O and interrupt driven I/O.ii) Define Fault tolerance. How it is related to redundancy? Explain different approaches for designing fault tolerance systems.5. Explain DMA mode of data transfer.6. Differentiate between CISC and RISC.7. What are superscalar processors? Explain the typical structure of a typical superscalar processor.

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