can-pciel user's manual

PROPRIETARY NOTICE All rights reserved by Janz Tec AG. No parts of this technical manual may be modified, copied or reproduced in any form or by any means for commercial use without the prior written permission of Janz Tec AG, Germany. All instructions, information and specification contained in this manual are for reference only and remain subject to change without announcement.

CAN-PCIeL

PCIexpress CAN Interface

(Hardware Manual)

Version 1.1

refers to product revision no. V 2.0

Title: CAN-PCIeL User's Manual

File: j:\as\entwicklung\projekte\hw\pc\can-pciel\doc\manual\can-pciel.doc

Pattern:

Created: ime, 22.10.2008

Last Update: ime, 07.03.2013

© Janz Tec AG 2013 Im Doerener Feld 8 D-33100 Paderborn Tel.: +49-5251-1550-0

Fax: +49-5251-1550-190

Email: [email protected]

Internet: www.janztec.com

CAN-PCIeL (Hardware Manual) Introduction 1 - 3

Rev. 1.1 © Janz Tec AG

Contents

1 Introduction 6

1.1 Hardware Features .............................................................................................................. 6 1.2 Functional Overview ............................................................................................................ 6

2 Safety Instructions 8

2.1 Installation and Maintenance ............................................................................................... 8 2.2 Ambient and Environmental Conditions ............................................................................... 8

3 Installation 9

3.1 Handling Instructions ........................................................................................................... 9 3.2 Components and Jumper Locations ..................................................................................10 3.3 Connecting IO signals ........................................................................................................11 3.4 Software Considerations ....................................................................................................11 3.5 Finding Free Resources .....................................................................................................11 3.5.1 System BIOS ................................................................................................................12

4 Programming Information 13

4.1 PCI Bus configuration space ..............................................................................................13 4.2 CAN address space ...........................................................................................................14 4.3 On-board registers .............................................................................................................14 4.4 nvSRAM .............................................................................................................................15 4.5 Interrupt programming .......................................................................................................15 4.5.1 CAN Interrupts ..............................................................................................................15 4.5.2 Board Number ...............................................................................................................16 4.5.3 CAN Controller Reset ...................................................................................................16

5 Appendix 18

5.1 Technical Data ...................................................................................................................18 5.2 References .........................................................................................................................20 5.3 Product History...................................................................................................................20 5.4 Manual History ...................................................................................................................20

1 - 4 CAN-PCIeL (Hardware Manual) Introduction

© Janz Tec AG Rev. 1.1

List of Figures figure 1: CAN-PCIeL block diagram ......................................................................................................... 7 figure 2: Mounting of CAN-PCIx/EXTO on CAN-PCIeL ........................................................................... 9 figure 3: Component side of CAN-PCIeL ...............................................................................................10 figure 4: Bracket for CAN-PCIeL boards ................................................................................................11 figure 5: Interrupt scheme.......................................................................................................................15 figure 6: Physical Dimensions ................................................................................................................19

List of Tables table 1: CAN-PCIeL standard products .................................................................................................... 6 table 2: User jumper functions ................................................................................................................10



About this Manual This is the Hardware Manual for the CAN-PCIeL CAN fieldbus controller board for PCI Express. It gives all necessary information to users and programmers of the CAN-PCIeL. We try to keep it compact, so there are no special section for users and programmers. Users that are no programmers might therefore only read the first sections (Introduction and Installation), and come back to the detailed sections when they need a special information. In any case, this manual assumes that the users, especially programmers, are familiar with their job. We do not give basic information about programming, computer hardware or describe operation of bus-systems. You will find pointers to advance information in section 4.2. The manual starts of with some Introduction to the CAN-PCIeL. This is some prose that describes the features and architecture of the CAN-PCIeL. You should already know this if you have bought the board! It then discusses some topics about Installation and Configuration of the product. The rest of the manual will then cover technical details about the CAN-PCIeL.

Conventions If numbers are specified in this manual, they will be either decimal or hexadecimal. We use C-notation to identify hexadecimal numbers (the 0x prefix). If we refer to low active signal names, they will suffixed by a “#” character. Some parts of the manual contains notices you have to observe to ensure your personal safety, or to prevent damage to property. These are visually marked with the following alert symbols:

DANGER indicates that death or severe personal injury will result if proper precautions are not taken.

WARNING indicates that death or severe personal injury may result if proper precautions are not taken.

CAUTION indicates that minor personal injury can result if proper precautions are not taken.

NOTICE indicates that damage to equipment can result if proper precautions are not taken.

indicates information that we think you should have read to save your time by avoiding common problems. Important suggestions that should be followed will also be marked with this sign.

Acronyms and Abbreviations EMC Electromagnetic capability.

ESD Electrostatic discharge.

RO Read Only.

RW Read and Write.

WO Write Only.

PCI Peripheral Component Interconnect

1 - 6 CAN-PCIeL (Hardware Manual) Introduction


1 Introduction

The CAN-PCIeL is a PCI Express compatible add-in card that is equipped with one or two non-intelligent CAN Interfaces. To increase the number of CAN channels up to four, the expansion module CAN-PCIx/EXTO can be mounted on CAN-PCIeL. With the CAN-PCIeL, the system integrator is able to build low-cost CAN connections for industrial need.

Material-No. Product Description

BO-FPC-32001 CAN-PCIeL/1 Non-Intelligent CAN Interface for PCIe Systems; one SJA1000 CAN controller

BO-FPC-32002 CAN-PCIeL/1O Non-Intelligent CAN Interface for PCIe Systems; one isolated SJA1000 CAN controller

BO-FPC-32021 CAN-PCIeL/1 Non-Intelligent CAN Interface for PCIe Systems; two SJA1000 CAN controller

BO-FPC-32022 CAN-PCIeL/1O Non-Intelligent CAN Interface for PCIe Systems; two isolated SJA1000 CAN controller

BO-FPC-32122 CAN-PCIeL/1O/NV/EX Non-Intelligent CAN Interface for PCIe Systems; two isolated SJA1000 CAN controller. 128 KB nvSRAM. Expansion connector for CAN-PCIx/EXTO

BO-FPC-22040 CAN-PCIx/EXTO Expansion Module to add two additional isolated SJA1000 CAN controller interfaces to CAN-PCIH/PCIL/PCIeL.

table 1: CAN-PCIeL standard products

1.1 Hardware Features Non intelligent CAN fieldbus controller for PCI Express systems Short card form factor 1 Lane PCI Express Rev1.0a interface (PEX8112) Only one PCI Express slot is occupied

Up to four CAN Interfaces with SJA1000 CAN controllers 11bit ID and 29bit ID CAN specifications supported ISO/DIS 11898, optionally isolated 9pol. D-Sub connector for each CAN interface at PCI Express bracket

Since V2.0 there is an optional nvRAM

1.2 Functional Overview The CAN-PCIeL bridges the local CAN controllers to the PCI Express. It uses the PCI9030 universal PCI to “anybus“-bridge and the PEX8112 as a bridge between the PCI Bus and PCI Express. Therefore most electrical parameters of the CAN-PCIeL are determined by these chips. The PCI9030 provides all the logic for a 32bit PCI 2.2 target interface. When programming with the CAN-PCIeL, you should be familiar with PCI [1] and the PCI9030 [2] chip. Refer to figure 1 for a block diagram of the CAN-PCIeL.



The PEX8112 is loading its configuration from an external serial EEPROM. The PCI9030, and thereby the PCI interface, is also configured from a serial EEPROM device. This configuration data includes memory spaces, access timing and PCI parameters. When the configurations are done, the PCI9030 behaves like a proper PCI Bus device. The PCI base address registers are set up so that the PCI-BIOS can assign addressing space to the CAN-PCIeL. A CAN-PCIeL is uniquely identified by the Device ID and Vendor ID of the PCI9030 chip, the Subsystem ID and Subsystem Vendor ID of the CAN-PCIeL itself. The CAN controllers are attached to the local bus of the PCI9030, address mappings are arranged so that the registers of each CAN controller are visible to the PCI Bus memory space. Additionally, there are some local status registers (i.e. interrupt status register) that can also be accessed via PCI memory space. As all CAN interrupts on this card are sharing a single PCI interrupt line, an interrupt status is readable, so that the CAN-PCIeL driver can detect pending interrupts. To support more flexible control of the interrupts, each interrupt can be disabled or enabled individually.

bus 32bit

Local PCIbus

PC

I Exp

ress

car

d e

dge

con

nect

or

ISO/DIS11898

9 pin D-Sub connector


ISO/DIS11898

SJA1000

SJA1000

ControlLogic

PCIbusslave

adapterPCI9030

EEPROM

PCI registers

Local-conf. regs.

PCI ExpressBridge

PEX8112

EEPROM

PCI Express regs

PCI registers

PCI Express

32bit

PCIbus1x Lane

ISO/DIS11898



ISO/DIS11898

SJA1000

SJA1000

Expansion modul

figure 1: CAN-PCIeL block diagram

2 - 8 CAN-PCIeL (Hardware Manual) Safety Instructions


2 Safety Instructions

Refer to page 5 for explanation of the warning notice system. The product described in this documentation may be operated only by personnel qualified for the specific task in accordance with the relevant documentation for the specific task, in particular its warning notices and safety instructions. Qualified personnel are those who, based on their training and experience, are capable of identifying risks and avoiding potential hazards when working with these products.

2.1 Installation and Maintenance

CAUTION This product is designed to be integrated into (industrial) computer systems.

DANGER This product may only be connected to power supply systems that are free of hazardous voltages (e.g. SELV).

WARNING The IO interfaces (connectors) of the product are only suited to be connected to SELV circuits.

2.2 Ambient and Environmental Conditions

WARNING This product does not provide a fire enclosure according to EN 60950-1. Installation is only permitted into computer systems that provide such enclosure.

CAUTION Do not operate the product beyond the specified ambient conditions.

DANGER Do not operate this product in potentially explosive atmosphere.

CAN-PCIeL (Hardware Manual) Installation 3 - 9


3 Installation

When opening the shipping package of the CAN-PCIeL, you should immediately check the contents of the package. In the package you will find information about the scope of delivery, as this depends on the options that you have ordered.

3.1 Handling Instructions When installing the CAN-PCIeL into a PC, you must obey some handling precautions to avoid damaging your board with electrostatic discharge.

When taking the board out of the anti-static bag in which it is delivered, you should wear a grounded anti-static wrist strap. The strap must also be connected to your working environment. It is

recommended to first touch the board at the bracket, as this has a defined resistive path of about 2M to the sensitive board electronics. Thereby a controlled discharge will occur. Before inserting the card into the PC, you should check whether the power supply has enough strength to provide the extra load for it. Turn off the PC power before inserting the card. When inserting the CAN-PCIeL into the PC, a second discharge defect could arise. You have to ensure a defined discharge! Do so by “connecting” the CAN-PCIeL bracket with the ground of your PC system. This is given by touching the PCI bracket, while wearing an anti-static wrist strap which is connected to the ground of the PC. If the PC is not boot after the CAN-PCIeL has been installed, turn the power off and contact us for help with your problem.

When mounting the CAN-PCIx/EXTO, please note that you must lock the extension board with the three screws that are delivered with the extension module.

1 1

2 2

figure 2: Mounting of CAN-PCIx/EXTO on CAN-PCIeL

3 - 10 CAN-PCIeL (Hardware Manual) Installation


3.2 Components and Jumper Locations

Jumper Function

J300/J301 Set CAN line termination CAN0 on

Open CAN line termination CAN0 off

J400/J401 Set CAN line termination CAN1 on

Open CAN line termination CAN1 off

HEX-Switch

0..15 Board Number. To be used by drivers to identify the board.

table 2: User jumper functions

Oscillator

U30

0U

400

U10

0

DCDC

J40

0

0

DCDC

J30

0

LED402

LED300PCI9030

PEX8112

PLD

EEPROM

SJA

1000

SJA

100

0

Opt

oco

uple

rs

Optocouplers

CAN-Transceiver

CA

N-T

rans

ceiv

er

HEX-Switch

EEPROM

J401

J301

figure 3: Component side of CAN-PCIeL

nvR

AM

CAN-PCIeL (Hardware Manual) Installation 3 - 11


3.3 Connecting IO signals The CAN-PCIeL is delivered with D-SUB connectors for the CAN I/Os. The connectors are assigned as defined by CiA DS102 or CiA DS301.

The CAN-PCIeL bracket has cut-outs for the 9pin D-SUB connectors for the CAN interfaces. Is one CAN interface equipped only, the cut-out of CAN1 is closed. This is the connector assignment for CAN0 and CAN1:

DSUB Flat cable

header

1 NC 1

2 CAN_L 3

3 GND 5

4 NC 7

5 NC 9

6 GND 2

7 CAN_H 4

8 NC 6

9 EXVCC 8

10

Note: For use of external transceiver a special version of the CAN-PCIeL exists, that provides TLL-level Tx and Rx signals of the CAN controller in place of CAN_H and CAN_L. This version provides +5V power on EXVCC pin to power the external transceiver. The +5V power has no fuse!

3.4 Software Considerations For any information about installing drivers and other software packages related to the CAN-PCIeL, refer to the documentation that comes with the driver or software.

3.5 Finding Free Resources This section should not exist at all, as PCI is said to be plug-and-play. It however does.

CAN0 CAN1

CAN0 CAN1LEDs LEDs

figure 4: Bracket for CAN-PCIeL boards

3 - 12 CAN-PCIeL (Hardware Manual) Installation


3.5.1 System BIOS

The first obstacle that must be checked is the BIOS of today’s PCI Bus motherboards. They have a “PNP and PCI setup” section, where the interrupt resources of the system are managed. Each of the 16 interrupt controller inputs that is not used for a special purpose (timer, FPU, etc), can basically be assigned for two purposes:

PNP/PCI: Interrupts that are assigned to this class can be dynamically assigned to PCI Bus devices or to plug-and-play devices when the system boots up.

Legacy ISA: These interrupts are not subjected to PNP/PCI. They can safely be used by ISA bus add-in cards, as the BIOS will treat them as reserved.

At least one of the interrupt lines must be left in PNP/PCI mode, so that the PCI BIOS can assign them to PCI Bus cards.

CAN-PCIeL (Hardware Manual) Programming Information 4 - 13


4 Programming Information

This describes the methods that are needed, when working with the CAN-PCIeL. It definitely relies on the PCI9030 EEPROM configuration as it is factory (JANZ) supplied. If you manage to clear or alter the EEPROM, then this chapter will no longer apply to you.

4.1 PCI Bus configuration space The board (the interface chip) is identified by a set of IDs in PCI configuration space as listed below:

Purpose Value Found in

Vendor ID 0x10B5 CFG space register 0x00

Device ID 0x9030 CFG space register 0x02

Subsystem Vendor ID 0x13C3 CFG space register 0x2C

Subsystem ID CAN-PCIeL /1 0x22xx CFG space register 0x2E

Subsystem ID CAN-PCIeL /2 0x23xx CFG space register 0x2E

The LSB of the Subsystem ID codes the hardware revision of the CAN-PCIeL board. Currently the following version coding is used:

LSB of Subsystem ID

CAN-PCIeL revision

Features

0x00 V1.0 -

0x01 V2.x -

0x11 V2.x nvSRAM installed

The PCI9030 provides address spaces to access the local configuration registers (in both I/O and memory range). These registers are used to configure the PLX behaviour (i.e. access times at the local bus or local bus configuration). They are not the same as the configuration space registers. Additionally three address spaces are configured through which the CAN controllers and the board-registers can be accessed.

PCI base address register

Local address space

Description

Size

0 - Local configuration registers (memory mapped) 128Bytes

1 - Local configuration registers (I/O mapped) 128Bytes

2 0 CAN address space 4KBytes

3 1 Reserved 4KBytes

4 2 On-Board registers 4KBytes

5 3 nvSRAM 1 MB

The actual addresses for these memory spaces are configured by the PCI-BIOS of your system every time the computer is booted. If you wish to access one of these spaces, then you need to read the actual addresses from the PCI configuration space! The CAN-PCIeL does not provide an expansion ROM.

4 - 14 CAN-PCIeL (Hardware Manual) Programming Information


4.2 CAN address space The CAN controllers of the CAN-PCIeL are accessed through the memory address space (Base address register 2).

Address Offset accesses: 0x000..0x0ff CAN controller 0 registers 0x100..0x102 CAN controller 0 control 0x200..0x2ff CAN controller 1 registers 0x300..0x302 CAN controller 1 control 0x400..0x4ff CAN controller 2 registers 0x500..0x502 CAN controller 2 control 0x600..0x6ff CAN controller 3 registers 0x700..0x702 CAN controller 3 control

Besides the registers of the SJA1000 (which are defined in the SJA1000 Manual), there are two additional registers which control the line termination and the PCI bracket LEDs. These registers are unique for each channel. The following is describing how to access channel0. The three other channels are accessed even, but the offset from the table above must be respected.

CAN_TERM0 0x100 (byte, rw)

7 6 5 4 3 2 1 0

reserved TERM

TERM Set to ‘0’ to disable the line-termination, set to ‘1’ to enable the

termination resistor. Reserved Reserved positions should not be changed. You should use read-modify-

write operation to change this register.

CAN_LED0 0x102 (byte, wo)

7 6 5 4 3 2 1 0

reserved LEDG LEDR

LEDR Write ‘1’ to turn red LED on, write ‘0’ to turn it off. LEDG Write ‘1’ to turn green LED on, write ‘0’ to turn it off. Reserved Reserved positions should be written as ‘0’ for compatibility with future

products. Notice: Front panel LEDs for CAN channel 2 and 3 are not implemented.

4.3 On-board registers This address space (Base address register 4) provides some on-board registers, runtime configuration purposes that are outside of the scope of the PCI9030’s local configuration registers.

Address Offset Read access Write access

0x1 (byte only!) INT_STAT INT_DISABLE

0x3 (byte only!) BOARD_NUM INT_ENABLE

0x5 (byte only!) EXTO_PRES RESET_ASSERT

0x7 (byte only!) - RESET_DEASSERT



4.4 nvSRAM This address space (Base address register 5) provides access to the nvSRAM device. The nvSRAM memory saves data into an internal backup EERPOM when power goes down. To provide energy for this task, a buffer capacitor is used. Therefore it is completely maintenance free as no battery is required.

Address Offset description 0x00000..0x7ffff reserved 0x80000..0x9ffff nvSRAM 0xa0000..0xfffff reserved

The nvSRAM can be accessed by 8-, 16- and 32 bit operations (read and write).

If nvSRAM is accessed by 16 or 32 bit operations, these are not atomar. In case of power down, it might happen that only parts of the 32 bit value are stored in the nvSRAM. Also notice that the PCI interface has buffers. Even if the write operation has been finished from CPU point of view, it might not have been saved into the memory. To make sure data has reached the memory, you need to read back the latest written content.

Address decoder 5 is not enabled on version 1.0 of the CAN-PCIeL, hence the resource is not available.

4.5 Interrupt programming

4.5.1 CAN Interrupts

The interrupt lines of all CAN controllers on the board are logically ored and share the PCI Bus interrupt (INTA#). Figure 4 shows the architecture for the internal interrupt handling of CAN-PCIeL. With the interrupt masking register (INT_MASK) the user is able to enable or disable the interrupt for any channel. To identify which controller has activated the interrupt the interrupt status register (INT_STAT) is providing this information.

To determine which CAN-controller has provoked the interrupt, the interrupt handler needs to read the interrupt status register:

INT_STAT 0x1 (byte, ro)

7 6 5 4 3 2 1 0

reserved CAN3 CAN2 CAN1 CAN0

CAN_INT1#

CAN_INT0#

CAN_INT2#

CAN_INT3#

&

&

&

&

≥1

PCI9030

LINTi1#

INTA# PCI_INTA#

INT_MASK INT_STATIM0

IM1

IM2

IM3

IS0

IS1

IS2

IS3

figure 5: Interrupt scheme

4 - 16 CAN-PCIeL (Hardware Manual) Programming Information


IS[3..0] Interrupt status bits. Each defined bit in this register reflects the status of the INT# pin of the corresponding CAN controller. A zero will be read when an interrupt is pending. If a CAN interrupt request line is disabled, then the corresponding bit is forced to ‘1’.

Reserved Reserved positions are undefined, and must not be considered. Software must mask them off.

The interrupt handling routine can freely choose an algorithm to assign priorities to the different interrupt sources on a CAN-PCIeL. CAN interrupt requests can be masked off by the CPU. This is done through the interrupt disable/enable registers. Interrupts are disabled after RESET, and you need to enable a CAN interrupt line before using it.

INT_DISABLE 0x1 (byte, wo)

7 6 5 4 3 2 1 0

Reserved IS3 IS2 IS1 IS0

INT_ENABLE 0x3 (byte, wo)

7 6 5 4 3 2 1 0

Reserved IS3 IS2 IS1 IS0

IM[3..0] Writing one of the bits disables/enables interrupts from the corresponding

CAN controller. Both registers are accessed in hot-1 technique: Writing a ‘1’ disables/enables further interrupts from the corresponding controller, writing ‘0’ does not affect the interrupt mask status of that controller. Bit IM0 corresponds to CAN controller 0 and so on. If a CAN interrupt request line is disabled, then this CAN controller will never appear in the INTSTAT register and it will not cause interrupts.

Reserved Reserved bit positions must be written as zero.

4.5.2 Board Number

If you plug several CAN-PCIeL boards into a system, they can only be distinguished by the PCI device

number. Sometimes it is unknown in which way physical slots are mapped to PCI device numbers. To

uniquely identify a specific CAN-PCIeL board, you can read the BOARD_NUM register. The value of this

register is controlled by the HEX switch on the CAN-PCIeL.

BOARD_NUM 0x3 (byte, ro)

7 6 5 4 3 2 1 0

BOARD_NUM

BOARD_NUM The value of the HEX switch. Values from 0 to 15 can be set by the HEX

switch.

4.5.3 CAN Controller Reset

To ensure a defined state of the CAN controllers at any time, it is possible to activate the RST# line of a controller via software. This can be done with the reset assert/deassert registers. During a PCI Bus reset, all CAN_RST# lines are activated, too.

RESET_ASSERT 0x5 (byte, wo)

7 6 5 4 3 2 1 0

Reserved R1 R0

RESET_DEASSERT 0x7 (byte, wo)

7 6 5 4 3 2 1 0

Reserved R1 R0



R[1..0] Writing one of the bits asserts/deasserts the RST# line of the

corresponding CAN controller. Both registers are accessed in hot-1 technique: Writing ‘1’ to a bit asserts/deasserts RST# of a selected controller, writing ‘0’ to a bit does not affect the state of the RST# line of a controller. Bit M0 corresponds to CAN controller 0 and so on.

Reserved Reserved bit positions must be written as zero. Note: The reset lines for channel 2 and 3 are provided, but take no effect on CAN-PCIH/EXTO module in version 1.1.

5 - 18 CAN-PCIeL (Hardware Manual) Appendix


5 Appendix

5.1 Technical Data

PCI express Type 1 Lane PCI Interrupt IRQA# CAN Controller SJA1000, CAN 2.0B Physical Layer ISO/DIS 11898 Isolation barrier optional, 500V Connector 9pol D-SUB Line termination On board 120Ohm, enabled by jumper or software Physical Dimensions PCB Size 130mm x 87mm (short card) Slot requirements 1 slot. Weight 85g Power Requirements +3,3V (±5%) 450mA ±12V (±5%) 150mA (2 channels), 300 mA (4 channels) Environmental Specifications Temperature range 0..+70°C (operating), -20..+85 (non operating) Humidity 0%..80%, non condensing

CAN-PCIeL (Hardware Manual) Appendix 5 - 19


131mm

87

mm

99

mm

figure 6: Physical Dimensions

5 - 20 CAN-PCIeL (Hardware Manual) Appendix


5.2 References These references direct you to manuals and specification that you might need to know when you attempt programming the CAN-PCIeL. Most of the documents can be downloaded from the Internet. Look for the web servers of the chip manufacturers. [1] PCI local bus specification, PCI Special Interest Group, Revision 2.2, December 1998. [2] PCI 9030 Data Book, Version 1.4, PLX Technology, May 2002. [3] Data Sheet: SJA1000 Stand-alone CAN controller, Philips Semiconductor, 2000 Jan 04. WWW-References Janz Tec AG: www.janztec.com PCI Special Interrest Group www.pcisig.org PLX www.plxtech.com Philips Semiconductor http://www.semiconductors.philips.com

5.3 Product History

Version Release Date

Name Changes

V1.0 11.09.2008 ime initial version

V2.0 21.05.2012 ime added a nvRAM option

5.4 Manual History

Version Release Date

Name Changes

1.0 23.10.2008 ime Initial version

1.1 07.03.2013 ime Added the description of the nvRAM option

can-pciel user's manual

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