cadence tutorial pdf

DESIGN AND VERIFICATION OF GRO-TDC

SUBMITTED BY

ALOK KUMAR CHAUDHARY

SHRI MATA VAISHNO DEVI UNIVERSITY

SUMMER INTERN 2013 STUDENT

AT

VNIT ,NAGPUR

VHDL Simulation of RTL Design

This chapter presents the main steps to perform the logic simulation of VHDL models with

the Modelsim tool from Mentor graphics .

1) First open the terminal window and login to server PG01@malashri

ssh -X PG01@malashri

cd Alok

mkdir rtltdc

copy all the vhdl files in the rtltdc directory

csh

source Xilinx_source.cshrc

cd rtltdc

2) Now we need to invoke Modelsim by giving command in rtltdc directory

vsim &

vsim & command will open a modelsim window

3) RTL logic simulation

a)Make sure your working directory is still rtltdc , otherwise change the working directory

Select File > change Directory ...

And select rtltdc directory

b) compiling the VHDL source files

select compile > compile ..

New window pop -up ,in which we select our all vhdl files(just simply click on all files with

ctrl ) and then click on compile .

If there is compilation error , message are displayed in red in the console pane otherwise

successfully compilation is done .

If there is error, Fix all the error then Recompile all the vhdl files

c) simulation with coverage

before doing simulation , go to compile > compile options and select Coverage , select the

following coverage as shown in figure below and click ok

Go to your Workspace library(left side ) , click on the + in front of the work library to see

its content (vhdl files ).Right click on tst_whole_digital_tdc_ckts_nxt (testbench) and click

on simulate with coverage .

Lots of window pops up as shown in figure below .

Select view > New window > wave

Type run 6000 ns in console window and click enter (to run simulation for 6000 ns).

Results

Carefully study the waveform(zoom in) , it should be functionally correct and check the

code coverage .

Code coverage should be more than 95% , code coverage depends upon RTL code of our

design and our testbench(test vector which we are giving to rtl design ) .we have to write

testbench in such a manner it will check all the combination of RTL design .

ii) Simulation with IOPAD

As we are working on ASIC design flow , In which we have to take our design up to chip

level or tape out .we have to connect or interface IOPAD (input output pad) with our RTL

design . IOPAD comes from the vendor library or technology library.

We are working with UMC 180nm technology, UMC 180nm provides Faraday180nm library.

Faraday180nm contains all the standard cells and IOPAD which helps for synthesis purpose

.we have to look what are the iopad available in this library .Faraday180nm contains

T33_GENERIC_IO (it contains all iopad , corned pad and Empty cells).

T33_GENERIC_IO available on server at

/cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m/2008Qv1.2/T33_GENER

IC_IO

T33_GENERIC _IO contains IOPAD like

XMD , XMC = INPUT PAD

YA2GSC,YA2GSD = OUTPUT PAD

We have to write a VHDL code for IOPAD and final top design (interface b/w RTL and IOPAD

).

First open the terminal window and login to server PG01@malashri

ssh -X PG01@malashri

cd Alok

mkdir finaltdc

copy all the vhdl files in the finaltdc directory . finaltdc directory must contains all previous

RTL code, VHDL code for IOPAD and final top design (vhdl code for interface b/w iopad and

rtl design).

csh


cd finaltdc

2) Now we need to invoke Modelsim by giving command in rtltdc directory

vsim &

vsim & command will open a modelsim window

First we need to create a New library (name = fsa0m_a_t33_generic_io) for simulation

purpose with iopad. In this new library we have to compile

fsa0m_a_t33_generic_io_Vtables.vhd,fsa0m_a_t33_generic_ioVcomponents.vhd and

fsa0m_a_t33_generic_io_VITAL.vhd files . All these vhdl files available on server

at

/cad/UMC_FARADAY

Faraday180nm_library/L180_MMRF/fsa0m/2008Qv1.2/T33_GENERIC_IO/FrontEnd/vhdl.

other option we may copy these three vhdl files in our directory and do compile , then

there will be no need for browse all these 3 files .

Select File > New >Library ... New window (create new library) pops up , where simply

write fsa0m_a_t33_generic_io and click ok .

Now we have to compile simulation files . go to compile > compile and change the library

name fsa0m_a_t33_generic_io

Compile all three vhdl files in a sequences fsa0m_a_t33_generic_io_Vtables ,

fsaom_a_t33_generic_io_Vcomponents and fsa0m_a_t33_generic_io_Vital.

Go to our workspace library (left side) and Click on the + in front of fsa0m_a_t

33_generic_io , where all the iopad present in fsa0m_a_t33_generic_io library

we have already check code coverage of our RTL design before in VHDL simulation likewise

no need to go for code coverage just simply go for functional simulation of your final top

design .

Just do all the steps as explain before in VHDL simulation . dont go for simulation with

coverage becoz iopad reduces the percentage graphs . simply go for simulate .

Steps for simulation :-

Compile > compile and select all vhdl files including iopad, final top design and then go for

compilation , make sure there is no error in console window otherwise check and remove

the error .

Go to your workspace library , click + in front of work . select and right click on your

testbench file(tst_final_top_design_nxt) . Go for simulate .

Lots of window comes , select view > New window > wave.

Type 10000 ns in console window and watch carefully your waveform for functional

verification .

All these steps already explain before in VHDL simulation .

RTL/LOGIC SYNTHESIS

For synthesis , we will use design compiler (synopsys).

As we confirm out RTL design is functionally correct, we need to synthesized the design and

create gate level netlist.

For synthesis , we need following files :-

Technology cell library (.db files)

VHDL/Verilog code (.vhd/.v).

Environment & Timing Constraints.

Before synthesis , we need to create a scripting file(.tcl file) for synthesis .where we define

all cell library , Design environment, Timing constraints and VHDL files.

------------------------------------finaltdc.tcl--------------------------------------------------------------------

set target_library

{/cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m_a/2009Q2v2.0/GENERIC_CORE/FrontEnd/s

ynopsys/fsa0m_a_generic_core_ff1p98vm40c.db

/cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m_a/2009Q2v2.0/GENERIC_CORE/FrontEnd/sy

nopsys/fsa0m_a_generic_core_ss1p62v125c.db


nopsys/fsa0m_a_generic_core_tt1p8v25c.db

/cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m_a/2008Q3v1.2/T33_GENERIC_IO/FrontEnd/s

ynopsys/fsa0m_a_t33_generic_io_ff1p98vm40c.db


ynopsys/fsa0m_a_t33_generic_io_ss1p62v125c.db


ynopsys/fsa0m_a_t33_generic_io_tt1p8v25c.db}

set link_library


ynopsys/fsa0m_a_generic_core_ff1p98vm40c.db


nopsys/fsa0m_a_generic_core_ss1p62v125c.db


nopsys/fsa0m_a_generic_core_tt1p8v25c.db


ynopsys/fsa0m_a_t33_generic_io_ff1p98vm40c.db


ynopsys/fsa0m_a_t33_generic_io_ss1p62v125c.db


ynopsys/fsa0m_a_t33_generic_io_tt1p8v25c.db}

set symbol_library


ynopsys/fsa0m_a_generic_core.sdb


ynopsys/fsa0m_a_t33_generic_io.sdb}

define_design_lib WORK -path "work"

analyze -library WORK -format vhdl {/home/anita/Alok/synthesis/vhdlcode/whole_digital_tdc_ckts_nxt.vhd

/home/anita/Alok/synthesis/vhdlcode/whole_adder_ckt_nxt.vhd

/home/anita/Alok/synthesis/vhdlcode/adder_7bit_nxt.vhd

/home/anita/Alok/synthesis/vhdlcode/pipo_nxt.vhd /home/anita/Alok/synthesis/vhdlcode/iopad_nxt.vhd

/home/anita/Alok/synthesis/vhdlcode/final_top_design_nxt.vhd

/home/anita/Alok/synthesis/vhdlcode/combo_asycoun_reg_nxt.vhd

/home/anita/Alok/synthesis/vhdlcode/bunch_coun_reg_nxt.vhd

/home/anita/Alok/synthesis/vhdlcode/bunch_coun_nxt.vhd

/home/anita/Alok/synthesis/vhdlcode/asy_coun_nxt.vhd

/home/anita/Alok/synthesis/vhdlcode/adder_8bit_nxt.vhd

/home/anita/Alok/synthesis/vhdlcode/adder_7_8bit_nxt.vhd

/home/anita/Alok/synthesis/vhdlcode/adder_9bit_nxt.vhd}

elaborate final_top_design_nxt -architecture TOP -library WORK

link

uniquify

set_operating_conditions -min_library fsa0m_a_generic_core_ff1p98vm40c -min BCCOM -max_library

fsa0m_a_generic_core_ss1p62v125c -max WCCOM

set_wire_load_model -name enG30K -library fsa0m_a_generic_core_ss1p62v125c

create_clock declk -period 94.20 -waveform {0 47.1}

set_input_delay 0.02 -clock declk clk1







set_input_delay 0.02 -clock declk rst

set_input_delay 0.02 -clock declk clk

set_input_delay 0.02 -clock declk t

set_output_delay 0.02 -clock declk Y1










report_port

set_max_area 0

uplevel #0 check_design

compile -exact_map

change_selection -name global -replace [get_timing_paths -delay_type max -nworst 1 -max_paths 1 -

include_hierarchical_pins]

report_timing -path full -delay max -max_paths 1 -nworst 1

report_area

report_power

report_timing > reports/timing.rpt

report_area > reports/area.rpt

report_power > reports/power.rpt

report cells > reports/cell.rpt

write_sdc final_top_design_nxt.sdc

write -hierarchy -format verilog -output /home/anita/Alok/netlist/final_top_design_nxt_syn.v

write -hierarchy -format vhdl -output /home/anita/Alok/netlist/final_top_design_nxt_syn.vhd

write_sdf -version 2.1 final_top_design_nxt_vlog.sdf

------------------------------END of TCL FILE -------------------------

target_library (.db files) :- This library specifies the name of the technology library which

help to build a circuit during synthesis. Design complier selects functionally correct gates

from the target library. It also calculates the timing of the circuit, using the vendor-supplied

timing data for these gates.

link_library (.db files) :- This library uses only for resolve references but does not use the

cells present in it for mapping as in case of target library. For a design to be complete, it

must connect to all the library components.

symbol_library (.sdb files) :- This library contains all the symbolic representation of logic

cells. Basically used for schematic generation.

define_design_lib :- define work as library.

analyze :- The analyze command will do syntax checking and create intermediate .syn files

which will be stored in the directory work library, the defined design library.

elaborate :- This command read all intermediate .syn files from work library and built the

design in the design compiler memory . It translates the design into a technology-

independent design (GTECH) from .syn files produced during analysis.

link : This command checks all of the designs and library component referenced in the

current design.

uniquify :- This command automatically select the most top design of the hierarchy of RTL

design .

set_operating_conditions : operating conditions include temperature, voltage and process

variation. Before a design can be optimize, we specify operating condition

(best,typical,worst) in which the design is executed to operate. we set worst condition as

Max. Library and best condition as Min. library to make it slow-fast process.

set_wire_load_model : Technology cell library contains various wire load model , depending

upon design select wire model or otherwise dont select any wire load model during

synthesis because design compiler by default choose wire load depending upon the design

complexity. The models include coefficients for area, capacitance, and resistance per unit

length.

create_clock : we have to select at which frequency we want to operate our design . if our

design is sequential , then we just select clock pin and give the frequency . If our design is

purely combinational, then we have create virtual clock like :

create_clock -period 40 -waveform {0 20} -name clk

set_dealy : set input and output dealy w.r.t clock .

set_max_area : This command helps the design compiler to synthesis our RTL design in

minimum area .

check_design : This step will check your design's netlist description for problems like

connectivity, shorts, opens, multiple instantiations.

compile : This command helps design compiler to synthesis design on the basis of

constraints(clock frequency, input output delay , clock lantency).

report : Report command are just to generate report file for area , power and timing .

write_sdf : generate sdf (standard delay format) file .

witre_sdc : generate sdc (standard delay constraints) file.

Now we have to run our scripting file (.tcl) in design complier

First login to anita@shri server and create working directory

ssh X anita@shri

mkdir Alok

cd ALok

---- create synthesis , reports, netlist directory and all necessary directory where do u want

to save ur reports, netlist files etc....

mkdir synthesis

mkdir reports

mkdir netlist

-----source the design complier ------------

csh

source /cad/synopsys_NEW/synopsys.cshrc

cd Alok

-------- now invoke the design compiler and run TCL file --------

design_vision xg f finaltdc.tcl

Make sure you are getting all these files in reports directory , verilog netlist in netlist

directory and sdf file.

View the schematics of your design , just simply click on schematic and select New design

schematics view.

Post synthesis simulation

The post-synthesis gate-level simulation uses the same testbench models as the ones

developed for the verification of RTL models and the same logic simulator. The simulation of

the Vhdl/Verilog netlist require models of the standard cells that are usually provided in the

design kit.

Files require for post synthesis simulation :

Gate level netlist (in vhdl) which we get after synthesis .

We have to create two new library for simulation

Library for iopad (name = fsaom_a_t33_generic_io) , as we create before .

Library (name = fsaom_a_generic_core) , this library require because after synthesis our

gate netlist (final_top_design_nxt) become technology dependent that why we need

simulation file for post synthesis simulation.

Simulation file contains all standard cells which require for functional simulation and all

these files available on server at

/cad/UMC_FARADAY

Faraday180nm_library/L180_MMRF/fsa0m/2009Q2v2.0/GENERIC_CORE/FrontEnd/vhdl.

All these three are simulation files

fsa0m_a_generic_core_Vcomponents.vhd

fsa0m_a_generic_core_Vtables.vhd

fsa0m_a_generic_core_VITAL.vhd

Login to server PG01@malashri

ssh X PG01@malashri

csh


cd Alok

mkdir synthesis

copy the netlist file (in vhdl) in synthesis directory , which we get after synthesis.

Invoke the modelsim simulator

vsim &

Create new library with name = fsa0m_a_t33_generic_io , follow all the steps as explained

before in simulation with iopad .

Create one more library with name = fsa0m_a_generic_core .

Select file > new > library and type fsa0m_a_generic_core

As we see new library is added in workspace library.

Select compile > compile and change the library name work to fsa0m_a_generic_core

Browse your simulation file fsa0m_a_generic_core_Vcomponents.vhd,

fsa0m_a_generic_core_Vtables.vhd ,fsa0m_a_generic_VITAL.vhd and compile all these

three files in sequences .

Click + in front of fsa0m_a_generic_core and see all the standard cells .

Check that , we have two library in our workspace

a) fsa0m_a_t33_generic_io b) fsa0m_a_generic_core

Check Both contains there standard cells .

Make sure we have to simulate gate level netlist file (final_top_design_nxt) , which we get

after synthesis

Steps for Post synthesis simulation :-

Select compile > compile and select gate level netlist (final_top_design_nxt.vhd) and then

go for compilation , make sure there is no error in console window otherwise check and

remove the error .

Go to your workspace library , click + in front of work library. select and right click on your

testbench file(tst_final_top_design_nxt) . Go for simulate .

Lots of window comes , select view > New window > wave.

Type 10000 ns in console window and watch carefully your waveform for functional

verification .

All these steps already explain before in VHDL simulation .

PLACE AND ROUTE USING CADENCE SOC ENCOUNTER

We are using the Cadence SOC Encounter version 8.1

After synthesis our design in Design compiler , the synthesized netlist was saved in verilog

format. We need to convert this synthesized design into a layout . For this purpose ,

Cadence SOC Encounter uses a verilog netlist and generate its layout view.

Files require for PNR tool :-

synthesis netlist (in verilog)

Timing constraint file (.sdc) , this file generated during synthesis in design compiler.

IO assignment file (.io) : if use IOPAD in design , we need to generate this file.

Login to anita@shri server

ssh X anita@shri

csh

source /cad/common_source.cshrc

cd Alok

mkdir encounter

-------- copy the synthesis netlist (final_top_design_syn.v), timing constraints file(.sdc) in

encounter directory .

------------Invoke the soc encounter tool in encounter directory , just simply type encounter.

encounter

encounter will open the soc encounter window.

Now we can start using encounter . First we need to import the synthesized netlist .

click on Design -> Import Design , a new window should pop-up . Now we need to fill up

required files :-

Verilog netlist files : use the browser buttom on the right to navigate to your synthesized

netlist ,likewise in my case(final_top_design_nxt_syn.v), make sure you click on Add , then

close.

Max Timing libraries : it contains two files , one for standard cell

(fsa0m_a_generic_core_ss1p62v125.lib) and other

fsa0m_a_t33_generic_io_ss1p62v125.lib) for IOPAD cells.

These files are available on server at

/cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m/2009Q2v2.0/GENERIC_CO

RE/FrontEnd/synopsys/fsa0m_a_generic_core_ss1p6v125c.lib

/cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m_a/2008Q3v1.2/T33_GENE

RIC_IO/FrontEnd/synopsys/fsa0m_a_t33_generic_io_ss1p62v125c.lib

Note : ss1p62v125 library is worst case that why we use as a Maximum library.

3) Min Timing libraries : it also contains two files ,

fsa0m_a_generic_core_ff1p98vm40c.lib (for standard cell) and

fsa0m_a_t33_generic_io_ff1p98vm40c.lib(for ioapd) . they are also available on server ,

likewise find on above link on yourself.

Note : ff1p98vm40c is best case that why we use as Minimum library .

Common Timing libraries : It contains fsa0m_a_generic_core_tt1p8v25c.lib and

fsa0m_a_t33_generic_io_ tt1p8v25c.lib .

Not e : tt1p8v25c.lib library is typical case .

LEF files : contains six lef files , 3 for each standard cell and for iopad cell.

For standard cells :-

/cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m/2009Q2v2.0/GENERIC_CO

RE/BackEnd/lef

a)header6_V55

b) fsa0m_a_generic_core

c) FSA0M_A_GENERIC_CORE_ANT_V55.6

For IOPAD cells :-


RIC_IO/BackEnd/lef

header6_V55

fsa0m_a_t33_generic_io

FSA0M_A_T33_GENERIC_IO_ANT_V55.6

6 ) Timing constraints file : Browse for timing constraints file(.sdc), likewise in my design

final_top_design_nxt.sdc . .sdc file is generated during synthesis.

IO Assignment file : Browse your io file , In my case final_top_design_nxt_save.io . You

have to create this io file . The only need for this file is to proper placement of input and

output pad . if designer or user wants to change the pins configuration , then he has to

modify the io file.

Now in same Design Import window select Advance tab and specify your Global nets

(VDD,GND) . click on ok, Also you save this as a .conf file. It will help to open project next

time.

Now we can see complete chip view, which has logic block and IO pins surrounding core

area , where we have to place all digital logic.

Now you have to specify floorplan , floorplan -> specify floorplan . Here, you decided DIE

size and core to IO boundary .

Now specifying Global nets , Floorplan -> connect Global net . specify all global nets to

power pins of standard cells.

Now create power rings around core area. Select Power => power planning => add rings.

It create power rings which supply power to vdd & gnd pins of standard cells. Select top &

bottom layer( Horizontal Layers) as metal5 and Vertical layers as metal6.

Always odd metal layers are Horizontal metal layers and even metal layer are Vertical

metals.

Now add strips to core area. Select Power => power planning => add strips.

Now for Faraday Library we have to change orientation of all corner pads. Double click on

corner pad it will show its property, where you can change its orientation. For top right

corner pad make R0,top left R90, bottom left R180 and bottom right R270

Now you have place all standard cells. Click on Place => standard cells, It will place all

standard cell in core area, you can view it by selecting physical view button

Now add all filler cells. Place => Physical cells => add fillers .

Also add IO filler Cells to fill gap between IO Pads. Place => Physical cells => Add IO fillers.

Find filler names in io lef file.

Now perform Trail Route

17 )Now clock tree. Select clock buffers which you want put in your design

18 ) After clock tree, go for global routing, where all power pins will routed to

power rings. Select Route => Special Route option.

19) Make sure your all power pads and power rings are routed properly and

then perform nano route to finalize the routing of design.

white cross makrs shows errors in related to connections or overlaps.Make sure your design

is error free.

Note :- In Faraday Library it will always point for VDD& GND pins X at top of pin, tools will

show connectivity error, but actually it not error. You can avoid it. Also tool will show

overlap error for IO fillers. This is also not considered as error, you can simply avoid overlap

error massage for filler cells. Other than this if you have any errors that you have correct. So

your final design will look like as follows.

20 ) Now extract RC values and other reports for further process of Static timing analysis

using simulation and STA tool.

21 ) Also save your design as netlist to perform final equivalence checking.

22) Now you can create GDS file. Select Design => Save => GDS/OASIS.

Note : while creating gds file, give out file name as .gds file and select proper

steamOut.map file from your technology library.

Faraday180nm_library/L180_MMRF/fsa0m_a/2009Q2v2.0/GENERIC_CORE/TECH/dffII/.

Save all necessary files : -

Go to Design -> save ->Floorpaln , Place , Route ,Netlist etc

PHYSICAL VERFICIATION IN CADENCE VIRTUOSO

After running place and Route on the synthesized design , you obtain a GDS file . you can

use this GDS file to import the layout from SOC Encounter into cadence Virtuoso layout

viewer. This allow you to verify the place and route tools have properly generated the

design and that your design is DRC clean .

You can verify this by :

Importing the LEF files for standard cells

Importing the LEF files for IOPAD cells

Importing the place and route layout(.gds file) to cadence Virtuoso.

Login to anita@vlsiserver

ssh X anita@vlsiserver

cd umc_work

---copy your GDS file in umc_work directory ---------------------------------------

Icfb &

-----icfb & command will open cadence tool----------------------------------------

Before importing your LEF file and GDS file . You have to create one library , where you can

import your gds file.

Go to File -> New -> library .

New window pops up ...

Fill all the information as shown below

Importing the LEF files for standard cells

Go to file -> import -> LEF

New window pops up

Here we have to import Two lef file for standard cells , so lef are available at :-

/cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m_a/2009Qv2.0/GENERIC_C

ORE/BackEnd/lef

fsa0m_a_generic_core.lef

Write path for LEF file name (fsa0m_a_generic_core.lef ) :-

cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m_a/2009Qv2.0/GENERIC_CO

RE/BackEnd/lef/ fsa0m_a_generic_core.lef

Target library name : FSA0M_A_GENERIC_CORE

Select Macro target view as abstract view and click apply

Similar select Macro target view as layout view and click apply

FSA0M_A_GENERIC_CORE_ANT_V55.6.lef

Write path for LEF file name (FSA0M_A_GENERIC_CORE_ANT_V55.6.lef) :-

cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m_a/2009Qv2.0/GENERIC_CO

RE/BackEnd/lef/ FSA0M_A_GENERIC_CORE_ANT_V55.6.lef

Target library name : FSA0M_A_GENERIC_CORE


Similar select Macro target view as layout view and click ok.

Importing the LEF files for IOPAD cells :-

Go to file -> import -> LEF

New window pops up

Here we have to import Two lef file for standard cells , so lef are available at :-


RIC_IO/BackEnd/lef

fsa0m_a_t33_generic_io.lef

Write path for LEF file name (fsa0m_a_t33_generic_io.lef ) :-


RIC_IO/BackEnd/lef fsa0m_a_t33_generic_io.lef

Target library name : FSA0M_A_T33_GENERIC_CORE


Similar select Macro target view as layout view and click apply

FSA0M_A_T33_GENERIC_IO_ANT_V55.6.lef

Write path for LEF file name (FSA0M_A_T33_GENERIC_IO_ANT_V55.6.lef) :-


RIC_IO/BackEnd/lef FSA0M_A_T33_GENERIC_IO_ANT_V55.6.lef

Target library name : FSA0M_A_T33_GENERIC_CORE


Similar select Macro target view as layout view and click ok.

Importing the place and route layout(.gds file) to cadence Virtuoso.

Go to file -> Import -> steam

New window pops up

Fill in the stream form as shown below .

Input file : final_top_design_nxt.gds

Library name : tdc_design_nxt

Leave other field blank

Select User defined data

Layer map table : stream.map

Click ok.

Note : stream.map available at server :-

/cad/UMC_FARADAY/UMC/UMC18_MIXMODE_RF/designkit/Cadence/stream.map

copy this stream.map file into umc_work directory , then browse this map file in layer map

table .

Select option : Fill it as shown below

A new window (stream in option) will pops-up

Fill the reference library order in sequence : FSA0M_A_GENERIC_CORE

FSA0M_A_T33_GENERIC_IO UMC_18_CMOS

Select Retain Reference library (no merge) , Do not overwrite existing cell and leave other

as a default , click ok in Stream in form

A pop-up message will indicate that PIPO STRMIN completed successfully.

Now you can see your layout , which you have imported in cadence virtuous .

Go to Tools -> library manager

Select for your library (tdc_design_nxt) , click on final_top_design_nxt (cell) and then

select layout (view) .

Click on Assura -> Run DRC

If there is DRC error , then remove all these error . Error are shown in error layer window.

So , you can physical verify your layout design by using Assura DRC in cadence Virtuoso

Import synthesized design into cadence composer schematics View

Once you have the schematics design saved as a verilog file , you may need to verify that the

place and route tools have properly displayed the design .you can verify this by :

Importing the place and route layout to Cadence Virtuoso. As you already did before

in Physical verification , where you import your GDS file from soc-encounter into

cadence virtuosos.

Importing the verilog netlist into a schematics in Cadence composer

Running LVS on the views to verify that they have the same netlist

*This section describe how you may import the synthesized netlist into cadence

composer schematic view

Before importing your synthesized netlist , we have to import verilog files of

standard cell and iopad cells.

Make sure you have verilog files of standard cell, iopad cell and synthesized netlist

in umc_work directory .

Verilog file of standard cell is available at : -/cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m_a/2009Qv2.0/GENERIC_CORE/FrontEnd/verilog/fsa0m_a_ge

neric_core_21.lib.src

Just rename the fsa0m_a_generic_core_21.lib.src to fsa0m_a_generic_core_21.v

when you copy this file in umc_work directory

Verilog file of iopad standard cell is available at :- /cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m_a/2008Q3v1.2/T33_GENERIC_IO/FrontEnd/verilog/fsa0m_a_

t33_generic_io_21.lib.src

Just rename the fsa0m_a_t33_generic_io_21.lib.src to fsa0m_a_t33_generic_io_21.v

when you copy this file in umc_work directory

Login to anita@vlsiserver

cd umc_work

icfb &

1) Importing verilog file of standard cell

Go to file , select import > verilog

New window pops-up

Target library name :- standardcelllib

Reference library : sample basic

Verilog files to import :- fsa0m_a_generic_core_21.v

Click ok , then window a pop-up which show that verilog file is import complete.

2) Importing verilog file of iopad cell


Same New window pops-up , you just have fill the information as shown below

Target library name :- iopadstandardcell

Reference library : sample basic

Verilog files to import :- fsa0m_a_t33_generic_io_21.v


3) Importing verilog file of synthesized netlist

Here ,you have to add libraries of standard cell and iopad cell, which you have

generated before


New window pops-up

Target library name :- TDCSCHEMATICS_NXT

Reference library : standardcelllib iopadstandardcell sample basic

Verilog files to import :- final_top_design_nxt_enc.v


Now you have to look for your schematics view which you have generated by verilog netlist

Go to CIW ,select tools > Library Manager > TDCSCHEMATICS_NXT (library) >

final_top_design_nxt (cell) >schematic (view)

Your look like this :-

SIMULATION AND RESULT

In this section we have presented the simulation, code coverage report and synthesis result

of the TDC . As we already describe the whole architecture of TDC , ASIC design flow of

Semi-Custom Design and what are the tool require in this design flow. Our next aim to show

the Simulation, Code-coverage report , Synthesis and Layout result of TDC which we carried

out throughout the ASIC design.

Code coverage Report :- It is a technique that allow the users to determine how their

source code is executed . It gives detailed information on statements that are executed

during the simulation . code coverage examines each executable statements and checks

how many times it has been executed . Many types of coverage report are available there ,

out of which three are very important

Statement coverage or line coverage :- It provides the most basic level of analysis. It

simply indicates that a particular line of code was exercised , if a VHDL code consist of 10

line and 8 lines of code were exercised in a test run then line coverage is 80%.

Branch coverage :- It consist branches of IF or Case statements and checks how many times

a true or false condition was met by each branch during the simulation .

Toggle coverage :- It is a program that measure a design activity within terms of changes of

signal logical values.

Coverage result[%] = (number of statements executed) / (total no. of statements) * 100 %

For code coverage report percentage should be more than 95% or approx around 95 %. In

our deisgn , Branch percentage less around 83.9% it is because of testbench which we using

for our RTL design is not so much effective to cover to branch coverage .Before writing a

testbench first we should know what corner points of RTL design are there so it will become

easy to write a testbench .

Functional simulation :- In figure shown below , it shows the simulation result of Time to

Digital converter (TDC) before the Synthesis . Functional simulation is simulated in

modelsim simulator. This functional simulation is totally independent of CMOS technology

library. Red line are undefined because these are power supply (VDD, GND, VCCIO, GNDIO) .

These power supply lines are comes into play during Placement and Route process.

* Synthesis Result

All the synthesis is done with Design compiler with Faraday 180 nm library .

Faraday 180nm library provides three different libraries :-

ff198vm40c (fast-fast) library is for best case analysis.

tt1p8v25c (typical ) library is for typical case analysis.

ss1p6v125c (slow-slow) library is for slow case analysis.

For synthesis of TDC , we are taking ss1p6v125c (slow-slow) library as maximum library and

ff198vm40c (fast-fast) library as minimum library. The maximum library will be used for

verifying minimum delay constraints (e.g. set-up times). The minimum library will be used

for verifying maximum delay constraints (e.g. hold times).

Report : power -analysis_effort low

Design : final_top_design_nxt

Version: B-2008.09-SP5

Date : Mon Jul 1 09:26:38 2013

Library(s) Used: fsa0m_a_generic_core_ff1p98vm40c

(File:/cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/f

sa0m_a/2009Q2v2.0/GENERIC_CORE/FrontEnd/synopsys/fsa0m_a_generic_core_ff1p98vm

40c.db)

fsa0m_a_t33_generic_io_ff1p98vm40c

(File:/cad/UMC_FARADAY/Faraday180nm_library/L180_MMRF/fsa0m_a/2008Q3v1.2/T33_

GENERIC_IO/FrontEnd/synopsys/fsa0m_a_t33_generic_io_ff1p98vm40c.db)

Operating Conditions: WCCOM

Library: fsa0m_a_generic_core_ss1p62v125c

Wire Load Model Mode: enclosed

Global Operating Voltage = 1.62

Power-specific unit information :

Voltage Units = 1V Capacitance Units = 1.000000pf Time Units = 1ns

Dynamic Power Units = 1mW(derived from V,C,T units) Leakage Power Units = 1pW

Cell Internal Power = 18.1065 uW (74%)

Net Switching Power = 6.4624 uW (26%)

--------------------------------------------

Total Dynamic Power = 24.5689 uW (100%)

Cell Leakage Power = 247.5292 nW

When performing timing analysis, Design Compiler must consider the worst-case and best-

case scenarios for the expected variations in the process, temperature, and voltage factors.

Report :timing -path full -delay max -max_paths



Date : Mon Jul 1 09:26:38 2013

Operating Conditions: WCCOM Library: fsa0m_a_generic_core_ss1p62v125c

Wire Load Model Mode: enclosed

Startpoint: A1/A4/temp_reg[0]

(rising edge-triggered flip-flop clocked by declk)

Endpoint : Y1 (output port clocked by declk)

Path Group : declk Path Type : max

Y1 (out) 0.00 2.29 r

data arrival time 2.29

clock declk (rise edge) 94.20 94.20

clock network delay (ideal) 0.00 94.20

output external delay -0.02 94.18

data required time 94.18

--------------------------------------------------------------------------------

data required time 94.18 ns

data arrival time -2.29 ns

----------------------------------------------------------------------------------

slack (MET) 91.89 ns

---------------------------------------------------------------------------------

Report : area



Date : Mon Jul 1 09:26:38 2013

Number of ports: 25

Number of nets: 46

Number of cells: 2

Number of references: 2

Combinational area: 102338.961316

Noncombinational area: 93786.507824

----------------------------------------------------

Total cell area: 196125.469140 um2

Process Variation Report :- This variation accounts for deviations in the semiconductor

fabrication process. Usually process variation is treated as a percentage variation in the

performance calculation.

*GDSII view of Time to Digital converter (TDC)

Fig GDSII view of Time to Digital converter (TDC)

This is the GDSII layout generated by SOC Encounterusing Faraday 180 nm library. It has

total 25 pins.11 are inputs and 10 are outputs pins ,4 pins power pins are for power supply

in each. All the stages are done check viz., floorplanning, placement, routing, antenna,

metal density, DRC in the same tool

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