cad software
DESCRIPTION
CasTRANSCRIPT
![Page 1: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/1.jpg)
CAD SoftwareVerilog HDL
![Page 2: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/2.jpg)
Figure 2.35. A typical CAD system.
Design conception
VerilogSchematic capture DESIGN ENTRY
Design correct?
Functional simulation
NoYes
No
Synthesis
Physical design
Chip configuration
Timing requirements met?
Timing simulation
![Page 3: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/3.jpg)
Design Entry
• The starting point in the process of designing a logic circuit is the conception of what the circuit is supposed to do and the formulation of its general structure.
• Two design methods:– Schematic capture– Writing source code in HDL
![Page 4: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/4.jpg)
Logic Synthesis
• Synthesis is the process of generating a logic circuit from an initial specification
• Synthesis CAD tools generate efficient implementations of circuits from such specifications
![Page 5: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/5.jpg)
Functional Simulation
• A circuit represented in the form of logic expressions can be simulated to verify that it will function as expected
• The simulator requires the user to specify valuations of the circuit’s inputs that should be applied during simulation
![Page 6: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/6.jpg)
Physical Design
• To determine exactly how to implement the circuit on a given chip
• The physical design tools map a circuit specified in the form of logic expressions into a realization that makes use of the resources available on the target chip
![Page 7: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/7.jpg)
Timing Simulation
• Electronic circuits cannot perform their function in zero delay
• propagation delay – takes a certain amount of time before a
corresponding change occurs– delay caused by signals that must propagate
along wires that connect various logic elements• A timing simulator evaluates the expected
delays of a designed logic circuit
![Page 8: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/8.jpg)
Circuit Implementation
• The circuit is implemented on an actual chip
• Two ways:– Custom-manufactured chip (ASIC) – chip
fabrication– Programmable hardware device – chip
configuration or chip programming
![Page 9: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/9.jpg)
Verilog HDL
• Hardware Description Language (HDL)• 1980s, developed by Gateway Design
Automation, which was later acquired by Cadence Design Systems
• 1990, Verilog was put into the public domain
• 1995, IEEE Standard called 1364-1995• 2001, IEEE Standard called 1364-2001
![Page 10: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/10.jpg)
2 ways to describe circuits
• Structural specification– a set of gate-level primitives that correspond to
commonly-used logic gates• Behavioral specification
– Using gate-level primitives can be tedious when large circuits have to be designed
– An alternative is to use more abstract expressions and programming constructs to describe the behavior of a logic circuit
![Page 11: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/11.jpg)
Figure 2.36. The logic circuit for a multiplexer.
Example 1
11
![Page 12: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/12.jpg)
Figure 2.37. Verilog code for the circuit in Figure 2.36.
Structural
12
![Page 13: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/13.jpg)
Figure 2.40. Using the continuous assignment to specify the circuit in Figure 2.36.
Behavioral
13
![Page 14: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/14.jpg)
Figure 2.42. Behavioral specification of the circuit in Figure 2.36.
14
![Page 15: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/15.jpg)
Figure 2.43. A more compact version of the code in Figure 2.42.
15
![Page 16: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/16.jpg)
Figure 2.39. Logic circuit for the code in Figure 2.38.
Example 2
16
![Page 17: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/17.jpg)
Figure 2.38. Verilog code for a four-input circuit.
module example2 (x1, x2, x3, x4, f, g, h);input x1, x2, x3, x4;output f, g, h;
and (z1, x1, x3);and (z2, x2, x4);or (g, z1, z2);or (z3, x1, ~x3);or (z4, ~x2, x4);and (h, z3, z4);or (f, g, h);
endmodule
Structural
17
![Page 18: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/18.jpg)
Figure 2.41. Using the continuous assignment to specify the circuit in Figure 2.39.
module example4 (x1, x2, x3, x4, f, g, h);input x1, x2, x3, x4;output f, g, h;
assign g = (x1 & x3) | (x2 & x4);assign h = (x1 | ~x3) & (~x2 | x4);assign f = g | h;
endmodule
Behavioral
18
![Page 19: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/19.jpg)
Figure 2.44. A logic circuit with two modules.
Hierarchical Verilog Code
19
![Page 20: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/20.jpg)
Figure 2.45. Verilog specification of the circuit in Figure 2.12.
Adder Module
20
![Page 21: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/21.jpg)
Figure 2.46. Verilog specification of the circuit in Figure 2.34.
Display Module
21
![Page 22: CAD Software](https://reader034.vdocuments.mx/reader034/viewer/2022042905/577cc3f91a28aba71197c371/html5/thumbnails/22.jpg)
Figure 2.47. Hierarchical Verilog code for the circuit in Figure 2.44.
Top-level Module
22