ca lp new_01

DOC/LP/01/28.02.02

LESSON PLAN LP- AP9222

LP Rev. No: 01

Date: 01-02-

2013

of 6

Sub Code & Sub Name : AP9222 COMPUTER ARCHITECTURE AND PARALLEL PROCESSING

Unit: I Branch: IT Semester: II

Unit syllabus:

UNIT I

THEORY OF PARALLELISM:

Parallel computer models - the state of computing, Multiprocessors and Multicomputers and Multivectors and SIMD computers, PRAM and VLSI models, Architectural development tracks. Program and network properties- Conditions of parallelism.

Objective: To impart knowledge in the basics of parallelism and parallel computer models.

SessionNo

Topics to be covered Time Ref, Page No

Teaching Method

1 Introduction to various Parallel computer models -the state of computing. Elements of modern computers, Evolution of computer architecture, Attributes of performance

50m 1(1-16) BB

2 Multiprocessors and Multicomputers-shared memory and distributed memory.

50m 1(17-22) BB

3 A Taxonomy of MIMD Computers 50m 1(23-24) BB4 Multivectors and SIMD computers-Vector

Supercomputers50m 1(25-28) BB

5 SIMD Supercomputers 50m 1(25-28) BB, OHP6 PRAM and VLSI models: Parallel Random-Access

machines50m 1(29-35) BB

7 Architectural development tracks-Multiple-Processor tracks 50m 1(36-43) BB8 Multivector and SIMD Tracks, Multithreaded and Dataflow

tracks50m 1(36-43) BB

9 Program and network properties- Conditions of parallelism 50m 1(44-51) BB

DOC/LP/01/28.02.02


LP Rev. No: 01

Date: 01-02-2013

of 6Sub Code & Sub Name : AP9222 COMPUTER ARCHITECTURE AND PARALLEL PROCESSING

Unit: II Branch: IT Semester: II

Unit syllabus:

UNIT II

PARTITIONING AND SCHEDULING:

Program partitioning and scheduling, Program flow mechanisms, System interconnect architectures. Principles of scalable performance - performance matrices and measures, Parallel processing applications, speedup performance laws, scalability analysis and approaches.

Objective: To learn about the performance metrics and measures, performance laws and partitioning and multiprocessor scheduling.

SessionNo


Teaching Method

10 Program partitioning and scheduling-Grain sizes and latency, Grain packing and scheduling

50m 1(52-60) BB

11 Program flow mechanisms-control flow and data flow comparison

50m 1(61-65) BB

12 System interconnect architectures-Static and Dynamic Connection networks

50m 1(66-83) BB

13 Principles of scalable performance- performance matrices and measures-Mean performance, efficiency, utilization

50m 1(89-95) BB

14 benchmarks and performance measures 50m 1(96-97) BB15 Parallel processing applications-Massive parallelism 50m 1(99-102) BB16 Scalability of parallel algorithms 50m 1(103-107) BB17 Speedup performance laws-Amdahl’s law 50m 1(108-115) BB18 Gustafson’s law, Scalability analysis and approaches. 50m 1(116-124) BB19 Tutorial 50m

DOC/LP/01/28.02.02


LP Rev. No: 01

Date: 01-02-2013


Unit: III Branch: IT Semester: II

Unit syllabus:

UNIT III

HARDWARE TECHNOLOGIES:

Processor and memory hierarchy advanced processor technology, superscalar and vector processors, memory hierarchy technology, virtual memory technology, bus cache and shared memory - backplane bus systems, cache memory organisations, shared memory organisations, sequential and weak consistency models.

Objective: To gain knowledge in advanced processor technologies and memory organizations.

SessionNo


Teaching Method

20 Processor and memory hierarchy- advanced processor technology-Design space of processors, Instruction-set architectures

50m 1(133-138) BB

21 CISC and RISC Scalar processors 50m 1(139-149) BB, OHP22 superscalar and vector processors- Superscalar processors,

VLIW architecture 50m 1(150-155) BB, OHP

23 Vector and symbolic processors 50m 1(156-159) BB, OHP24 memory hierarchy technology – Inclusion, Coherence, and

locality, Memory capacity planning50m 1(160-166) BB, OHP

25 virtual memory technology – TLB, Paging and Segmentation, Memory Replacement Policies.

50m 1(167-181) BB, OHP

26 bus cache and shared memory- backplane bus systems 50m 1(182-191) BB27 cache memory organizations – Cache addressing models,

Direct mapping and Associative Caches 50m 1(192-197) BB, OHP

28 Set-Associative and Sector Caches 50m 1(198-204) BB, OHP29 shared memory organizations 50m 1(205-212) BB, OHP30 sequential and weak consistency models 50m 1(213-220) BB

DOC/LP/01/28.02.02


LP Rev. No: 01

Date: 01-02-2013


Unit: IV Branch: IT Semester: II

Unit syllabus:

UNIT IV

PIPELINING AND SUPERSCALAR TECHNOLOGIES:

Parallel and scalable architectures, Multiprocessor and Multicomputers, Multivector and SIMD computers, Scalable, Multithreaded and data flow architectures.

Objective: To know about the parallel and scalable, multithreaded, and dataflow architectures

SessionNo


Teaching Method

31 Pipelining and Super Scalar techniques - Introduction 50m 1(227-260) BB32 Parallel and scalable architectures-Multiprocessor and

Multicomputers. Multiprocessor system Interconnects, Cache Coherence and Synchronization mechanisms.

50m 1(281-311) BB

33 Generation of Multicomputers, Message-Passing mechanisms

50m 1(312-329) BB

34 Multivector and SIMD computers- Vector processing principles, Multivector multiprocessors

50m 1(341-364) BB

35 Compound Vector Processing, SIMD Computer organizations

50m 1(372-391) BB

36 Scalable, Multithreaded and data flow architectures – Latency-hiding techniques, multithreading

50m 1(408-432) BB

37 Fine-grain multicomputers 50m 1(434-443) BB38 Scalable and Multithreaded architectures 50m 1(444-457) BB39 Dataflow and hybrid architectures 50m 1(458-464) BB40 CAT I

DOC/LP/01/28.02.02


LP Rev. No: 01

Date: 01-02-2013


Unit: V Branch: IT Semester: II

Unit syllabus:

UNIT V

SOFTWARE AND PARALLEL PROGRAMMING:

Parallel models, Languages and compilers, Parallel program development and environments, UNIX, MACH and OSF/1 for parallel computers.

Objective: To get an idea about the different software’s for parallel programming.

SessionNo


Teaching Method

41 Parallel models, Languages and compilers – parallel programming models.

50m 1(473-483) BB

42 parallel languages and compilers 50m 1(484-490) BB43 Dependence analysis of data arrays 50m 1(491-500) BB44 Code optimization and scheduling 50m 1(501-519) BB45 Loop parallelization and pipelining 50m 1(520-530) BB46 Parallel program development and environments – Parallel

programming environments, Synchronization and multiprocessing modes.

50m 1(537-551) BB

47 Shared variable program structures, Message-passing program development

50m 1(552-561) BB

48 Mapping programs onto multicomputers. UNIX, MACH and OSF/1 for parallel computers

50m 1(562-576) BB

49 CAT II

DOC/LP/01/28.02.02


LP Rev. No: 01

Date: 01-02-2013

of 6Sub Code & Sub Name : AP9222 COMPUTER ARCHITECTURE AND

PARALLEL PROCESSING

Branch: IT Semester: II

Course Delivery Plan:

Week 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

I II I II I II I II I II I II I II I II I II I II I II I II I II I II I II

Units 1 2

3 4 5

REFERENCES:

1. Kai Hwang, " Advanced Computer Architecture ", McGraw Hill International,2001.

2. Dezso Sima, Terence Fountain, Peter Kacsuk, ”Advanced Computer architecture– A design Space Approach” , Pearson Education , 2003.

3. John P.Shen, “Modern processor design . Fundamentals of super scalar processors”, Tata McGraw Hill 2003.

4. Kai Hwang, “Scalable parallel computing”, Tata McGraw Hill 1998. 5. William Stallings, “ Computer Organization and Architecture”, Macmillan

Publishing Company, 1990.6. M.J. Quinn, “ Designing Efficient Algorithms for Parallel Computers”, McGraw

Hill International, 1994. 7. Barry, Wilkinson, Michael, Allen “Parallel Programming”, Pearson Education

Asia , 20028. Harry F. Jordan Gita Alaghband, “ Fundamentals of parallel Processing”, Pearson

Education , 20039. Richard Y.Kain, “ Advanced computer architecture –A systems Design

Approach”, PHI, 2003.

Prepared by Approved bySignature

Name Dr. G. SumathiProf./IT

Prof.E.G.GovindanHOD/IT

Date 01-02-2013 01-02-2013

ca lp new_01

Documents