buck smps design.(kt1609)

8/3/2019 Buck Smps Design.(Kt1609)

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BUCK SMPS

DesignPower Electronics

Coursework Part 1

Konstantinos Tsakalis (kt1609)

11/8/2011

Design Specifications:

Input voltage: 20 V (2 V)

Output voltage: 5 V (100 mV ripple)

Maximum output current: 2 A, continuous,

resistive loads onlyOutput Current ripple: max 5% at maximum

output power

Switching frequency: 90% at full load

Maximum inductor volume of 7.5 cm3

.


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1. Basic Converter Designa) Inductor sizing

The maximum inductor current ripple is given by

= L = f Ignoring the voltage drop on the switch (or MOSFET), the current ripple requirement is satisfied if

.b) Worst case peak and RMS inductor currentThe worst case peak inductor current is the current ripple plus the output current (assuming

continuous operating mode) :f

= f

The worst case inductor RMS current is .The peak inductor current is directly proportional to the output voltage ripple. Keeping it small is

important for the quality of a power supply.

All the resistive losses due the parasitic resistance of the inductor and the other non ideal

components are proportional to the square of inductor RMS current thus directly affects theefficiency of the power supply.

c) Capacitor sizing

Assuming ideal components the cut-off frequency of the LC filter is = . For the minimuminductor value from above this gives = f. Choosing the cut-off frequency to be an order ofmaginude less than switching frequency and =0.25 this yields = .The maximum output voltage ripple is given by:

=.

=

=

f (*) Substituting maximum on for the minimum inductorvalue (which is simply 2*(5% of Iomax) = 0.2A peak-peak

we have : = f =

ffor 200mV peak -peak voltage ripple.

The results from the calculation of the capacitor from a specified voltage ripple and from the

cookbook method are very similar.

From (*) : =

f Manipulation and substitution of =

yields :

=

From this is clear the relationship between the chosen ration of frequencies and

the output voltage ripple ratio. Applying the cookbook method for the ratio of the frequencieswill result to a ripple :

1

d) Switch selection

The three options for the switch in the SMPS are:

BJT: Must operate in saturation which requires large base current. The operation in deep saturation

results in higher turn-off times which make it slower. Also the use of BJT requires complex

configuration. Finally differences in temperature can significantly affect it's behaviour and make it

unstable.

IBGT: Are very slow and there commonly used but for much higher power applications.

Power MOSFETS: They provide excellent current and voltage blocking for the desired ratings.


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They are much faster than the other two solutions and require less power to drive them. Also are

thermal stable. Thus we will choose a power MOSFET which meet our voltage and current ratings

Static and Dynamic Converter ModeNon Ideal DiodeThe converter voltage radio depends on the voltage drop across the non-deal switch and the diode.

This can be calculated from the steady state condition: = = + = ++ = (ignoring Vswitch)Thus should be slightly increased to account for the diode drop (=0.27) for the particular SMPS.Open Loop Transfer functionThe transfer function of our open loop ideal Buck SMPS is :

ss = VI sLC+s R+ = VI

s+

Rs+

Thus = and = .

The system overshoot percentage is given by 100

=100

The settling time is about = = 8 and the oscillation frequency of the output voltage is = 1 The two poles are located to . If1 0 thenboth poles are real, the system is overdamped and the output voltage will not oscillate and will not

overshoot. Otherwise the oscillation frequency is = {}{}

2. Simulation of Ideal Converter in Open Loop

From all the analysis in the second section its clear that we need to determine a switching

frequency, keeping in mind the restrictions for the inductor volume and thus size. For the following

simulations with ideal components, the switching frequency is chosen 90kHz which leads to a

236 inductor and 1.5F capacitor (approximate from equations in Section 1). A lower frequencywould mean smaller switching losses from the mosfet and the driver but also the need for a larger

inductor, which leads to significant higher ESL which is the major power loss factor as can be seen later

on. Also a larger inductor is makes very difficult to achieve the size specifications.

Figure 2: PSpice model of ideal converter1) Efficiency


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To model an ideal converter, the of the switch reduced from 1 to 1 and the to 10.However the Dbreak diode has a voltage drop of 0.8V (measured for = 2.5 duringconduction. This will result to a power loss Pdiode = VdropD1 = 1.2WAlso the output voltage will not be 5V for a duty cycle 0.25 but = 1 = 4.4(for 2.5 ). Thus the efficiency is

=

+=

..

.+.

. = 0.864.

The efficiencies (in steady state) from the spice simulation are:

() Efficiency (%)2.5 1.76 85.9 (slightly smaller than

calculate because of the

finite conductivity of the switch)

5 0.9 86.8

10 0.45 87.5

20 0.22 87.8

100 (discontinuous) 0.06 93.9

The efficiency is slightly increased with lighter resistive loads because the forward voltage drop of

the diode is smaller for smaller currents.

Efficiency (%) ()18 3.87 84.6 2.5

20 4.37 85.9 2.5

22 4.86 87 2.5

The efficiency increases as the output voltage increases since the voltage drop in the diode (and thus

the losses) remains steady for such small fluctuations in current, but the output power increases.

2) Start-up behaviour

The figure above depicts the transient response of the output voltage. From the spice using Evaluate

Measurement :

2.5 5 10 25 100%overshoot - - 13 41 30Settling(5%)

262 120 57 154 220

Rise 184 86 42 34 33


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Oscillation

freq.- - 43kHz 53.4kHz 55Khz

4.4 4.41 4.42 4.5 6.4The frequency of oscillation is very small compared to the settling time and cannot be accurately

measured from the simulation waveforms. From the transfer function in section 1 the oscillation

frequency is

= {}

{}for

6. Thus we calculate the theoretical

Oscillation frequencies.

3) Extreme loads

Under extreme Load conditions (2.5 which draw the maximum specified current and open-circuit

(used a 10M resistor)) we observe the following output voltage:

We see a huge difference to Voltage ratios .

When we draw the maximum current the voltage

ratio is slightly under the duty-cycle (0.24). When

we draw the minimum current the Voltage ratio

becomes 1. This happens because the output

current is so small that during the off time the

inductor current will reduce to zero and the

converter will operate in discontinuous mode.

Then the ratio is =

+

, which almost is

almost 1 for low Io.

Specifically the converter enters discontinuous

mode when

. For the above implementation any resistive load

greater than 49 will put the converter in discontinuous mode.

From the s domain equations we would expect a large load to cause a small damping (near to zero)

and cause wild oscillations and a very large settling time (8RC). But because the period of our

pulses is very small compared to the settling time, the

resulting output voltage is not a step response but a pulse

train response. By convolving the pulse train with the

impulse response (which decays very slowly in case of

large R) is easy to show that the output voltage will reach

fast and smoothly the maximum allowable value.

On the left is the output voltage for 10

load when the period of pulse train is large,

and the output voltage is indeed a step

response

3. Real Components ChoicesAll the components chosen below have voltage and current ratings well above the specifications of

the converter.Inductor:1422435C (220) with ESL=0.096

IMPULSE REPONSE FOR 10Mfrom t=0 to

t=1sec


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http://onecall.farnell.com/murata-power-solutions/1447423c/inductor-470uh-2-

3a/dp/1077019?Ntt=1447423C

Is an inductor within the specified size limits (7.48cm3), it has a closed loop core and thus the

magnetic flux will not escape to affect the PCB track. Finally it has a relative low series resistance.

MOSFET:

http://uk.rs-online.com/web/p/products/7394866/An excellent (but quite expensive) MOSFET with very low = 3.6 , and with small turn onand turn off times to ensure minimum losses. It has also a low Gate charge (low total input

capacitance) which will result in faster switching and less losses from the driver. In reality a cheaper

MOSFET with higher and the same (even lower) speed can be used without affecting theefficiency since the conductivity losses are insignificant compared to the switching losses.MOSFET DRIVER:

http://onecall.farnell.com/international-rectifier/ir2181pbf/driver-mosfet-high-low-side-

2181/dp/1023243.

The driver of the MOSFET needs to be able to supply a relative large current for a very short period

of time to charge the stray input capacitance of the mosfet gate as quickly as possible and turn it on.

The existence of a SPICE model was a factor for the above choice. In reality, to accomplishsynchronous rectifications we will use the following.http://docs-

europe.electrocomponents.com/webdocs/0c91/0900766b80c91a9b.pdfwhich also can provide

higher current. Also in the real implementation the gate resistors have to be chosen to limit the

current to avoid destroying the MOSFET. For the driver chosen in SPICE simulations the maximum

current is within the limits of the mosfet.DIODE:

http://onecall.farnell.com/nxp/pmeg3030ep/diode-schottky-rec-30v-3a-

sod128/dp/1829195?Ntt=PMEG3030EPA schottky diode with low voltage drop.CAPACITOR:

http://uk.farnell.com/sanyo/25sh1-5m/capacitor-1-5uf-25v/dp/9189432 Capacitance:1.5F ESR:0.3

4. Simulations and Analysis with real components
http://onecall.farnell.com/murata-power-solutions/1447423c/inductor-470uh-2-3a/dp/1077019?Ntt=1447423Chttp://onecall.farnell.com/murata-power-solutions/1447423c/inductor-470uh-2-3a/dp/1077019?Ntt=1447423Chttp://uk.rs-online.com/web/p/products/7394866/http://uk.rs-online.com/web/p/products/7394866/http://onecall.farnell.com/international-rectifier/ir2181pbf/driver-mosfet-high-low-side-2181/dp/1023243http://onecall.farnell.com/international-rectifier/ir2181pbf/driver-mosfet-high-low-side-2181/dp/1023243http://docs-europe.electrocomponents.com/webdocs/0c91/0900766b80c91a9b.pdfhttp://docs-europe.electrocomponents.com/webdocs/0c91/0900766b80c91a9b.pdfhttp://docs-europe.electrocomponents.com/webdocs/0c91/0900766b80c91a9b.pdfhttp://docs-europe.electrocomponents.com/webdocs/0c91/0900766b80c91a9b.pdfhttp://onecall.farnell.com/nxp/pmeg3030ep/diode-schottky-rec-30v-3a-sod128/dp/1829195?Ntt=PMEG3030EPhttp://onecall.farnell.com/nxp/pmeg3030ep/diode-schottky-rec-30v-3a-sod128/dp/1829195?Ntt=PMEG3030EPhttp://uk.farnell.com/sanyo/25sh1-5m/capacitor-1-5uf-25v/dp/9189432http://uk.farnell.com/sanyo/25sh1-5m/capacitor-1-5uf-25v/dp/9189432http://uk.farnell.com/sanyo/25sh1-5m/capacitor-1-5uf-25v/dp/9189432http://onecall.farnell.com/nxp/pmeg3030ep/diode-schottky-rec-30v-3a-sod128/dp/1829195?Ntt=PMEG3030EPhttp://onecall.farnell.com/nxp/pmeg3030ep/diode-schottky-rec-30v-3a-sod128/dp/1829195?Ntt=PMEG3030EPhttp://docs-europe.electrocomponents.com/webdocs/0c91/0900766b80c91a9b.pdfhttp://docs-europe.electrocomponents.com/webdocs/0c91/0900766b80c91a9b.pdfhttp://onecall.farnell.com/international-rectifier/ir2181pbf/driver-mosfet-high-low-side-2181/dp/1023243http://onecall.farnell.com/international-rectifier/ir2181pbf/driver-mosfet-high-low-side-2181/dp/1023243http://uk.rs-online.com/web/p/products/7394866/http://onecall.farnell.com/murata-power-solutions/1447423c/inductor-470uh-2-3a/dp/1077019?Ntt=1447423Chttp://onecall.farnell.com/murata-power-solutions/1447423c/inductor-470uh-2-3a/dp/1077019?Ntt=1447423C


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1) Efficiency

For duty cycle 0.25 the output voltage is 4.8V because there is an approximate 0.25V drop in the

diode. Thus for 2.5 = 1,92.The expected losses are

MOSFET switching and conduction:

= ( ) = 201.92902060=138mW = = 3.68 3.6 0.25 =3.3mWGate Driver: = = 20 70 10 9 0 1 0 = 126Inductor: = = 3.680.096 = 350Diode: Pdiode = VdropD1 = 360mWPower at load = = 9.216Thusexpected efficiency: =90.4%

PSpice Simulation Results

The efficiencies under The losses from the various

various loads are: components (for = 2.5)() Efficiency (%)2.5 89.9

4 90.3

6 90.1

10 88.9

15 87.4

25 83.8

50 discontinuous 76.7

100 83

150 85200 85

Efficiencies under various input voltages:

Efficiency(%) ()18 4.27 89.5 2.5

20 4.8 89.9 2.5

22 4.86 90.2 2.5

Losses are reasonably close to the calculated. The major cause of power loss is the inductor series

resistance and the diode.2) Start-up behaviour

Component Diode Mosfet Driver Others(mW)

390 143 150 354 negligible


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The figure above depicts the transient response of the output voltage. From the simulation:

2.5 4 6 10 15 25 50 100%overshoot - - - 8.7 23 40 56 41

Settling(5%)

295uS 174uS 120uS 130uS 160uS 210uS 145uS 260uS

Rise 154uS 95uS 58uS 32uS 24uS 22uS 19.5uS 23.5uSOscillation

freq.

4.83 4.94 5 5.6 6.42 7.45 8.6 9.4 Vss Vss Vss 5.1 6 7 8.1 8.95

As increases further than 50 the output voltage goes significantly over 5V since theconverter enters discontinuous operation. The conversion ratio becomes:

=

+

In order to achieve output voltage 5V for 20V input the duty cycle has to be increased to 0.28. But

this is not an issue since later we will introduce dynamic control of the duty cycle.3) Extreme loads The same behaviour as in the ideal case in section 2.3

5. Synchronous RectificationAs shown in the previous simulation the efficiency of the SMPS is hardly the minimum required

(90%). However the 45% of the losses are due to the voltage drop across the non-ideal diode. A

trade-off can be done between improved efficiency and increased cost & complexity. The diode can

be replaced with a second MOSFET which act as a switch. During the on-time (when inductor

stores energy) the mosfet is off and during the off-time (when inductor releases energy) the mosfet

turns on.

Then the power losses from the diode

= 1 become

=

1 plus

the switching losses.

However if both MOSFETs conduct simultaneously offer a low impedance path which effectively is

a short-circuit of the power supply with the ground. To avoid this there must be a certain delay

before either of the fets switched on to ensure that the other has switched off. To accomplish this

there must be a short time where neither the mosfets conduct, the dead-time. However this dead-

time results in excess power loss as we will see .

In practice the dead time generation can be achieved using a driver like this one

http://uk.rs-online.com/web/p/mosfet-power-drivers/6613034/unfortunately I couldnt find a spice

model for any mosfet driver with non-independent logic inputs, so I used two independent control

signals.
http://uk.rs-online.com/web/p/mosfet-power-drivers/6613034/http://uk.rs-online.com/web/p/mosfet-power-drivers/6613034/http://uk.rs-online.com/web/p/mosfet-power-drivers/6613034/


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In SPICE its easy to generate the two differentcontrol signals with very small dead time using

separate Pulse generators. Of course such

implantation its only for constant .

Simulation Results : Efficiency

The output voltage now goes to 4.9V with

=0.25 because there is no voltage drop at the

diode.

Thus = 9.6Components power losses under maximum load (2.5

Component syncFET(red) Mosfet(green) Driver(yellow)Including all related

components

(blue) Others (mW) 85 265 155 368 negligibleWe note that:

The upper MOSFET power consumption has increased by 85mW

Driver consumption has almost doubled (+75mW), since now drives two MOSFETS

There is a major reduction in the losses from diode (almost 300mW).

The efficiency has increased by 2% and is now 91.6% under maximum load.

The excess power consumption in the upper MOSFET is due to the dead time. When none of the

MOSFETS conduct, the freewheeling diode of the upper MOSFET is in brought in conduction.Before the MOSFET turn on the freewheeling diode has to turn off. In order for the diode to switch

off, all the minority carriers stored in it have to be removed. This reverse-recovery current has to be


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absorbed by the MOSFET, causing additional power losses.

The reverse recovery losses are = = 58

In yellow is the gate voltage of the synchronous mosfet

and in green the Drain voltage of the upper MOSFET.

The oscillations in the left upper corner are the effect

of the reverse recovery.

The synchronous rectifier can be implemented in two

ways:

Using the additional mosfet to emulate the diode (by sensing the voltage across the upper MOSFET

and witching the lower MOSFET accordingly e.g http://www.irf.com/product-

info/datasheets/data/ir1168.pdf) . This rectifier would allow the current to flow only in one direc-

tion. When the inductor current drops to zero the rectifier turns off and this will cause ring-ing across the rectifier due to the parasitic capacitance.

The second way of implementing a synchronous rectifier

is by complementary switching the two MOSFETs usingtiming logic as in simulations above. This will cause a

continuous conduction even with small loads since the

MOSFET now conducts both directions. Under small

loads which cause inductor current to go to zero, the

mosfet will continue to conduct and will produce a nega-

tive inductor current as shown in figure. When the upper

mosfet turns on the inductor current will be negative and

the converter will transfer power from the output to the

input with ohmic losses. During the negative-inductor-

current interval, the circuit temporarily acts like a boost

converter.

7. Closed Loop System

The output voltage of the BUCK smps converter

depends on varying load and input voltage

conditions. Also the output the voltage

conversion ratio depends on varying parameters

of the non-ideal components. By adding feedbackwe can adjust the duty cycle of the converter and

regulate the output voltage to the required
http://www.irf.com/product-info/datasheets/data/ir1168.pdfhttp://www.irf.com/product-info/datasheets/data/ir1168.pdfhttp://www.irf.com/product-info/datasheets/data/ir1168.pdfhttp://www.irf.com/product-info/datasheets/data/ir1168.pdf


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reference level (5V).

The open loop buck smps circuit is nonlinear, but can simply approximated (detail in notes) as apulse train with average value is which is applied in passive low-pass filter.Thus the transfers function of the open loop BUCK smps is

= + + or including the

parasitic components: = ++ ++++ ++

For L=220 = 0.096C=1.4F = 0.01The frequency response of the open loop system for = 2.5 , 6 ,10, 26 can be seen from theBode plots:

From the above plot we can see that for = 2.5 the phase margin is 90 which is very good.However for higher load resistors, the phase margin is very small and this could cause instability inthe closed loop. This is the first indication for the need to compensate.

Here we can see the

closed loop step

response of the system

with unity feedback,

without any

compensation:

The system has a very

fast response (in thescale of tens/hundreds

sec) under all loads.

Double complex poles of

LC filter. In the case of

R=2.5 is a single realSecond real pole

in the case R=2.5

(or if generally

Large zero due to

capacitor and its own

equivalent resistance

adds 90

0.827


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There is no overshoot for a 2.5 load but the overshoot for lighter loads is too high. Also the steady

state error is large and this could seriously affect the purpose of the control system, to read the

output voltage and adjust the duty cycle it, to fix it.

The steady state error can be decreased by increasing the proportional gain of the open loop.

The resulting closed loop response for a proportion gain 20 is this:

Now the steady error has

decreased to a negligiblelevel, response is faster

(settling time is about

40S) but the overshoot is

unacceptable even for the

heaviest load. Another

side effect of the

increased gain is in the

increased bandwidth of

the closed (and open)

loop.

As can be seen from the

closed loop Bode plots

the bandwidth now

extends to 120 kHz and

allows the switching

frequency parasitic

components to enter the

control loop and possibly

cause random switching.

Thus a proportional

compensator is not

enough and should use

another type of

compensation to eliminate the steady state error. If we want to compensate for < 6 a PIcompensator is good enough, but for bigger resistors where a complex pair of poles emerges a PID

compensator is needed to counteract the effect of the under-damped resonance at the double pole

frequency. However if we choose aUsing MATLABs sisotool for the system with = 7 , with the desired bandwidth to be about9kHz and 60 degrees phase margin we get the following compensator

= 7105 (+.) .However for large load resistors at load the resonant peak occurs for low frequencies with a very

low phase margin and this could cause instability. (The maximum value of is the seriesresistance of the potential divider at output which has to be large so doesnt affect the converter).

To ensure unconditional stability for all load resistors we choose a PID compensator

G=1

G=20


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With a mix of the cookbook method at [3] and

some tuning with the matlab sisotool we get

the following PID compensator:

The gain

is derived assuming that a potential is used

to measure the output voltage.

The resulting closed loop response for

= 2.5 5

We have a very small overshoot (less than 3%) for

= 2.5 and a settling time about 350S.

The bandwidth is now 3300Hz.

We can increase the bandwidth

by increasing the proportional

gain of the compensator. This

will increase overshoot but we

can tolerate this since the

specifications allow overshoot

up to 10%

7.2 Closed loop PSpice Model

ote: A switch was usedinstead of a MOSFET

because the MOSFET

created convergence

problems and auto

convergence reduced the

accuracy so much that the

ripples in the output

voltage were not

represented.

The SPICE simulation results for = 2.5 5

Gain 4170100

Zeros [-25000;-50000]

Poles [-2200000;-565000;0]


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The Evaluate Measurement

tool gives overshoot 1.9% for

both loads. Auto convergence

has been used for the above

result and such I dont know

how accurate the results are.

Compensation Network using Opamps

The chosen compensator has the

following parameters

The generic PID controller depicted above has the following transfer function

Solving the system for

R1=5000;syms R2R3C1C2C3;

gain=(R1+R3)/(R1*R3*C1); zero1=1/(R2*C2); zero2=1/((R1+R3)*C3);

pole1=(C1+C2)/(R2*C1*C2); pole2=1/(R3*C3);

S=solve(gain-4170100,zero2-50000,zero1-25000,pole1-2200000,pole2-

565000); S=[S.R2 S.R3 S.C1 S.C2 S.C3]

yields the values depicted on the figure. In the Apendix can be seen the closed loop Behaviour .

By moving the second zero and second pole we can adjust the behaviour of the compensator and

trade-off between speed, overshoot and bandwidth. Thus it would be useful to select R3 to beadjustable.

Gain 4170100

Zeros [-25000;-50000]

Poles [-2200000;-565000;0]


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The frequency response of the compensator simulated at PSpice:

References:[1]EE3-14: Power Electronics and Machines notes

[2]MOSFET Power Losses Calculation Using the Data-Sheet Parameters

http://www.btipnow.com/library/white_papers/MOSFET%20Power%20Losses%20Calculation%20

Using%20the%20Data-Sheet%20Parameters.pdf

[3]Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators

http://www.intersil.com/data/tb/tb417.pdf
http://www.btipnow.com/library/white_papers/MOSFET%20Power%20Losses%20Calculation%20Using%20the%20Data-Sheet%20Parameters.pdfhttp://www.btipnow.com/library/white_papers/MOSFET%20Power%20Losses%20Calculation%20Using%20the%20Data-Sheet%20Parameters.pdfhttp://www.btipnow.com/library/white_papers/MOSFET%20Power%20Losses%20Calculation%20Using%20the%20Data-Sheet%20Parameters.pdfhttp://www.intersil.com/data/tb/tb417.pdfhttp://www.intersil.com/data/tb/tb417.pdfhttp://www.intersil.com/data/tb/tb417.pdfhttp://www.btipnow.com/library/white_papers/MOSFET%20Power%20Losses%20Calculation%20Using%20the%20Data-Sheet%20Parameters.pdfhttp://www.btipnow.com/library/white_papers/MOSFET%20Power%20Losses%20Calculation%20Using%20the%20Data-Sheet%20Parameters.pdf

buck smps design.(kt1609)

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