b.tech project guidelines and schedule

1. I. GUIDELINES FOR CONDUCT OF B TECH FINAL YEAR PROJECTS 2014-15

1. Procedure for the Preparation of Project Description Document (PDD):

a. Each faculty member should give five to six projects (problem definitions) along with description in the form of a project description document (PDD) by 11th AUG 2014 to the project coordinator. The format for the same is available with the departments.

b. The project coordinator should conduct a PRC meeting to evaluate the PDDs submitted by the faculty on 14th AUG 2014.

c. The suggestions made by the PRC to be intimated to the faculty and the corrected PDDs to be collected before 18th AUG2014.

d. A single spiral bound booklet to be prepared containing all the PDDs given by all the faculty members and copies of the same may be maintained in the department.

e. A soft copy (in pdf format) containing all the PDDs to be prepared and sent to all the students through email by 2nd Dec 2014.

f. The soft copy to be also made available in the college portal by 02nd Dec 2014.2. The project schedules containing the duration and deadlines for all the project related activities to

be intimated to the students by 02nd Dec 2014.3. Procedure for Formation of Project Batches:

a. Project batches should not contain more than three students. The project batches made according to section wise.b. Department-wise merit list containing top 34%, middle 33%, and bottom 33% of the students

in the department to be prepared and intimated to the students by 31st JULY 2014. c. Each student from the top 34% should be allowed to select one student from middle 33%

and another from bottom 33% as project batch members. d. Formation of batches to be completed by 14th AUG 2014.

4. Procedure for Allocation of Projects and Project Guides to Students:a. Allocation of projects to be done based on the merit list by conducting counseling sessions

on or before 19th Dec 2014. b. During the counseling session, top 34% students along with their batch members to be called

in the order of merit and to be made to select the project from the list of projects given in the PDD.

c. The students should select a project that is not already allotted to a previous batch in the order of merit.

d. The project guide for the students should be the faculty member, who has proposed the project.

5. Procedure for Formation of Project Evaluation Committee (PEC)a. The committee to be formed with the following members:

i. Head of the Departmentii. Project coordinator

iii. Two senior faculty members of the departmentiv. One additional senior faculty member from other department if warrantedv. Internal and external guides

6. Procedure for Submission and Evaluation of Project Abstracts:a. Project abstracts in the prescribed format attested by the project guide to be submitted by

all the project batches by 27th Dec 2014 to the project coordinator.b. The project coordinator should conduct a PEC (Project Evaluation Committee) to assess the

quality of abstracts.c. Quality assessment of abstracts and rejection or acceptance to be declared by 31st Dec 2014.d. Students whose abstracts are selected should start the project work from 02nd Jan 2015.e. Students whose abstracts are rejected should resubmit their abstract with corrections

suggested by the faculty by 31st Dec 2014.f. If the abstracts are rejected after resubmission, students are not allowed to do the project

for this academic year.7. Procedure for Establishment of Project Laboratories:

a. The PDDs given by all the faculty members to be consolidated on the basis of hardware and software requirements.

b. A list of various hardware and software requirements to be prepared based on the consolidation made.

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c. A project laboratory satisfying the listed hardware and software requirements to be established by 15th Dec 2014.

8. Technology training to be conducted for the students in platform areas during literature survey phase.

9. Students are not to be allowed to take up any projects outside the college.10. Students are allowed to do only experimental projects and no study projects are allowed.11. Each student has to pay Rs.5000 towards the project expenses on or before 22nd Dec 2014.12. Students having more than 15 backlogs are not to be made eligible for doing project work.13. Procedure for Conducting Domain Knowledge and Platform Knowledge Test:

a. Students to be tested in domain area after literature survey phase and platform area after design and analysis phase during project work.

b. The project guides should prepare a descriptive question paper containing 5 questions in the domain area of the project each carrying two marks for each project they are guiding.

c. Similarly, 5 questions to be prepared in the platform area of the project.d. Common question paper for two different projects may be prepared if the domain and

platform areas of both the projects are same.e. Each test to be conducted and evaluated for 10 marks.f. Students to be allowed to proceed to the next phase only if they secure qualifying score (at

least 60%) in each test.g. Project guides should intimate the syllabus for the domain knowledge and platform

knowledge tests to their students well in advance.14. Procedure for Conducting Project Written Examination:

a. A project written examination to be conducted at the end of the semester for all the students who successfully complete the all the phases of the project.

b. The examination should contain 40 multiple choice/fill-in-the-blank questions prepared by project guides for each project they are guiding.

c. The questions to be given from domain and platform areas of the project and may include questions on design, analysis, and testing phases of the project.

d. The examination should be conducted and evaluated for 40 marks.15. All the student presentations of projects and viva voce examinations will be video shot and copy of

it will be given to the candidates in the form of a CD.16. Procedure for Project Seminar Presentations:

a. All the project seminar presentations must be made by the students by preparing a PowerPoint presentation over a LCD projector.

b. Before the presentation the students should get the approval for proceeding with the seminar from the project guide.

c. All the students in the project batch must be present and participate in the seminar.d. Seminar presentations to be evaluated by PEC for 15 marks.

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III. PROJECT SCHEDULE FOR B TECH FINAL YEAR – 2014-15

S.No Activity Duration Deadline

1 Display of Project Schedules 28th July 2014

2 Preparation and Display of Merit Lists 31st July 2014

3 Formation of Project Batches 14th Aug. 2014

4 Preparation and Display of PDDs 2nd Dec. 2014

5 Establishment of Project Laboratories 15th Dec. 2014

6 Allocation of Projects 19th Dec. 2014

7 Abstract Submission 29th Dec. 2014

8 Quality Assessment of Abstracts and Abstract seminar 31st Dec. 2014

9 Commencement of Project Work 2nd Jan. 2015

10 Literature Survey 1 Weeks 9th Jan. 2015

11 Domain Knowledge Test (10 Marks) 1 Day 12th Jan. 2015

12 Project Seminar I (15 Marks) 1 Day 16th Jan. 2015

13 Design and Analysis Phase 3 Weeks 6th Feb. 2015

14 Platform Knowledge Test (10 Marks) 1 Day 7th Feb. 2015

15 Project Seminar II (15 Marks) 1 Day 11th Feb. 2015

16 Implementation Phase 3 Weeks 2nd Mar. 2015

17 Result Analysis 1 Weeks 9th Mar 2015

End Semester Project Examination

a. Submission of Manuscript Copy of the Project 1 Day 10th Mar 2015

b. Project written examination (40 MCQ/FIB) (40 Marks) 1 Day 11th Mar 2015

c. Review of Project Manuscripts and Intimation of Corrections 1 Weeks 18th Mar 2015

d. Project Report Submission (40 Marks) 1 Week 25th Mar 2015

e. Presentation of project work (video shoot) (40 Marks) 1 Day 1 Week of April 2015

f. Viva Voce Examination (video shoot) (30 Marks) 1 Day 1 Week of April 2015

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2. INDEX OF THE PROJECTS (GUIDE WISE)

Sl No.

Name Of The Faculty Designation Title Of The Project Page

No.

I

Prof. K.V.Srinivasa

Rao Professor

1. Array Of Two Horn Antenna For More Directivity- Hardware Implementation And Testing2. Simulation Of Rectangular Micro strip Antenna Using HFSS Software – Performance Evaluation

3. Design , Simulation And Testing Of Helical Antennas.

4. Design Of Waveguide Windows For Variable Reactances – Implementation And Testing

II Mr.V.Kumar Swamy

Assoc.Prof. & Hod

1. A Modified Approach For Symmetric Key Cryptography Based On Blowfish Algorithm2. An Efficient FPGA Implementation Of The AdvancedEncryption Standard Algorithm

III Ms. T. Sireesha Assoc. Prof.

1. Performance Evaluation Of CSA Multiplier , Braun Multiplier And Vedic Multiplier Using Microwind

2. Side-Channel Attack Tolerant Logic Styles And Its Application On SBOX Of Des System Using Spice.3. Design And Implementation Of High Performance 64 Bit Mac Unit For Dsp Applications.4. A High Performance Binary To Bcd Converter For Decimal Multiplication

5. Scalable Digital CMOS Comparator using a parallel prefix tree

6. An ALU Optimized for area and power

V Mr. I.V.S Rama Sastry

Assoc. Prof.

1. Design And Microstrip Feed Rectangular Microstrip Antenna

2. Design And Simulation Of Probe Feed A Square Microstrip Antenna

3. Design Of 2x1 Microstrip Antenna Array

4. Bandwidth Improvement Technique For A Square Microstrip Antenna5. Design Of High Frequency Low Pass/High Pass Filter Using Microstrip Lines.

VI Mr. G. M. Ganesh Assoc. Prof.

1. Performance Analysis Of Multi User Ds-CDMA System Over AWGN Channel In Mobile Environment

2. Design And Implementation Of 8-Psk System In AWGN Channel Using Matlab

3. Performance Of Symmetrical Pam For The Optimum Receiver In AWGN Channel

4. Design And Implementation Of FDMA System For Wireless Communications

VII Mr. Vinod Chavan

Assoc. Prof.

1. The Application Of Pic And Zigbee Technology Wireless Networks In Monitoring Mine Safety System

2. Design Of Embedded Ethernet Based Web Server For Interface For Monitoring And Controlling

3. Passenger Bus Alert System For Easy Navigation Of Blind

4. Design Of An Efficient And Optimized Algorithm For Serial-Parallel Multiplication Using Aop

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5. Human Health Monitoring Using Wireless Sensors Network

VIII Mr. K. Satish Assoc. Prof.

1. Vlsi Implementation Of Sha-2 Algorithm

2. Test Data Compression With Efficient Dictionary Selection Method

3. Performance Analysis Of Manet Routing Protocols

IX Mr. C. Pramod Kumar

Asst. Prof.

1. Remote Guidance For The Blind — A Proposed Tele Assistance System

2. Remote Control For Rural Irrigation

3. Automatic Accident Detection And Ambulance Rescue With Intelligent Traffic Light System

XMr. Shravan

Kumar Reddy M

Sr. Asst. Prof.

1. Orthogonal Frequency Divisional Multiplexing For Wireless Networks

2. Pulse Shaping Filters With Isi Free Properties

3. Statistical Region Merging

4. SVD Based Image Compression

5. Image Segmentation Techniques

XI Mr. Sravan Kumar R. Asst. Prof.

1. FPGA Implementation Of Combinational Lock For Security System

2. FPGA Implementation Of FIFO Controller

3. FPGA Implementation Of Vending Machine Using State Machines

4. Design Of Low Power And High Speed Configurable Booth Multiplier

XII Mr.A.Sai Prasad Goud Asst. Prof.

1. Implementation Of BIST For Testing Combinational Circuit Using FPGA

2. Home Automation System Design Using Verilog Hdl.

3. FPGA Implementation Of Intelligent Car Parking System For Real Time Application

XIIIMr.N.Pradeep Kumar Goud

Asst. Prof.

1. Implementation Of Touch Screen Based Home Appliances Control System Using Arm7 Lpc2148 And Zigbee2. Touch Screen And Zigbee Based Wireless Communication Assistant For Dumb/Illiterates In Airlines

3. Implementing Agricultural Field Management System Using GSM

4. Anti Theft Controlling System Using Embedded System

5. Design And Application Of Mobile Embedded System For Home Care Application

XIV Ms.T.Saritha Asst. Prof.

1. Reduction Of Leakage Current And Power In Full Subtract or Using Mtcmos Technique2. FPGA Implementation Of Alamouti Mimo Selection For Receiver-Antenna Selection Combining

3. Design Of Optimized Cic Decimator And Interpolator In FPGA

4. Error Detection In Majority Logic Decoding Of Euclidean Geometry Low Density Parity Check (Eg-Ldpc) Codes

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Aurora’s Engineering College, BhongirPROJECT DESCRIPTION DOCUMENT (Not to exceed one page)

Faculty Name K.V.SRINIVASA RAO

Department E.C.E.

Project Title ARRAY OF TWO HORN ANTENNAS FOR MORE DIRECTIVITY- HARDWARE IMPLEMENTATION AND TESTING

Description

Horn Antenna is widely used in most of the microwave communication systems both at transmitter and receiver end. The gain of the antenna depends on the aperture area and flare angle. Instead of doing with a single horn, many horns can be arranged as a linear array so that more directivity can be achieved. The project is about the theoretical calculations for directivity and performance along with array factor calculations in case of a two-horn antenna system .

Hardware/Equip. Requirements Klystron microwave bench setup, horn antennas, VSWR meter.

Software Requirements Matlab 7.1, Windows 7

Project Activity Recommended Duration Suggested Duration by Faculty

Literature Survey 3 weeks 3 weeks

Analysis and Design 4 weeks 4 weeks

Implementation/Experimentation 3 weeks 3 weeks

Result Analysis 2 weeks 2 weeks

Documentation 1 week 1 week

Overall 13 weeks 13 weeks

Suggested Readings

Books1. Books Antenna Handbook – Johnson2. Antenna theory and design - Belanis

Journals1. IEEE transactions on Antennas and propagation2. IEEE transactions on digital communications3. Antennas and propagation magazine

Websites1. www.antenna-theory.com/antennas/patches/antenna.php2. www.orbanmicrowave.com

Any other information

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http://www.orbanmicrowave.com/



Department E.C.E.

Project Title SIMULATION OF RECTANGULAR MICROSTRIP ANTENNA USING HFSS SOFTWARE – PERFORMANCE EVALUATION

Description

In the present day research work connected with the design and simulation of microstrip antennas HFSS software is widely used worldwide. The advantage of HFSS software is that the designer can directly model the structure and can investigate its performance. The simplest of all microstrip antennas is the rectangular patch which can easily be fabricated on a substrate. The Project is about the design and simulation and modeling of it using HFSS software. Performance evaluation also will be made in regard to the directional characteristics of the antenna .

Hardware/Equip. Requirements -

Software Requirements

HFSS, Windows 7








Suggested Readings

Books1. Books Antenna Handbook – Johnson2. An tenna theory and design - Belanis


Websites1. www.antenna-theory.com/antennas/patches/antenna.php2. www.orbanmicrowave.com


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Department E.C.E.

Project Title DESING , SIMULATION AND TESTING OF HELICAL ANTENNAS

Description

Helical antenna can be used in axial mode of operation for high directivity. As it is cheaper and easier to construct and de4sign it can be used as an alternative to parabolic antenna. This is used at VHF and UHF. The project involves in the design of helical antenna in VHF range and is tested for its performance.

Hardware/Equip. RequirementsSoftware Requirements

Matlab 7.1








Suggested Readings

1. Books Antenna Handbook – Johnson2 . Antenna theory and design – Belanis3 Microwave engineering - Reich


Websites1.www.antenna-theory.com/antennas/patches/antenna.phpPurpose: For learning basic concepts on Microstrip Antenna2. www.orbanmicrowave.com


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Department E.C.E.

Project Title DESIGN OF WAVEGUIDE WINDOWS FOR VARIABLE REACTANCES – IMPLEMENTATION AND TESTING

Description

Microwave windows are used for getting required reactance and are used in microwave repeaters as equalizers. Though irises can be used they are not precise and are very unstable in their values. Windows are simple to design for any required reactance. These are used during the signal transmission through a waveguide at a specific calculated position. The project involves the designing of rectangular windows and the calculation of reactance for various dimensions.

Hardware/Equip. Requirements Windows 7

Software Requirements Matlab 7.1








Suggested Readings

Books : 1. Antenna Handbook – Johnson

2. Antenna theory and design - Belanis 3. Microwave engineering - Reich

Journals1. IEEE transactions on Microwave engineering

Websites1.www.antenna-theory.com/antennas/patches/antenna.phpPurpose: For learning basic concepts on Microstrip Antenna2. www.orbanmicrowave.com


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Faculty Name V. Kumara Swamy

Department ECE

Project Title A Modified Approach for Symmetric Key Cryptography Based on Blowfish Algorithm

Description

The principal goal of designing any encryption algorithm is to hide the original message and send the non readable text message to the receiver so that secret message communication can take place over the web. The strength of an encryption algorithm depends on the difficulty of cracking the original message. A number of symmetric key encryption algorithms like DES, TRIPLE DES, AES, BLOWFISH has been developed to provide greater security affects one over the other. Although the existing algorithms have their own merits and demerits but this project presents a new approach for data encryption based on Blowfish algorithm. The blowfish algorithm is safe against unauthorized attack and runs faster than the popular existing algorithms. With this new approach we are implementing a technique to enhance the security level of blowfish algorithm and to further reduce the time for encryption and decryption.

Hardware/Equip. Requirements PC, CPLD/FPGA Board

Software Requirements Xilinx ISE/Model Sim , Leonordo Spectrum








Suggested Readings

Books1. William stallings, Cryptography and Network Security , 5Th Edtn, Prentice Hall, New Delhi, 20112. Bernard menezes, Network Security and Cryptography, 1st Edtn, Cengage Learning India , 20103. Behrouz A.Forouzan, Cryptography and Network Security,2nd Edition, TMH, 2010

Journals1.International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958,Volume-1, Issue-6, August 2012 2. International Journal of Engineering and Research & Technology (IJERT) ISSN: 2278-0181, Volume-2, Issue 8, August 2013Websiteswww.ijeat.org, www.mecs-press.org


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http://www.ijeat.org/


Faculty Name V. Kumara Swamy

Department ECE

Project TitleAn efficient FPGA implementation of the AdvancedEncryption Standard algorithm

Description

A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this project. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S-box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.

Hardware/Equip. Requirements PC, CPLD/FPGA Board

Software Requirements Xilinx ISE/Model Sim , Leonordo Spectrum








Suggested Readings

Books1. William stallings, Cryptography and Network Security , 5Th Edtn, Prentice Hall, New Delhi, 20112. Bernard menezes, Network Security and Cryptography, 1st Edtn, Cengage Learning India , 20103. Behrouz A.Forouzan, Cryptography and Network Security,2nd Edition, TMH, 2010

Journals2. International Journal of Reconfigurable and Embedded Systems (IJRES)Vol. 1, No. 2, July 2012, pp. 67~74ISSN: 2089-4864Websites : ieeexplore.ieee.orgiaesjournal.comwww.researchgate.net


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Faculty Name T.Sirisha

Department ECE

Project Title Performance Evaluation of CSA Multiplier , Braun Multiplier and Vedic Multiplier using MICROWIND

Description

Multiplication is a fundamental operation in most signal processing algorithms. Multipliers consumes large area, long latency and more power. Therefore designing multipliers having low-power consumption, minimum area is an important part in low-power VLSI system design. There has been extensive work on low-power multipliers at technology, physical, circuit and logic levels. These low-level techniques are not unique to multiplier modules and they are generally applicable to other types of modules. In the past multiplication was generally implemented via a sequence of addition and shift operations. Multiplication can be considered as a series of repeated additions. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product. When the operands are interpreted as integers, the product is generally twice the length of operands in order to preserve the information content. This repeated addition method that is suggested by the arithmetic definition is slow that it is almost always replaced by an algorithm that makes use of positional representation. It is possible to decompose multipliers into two parts. The first part is dedicated to the generation of partial products, and the second one is to collects and add them. Following multipliers are designed using DSCH2 and Microwind VLSI CAD tools and performance is evaluated and results are compared. 1. CSA multiplier. 2. Braun array multiplier. 3. Proposed Vedic multiplier

Hardware/Equip. Requirements PC


DSCH2 VLSI CAD tools and MICROWIND 3.0 VLSI CAD tools


Literature Survey 3 weeks 4 weeksAnalysis and Design 4 weeks 3 weeksImplementation/Experimentation 3 weeks 3 weeksResult Analysis 2 weeks 2 weeksDocumentation 1 week 1 weekOverall 13 weeks 13 weeks

Suggested Readings

Books:

Journals:1. Muhammad H. Rais and Mohammed H. Al Mijalli, Virtex-5 FPGA Based Braun’s Multipliers, IJCSNS International Journal of Computer Science and Network Security, VOL.11 No.8, August 2011. 2. Nirlakalla Ravi, Anchula Satish, Dr.Talari Jayachandra Prasad and Dr. Thota Subba Rao, A New Design for Array Multiplier with Trade off in Power and Area, IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 3, No. 2, May 2011. 3. Prabha S. Kasliwal, Dr. B. P.Patil, Dr. D.K.Gautam, Performance Evaluation of Squaring Operation using Vedic Mathematics, IETE Journal of Research, Vol 57 ,Issue 1, Jan-Feb 2011,pp 39-414. S.Savari Rani, S.Ramasamy, C.Christober Asir Rajan, and V.Harini, An 8x8 Subthreshold Braun Array Multiplier in 32nm CMOS Technology for Wireless SensorNodes, International J. of Recent Trends in Engineering and Technology, Vol. 3, No. 2, May 2010.5. Raminder Preet Pal Singh, Parveen Kumar, Balwinder Singh, Performance Analysis of 32-Bit Array Multiplier with a Carry Save Adder and with a Carry-Look-Ahead Adder, International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009. 6. C. Senthilpari, Ajay Kumar Singh, K. Diwakar, Design of a low-power, high performance, 8*8 bit multiplier using a Shannon-based adder cell, IEEE Electr. (2008). 7. M. Mottaghi-Dastjerdi, A. Afzali-Kusha, and M. Pedram , A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture, To appear in IEEE Trans. on VLSI Systems, 2008 .

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Websites:


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Faculty Name T.Sirisha

Department ECE

Project Title Side-Channel Attack Tolerant Logic Styles and its application on SBOX of DES system using SPICE.

Description

The objective of the project is to implement SBOX of a DES cryptosystem with standard CMOS logic style and different side-channel attack tolerant (SCAT) logic styles. Then a comprehensive comparison of the power, area, speed and SCAT of these implementations will be made. This also deal with the Spice simulation and layout design of non-standard logic styles. The contribution of this project is to explore the design trade-off between various MOS logic styles with the same metrics, especially the cost of applying SCAT logic styles to deep sub-micron cryptosystems.



SPICE Design Evaluation tools.








Suggested Readings

Books:

Journals: 1.W. Fischer, B. M. Gammel,Masking at the Gate Level in The Presence ofGlitches, in the proceedings of CHES 2005, Lecture Notes in Computer Science,vol 3659, pp 187-200, Edinburgh, Scotland, August 2005. 2.S. Guilley, P. Hoogvorst, Y. Mathieu, R. Pacalet,The Backend Duplication Method: A Leakage-Proof Place-and-Route Strategy for ASICs, in the proceedings of CHES 2005, LNCS, vol 3659, pp 383-397, Edinburgh, UK,Sept. 2005.3. I. Hassoune, F. Mac e, D. Flandre, J.-D. Legat,Low-swing current mode logic(LSCML): a new logic style for secure ́�smart cards against power analysis attacksin Microelectronics Journal, vol 37, num 9, pp 997-1006, Elsevier, September 2006Websites:


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Faculty Name T.Sireesha

Department E.C.E

Project Title IMPLEMENTATION OF A LOW POWER DUAL EDGE - TRIGGERED STATIC D- FLIP FLOP USING MICROWIND.

Description

This project deals with the new architecture of low power dual-edge triggered Flip-Flop (DETFF). In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered Flip-Flop (SETFF). In this project conventional and proposed DETFF are to be implemented and compared at same simulation conditions. the proposed DETFF design is suitable for low power and small area applications.











Suggested Readings

Books : 1. Frank Propen, “Low power design guide” reference book. 2. Neil H.E.,David Harris, “CMOS VLSI Design” Third Edition, Boston: Pearson, 2005 .

Journals[1] Stojanovic, V.; Oklobdzija, V.G., "Comparative analysis of master-slave latches and flip-flops forhigh-performance and low-power systems," Solid-State Circuits, IEEE Journal of , vol.34, no.4, pp.536,548, Apr 1999.[2] Nedovic, Nikola; Aleksic, M.; Oklobdzija, V.G., "Conditional pre-charge techniques for powerefficient dual-edge clocking," Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on , vol., no., pp.56,59, 2002.[3] Nedovic, Nikola; Aleksic, M.; Oklobdzija, V.G., "Comparative analysis of double-edge versus single edge triggered clocked storage elements," Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , vol.5, no., pp.V-105,V-108 vol.5, 2002.[4] Phyu, M.-W.; Goh, W.L.; Yeo, K.-S., "A low-power static dual edge-triggered flip-flop using anoutput-controlled discharge configuration," Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on , vol., no., pp.2429,2432 Vol. 3, 23-26 May 2005.[5] Dai, Yanyun, and Shen, Jizhong, “Structure and design method for pulse-triggered flip–flops atswitch level”, J. Cent. South Univ. Technol., 17, (6), pp. 1279–1284, 2010.[6] Xue-Xiang Wu; Ji-Zhong Shen, "Low-power explicit-pulsed triggered flip-flop with robustoutput," Electronics Letters , vol.48, no.24, pp.1523,1525, November 22 2012.International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013Websites: 1. http://www.altera.com/literature/cp/cp-pwropt.pdf


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http://www.altera.com/literature/cp/cp-pwropt.pdf



Department E.C.E

Project TitleDESIGN AND IMPLEMENTATION OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC LOGIC UNITUSING VHDL.

Description

Reversible Logic is gaining significant consideration as the potential logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the outputs. Significant contributions have been made in the literature towards the design of fault tolerant reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in any computing device and it has to be made fault tolerant. In this project we aim to design one such fault tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed ALU can generate up to seven Arithmetic operations and four logical operations.

Hardware/Equip. Requirements

PC


FPGA ADV ,ModelSim Simulator & Leonardo Spectrum Synthesis tools.








Suggested Readings

Books: 1. Frank Propen, “Low power design guide” reference book. 2. Neil H.E.,David Harris, “CMOS VLSI Design” Third Edition, Boston: Pearson, 2005 . 3. Anantha P. Chandrakasan and Robert W. Brodersen “Minimizing Power Consumption in CMOS Circuits” Department of EECS,University of California at Berkeley.

Journals[1] R. Landauer,”Irreversibility and Heat Generation in the Computational Process”, IBM Journal of R&D,1961[2] C.H. Bennett, “Logical reversibility of Computation”, IBM J. Research and Development, pp.525-532, November 1973.[3] A. Peres, Reversible logic and quantum computers, Phys. Rev. A 32 (1985) 3266–3276.[4] E. Fredkin and T. Toffoli,”Conservative Logic”, Int’l J. Theoretical Physics Vol 21, pp.219-253,1982.[5] R Feynman “ Quantum Mechanical Computers”, Optical News, Vol.11, pp 11-20, 1985[6] Krishna Murthy, Gayatri G, Manoj Kumar “Design of Efficient Adder Circuits Using Proposed ParityPreserving Gate” VLSICS Vol.3, No.3, June 2012.[7] Haghparast, M. and K. Navi, “ A novel fault tolerant reversible gate for nanotechnology basedsystems”. Am. J. Appl. Sci., 5(5).2008[8] Md. Saiful Islam et.al” Synthesis of fault tolerant Reversible logic”IEEE 2009[9] Rakshith Saligram and Rakshith T.R. “Design of Reversible Multipliers for linear filteringApplications in DSP” International Journal of VLSI Design and Communication systems, Dec-12[10] B. Parhami, “Fault tolerant reversible circuits”, Asimolar Conf. Signal systems and computers”,October 2006

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Websites: 1. http://en.wikipedia.org/wiki/Power_optimization_(EDA) 2. http://www.altera.com/literature/cp/cp-pwropt.pdf


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http://en.wikipedia.org/wiki/Power_optimization_(EDA)



Department E.C.E

Project Title Design and Implementation of Power efficient carry propagate adder using microwind

Description

This Project deals with performance of proposed Carry Propagate Adder based on GDI (Gate Diffusion Input)technique. . In GDI cell, inputs are applied at source/drain of nMOS and pMOS as well as gate input. There are total three inputs (N, P, and G) with one output.GDI technique is power efficient technique for designing digital circuit that consumes less power as compare to most commonly used CMOS technique. GDI also has an advantage of minimum propagation delay, minimum area required and less complexity for designing any digital circuit. We designed Carry Propagate Adder using GDI technique and compared its performance with CMOS technique in terms of area, delay and power dissipation. Circuit designed using CADENCE EDA tool and simulated using SPECTRE VIRTUOSO tool at 0.18m technology. Comparative performance result shows that Carry Propagate Adder using GDI technique dissipated 55.6% less power as compare to Carry Propagate Adder using CMOS technique.











Suggested Readings

Books : Morris Mano, Digital System Design, 3rd Edition

Journals[1] Radu Zlatanovici, Sean Kao, and Borivoje Nikolic, “Energy–Delay Optimization of 64-Bit CarryLookahead Adders With a 240 ps 90 nm CMOS Design Example”, IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL. 44, NO. 2, FEBRUARY 2009 [2] Arkadiy morgenshtein, Alexander fish and Israel a .wagner, “Gate Diffusion input (GDI): A power efficient method for digital combinatorial circuits”, IEEE Transaction on very large scale integration (VLSI) systems vol.10, no. 5 October 2002.[3] Arkadiy Morgenshtein, Idan Shwartz and Alexander Fish, “Gate Diffusion Input (GDI) Logic in Standard CMOS Nanoscale Process” 2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel[4] N.H.E.Weste, David Harris Ayan Banerjee, “CMOS VLSI design, Pearson Education Publication, Sixth Impression, 2008[5] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low- power CMOS digital design,” IEEE J. Solid-State Circuits, vol. 27, pp. 473–484, Apr. 1992.[6] A. P. Chandrakasan and R.W. Brodersen, “Minimizing power consumption in digital CMOS circuits,” Proc. IEEE, vol. 83, pp. 498–523, Apr. 1995.[7] W. Al-Assadi, A. P. Jayasumana, and Y. K. Malaiya, “Pass-transistor logic design,” Int. J. Electron., vol. 70, pp. 739–749, 1991.[8] K. Yano, Y. Sasaki, K. Rikino, and K. Seki, “Top-down pass-transistor logic design,” IEEE J. SolidState Circuits, vol. 31, pp. 792–803, June 1996.[9] V. Adler and E. G. Friedman, “Delay and power expressions for a CMOS inverter driving a resistive capacitive

18

load,” Analog Integrat. Circuits Signal Process., vol. 14, pp. 29–39, 1997.[10] J. R. Burns, “Switching response of complementary symmetry MOS transistor logic circuits,” RCA Rev., vol. 25, pp. 627–661, Dec. 1964.Websites:


19


Faculty Name B.Gouri Sivanandhini

Department E.C.E

Project Title Design and implementation of High Performance 64 bit MAC Unit for DSP Applications.

Description

MAC unit is an inevitable component in many digital signal processing (DSP)

applications involving multiplications and accumulations. MAC unit is used for high

performance digital signal processing systems. The speed of the multiplication and

addition arithmetic determines the execution speed and performance of the entire

calculation . A design of high performance 64 bit Multiplier-and-Accumulator (MAC) is

proposed. The multiplier is designed using modified Wallace multiplier and the adder is

done with carry save adder.

Hardware/Equip. Requirements FPGA/CPLD Trainer Kit

Software Requirements Xilinx tools


Literature Survey 3 weeks 03

Analysis and Design 4 weeks 04

Implementation/Experimentation 3 weeks 03

Result Analysis 2 weeks 02

Documentation 1 week 01

Overall 13 weeks 13

Suggested Readings

Books: Dsp processors and its Architecture by avtar singh

Journals

Websites:


20



Department E.C.E

Project Title A High performance Binary to BCD Converter for Decimal Multiplication

Description

Decimal data processing applications have grown exponentially in recent years thereby

increasing the need to have hardware support or decimal arithmetic. Binary to BCD

conversion forms the basic building block of decimal digit multipliers. A novel high speed

low power architecture for fixed bit binary to BCD conversion is proposed. Decimal

arithmetic operations are generally slow and complex, its hardware occupies more area.

They are typically implemented using iterative approaches or lookup table based

reduction schemes.

Hardware/Equip. Requirements FPGA/CPLD Trainer Kit

Software Requirements Xilinx tools







Overall 13 weeks 13

Suggested Readings

BooksDsp processors and its Architecture by avtar singh

journal

Websites:


21

Aurora’s Engineering College, Bhongir

PROJECT DESCRIPTION DOCUMENT (Not to exceed one page)


Department E.C.E

Project TitleScalable Digital CMOS Comparator using a parallel prefix tree

Description

Comparators are key design elements for a wide range of applications in scientific

computation and image/signal processing.

A comparator design featuring wide range and high speed operation using conventional

digital CMOS cells is proposed. Comparator exploits a novel scalable parallel prefix

structure that leverages the comparison outcome of the MSB, proceeding bitwise towards

the LSB only when compared bits are equal. This method reduces dynamic power

dissipation by eliminating unnecessary transitions.


Software Requirements MICROWIND







Overall 13 weeks 13

Suggested Readings

Books:“Fundamentals of CMOS VLSI Design”, by V.G Kiran kumar,H.R.Nagesh , pearson publications,2011

Journals: Saleh abdel hafeez, A Gordon ross and Behrooz parhami,”scalable digital CMOS Comparator using a parallel prefix tree”, IEEE Transaction on VLSI System. Websites: www.ijser.org www.researchgate.net


22

Aurora’s Engineering College, Bhongir

PROJECT DESCRIPTION DOCUMENT (Not to exceed one page)


Department E.C.E

Project TitleAn ALU Optimized for area and power

Description

In the era of growing technology and scaling of devices up to nanometer, the ALU are to

be designed with compact size less power and propagation delay. Design of 4 bit ALU by

including the concept of gate diffusion input(GDI) technique is proposed.

GDI cells are used in design of multiplexer and full adders which are then associated to

realize ALU.


PC

Software Requirements MICROWIND







Overall 13 weeks 13

Suggested Readings

Books:“Fundamentals of CMOS VLSI Design”, by V.G Kiran kumar,H.R.Nagesh , pearson publications,2011

Journals: Vivechana Dubey and Ravi mohan sai ram,”An ALU optimized for area and power”, IEEE Transaction 2014 ACCT. Websites: www.ijettcs.org www.researchgate.net


23


Faculty Name I.V.S.Rama Sastry

Department ECE

Project Title Design of Microstrip feed Rectangular Microstrip antenna APPLICATION: Wireless LAN application

Description

In high performance aircraft, space craft, satellite and missile applications, where size, weight, cost, performance ,ease of installation and aerodynamic profiles are constraints, low profile antennas may be required. Presently there are many other government and commercial applications, such as mobile radio and wireless communications that have similar specifications. To meet these requirements microstrip antennas can be used. The simplest form of microstrip antenna consists of radiator on one side of the substrate material and ground on the other side. There are numerous advantages of microstrip antennas in wireless communication system because of its desirable characteristic.. To increase the rate of data transfer, increased antenna bandwidth is required. Various schemes have been suggested for the design of antenna to get large bandwidth..Many other broadband techniques are used in Microstrip antennas include thick substrates, employing parasitic elements either in coplanar or stacked configurations with other approaches such as cutting slots inside the regular MSA geometries or changing the shapes of MSA to a diamond shape.The main aim of this project to design a rectangular microstrip antenna at a frequency of 2.45 GHz (Wireless LAN frequency) using transmission line model. It is fed with 50 ohms microstrip line.The design calculations can be done by using MATLAB software tool and the various parameters of rectangular MSA Viz input impedance, gain, return loss, VSWR can be obtained by using High frequency simulation software version 12.1.



1. Microstrip Antennas simulation softwares (any one): HFSS/IE3D/FEKO` 2.MAT LAB (For design calculations)


Literature Survey 3 weeks 20hrs

Analysis and Design 4 weeks 25hrs

Implementation/Experimentation 3 weeks 24hr

Result Analysis 2 weeks 16hrs

Documentation 1 week 10hrs

Overall 13 weeks 104hrs

Suggested Readings

Books: 1.Constaine A. Balanis, “Antenna Theory analysis and design”, Second/ Third Edition 2..Girish Kumar and K.P. Ray : Broad band Microstrip Antennas” Artech House, Antennas and Wave propagation Library,2003 Edition

1. Journals“Rectangular Microstrip Patch Antenna at 2GHZ on Different Dielectric Constant for Pervasive Wireless Communication”, Md. Maruf Ahamed, Kishore Bhowmik, Md. Shahidulla, Md. Shihabul Islam, Md. Abdur Rahman , International Journal of Electrical and Computer Engineering (IJECE).Vol.2, No.3, June 2012, pp. 417 ~ 424 ISSN: 2088-8708.

2. “Analysis And Design of Rectangular Microstrip Patch Antenna On Different Resonant Frequencies For Pervasive Wireless Communication” Md. Maruf Ahamed, Kishore Bhowmik, Abdulla Al Suman.international journal of scientific & technology research volume 1, issue 5, june 2012 issn 2277-8616.

3. Design of a compact Microstrip Patch Antenna for use in Wireless ...etd.lib.fsu.edu/theses/available/etd-04102004-143656/.../Chapter4.pdf Microstrip patch antenna design and results, Chapter-4.p.p 48-50

4. Websites www.antenna-theory.com/antennas/patches/antenna.phpPurpose: To understand the basic concepts &Design of Microstrip.

5. www.iaesjournal.com/online/index.php/IJECE/article/view/341/pdf

24

Purpose:to understand the design of rectangular Microstrip antenna6. ieeexplore.ieee.org › ... › Signal Processing and Communication

Purpose:To familiar in the design of rectangular Microstrip antenna.


Testing is not possible. Hardware can be made. Only Simulation Results to be executed.

25



Department ECE

Project Title A Design of a probe feed Square patch antenna at a frequency of 1.8GHz APPLICATION: Wireless LAN application

Description

Description: There are numerous advantages of microstrip antennas in wireless communication system because of its desirable characteristic. But there are various disadvantages of microstrip antenna such as narrow bandwidth typically 1-5% and low gain which is the major limiting factor for the application of these antennas. To increase the rate of data transfer, increased antenna bandwidth is required. Various schemes have been suggested for the design of antenna to get large bandwidth. Although these antennas have good impedance bandwidths, but have bidirectional radiation pattern which further reduces the gain .Many other broadband techniques are used in Microstrip antennas include thick substrates, employing parasitic elements either in coplanar or stacked configurations with other approaches such as cutting slots inside the regular MSA geometries or changing the shapes of MSA to a diamond shape. In this project work, a Square microstrip antenna at a frequency 1.8GHz will be designed using transmission line model and its various parameters Viz input impedance, gain, return loss, VSWR, BW .. can be obtained by using High frequency simulation software version 12.1



1. Microstrip Antennas simulation softwares (any one): HFSS/IE3D/FEKO2.MAT LAB (For design calculations)








Suggested Readings

Books: 1.Constaine A. Balanis, “Antenna Theory analysis and design”, Second/ Third Edition 2..Girish Kumar and K.P. Ray : Broad band Microstrip Antennas” Artech House, Antennas and Wave

propagation Library,2003 Edition.

Journals: 1. International Journal of Application or Innovation in Engineering & Management (IJAIEM)“Design, Simulation and Analysis of a Square Shaped S band Microstrip Antenna”... Web Site: www.ijaiem.org Volume 2, Issue 1, January 2013.2. .International Journal of Innovative Technology and Exploring Engineering (IJITEE)ISSN: 2278-3075, Volume-1, Issue-1, June 2012“Design of a Square Microstrip Patch Antenna” Shruti Vashist, M.K.Soni, Pramod Singal.3. International Journal of Advanced Research in Computer Science and Software Engineering , Volume 3, Issue 8, August 2013 ISSN: 2277 128X ,www.ijarcsse.com“Design, Simulation and Analysis of a Square Shaped S-band”

Websites: 1.www.antenna-theory.com/antennas/patches/antenna.phpPurpose: 2.www.orbanmicrowave.com 3.www.ijarcsse.com/docs/papers/Volume_3/8.../V3I8-0177.pdf


26


Testing is not possible. Hardware can be made. Only Simulation Results to be executed

27



Department ECE

Project Title Bandwidth improvement technique for a square microstrip antennaAPPLICATION: Wireless LAN application

Description

Description:.A reasonable thickness should be considered in the selection of substrate and the bandwidth would be enhanced using additional techniques. Various techniques have been implemented in the past to overcome these shortcomings including the use of modifying the shape of the patch, making slots on patch (V-slot, U-slot, H-slot, diagonal slot, square, ring slot antennas, etc) by different feeding methods in single layer and multilayer configurations.In this work we introduce one of the BW enhancement techniques.on microstrip antenna .The main objective of this project is to design a basic a Rectangular/Square microstrip antenna at a frequency of 2.45 GHz (Wireless LAN frequency) using transmission line model. A slot is introduced on the radiator, to enhance the BW. The slot may be either V or U shape. The design calculations can be done by using MATLAB software tool and the various parameters of rectangular MSA Viz input impedance, gain, return loss, VSWR can be obtained by using High frequency simulation software version 12.1.


1. Microstrip Antennas simulation softwares (any one): HFSS/IE3D/FEKO2.MAT LAB 7.0(For design calculations








Suggested ReadingsBooks: 1.Constaine A. Balanis, “Antenna Theory analysis and design”, Second/ Third Edition

2..Girish Kumar and K.P. Ray : Broad band Microstrip Antennas” Artech House, Antennas and Wave propagation Library,2003 Edition

Journals:1 “Bandwidth Enhancement for Microstrip Patch Antenna Using Stacked Patch and Slot” IEEE 2“Bandwidth Enhancement of Probe Fed Microstrip Patch Antenna”

International Journal of Electronics Communication and Computer Technology (IJECCT) Volume 3 Issue 1 (January 2013) ISSN:2249-7838 IJECCT | www.ijecct.org 368

Websites: 1 www.ijecct.org 368 2.www.iosrjournals.org www.iosrjournals.org 15 | Page ISSN: 2278-2834, ISBN: 2278-8735. Volume , Issue 4 (Sep-Oct. 2012), PP 15-18



28



Department ECE

Project Title Design of 2x1 microstrip antenna array.APPLICATION: Wireless communication systems

Description

Description: Antennas play a very important role in the field of wireless communications. Some of them are parabolic reflectors, patch antennas, slot antennas and folded dipole antennas. Each type of antenna is good in its own properties and usage. We can say antennas are the backbone and almost everything in the wireless communication without which the word could have not reached at this age of technology .Patch antennas play a very significant role in today's world of wireless communication systems. A microstrip patch antenna is very simple in the construction using a conventional microstrip fabrication technique. The patch can take any shape but rectangular and circular configurations are the most commonly used configurations. These patch antennas are used as simple and for the widest and most demanding applications. Dual characteristics, circular polarizations, dual frequency operation, frequency agility, broad band width, feed line flexibility and beam scanning can be easily obtained from these patch antennas..A microstrip antenna consists of conducting patch on a ground plane separated by dielectric substrate. Low dielectric constant substrates are generally preferred for maximum radiation. Microstrip antennas are very versatile and are used, among other things, to synthesize a required pattern that cannot be achieved with a single element. In addition, they are used to scan the beam of an antenna system, increase the directivity, and perform various other functions which would be difficult with any one single element. The elements can be fed by a single line or by multiple lines in a feed network arrangement. In this project work a two elementa antenna array has been proposed to develop the performance of this antenna. A single feed is provived for both elements.. The performance characteristics of the antenna array, i.e. radiation patterns, reflected loss, efficiency and antenna gain, etc. can be obtained by using electromagnetic simulator HFSS simulation results.


1. Microstrip Antennas simulation softwares (any one): HFSS/IE3D/FEKO2.MAT LAB 7.0(For design calculations)








Suggested ReadingsBooks: 1.Constaine A. Balanis, “Antenna Theory analysis and design”, Second/ Third Edition

2..Girish Kumar and K.P. Ray : Broad band Microstrip Antennas” Artech House, Antennas and Wave propagation Library,2003 Edition3.David.M.Pozar, “ Microwave Engineering”, Second Edition, 1993,John Wiley&Sons,INC

Journals: 1.International Journal of Electronic Engineering Research , © Research India Publications Volume 1 Number 1 (2009) pp. 71–77,http://www.ripublication.com/ijeer.htm

29

2. Modeling and simulation of Microstrip patch array for smart antennas by K Meena - Cited by 8 - Related articleswww.cscjournals.org/csc/manuscript/Journals/IJE/volume3/.../IJE-131.pd...

Websites: 1. www.idc-online.com/.../Design%20of%20an%208X1%20Square%20Mi... 2.Design of an 8X1 Square Microstrip Patch. Antenna Array. V.R. Anitha. 1 and S. Narayana Reddy.

Dept of EEE, SV University, Tirupati. 2.



30

https://scholar.google.co.in/scholar?bav=on.2,or.r_qf.&biw=1366&bih=634&bvm=pv.xjs.s.en_US.zw3S-PWncBk.O&um=1&ie=UTF-8&lr&q=related:hLHXVo-v0P8NtM:scholar.google.com/

https://scholar.google.co.in/scholar?bav=on.2,or.r_qf.&biw=1366&bih=634&bvm=pv.xjs.s.en_US.zw3S-PWncBk.O&um=1&ie=UTF-8&lr&cites=18433426304999600516

http://www.cscjournals.org/csc/manuscript/Journals/IJE/volume3/Issue6/IJE-131.pdf



Department ECE

Project Title Design of high frequency Low pass/High pass filter using microstrip lines.APPLICATION: Wireless Communication systems

Description

Description: The microwave filters are based on distributed parameters rather than lumped inductors and capacitors. For low-power applications, stripline and microstrip filters are extensively used because of their low cost and repeatability. For high-power requirements, waveguide structures are utilized. Microstrip line is bimetallic which contain two metallic surface separated with a small distance, having a dielectric material between them.. The filter is required in all RF-communication techniques. Low Pass Filters play an important role in wireless power transmission systems. Transmitted and received signals have to be filtered at a certain frequency with a specific bandwidth. In this paper the design of filter is done in the ISM (Industrial, Scientific and Medical) band whose frequency lies between 1.55GHz- 3.99GHz. After getting the specifications required, we realized the filter structure with the help of HFSS software, and the filter characteristics and its various parameters Viz,insertion loss,S-paramers can be obtained from software simulation results.


1. Microstrip Antennas simulation softwares (any one): HFSS/IE3D/FEKO2.MAT LAB 7.0(For design calculations)








Suggested ReadingsBooks: 1.David.M.Pozar, “ Microwave Engineering”, Second Edition, 1993,John Wiley&Sons,INC 2. Reinhold Ludwig, Gene Bogdanow “ RF circuits Design Theory and Applications “ , 2 nd Edition,Pearson

publication

Journals: 1.“Design and Simulation of Magic Tee and Ring Hybrid Coupler using Ansoft HFSS” Parul Dawar Dept. of ECE, Guru Tegh Bahadur Institute of Technology, Rajouri Garden,New Delhi, India.pp No.199-203, IJCST Vol. 2, Issue 1, March 2011; I S S N : 2 2 2 9 - 4 3 3 3 ( P r i n t ) | I S S N : 0 9 7 6 - 8 4 9 1 2.Broad-Band Design of Improved Hybrid-Ring 3-dB Directional Couplers”. Dong Il Kim; Naito, Y.; "Microwave Theory and Techniques,IEEE Transactions, 1982 , pp. 2040 - 2046”,

Websites: www.gooogle.com for this topic



31

http://www.gooogle.com/

Aurora’s Engineering College, BhongirPROJECT DESCRIPTION DOCUMENT

Faculty Name G.M.GANESH

Department ECE

Project Title Performance Analysis of Multi User DS-CDMA System Over AWGN Channel in Mobile Environment

Description

Multiple Access Communications allows more than one sender use the same channel for transmission with potential problem of collision when sent simultaneously. In CDMA, each user is provided with an individual and distinctive PN code. The CDMA System uses in today’s 3G and 4G Mobile Communications.This project will include Transmitter design module, AWGN channel and Receiver design module. This project implemented using MATLAB software and also verify with theoretical results.

Hardware/Equip. Requirements COMPUTER SYSTEM ,Lenovo company,2GB RAM,250GB HD

Software Requirements MATLAB 2010 a.








Suggested Readings

Books : 1) Wireless communications -2002 edition, PHI, RAPPAPORT. 2) Digital communications -4th edition, TMG,JOHN.G.PROAKIS 3) Digital Communications – 2nd edition, PHI, BERNALD SKLAR.

Journals: 1) Overview of CDMA Evolution Toward Wideband CDMA,IEEE Communications,Vol.1,No.1,19981) 2) Performance Analysis of CDMA Based Wireless Communication Systems Using Simplified Improved

Gaussian Approximation Method, IEE Transaction On Communications, 19 May 2004.2) 3) Venkategowda, N.K.D.; Jagannatham, A.K., \WR based semi-blind channel estimation

for frequency-selective MIMO MC-CDMA systems," 2012 IEEE Wireless Communications and Networking Conference (WCNC), pp.317-321, 1-4 April 2012.

Websites : 1) www.mathworks.com 2) www.wikipedia.com




Department ECE

32

http://www.wikipedia.com/

http://www.mathworks.com/

Project Title Design and implementation of 8-PSK System in AWGN Channel using MATLAB

Description

As the digital communications industry continues to grow and evolve, the applications of modulation techniques continue to grow as well. In digital communication system design, the main objective is to receive data as similar as the data sent from the transmitter. In digital modulation schemes, the PSK system has less probability of error than any other digital modulation schemes like ASK,FSK and DPSK systems . The proposed system consists of transmitter block, AWGN channel and receiver block. This project implemented using MATLAB software and also verify with theoretical results.

Hardware/Equip. Requirements COMPUTER SYSTEM with Internet connection

Software Requirements MATLAB 2010A.








Suggested Readings

Books : 1) MATLAB Help Documents, Communications Toolbox.,2007. 2) Digital communications -4th edition, TMG,JOHN.G.PROAKIS 3) Digital Communications – 2nd edition, PHI, BERNALD SKLAR.

Journals: 1) IEEE Transaction on Communications. 2) IEEE International, Mobile Radio Personal Communication. 3) IEEE Transaction on Spread Spectrum

Websites : 1) www.mathworks.com 2) www.wikipedia.com


33





Department ECE

Project Title Design and Implementation of FDMA System for Wireless Communications

Description

For radio systems there are two resources, frequency and time. Division by frequency, so that each pair of communicators is allocated part of the spectrum for all of the time, results in Frequency Division Multiple Access (FDMA). FDMA System allows more than one sender use the allocated channel band for transmission with potential problem of collision when sent simultaneously. In FDMA, each user is provided with an individual and distinctive carrier frequency. The FDMA System useful in analog and multi carrier mobile communication systems. This project will include Transmitter design module, AWGN channel and Receiver design module. This project implemented using MATLAB software and also verify with theoretical results.

Hardware/Equip. Requirements COMPUTER SYSTEM ,Lenovo 2GB RAM,250GB HD.

Software Requirements MATLAB 2010 a.








Suggested Readings

Books : 1) MATLAB Help Documents, Communications Toolbox.,2007. 2) Digital communications -4th edition, TMG,JOHN.G.PROAKIS 3) Digital Communications – 2nd edition, PHI, BERNALD SKLAR.Journals: 1) Spread Spectrum For Global Communications-II, IEEE Transaction On Communications,Vol .18,No.11.Jan 2000.Page No.1-5. 2) Anti-jamming message Driven Frequency Hopping –Part-I:System Design- IEEE WirelessCommunication,Vol.12,issue 1,page 70-79,Januvary 2013.

3) 3) Venkategowda, N.K.D.; Jagannatham, A.K., \WR based semi-blind channel estimationfor frequency-selective MIMO MC-CDMA systems," 2012 IEEE Wireless Communications and Networking Conference (WCNC), pp.317-321, 1-4 April 2012. Websites : 1) www.mathworks.com 2) www.wikipedia.com


34





Department ECE

Project Title Performance of Symmetrical PAM for the Optimum Receiver in AWGN Channel

Description

Binary digital data can be represented as either a symmetrical polar or a asymmetrical unipolar PAM signal. The binary rectangular PAM transmitter and simple filtered PAM receiver can be implemented in the presence of AWGN with the optimum receiver (matched filter). A bit error analysis for the binary symmetrical rectangular PAM communication system with the optimum receiver can be obtained by using the ratio of Eb/No as the SNR parameter. This project implemented using Simulink software.


COMPUTER SYSTEM ,Lenovo,2GB RAM,250 GB HD.

Software Requirements MATLAB 2010a AND SIMULINK




Implementation /Experimentation 3 weeks 3 weeks




Suggested Readings

Books : 1) MATLAB Help Documents, Communications Toolbox.,2007. 2) Digital communications -4th edition, TMG,JOHN.G.PROAKIS 3) Digital Communication Systems Using MATLAB and Simulink – Dennis Silage

Journals: 1) Performance improvement of PAM DS UWB signal in AWGN Channel based on EMD –Signal Processing Systems(ICSPS),5-7 July 2010,Vol.3,Pages 139-142. 2) Ultra Wideband System Performance studies in AWGN Channel with Intentional Interference-Hamalainen Websites : 1) www.mathworks.com 2) www.dennis-silage.com


35



Faculty Name Mr. Vinod Chavan

Department E.C.E

Project TitleThe Application Of PIC and Zigbee Technology Wireless Networks In Monitoring Mine Safety System

Description

The foremost critical task for coal mine is of keeping track of miners spread out across a large mining areas .It becomes even difficult when mine tunnels collapse. Many mines use a radio system to track miners, but when a collapse occurs, the base stations connected by a thin wire often are rendered useless. In this project to overcome the demerits of radio system we used wireless technology for tracking the miners. For this purpose a small RF transmitter module is equipped to each person entering a mine. Each transceiver placed in the mine look after the location of miners. The transceivers communicate with base stations through zigbee module. In addition of tracking the location of miners we also include sensors such as temperature & humidity to intimate the base station & miners when some atmosphere changes occur. Mine operators are now able to monitor the real-time locations of each miner to better pinpoint their locations in the event of an emergency. Even after a full-day of use, mine operators can locate an individual miner within ten feet.


Pic Microcontroller, RF Module, Zigbee Module and Sensors


MPLAB, Embedded C








Suggested Readings

BooksWireless sensor networks, K.Sohraby PIC Microcontroller and Embedded Systems : Using assembly and C for PIC 18 , Danny Causey, Rolin McKinlay, Muhammad Ali Mazidi, 1st EditionJournalsInternational Conference: Computing, Communication, Control, and Management, 2008. CCCM '08

Websites:www.ieeexplore.ieee.org www.researchgate.net


36

http://www.researchgate.net/



Department E.C.E

Project Title Design of Embedded Ethernet based web server for Interface for Monitoring and Controlling

Description

Computer communication systems and especially the Internet are playing an important role in the daily life. Using this knowledge many applications are imaginable. Home automation, utility meters, appliances, security systems, card readers, and building controls, which can be easily, controlled using either special front-end software or a standard internet browser client from anywhere around the world.

Web access functionality is embedded in a device to enable low cost widely accessible and enhanced user interface functions for the device. A web server in the device provides access to the user interface functions for the device through a device web page. A web server can be embedded into any appliance and connected to the Internet so the appliance can be monitored and controlled from remote places through the browser in a desktop.

The aim of the project is to control the devices or equipment’s from the remote place through a web page. Here all the devices, which are to be controlled, are connected to the relays (acts as switches) on the web server circuit board. The web-server circuit is connected to LAN or Internet. The client or a person on the PC is also connected to same LAN or Internet. By typing the IP-address of LAN on the web browser, the user gets a web page on screen; this page contains all the information about the status of the devices. The user can also control the devices interfaced to the web server by pressing a button provided in the web page.


ARM processor, Relay unit , Sensor module


KEIL Compiler, Philips Programmer, EMBEDDED C








Suggested Readings

Books : Ethernet: the definitive guide, Charles E. SpurgeonARM Processor , e-book

Journals :International Journal of Advanced Research in Computer and Communication EngineeringVol. 2 , Issue 5, May 2013Websites: www.ijarcce.com


37



Department E.C.E

Project Title Passenger BUS Alert System for Easy Navigation of Blind

Description

Talking signs, guide cane, echolocations are all useful in navigating the visually challenged people to reach their destination, but the main objective is not reached that it fails to join them with traffic. In this project we propose a bus system using wireless sensor networks (WSNs).The blind people in the bus station is provided with a ZigBee unit which is recognized by the ZigBee in the bus and the indication is made in the bus that the blind people is present in the station. So the bus stops at the particular station. The desired bus that the blind want to take is notified to him with the help of speech recognition system HM2007. The blind gives the input about the place he has to reach using microphones and the voice recognition system recognizes it .The input is then analyzed by the microcontroller which generates the bus numbers corresponding to the location provided by the blind. These bus numbers are converted into audio output using the voice synthesizer APR 9600. The ZigBee transceiver in the bus sends the bus number to the transceiver with the blind and the bus number is announced to the blind through the headphones. The blind takes the right bus parked in front of him and when the destination is reached it is announced by means of the GPS-634R which is connected with the controller and voice synthesizer which produces the audio output. This project is also aimed at helping the elder people for independent navigation


Microcontroller, Wireless sensor networks, Speech Recognition System, Voice Synthesizer, GPS, Zigbee.


Embedded C








Suggested Readings

Books :Wireless sensor networks, K.SohrabyARM Processor , e-bookJournals :International Conference on Circuits, Power and Computing Technologies [ICCPCT-2013]Websites: www.ieee.orgwww.niueee.in


38

http://www.niueee.in/

http://www.ieee.org/



Department E.C.E

Project Title HUMAN HEALTH MONITORING USING WIRELESS SENSORS NETWORK

Description

Wireless devices have invaded the medical area with a wide range of capability. To monitor the patient details in periodic interval is on overhead using existing technologies. To overcome this we have changed recent wireless sensor technologies. In general, different sensors are used to gather patient medical information without being injecting inside the body by this we are achievingremote monitoring and data gathering of patients. This adds the advantages of mobility. There is no need for a doctor to visit the patient periodically.


ARM processor, Relay unit , Sensor module


KEIL Compiler, Embedded C








Suggested Readings

BooksWireless sensor networks, K.SohrabyARM Processor , e-book

JournalsInternational Journal of Application or Innovation in Engineering & Management (IJAIEM)Websites:www.ijaiem.org


39



Department ECE

Project Title Design Of An Efficient And Optimized Algorithm For Serial-Parallel Multiplication Using AOP

Description

Efficient and optimizing an algorithm for hardware-efficient AOP-based on serial-parallel multiplication, and to perform circuit level optimization to reduce the area and the time complexities of implementation .Finite field multiplication over GF(2m) based on irreducible all one- polynomials (AOP), where the modular reduction of degree is achieved by cyclic-left-shift without any logic operations. A regular and localized bit-level dependence graph (DG) is derived from the proposed algorithm and mapped into an array architecture, where the modular reduction is achieved by a serial-in parallel out shift-register. In this thesis dependence graph is drawn using algorithm and then this dependence graph is regularized to perform unique operation at different nodes and finally this regularized dependence graph is mapped into dedicated hardware which consists of array of program element and the required multiplication is performed by using 2(m+1) D Flip Flops ,(m+1) AND gates and (m+1) XOR gates.

Hardware/Equip. Requirements -


Modelsim Xilinx Edition (MXE)








Suggested Readings

Books

JournalsIEEE Publications,2013

Websites


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Faculty Name K.SATISH

Department E.C.E

Project Title VLSI IMPLEMENTATION OF SHA-2 ALGORITHM

Description

The Secure Hash Algorithm is a family of cryptographic hash functions. A family of two similar hash functions, with different block sizes, known as SHA-256 and SHA-512. They differ in the word size; SHA-256 uses 32-bit words where SHA-512 uses 64-bit words. The SHA-256 compression function operates on a 512-bit message block and a 256-bit intermediate hash value. It is essentially a 256 bit block cipher algorithm which encrypts the intermediate hash value using the message block as key.


Software Requirements Xilinx-ISE(VHDL), Modelsim simulator








Suggested Readings

Books1. William Stallings ,Cryptography and network security: principles and practices-4th edition Pearson

Education Inc. 2. J. Bhasker, A VHDL Primer, Third Edition, Prentice Hall Publication, 2009

Journals1.Chaves R, Kuzmanov G, Sousa L, Vassiliadis S (2006) Improving SHA-2 hardware implementations.: Cryptographic Hardware and Embedded Systems-CHES 2006, pp 298–310.Websites:http://en.wikipedia.org/wiki/SHA-2www.nsit.gov


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http://books.google.co.in/url?client=ca-print-pearson_india&format=googleprint&num=0&channel=BTB-ca-print-pearson_india+BTB-ISBN:8177587749&q=http://pearson.vrvbookshop.com/book/cryptography-network-security-william-stallings/9788177587746&usg=AFQjCNHmHmFe0mGnvHDb8CHGem-lDYUApA&source=gbs_buy_r

http://books.google.co.in/url?client=ca-print-pearson_india&format=googleprint&num=0&channel=BTB-ca-print-pearson_india+BTB-ISBN:8177587749&q=http://pearson.vrvbookshop.com/book/cryptography-network-security-william-stallings/9788177587746&usg=AFQjCNHmHmFe0mGnvHDb8CHGem-lDYUApA&source=gbs_buy_r

http://en.wikipedia.org/wiki/Cryptographic_hash_function


Faculty Name Mr.K.SATISH

Department ECE

Project Title

Performance analysis of MANET routing protocols

Description

In this project the performance of the TCP over different Mobile Ad-hoc Network Routing Protocols is evaluated by using the network simulator (NS2). The routing protocols used in the simulations are Ad-hoc On Demand Distance Vector Routing protocol (AODV), Dynamic Source Routing protocol (DSR) and Destination Sequenced Distance Vector routing protocol (DSDV). The DSDV is a table driven algorithm. DSR is source routing algorithm i.e. source appends the complete route for the packet to reach the destination in the packet’s header. AODV is an on demand routing protocol. Performance metrics are throughput and window size.


PC

Software Requirements LINUX,Network simulator-NS-2,








Suggested Readings

Books :Andrew. S. Tanenbaum, COMPUTER NETWORKS, 4th Edition, Pearson Education.

1 Mahbub Hassan, Raj Jain, High performance TCP/IP Networking –PHI, 2005.

Journals: G. Holland and N. Vaidya, “Analysis of TCP performance over mobile ad hoc networks,” Proceedings of ACM Mobicom, pp. 219–230,

Websiteswww.isi.edu/nsnam/ns/www.mecs-press.org/ijcnis/ijcnis-v5-n9/IJCNIS-V5-N9-6.pdf


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Faculty Name Mr.K.SATISH

Department ECE

Project Title Test Data Compression with Efficient Dictionary Selection Method

Description

In System on Chips(SoC), if circuit density increases, test data volume increases to test the circuit, it requires larger memory sizes. If memory size is high we get more faults. To detect these faults we have to go for ATE(Automatic Test Equipment) or BIST(Built in Self Test) methods. Instead to decrease size of memory, the solution is going for Compression.Compression schemes are classified into two general groups: dictionary and bit masking schemes.



The Project implemented in Hardware Description Language (HDL) and Simulation & Synthesis is performed on Xilinx ISE .








Suggested Readings

Books1. M. Abramovici, M. A. Breuer, and A.D. Friedman, “Digital System Testing and Testable Design”,. IEEE Press, New York, 1990, 652 pages 2. Neil H.E. Weste, David Harris, Ayan Banerjee ,CMOS VLSI Design: A Circuits and Systems Perspective, Thrid Edition, Pearson,2009Journals1. BASU AND MISHRA: Test data compression using efficient Bitmask and dictionary selection methods- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS2.L. Li, K. Chakrabarty, and N. Touba, “Test data compression using dic- tionaries with selective entries and fixed-length indices,” ACM Trans. Des. Autom. Electron. Syst., vol. 8, no. 4, pp. 470–490,Websites

1. www.cise.ufl.edu/~kbasu/tvlsi09.pdf 2. http://www.sciweavers.org/publications/test-data-compression-using-efficient-bitmask-and-

dictionary-selection-methods


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Faculty Name C.Pramod Kumar

Department E.C.E

Project Title Remote guidance for the blind — A proposed tele assistance system

Description

The concept is based on the idea that a blind pedestrian can be aided by spoken instructions from an operator who receives a video stream from a camera carried by the visually impaired user. An early prototype utilizing two laptop PCs and a wireless Internet connection is used in orientation and mobility trials, which aim to measure the potential usefulness of the system and discover possible problems with user-operator communication or device design.

Hardware/Equip. Requirements Sensor, SMPS, Transmitter and Receiver.

Software Requirements Microcontroller programming/Embedded C Programming








Suggested Readings

Books Instrument Engineers' Handbook, Vol. 1: Process Measurement and Analysis Hardcover by Bela G.

Liptak (Editor) Transducer and instrumentation by dvsmurthy

Journals1. Bujacz, M.; Baranski, P.; Moranski, M.; Strumillo, P.; Materka, A, "Remote guidance for the blind — A

proposed teleassistance system and navigation trials," Human System Interactions, 2008 Conference on , vol., no., pp.888,892

2. Shoval, S.; Borenstein, J.; Koren, Y., "Mobile robot obstacle avoidance in a computerized travel aid for the blind," Robotics and Automation, 1994. Proceedings., 1994 IEEE International Conference on , vol., no., pp.2023,2028 vol.3,

Websites:


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http://www.amazon.com/s/ref=dp_byline_sr_book_1?ie=UTF8&field-author=Bela+G.+Liptak&search-alias=books&text=Bela+G.+Liptak&sort=relevancerank




Department E.C.E

Project Title Remote Control for Rural Irrigation

DescriptionThis project is to help farmers to keep their water motor pumps turned on continuously. To help farmers overcome this issue, and save wastage of water and electricity, and to control the pumps remotely,


GSM modem, SMPS, Microcontroller and allied circuitryTone generator, Infrared sensing, Antenna for GSM modem

Software Requirements Microcontroller programming/Embedded C Programming








Suggested Readings


Liptak (Editor) Transducer and instrumentation by dvs murthy

Journals1.Ahmed, V.; Ladhake, S.A, "Innovative Cost Effective Approach for Cell Phone Based Remote Controlled Embedded System for Irrigation," Communication Systems and Network Technologies (CSNT), 2011 International Conference on , vol., no., pp.419,422, 3-5 June 20112International Journal of Science and Research (IJSR) ISSN (Online): 2319-7064 Impact Factor (2012): 3.358 Automatic Ambulance Rescue System Using Shortest Path Finding Algorithm .

Websites:


45





Department E.C.E

Project Title AUTOMATIC ACCIDENT DETECTION AND AMBULANCE RESCUE WITH INTELLIGENT TRAFFIC LIGHT SYSTEM

Description

The ambulance is controlled by the control unit which furnishes adequate route to the ambulance and also controls the traffic light according to the ambulance location and thus reaching the hospital safely.The controller identifies the location of the accident spot through the sensor systems in the vehicle which determined the accident and thus the controller walks through the ambulance to the spot. This scheme is fully automated, thus it finds the accident spot, controls the traffic lights, helping to reach the hospital in time


Non-Intrusive types of sensor is fitted on the road,GSM modem, SMPS power supply with battery back-up, Microcontroller and allied circuitry, Fire sensor, Vibration sensor, Max 232, Infrared sensing, Antenna for Gps system.


Microcontroller programming/Embedded C Programming








Suggested Readings


Liptak (Editor) Transducer and instrumentation by dvs murthy

Journals1.Fogue, M.; Garrido, P.; Martinez, F.J.; Cano, J.-C.; Calafate, C.T.; Manzoni, P., "Automatic Accident Detection: Assistance Through Communication Technologies and Vehicles," Vehicular Technology Magazine, IEEE , vol.7, no.3, pp.90,100, Sept. 20122Wang Wei; Fan Hanbo, "Traffic accident automatic detection and remote alarm device," Electric Information and Control Engineering (ICEICE), 2011 International Conference on , vol., no., pp.910,913, 15-17 April 2011Websites:


46




Faculty Name Shravan Kumar Reddy M

Department E.C.E

Project Title Orthogonal Frequency Divisional Multiplexing for Wireless Networks

Description

Orthogonal frequency division multiplexing (OFDM) is a special case of multicarrier transmission, where a single data stream is transmitted over a number of lower rate subcarriers. In July 1998, the IEEE standardization group decided to select OFDM as the basis for their new 5GHz standard, targeting a range of data stream from 6 up to 54 Mbps. This new standard is the first one to use OFDM in packet-based communications, while the use of OFDM until now was limited to continuous transmission systems. In this project, transmitter and receiver were simulated according to the parameters established by the standard, to evaluate the performance and different possibilities in the implementation


PC


MATLAB








Suggested Readings

Books1. Ramjee Prasad, “OFDM for wireless communications”, Universal Personal Communications, 2004 edition.

2. John G. Proakis, “Digital Communications.” Fourth Edition, McGraw Hill, New York, 2001.

Journals1. Gerhard Bauch, Senior Member, IEEE, and Javed Shamim Malik, “Cyclic Delay Diversity with Bit-Interleaved Coded Modulation in Orthogonal Frequency Division Multiple Access”. IEEE Transactions on Wireless Communications, Vol. 5, No. 8, October 2006. pp. 2092-2100.

Websites:1. http://www.dsplog.com


47

http://www.dsplog.com/



Department E.C.E

Project Title Pulse shaping filters with ISI free properties

Description

Pulse shaping is the process of changing the waveform of transmitted pulses. Its purpose is to make the transmitted signal suit better to the communication channel by limiting the effective bandwidth of the transmission. By filtering the transmitted pulses this way, the inter symbol interference caused by the channel can be kept in control. In RF communication pulse shaping is essential for making the signal fit in its frequency band. Typically pulse shaping occurs after line coding, and before modulation. All the simulation work is done using MATLAB software.


Software Requirements MATLAB








Suggested Readings

Books1. John G. Proakis, “Digital Communications.” Fourth Edition, McGraw Hill, New York, 2001.

Journals1. X. G. Xia, “A family of pulse-shaping filters with ISI Free matched and unmatched filter properties”, IEEE Trans.

Communications., vol. 45, no 10. pp.1157-1158, Oct. 1997.

2. N. S. ALAGHA and P. KABAL, ‘Generalized Raised-Cosine Filters,’ IEEE Transactions on Communications, VOL. 47, NO. 7, pp. 989-997,JULY 1999.

Websites:1. http://www.dsplog.com 2. www.mathworks.com


Date

48




Department E.C.E

Project Title Statistical region merging

Description

Segmentation is the process of partitioning an image into disjoint and homogeneous regions. In recent days, there is lot of increase in speed of execution of algorithm and cost of computation is also decreased. So many advanced techniques have been developed for segmentation of color images. Statistical Region Merging (SRM) algorithm is one of such algorithms. SRM is a linear-time fast and simple region growing segmentation algorithm based on an adaptive statistical threshold merging predicate on color channels that does not require maintaining dynamically the region adjacency graph. SRM handles nicely occlusion, noise and user-input bias.










Suggested Readings

Books1. Rafael C. Gonzalez and Richard E. Woods, "Digital Image Processing"' Addison-Wesley, Fifth Indian Reprint - 2000.Journals1. Richard Nock and Frank Nielsen, “ Statistical Region Merging”, IEEE transactions on Pattern Analysis and Machine

Intelligence, Nov.2004, vol.26, page(s) 1452-1458.

Websites:1. www.mathworks.com


Date

49



Department E.C.E

Project Title Image segmentation techniques

Description

Segmentation techniques like region growing segmentation and edge detection using different operators like sobel, prewitt, canny are used to detect surface deformities. All the simulation work undertaken during this mini project is performed in MATLAB v.7. The reasons for choosing MATLAB are compactness (complex algorithms can be expressed in a very few lines of code) and graphics support.



MATLAB








Suggested Readings

Books1. Rafael C. Gonzalez and Richard E. Woods, "Digital Image Processing"' Addison-Wesley, Fifth Indian Reprint -

2000.

Journals

Websites:1. www.mathworks.com


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Faculty Name M Shravan Kumar Reddy

Department E.C.E

Project Title SVD based image compression

Description

Any mxn matrix can be factored into the product of an orthogonal matrix times a diagonal matrix times another orthogonal matrix. This is called the Singular Value Decomposition (SVD) of a matrix. The goal of studying the SVD of a matrix is to create approximations of the full mxn matrix by only using some of the terms of the diagonal matrix in the decomposition. This approximation of the full matrix is the basis of image compression using SVD, since images can be viewed as matrices with each pixel being an element of a matrix. In this project, we will prove the theorem of Singular Value Decomposition (SVD), and compute the SVD of a matrix example by calculation and by using MATLAB. We will also explain how the SVD can be applied to compress images, and implement the image compression algorithm developed for a sample image by using MATLAB.










Suggested Readings

Books :[1] Rafael C. Gonzalez and Richard E. Woods, "Digital Image Processing"' Addison-Wesley, Fifth Indian Reprint - 2000.

Journals[1] Kalman, Dan. “A Singularly Valuable Decomposition.” The college Mathematics Journal.Vol.27 No.1 Jan 1998, 2-23.

Websites:[1] www.mathworks.com


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Faculty Name R. Sravan kumar

Department E.C.E

Project Title FPGA implementation of combinational lock for security system.

Description

This project mainly deals with the security system by using combinational circuit. We have to generate a particular combinational circuit for testing and we have to store the security code in memory. This is implemented using state machine concept. If the input pattern is same as the pattern stored in memory then it will unlock the equipment.

Hardware/Equip. Requirements Spartan 3E FPGA

Software Requirements Xilinx 10.1 or higher







Overall 13 weeks 13 weeks.

Suggested Readings

BooksVerilog hdl by padmanabhan , verilog hdl by palnitker and verilog hdl by j.bhakar.

Journals

Websites:Nptel.iitm.ac.in



52


Department E.C.E

Project Title FPGA implementation of FIFO controller.

DescriptionThis project mainly deals with data storage and flow within the memory of chip. Here, perfect synchronization is maintained for read and write cycles between memory chips if we are performing an interface operation.










Suggested Readings


Journals



53



Department E.C.E

Project Title FPGA implementation of vending machine using state machines.

DescriptionThis project mainly develops an automatic vending machine which is controlled by state machines which has states upto 3 i.e state1 for Rs1, state2 for Rs2, etc. The items will dispatch based on the users input to the vending machine.










Suggested Readings


Journals



54


Faculty Name SRAVAN KUMAR R.

Department E.C.E

Project Title DESIGN OF LOW POWER AND HIGH SPEED CONFIGURABLE BOOTH MULTIPLIER

DescriptionTo Design a low power and high speed configurable booth multiplier that supports single 16X16 multiplication, single 8X8 multiplication and twin parallel 8X8 multiplication operations.


PC

Software Requirements Xilinx-ISE(VHDL), Modelsim simulator








Suggested Readings

Books :Digital Signal Processing by Johny, PHI PublicationsCircuit Desing using VHDL by PedroniVHDL by B.BhaskarDigital Signal Processing by Vallavraj&Salivahanan

Journals[1]. J. Choi, J. Jeon, and K. Choi, “Power minimization of function units by partially guarded computation,” in Proc. Int. Symp. LowPower Electron. Des., Jul. 2000, pp. 131–136.[2]. Fayed A and M. A. Bayoumi, “A novel architecture for low-power design of parallel multipliers,” in Proc. IEEE Comput. Soc.Annu Workshop VLSI, Apr. 2001, pp. 149–154.[3]. N. Honarmand and A. A. Kusha, “Low power minimization combinational multipliers using data-driven signal gating,” in Proc.IEEE Int. Conf. Asia-Pacific Circuits Syst., Dec. 2006, pp. 1430– 1433.[4]. K.-H. Chen and Y.-S. Chu, “A spurious-power suppression technique for multimedia/DSP applications,” IEEE Trans. Circuits Syst.I, Reg. Papers, vol. 56, no. 1, pp. 132–143, Jan. 2009.Websites :www.howstuffswork.com, www.xilinx.com, www.wikipedia.com


55


http://www.xilinx.com/

http://www.howstuffswork.com/


Faculty Name Sai Prasad Goud A

Department E.C.E

Project Title Implementation of BIST for testing combinational circuit using FPGA

DescriptionThis project mainly deals with the testing of any combinational circuit with the random test vectors which is to be applied to combinational circuit to test the functionality of the circuit.










Suggested Readings


JournalsIjdacr

Websites:


56


Faculty Name Sai Prasad Goud A

Department E.C.E

Project Title FPGA implementation of intelligent car parking system for real time application

DescriptionThis project mainly deals with the car parking systems which is done automatically in a step by step process to verify the identity, parking space in slots etc. This can be designed using verilog hdl and can implemented in real time applications.










Suggested Readings


JournalsIjcsi

Websites:


57


Faculty Name Saiprasad goud A

Department E.C.E

Project Title Home automation system design using verilog HDL.

DescriptionThis project mainly deals with the efficient design of home automation system using verilog HDL and a possible solution where the user controls the devices by employing an FPGA interface to which the devices and sensors are interfaced.


Spartan 3E-FGPA board


Xilinx 10.1 or higher








Suggested Readings


JournalsInternational conference on recent trends in computer and information engineering-2013.

Websites:


58


Faculty NameN.PRADEEP KUMAR GOUD

Department E.C.E

Project TitleTouch Screen and Zigbee Based Wireless Communication Assistant For Dumb/Illiterates In Airlines

Description

As there a different language in the world and it is impossible to know all the languages. So, in this project a device is built that helps illiterate/dumb people in expressing their needs with other language people (Air hostess) i.e. request them if they need anything in the flight like coffee, tea, drinks etc. In this project Touch screen Technology is used to make it easy even to illiterates to operate to convey their needs as it includes images, which indicates the needs. This even reduces the difficulty to airhostess in receiving the passengers with different languages


Micro controller , Zigbee Touch screen


Embedded C KEIL µVision IDE








Suggested Readings

Books Embedded Design with the PIC 18F452Micro Controller by John Peatman, published2003 by prentice

Hall. PIC Micro Controller An Introduction to software & hardware interfacing,1st Edition,Han Way Huang,

Leo Chartrand, published 2004 by Delmav Cengage Learning

Journals

Websites www.freescale.com www.networkworld.com www.touchscreens.com


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Faculty Name N.PRADEEP KUMAR GOUD

Department E.C.E

Project TitleDesign And Application Of Mobile Embedded System For Home Care Application

Description

In this project a low cost GSM based home security system is developed using

embedded secured system with ARM microcontroller. This system need to be

mounted in house, which is continuously monitored. The security system consists of

two modules, GSM modem and microcontroller board interfaced with different

sensors.


Microcontroller (Lpc 2148), Temperature sensor, IR Sensor, Gas Sensor, GSM Modem


Embedded C,KEIL µVision IDE








Suggested Readings

BooksEmbedding systems design- Oliver BarleyArm system developer’s guide- Steve Furber

Journalshttp://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/30/4560070/04560131.pdf?arnumber=4560131

Websites: www.nxp.com www.keil.com www.electronicsforyou.com www.national.com


60

http://www.national.com/

http://www.electronicsforyou.com/

http://www.keil.com/

http://www.nxp.com/

http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/30/4560070/04560131.pdf?arnumber=4560131



Department E.C.E

Project Title ANTI THEFT CONTROLLING SYSTEM USING EMBEDDED SYSTEM

Description

This Project anti theft control system for automobiles tries to prevent the theft of a vehicle using GSM-SMS services. The present system is an excellent and cost effective to prevent car theft .Here the user owning a car types a password if it matches with the existing only the vehicle gets started for the symbolic representation relay turns ON. The user can give three attempts to match the password. If it fails automatically it alerts the by using GSM modem exact message will be given to the owner of the vehicle. If the password matches then the user has to insert the key to start the vehicle. This technique helps in taking fast steps towards an attempt to steal . The design is robust and simple

Hardware/Equip. Requirements Microcontrolller(LPC 2148),GSM ,LCD,RS232


Embedded C , KEIL µVision IDE








Suggested Readings

BooksRaj Kamal "Embedded Systems - architecture, programming and design"Second Edition 2009

JournalsB.G.Nagaraja, Ravi Rayappa, M.Mahesh, Chandrasekhar M Patil, Dr TC Manjunath:'Design and Development of GSM based vehicle theft control system' Advanced Computer Control ICACC '09 International conference.pp 148Websites:http://www.nationmaster.com/red/pie/ cri-car-the-crime-car-thefts http://www.unitracking. com/howitworks.html


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Department E.C.E

Project Title Implementation of Touch screen Based Home Appliances Control System Using ARM7 LPC2148 and Zigbee

Description

A home appliance control system (HACS) is a system which provides various services to remotely operate on home appliances, such as microwave oven, TV, and garage door etc through remote devices such as mobile phone, desktop and palm-top. In order to activate home appliances and to allow for different ways of cooking, the HACS needs mechanisms for communication between the different devices in the system, and for coordination among the various processes running on such devices.Zigbee is one such mechanism by which wireless communicaion can be established


LPC 2148 ARM controller, touch screen ,Zigbee


KEIL U VISION








Suggested Readings

BooksARM System-On-Chip Architecture(2nd Edition) - By Steve Furber

ARM System Developer Guide-By Andrew Sloss, Dominic Slymes, Chris Wright

8051 Microcontrollers, Hardware,Software and Applications-By D.M Calcutt

Embedded System Design- By Frank Wahid

Embedded System Design(Second Edition)-By Steve Heath

The Insider’s Guide to the Philips ARM 7,based microcontrollers-Trevor Martin

Journal

Websites:www.electronicsforyou.com www.national.com www.et.nmsu.edu


62

http://www.et.nmsu.edu/

http://www.national.com/

http://www.electronicsforyou.com/


Faculty Name T.Saritha

Department E.C.E

Project Title FPGA Implementation of Alamouti MIMO Selection for Receiver-Antenna Selection Combining

Description

The Alamouti multiple-input mUltiple-output (MIMO) detector based on the log-likelihood ratio (LLR) selection statistic for receiver-antenna selection combining (SC) is implemented on an FPGA platform, where hardware simulation using Verilog HDL is illustrated, and the BPSK signaling is considered.

Hardware/Equip. Requirements no

Software Requirements Verilog hdl








Suggested Readings

Books: 1. D. Gore and A. Paulraj, "MIMO antenna subset selection with space time coding," IEEE Trans. Signal Process., pp.2 580-2588, Mar.2 002. 2. Bahceci, T. M. Duman, and Y. Altunbasak, "Antenna selection for multiple-antenna transmission systems: Performance analysis and code construction," IEEE Trans. In! Theory, pp.2 669-2681, Oct.2 003.

Journals:1.Journal on FPGA implementation of MIMO module2.Journal on ALAMOUTI STBC.

Websites: www.dsplog.com rfwireless-world.com


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Department E.C.E

Project Title Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique

Description

In this paper a full subtractor using MTCMOS technique design is proposed. Reducing power dissipation is one of the most principle subjects in VLSI design today. But Scaling causes sub threshold leakage currents to become a large component of total power dissipation. Using MTCMOS approach compare leakage current and leakage power of full subtractor in active mode. simulation result is performed at 0.7 volt using cadence virtuoso tool in 45nanometer technology.


nil


Xilinx








Suggested Readings

Books: 1.Neil Weste and D. Harris, “CMOS VLSI Design: A Circuit and System Perspective Pearson Addition Wesley, third Edition, 2005.

2.Ken Martin, Digital Integrated Circuit Design, Oxford University Press, New York, 2000.

Journal: Design of Low Power Half-Subtractor Using AVL Technique Based on 65nm CMOS Technology

Websites: 1.www.pearsonhighered.com 2. www.pptsearch365.com


64



Department E.C.E

Project Title Design of Optimized CIC Decimator and Interpolator in FPGA

Description

This paper analyzes optimized architecture and implementation aspects of decimator and interpolator using CIC filter. CIC filters function as efficient anti-aliasing filters before downsampling of signals in decimation process and as anti- imaging filters after upsampling of signals in interpolation process. This paper also discusses about pipelining, throughput and area reduction techniques and performance analysis with respect to the number of stages (N) and rate change factor (R) of the filter.


Not required


Modelsim and Matlab








Suggested Readings

Books:1.Fredric J. Harris, Multirate Signal Processing for Communicating Systems, 2004.

2.Ricardo A. Losada,”Digital Filters with Matlab” ,The Mathworks Inc. ,May 2008.

Journal: Journal on FPGA-Based Design of High-Speed CIC Decimator for Wireless Applications

Websites:1. www.enggjournals.com 2. ieeexplore.ieee.org



65

http://www.enggjournals.com/


Department E.C.E

Project Title Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes

Description

In this brief, the detection of errors during the first iterations of serial one step Majority Logic Decoding of EG-LDPC codes has been studied. The objective was to reduce the decoding time by stopping the decoding process when no errors are detected. The simulation results show that all tested combinations of errors affecting up to four bits are detected in the first three iterations of decoding. These results extend the ones recently presented for DS-LDPC codes, making the modified one step majority logic decoding more attractive for memory applications. The designer now has a larger choice of word lengths and error correction capabilities.

Hardware/Equip. Requirements ---

Software Requirements xilinx






Documentation 1 week 1 weeks


Suggested Readings

Books: 1) H. Naeimi and A. DeHon, “Fault secure encoder and decoder fornanomemory applications 2) H. Tang, J. Xu, S. Lin, and K. A. S. Abdel-Ghaffar, “Codes on finitegeometries,”

Journals:

1) IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 17, no. 4, pp. 473–486, Apr. 2009Websites: 1)ita.ucsd.edu 2) en.wikipedia.org


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b.tech project guidelines and schedule

Documents

project guides

project schedules

project coordinatoriii

project work

formation of project

project batch members

project related activities

senior faculty members