b.supmonchai goals of this chapter · 2009-11-12 · b.supmonchai july 4th, 2005 2102-545 digital...

B.Supmonchai July 4th, 2005

2102-545 Digital ICs 1

Chapter 7

Sequential Circuits

Boonchuay SupmonchaiIntegrated Design Application Research (IDAR) Laboratory

August 20, 2004; Revised - July 4, 2005

2102-545 Digital ICs Sequential Logic 2

B.Supmonchai

Goals of This Chapter

q Implementation techniques for

ß Register: latches and flipflops

ß Schmitt Triggers

ß Oscillator, pulse generators

q Static versus Dynamic Realization

q Clocking Strategies


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Storage Mechanisms

Positive Feedback Charge-Based

COMBINATIONALLOGIC

Inputs Outputs

Next stateCurrent State

Q DState

Register

CLOCK

Sequential Logic

STATIC DYNAMIC


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Static vs Dynamic Storageq Static storage

ß preserve state as long as the power is on

ß have positive feedback (regeneration) with an internalconnection between the output and the input

ß useful when updates are infrequent (clock gating)

q Dynamic storage

ß store state on parasitic capacitors

ß only hold state for short periods of time (milliseconds)

ß require periodic refresh

ß usually simpler, so higher speed and lower power




B.Supmonchai

Latches versus Flipflopsq Latches (with Clock)

ß level sensitive circuit that passes inputs to Q when the clock ishigh (or low) - transparent mode

ß input sampled on the falling edge of the clock is held stablewhen clock is low (or high) - hold mode

q Flipflops (edge-triggered)

ß edge sensitive circuits that sample the inputs on a clocktransitionÿ positive edge-triggered: 0 Æ 1

ÿ negative edge-triggered: 1 Æ 0

ß built using latches (e.g., master-slave flipflops)


B.Supmonchai

Vi2 Vo2Vo1Vi1

Cascaded Inverters

A

Vi1 = Vo2

Vi2

= V

o1

B

C

Review: The Regenerative Property

q Small deviation frombias point C (e.g., fromnoise) is amplified andregenerated around thecircuit loop until eitherpoint A or B is reached

q If the gain in thetransient region is largerthan 1, only A and B arestable operation points.C is a metastableoperation point.


B.Supmonchai

Review: Bistable Circuits

q The cross-coupling of twoinverters results in abistable circuit (a circuitwith two stable states)

q Have to be able to change the stored value by making A(or B) temporarily unstable by increasing the loop gainto a value larger than 1

ß done by applying a trigger pulse at Vi1 or Vi2

ß the width of the trigger pulse need be only a little larger thanthe total propagation delay around the loop circuit (twice thedelay of an inverter)

Vi1

Vi2


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Review: SR Latch

disallowed0011

reset1010

set0101

memory!QQ00

Action!QQRSS

RQ

!Q




B.Supmonchai

Review: Clocked D Latch

clock

D L

atch

QD

clock

D

Q

!Q

clock

transparent mode

hold mode

In our courseAll latches meanclocked latches


B.Supmonchai

D

Clk

Q D

Clk

Q

q Flipflop

stores data whenclock rises (falls)

Clk

D

Q

Clk

D

Q

Latches versus Flipflops IIq Latch

stores data whenclock is low (high)


B.Supmonchai

Positive and Negative Latches

In

Out

Clk

OutStable

OutFollow In

OutStable

OutFollow In

D Q

G

In Out

Clk

Positive Latch

In

Out

Clk

OutStable

OutFollow In

OutStable

OutFollow In

D Q

G

In Out

Clk

Negative Latch


B.Supmonchai

• N latch is transparentwhen f = 0

• P latch is transparent when f = 1

Latch-Based Design

NLatch

PLatch

f

Logic

Logic




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clock

D QIn Out

Out outputstable

outputstable

time

clock

In datastable

time

time

tsu thold

tc-q

Timing Metrics


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Timing Definitions

q Setup time, tsetup is the time that the data inputs(D) must be valid before the clock transitionß 0 to 1 transition for a positive edge-triggered device

ß 1 to 0 transition for a negative edge-triggered device

q Hold time, thold is the time that the data inputsmust remain valid after the clock edge

q Propagation Delay, tc-q is the worst casepropagation delay (with reference to the clockedge)ß time to copy D to Q


B.Supmonchai

T ≥ tc-q + tplogic + tsutcdreg + tcdlogic ≥ thold

T (clock period)

System Timing Constraints

COMBINATIONALLOGIC

Inputs Outputs

Next stateCurrent State

Q DState

Register

CLOCK

tcd: contamination delay = minimum delay


B.Supmonchai

Notes on System Timing Constraintsq It is important to minimize the values of the timing

parameters associated with the register.

q In modern high-performance systems, the registerpropagation delay and set-up times account for asignificant portion of the clock period.

ß DEC Alpha EV6 has a maximum logic depth of 12 gates andthe register overhead accounts for about 15% of the clockperiod.

q Hold time becomes an issue when there is little logicbetween registers or when the clocks at differentregisters are somewhat out of phase due to clock skew.




B.Supmonchai

Building A (Static) Latch

CLK

CLK

CLK

D

Q

Cutting the feedback loop(Mux-based latch)

Overpowering the feedback loop(as in Static RAM)

For a latch, use the clock as a decoupling signal, thatdistinguishes between the transparent and opaque states

D

CLK

CLK

D

can implement as NMOS-only


B.Supmonchai

Q = !clk & Q | clk & DQ = clk & Q | !clk & D

Negative Latch

Q

D

clk

0

1

feedback

transparent when theclock is low

q Change the stored value by cutting the feedback loop

MUX Based Latches

Positive Latch

Q

D

clk

1

0

feedback

transparent when theclock is high


B.Supmonchai

!clk

clk

input sampled(transparent mode)

feedback(hold mode)

TG MUX Based Latch Implementation

Q

D

clk

clk

!clk

Positive Latch

clk load is two transistors (and twofor !clk) = clock load of 4

Having to generate both clk and !clk(nonoverlapping clocks)


B.Supmonchai

QD

clk !Q

!clk

Reduced clock load, butthreshold drop at output ofpass transistors so reducednoise margins and performance

PT MUX Based Latch Implementation

!clk

clk

input sampled(transparent mode)

feedback(hold mode)




B.Supmonchai

clk

T ≥ tc-q + tplogic + tsu

Thigh < tc-q + tcdlogic

CombinationalLogic

clk

Sta

teR

egis

ters

B B’B

Which value of B is stored?

Latch Race Problem

Two-sided clock constraint


B.Supmonchai

clk

QM

Q

D

clk

D F

F

QD

clk = 0 transparent hold

clk = 1 hold transparent

0

1 Q1

0

D

clk

Q

clk

SlaveMaster

QM

Master Slave Based ET Flipflop


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T1

T2 Q

D

clk

QM

I1

I2 I3

I4

I5 I6

T3

T4

Master Slave

!clk

clk

master transparentslave hold

master holdslave transparent

20 Transistors* 8 clock loads* Ignore clk buffer

MS ET Implementation


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q Assume propagation delays are tpd_inv and tpd_tx, that thecontamination delay is 0, and that the inverter delay toderive !clk is 0

q Set-up time - time before rising edge of clk that D mustbe valid

q Propagation delay - time for QM to reach Q

q Hold time - time D must be stable after rising edge of clk

MS ET Timing Properties

tsu = 3 * tpd_inv + tpd_tx

tpd = tpd_inv + tpd_tx

thold = 0




B.Supmonchai

Notes on MS ET Timing Propertiesq Set-up timeß How long before the rising edge does D have to be stable such

that QM samples the value reliably?

ß D has to propagate through I1, T1, I3 and I2 before the risingedge to ensure that the node voltages on both terminals of T2are the same value.

q Propagation delay timeß Since the delay of I2 is included in the set-up time, the output

of I4 is valid before the rising edge of clk, so the delay issimply the delay through T3 and I6

q Hold timeß since T1 turns off when the clock goes high, any changes in D

after clk goes high are not seen, so hold time is 0


B.Supmonchai

Set-up Time Simulation

D clk

QM

I2 out

tsetup = 0.21 ns

works correctly

Vo

lts

Time (ns)

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.2 0.4 0.6 0.8 1

Q


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Set-up Time Simulation II

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.2 0.4 0.6 0.8 1

Vo

lts

Time (ns)

D clk

QM

I2 out

tsetup = 0.20 ns

Q

the clock is enabled before the nodes on both sidesof the transmission gate T2 settle to the same value

Fails!


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Propagation Delay Simulation

tc-q (LH) = 160 psec tc-q (HL) = 180 psec

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Vo

lts

Time (ns)

tc-q (LH) tc-q (HL)

propagation delay is measured from the 50% pointof the clk edge to the 50% point of the Q output

DClk Q




B.Supmonchai

Reduced Load MS ET FF

!clkclk

QD

!clk clk

I1

I2 I4

I3

QM T2T1

q Clock load per register is important since it directlyimpacts the power dissipation of the clock network.

q Can reduce the clock load (at the cost of robustness) bymaking the circuit ratioed

ß to switch the state of the master, T1 must be sized to overpower I2

ß to avoid reverse conduction, I4 must be weaker than I1

reverse conduction

12 Transistors 4 clock loads


B.Supmonchai

Non-Ideal Clocks

!clk

clk

Ideal clocks

!clk

clk

Non-Ideal clocks

1-1 Overlap 0-0 Overlap

q Clk and !clk are never perfect inversions of one anotherß We must generate !clk and route both signals

ß Variations can exist in the wires used to route the two clocksignals and load capacitances may vary

q Non-ideal clocks create skew resulting in clock overlap


B.Supmonchai

!QD

clkX

!clk

!clk Q

clk

B

AP1

P2

P3

P4

I1 I2 I3 I4

Race condition – direct path from D to Q during the short timewhen both clk and !clk are high (1-1 overlap)

Undefined state – both B and D are driving A when clk and !clkare both high

Dynamic storage – when clk and !clk are both low (0-0 overlap)

Race

Example of Clock Skew Problems


B.Supmonchai

clk1

clk2



dynamicstorage

tnon_overlap

Pseudostatic Two-Phase ET FF

!QD

clk1X

clk2

clk2 Q

clk1

B

AP1

P2

P3

P4

I1 I2 I3 I4




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Two Phase Clock Generator

clk

clk1

clk2

A

B

clk

A

B

clk1

clk2


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!clk

clk

Power PC Flipflop

master transparentslave hold master hold

slave transparent

Æ11 0

1 1D Q

clk

!clk

!clk

clk

0 Æ0 Æ0Æ1

16 Transistors 8 clock loads


B.Supmonchai

S

QR

Q

Cross-coupled NANDs

This is not used in datapaths any more,but is a basic building block for memory cell

Overpowering The Feedback LoopClocked SR Latch

S R

clkclk

!QQ

M1

M2

M3

M4

M5

M6

M7

M8


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10onoff

off ->onoff ->on

Æ 0

1 ¨

Æ on

Æ on

Æ off

Æ off

1 0

on

off

off

onS R

clkclk

!QQ

M1

M2

M3

M4

M5

M6

M7

M8 0 Æ 10 Æ 1

Ratioed CMOS Clocked SR Latch

8 Transistors2 Clock loads** sized

q No static power consumption, but a ratioed devicewhere sizing is critical to ensure proper functionalityß M7, M8 must overcome M4 to bring Q low, so must M5, M6

over M2




B.Supmonchai

Sizing Issues

0

0.5

1

1.5

2

2 2.5 3 3.5 4

(W/L)5 and 6

!Q (

Vo

lts)

(W/L)2 and 4 = 1.5mm/0.25 mm(W/L)1 and 3 = 0.5mm/0.25 mm

so (W/L)5 and 6 > 3

Output voltage depends on pull-down transistor width


B.Supmonchai

Transient Response

S

0

1

2

3

0 0.4 0.8 1.2 1.6 2

!Q (

Vo

lts)

Time (ns)

W=1 µmW=0.9 µm

W=0.8 µm

!Q

W=0.5 µmW=0.6 µmW=0.7 µm

Individual device ratio for M5 or M6 must be larger than approx. 6.

Analysis results give 2.26 (instead of 3) since it doesn’t take into accountchannel length modulation and DIBL (drain induced barrier loading).


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clkclk

SR

M1

M2

M3

M4

M5

M6 SR

clk

!QQ

clk

6 Transistor CMOS SR Latch

6 Transistors2 Clock loads

q Problems with noisemargins and staticpower consumptiondue to threshold dropacross pass transistors

q Once again, sizing isimportant - especiallyM5 and M6


B.Supmonchai

Review: Storage Mechanisms

D

CLK

CLK

Q

Dynamic (charge-based)

CLK

CLK

CLK

D

Q

Static(Positive Feedback)

Useful when update is infrequent Simpler, Faster, and Lower Power




B.Supmonchai

!clk clk

T1 T2I1 I2 QQM

D

C1 C2

clk !clk

!clk

clk



master slave

tsu =thold =tc-q =

tpd_tx

zero2 tpd_inv + tpd_tx

Dynamic ET Flipflop



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0-0 overlap race condition toverlap0-0 < tT1 + tI1 + tT2

1-1 overlap race condition

toverlap1-1 < thold

Dynamic ET FF Race Conditions!clk clk

T1 T2I1 I2 Q

QM

D

C1 C2

clk !clk

!clk

clk


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clk2

clk1tnon_overlap



Dynamic Two-Phase ET FFclk1 clk2

T1 T2I1 I2 Q

QM

D

C1 C2

!clk1 !clk2


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Pseudostatic Dynamic Latchq Robustness considerations limit the use of dynamic FF’sß Coupling between signal nets and internal storage nodes can

inject significant noise and destroy the FF state

ß Leakage currents cause state to leak away with time

ß Internal dynamic nodes don’t track fluctuations in VDD thatreduces noise margins

q A simple fix is to make the circuit pseudostaticclk

T1D

!clk

Slight increase in delay(adds to the capacitive load)and power consumption,but it improves noiseimmunity significantly




B.Supmonchai

clk

!clk

!clk

clk

QM

C1 C2

QD

M1

M3

M4

M2 M6

M8

M7

M5

Master Slave



on

on

off

off

on

onoff

off

C2MOS (Clocked CMOS) ET Flipflop

!clk

clk


Insensitive to clockoverlap as long as therise and fall times ofthe clock edges aresufficiently small


B.Supmonchai

C2MOS FF 0-0 Overlap Case

0 0QM

C1 C2

QD

M1

M3

M4

M2 M6

M8

M7

M5

!clk

clk

!clk

clk


B.Supmonchai

Notes on C2MOS FF 0-0 Overlap Caseq Does any new data sampled during the overlap window

propagate to Q (race)?ß New data is sampled on QM, but cannot propagate to Q since

M7 is off (slave is in hold).

ß Any new data sampled on the falling clock edge is not seen at Q

q For clocking on the left: at the end of the overlap period!clk = 1 and both M7 and M8 turn off, putting the slavein the hold mode

q For the clocking on the right: at the end of the overlapperiod clk = 1 and both M3 and M4 turn off, putting themaster in the hold mode (affects setup time as well)

q The result: the FF is slower (slower tc-q time)2102-545 Digital ICs Sequential Logic 48

B.Supmonchai

!clk

clk

!clk

clk

1-1 overlap constraint: toverlap1-1 < thold

11

QM

C1 C2

QD

M1

M3

M4

M2 M6

M8

M7

M5

C2MOS FF 1-1 Overlap Case




B.Supmonchai

Notes on C2MOS FF 1-1 Overlap Caseq New data is sampled on QM, but cannot propagate to Q

since M8 is off (slave is in hold).

q A bit more problematic than 0-0 overlap.ß It must enforce a hold time on D, so that changing D which

reaches QM is not copied to Q when overlap time is over -ÿ first clocking condition.

ß By imposing a hold time on D - that D must be stable duringclock overlap - overcome this problem as well

q However, possible race can occur if the rise/fall times ofthe clock are sufficiently slow.ß Works correctly as long as the clock rise/fall times is smaller

than approximately five times the propagation delay of theflipflop.


B.Supmonchai

C2MOS Transient Response

Q(3)

Q(0.1)

-0.5

0

0.5

1

1.5

2

2.5

3

0 2 4 6 8

Time (nsec)

Vo

lts

clk(0.1 ns)

QM(3)

clk(3 ns)

For slow clocks, potential for a race condition exists


B.Supmonchai

clk clkIn

Q

Positive LatchNegative Latch

transparent when clk = 1hold when clk = 0

clk clkIn Q

hold when clk = 1transparent when clk = 0

True Single Phase Clocked (TSPC) Latches

q Uses only a single clockß No clock overlap (skew) to worry about ; reduced clock load


B.Supmonchai

clk clkInQ

PUN

PDN

clk clk

A

Q

B

BA

Embedding Logic in TSPC Latch

q Logic can be embedded into latch (or FF)ß Reduce delay overhead associated with the latch

A AND B




B.Supmonchai

Notes on Embedding Logic in TSPC Latch

q Set-up time increased, but overall performanceimproved

ß The increase in the set-up time is typically smaller than thedelay of an AND gate.

ß For example, using minimum size devices set-up of ANDlatch is 140 psec.

ß Using the conventional approach of AND gate followed bylatch has an effective set-up time of 600 psec.

q Technique used extensively in the design of the EV4DEC Alpha microprocessor and many other highperformance processors.


B.Supmonchai



ononoffoff

on on

offoff clk clkD

Master Slave

clk clk QQM

clk

12 Transistors 4 Clock loads

TSPC ET FF

Virtually all constraints removed - no clocks to overlap, no race


B.Supmonchai

Notes on TSPC ET FF

q Warning! - similar to C2MOS, TSPC flipflopsmalfunction when the slope of the clock is notsufficiently steep.

ß Slow clock cause both the NMOS and PMOSclocked transistors to be ON simultaneously,resulting in undefined values of the states and raceconditions.

ß Clock slopes thus must be carefully engineered. Ifnecessary, local buffers must be introduced to ensurethe quality of the clock signal


B.Supmonchai

clkD clkQ

clk

clk

XY

M1

M2

M3 M6

M5

M4 M7

M8

M9

I1 I2 I3

Simplified TSPC ET FF

I1 holdI2 evaluateI3 sample (transparent)

I1 sample (transparent)I2 prechargedI3 hold

onoff

on

off

Æ DÆ D

clk

on

on

off

off

Æ 1

Æ !D

9 Transistors*4 Clock loads*(11 if Q is needed)




B.Supmonchai

Notes on TSPC ET FFq On the positive edge of the clock, note that the node X

transitions to a low if D is high. Therefore, the inputmust be kept stable until the value on node X before therising edge of the clock propagates to Y

ß Hold time of the register (less than 1 inverter delay since ittakes 1 inverter delay for the input to affect node X).

q Propagation delay is essentially three inverters sincethe value on node X must propagate to output Q

q Set-up time is the time for node X to be valid – oneinverter delay


B.Supmonchai

Sizing Issues in Simplified TSPC ET FF

0

1

2

3

0 0.2 0.4 0.6 0.8 1

Time (nsec)

Vol

ts

clk

!Qorig

Qorig

!Qmod

Qmod

Transistor sizing

Original width M4, M5 = 0.5mm M7, M8 = 2mm

Modified width M4, M5 = 1mm M7, M8 = 1mm

Sizing is critical – with improper sizing glitches may occur dueto race condition when the clock transitions from low to high


B.Supmonchai

Positive Latch Negative Latch

transparent when clk = 1hold when clk = 0

hold when clk = 1transparent when clk = 0

clkInQ

AclkIn Q

A

When In = 0, A = VDD - VTn When In = 1, A = | VTp |

Split-Output TSPC Latches


B.Supmonchai

Split-Output TSPC ET FF8 Transistors*2 Clock loads*(10 if Q is needed)

Which edge-triggered?

q Downside is not all node voltages in the latch experiencefull logic swing due to threshold drop.

ß E.g., for positive latch when D=0 and clk=1, A=Vdd-Vth (Alsolimits the amount of Vdd scaling possible with this latch).

clkD

Qclk QM

A




B.Supmonchai

Master-Slave Flipflop Pulse-Triggered Flipflop

D

Clk

Q D

Clk

Q

Clk

DataL1 L2

Pulse-Triggered Flipflops

q Another approach to design an edge-triggeredflipflop is to use pulse-triggered.

LData

D

Clk

Q

Clk


B.Supmonchai

0 ONVdd

OFF OFF

11 0ON

Xclk

D

Q

M1

M2

M3

M4

M5

M6

P1

P2

P3

!clkd

1/0ON/OFF

0/Vdd ON/OFF

1/0

0 OFF

1

1OFF

ON ON

ON

Pulsed FF (AMD-K6)q Pulse registers - a short pulse (glitch clock) is generated

locally from the rising (or falling) edge of the systemclock and is used as the clock input to the flipflop


B.Supmonchai

Notes on Pulsed FFq Race conditions are avoided by keeping the transparent

mode time very short (during the pulse only)

q Reduce clock load but substantially increase complexityin verification

q The transparency period determines the hold time.ß The window must be wide enough for the input data to

propagate to Q.

q The set-up time can be NEGATIVE (if the transparencywindow is longer than the delay from input to output).ß This is attractive, as data can arrive at the register even after

the clock goes high, meaning that time can be borrowed fromthe previous cycle.


B.Supmonchai

0

0

1

1

1

1

1

0

1

0

1

Sense Amp FF (StrongArm SA100)q Sense amplifier is a circuit that accept small swing input

signals and amplify them to full rail-to-rail signals

clk

D

Q

!Q

M1

M2

M3

M5

M6

M4

M9

M7

M8

M10

!S

!R

X

Y




B.Supmonchai

Notes on Sensed Amp FFq The key is transistor M4 (in the middle of Sensed amp);

it delays signals that pass through to the other side of itsterminal, making the change on the other side slowerß When D = 1, Y changes after X due to the delay of M4. By the

time M6 reacts to the change at its terminal, it is alreadyturned off by the terminal voltage at M4 (a 0). Thus, M6holds a 1.

q M4 also provides DC-leakage path to ground for eithernode X or Y in case that the inputs change their valueafter the positive edge of CLK arrives.

q Advantages are reduced clock load and that it can beused as a receiver for reduced swing differential busesß Where does the differential signal enter?


B.Supmonchai

Flipflop Comparison Chart

203 (clk)SenseAmpSA 100

195 (clk)DynamicAMD K6

102 (clk)DynamicS-O TSPC

3tpinvtpinvtpinv114 (clk)DynamicTSPC

2tpinv+tptx

tpinv+tptx

tpFF

84 (clk-!clk)DynamicC2MOS

to1-1tptx84 (clk-!clk)DynamicT-gate

168 (clk1-clk2)Ps-Static2-phase

168 (clk-!clk)StaticPowerPC

03tpinv+tptx208 (clk-!clk)StaticMux

tholdtset-up#tr#clk ldTypeName


B.Supmonchai

Choosing a Clocking Strategyq Choosing the right clocking scheme affects the

functionality, speed, and power of a circuit

q Two-phase designsß + robust and conceptually simple

ß - need to generate and route two clock signals

ß - have to design to accommodate possible skew between thetwo clock signals

q Single phase designsß + only need to generate and route one clock signal

ß + supported by most automated design methodologies

ß + don’t have to worry about skew between the two clocks

ß - have to have guaranteed slopes on the clock edges


B.Supmonchai

Non-Bistable Sequential Circuits

q Previously, we have defined a circuit having twostable states a bi-stable circuit

q Other regenerative circuits, which are non-bistable:ß Monostableÿ Only one stable state -> Pulse generators, One-shot circuits

ß Astableÿ No stable states -> Oscillator, On-chip clock generator

ß Schmitt Triggerÿ A special regenerative circuit exhibiting hysteresis in VTC.




B.Supmonchai

In Out

Schmitt Trigger

Non-Bistable Sequential Circuits

Vin

Vout VOH

VOL

VM– VM+

2 important properties

ß Hysteresis

ß Fast Transition Timeat the output


B.Supmonchai

Noise Suppression using Schmitt Trigger

VIN

t0 t

VM+

VM-

VOUT

tt0 + tp

Example: Switch Debouncer


B.Supmonchai

CMOS Schmitt Trigger

M1

M4M2

M3

VIN VOUT

X

VDDMoves switchingthreshold of thefirst inverter

Adapting the ratio between PMOS and NMOS, depending upon thedirection of the transition results in a shift in switching threshold

Low-to-High reff = kM1/(kM2 + kM4)

High-to-Low reff = (kM1 + kM3)/kM2


B.Supmonchai

Schmitt Trigger Simulated VTC

2.5

VM2

VM1

Vin (V)

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

Vou

t(V)

2.5

k = 2k = 3

k = 4

k = 1

Vin (V)

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

Vou

t(V)

Effect of varying the ratio of thePMOS device M4

Voltage Transfer Characteristicswith hysteresis

M1 = 1 mm/0.25 mm, M2 = 3 mm/0.25 mm, M3 = 0.5 mm/0.25 mm

M4 = 1.5 mm/0.25 mm M4 = k x 0.5 mm/0.25 mm




B.Supmonchai

CMOS Schmitt Trigger (2)

How does the gate operate?

M2

VIN VOUT

XM1

M5

M6

M3

M4

Sketch VTC and find expression for VM- and VM+


B.Supmonchai

Review: Ring Oscillator

0.0

0.0

0.5

1.0

1.5

2.0

2.5V1 V3 V5

3.0

20.50.5

time (ns)

1.0 1.5

Period: T = 2 x tp x N

tp

Different Clock Duty-Cyclesand phases can be derivedusing simple logic operations


B.Supmonchai

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5Vcontr (V)

0.0

2

4

6

tpHL (

nsec)

propagation delay as a functionof control voltage

Voltage Controller Oscillator (VCO)q Oscillation frequency of a VCO is a function (typically

nonlinear) of a control voltage

Delay of a current starved inverter depends on the currentlimit available to discharge the load capacitance of the gate


B.Supmonchai

Current-Starved Inverter Simulation

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5Vcontr (V)

0.0

2

4

6

tpHL (

nsec)

propagation delay as a functionof control voltage

Vctrl (V)t p

HL (

ns

ec)

q The device is in thesubthreshold regionwhen Vctrl is smallerthan VT, resulting inlarge variations of tpas the drive currentis exponentiallydependent on thedrive voltage

ß Delay sensitive tonoise and variationin Vctrl




B.Supmonchai

Differential Delay Element and VCO

two stage VCO

v 1v 2

v 3

v4

- Inverting Inputs/Outputs+ Non-Inverting Inputs/Outputs

Oscillator with even numberof stages can be implemented

in2

Vctrl

Vo2 Vo1

in1

delay cell

+

+

-

-

Differential-type VCO has better immunity to common modenoise (e.g., supply noise) but consume more power


B.Supmonchai

2-Stage VCO Simulation

0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

2 0.51.5

V 1 V 2 V 3 V 4

time (ns)2.5 3.5

The In-Phase and Quadrature Phase are produced simultaneously

b.supmonchai goals of this chapter · 2009-11-12 · b.supmonchai july 4th, 2005 2102-545 digital...

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