bsc architecture

BSC Architecture Siemens

MN1780EU08MN_00011

Contents

1 Functions of the BSC 3

1.1 Traffic Channel Switching 5

1.2 Signaling Information Processing 9

2 Functions of the BSC Modules 13

2.1 Switching Network (SN16 or SN64) 16

2.2 Peripheral Processor for CCSS7 (PPCC) 17

2.3 Peripheral Processor for LAPD (PPLD) 18

2.4 Telephony Processor (TDPC, MEMT) 19

2.5 Administrative Processors (MPCC, ME2M, UBEX) 20

2.6 Line Termination (QTLP or DTLP) 22

2.7 Mass Storage (DK40) 26

2.8 O&M Interface (IXLT) 28

2.9 Clock Unit (PLLH) 31

2.10 Packet Control Unit (PCU) 32

3 Bus Systems 34

4 Rack Configuration 37

4.1 Base Subrack 40

4.2 Expansion Subrack 42

5 BSC Capacity 45

6 Exercises 47

BSC Architecture

Siemens BSC Architecture

MN1780EU08MN_00012


MN1780EU08MN_00013

1 Functions of the BSC


MN1780EU08MN_00014

The Base Station Controller (BSC) is the central controller of the Siemens BaseStation (SBS) and provides interfaces to the BTSE, TRAU, SGSN, LMT and OMC.

The BSC provides the following functions:

� Traffic channel switching

� Signaling information processing

� O&M handling and alarm monitoring

BTSE

BTSE

TRAULink

Interface

SN Link

Interface

BSC

Control

LMTOMC

BSC

SGSN

Fig. 1 BSC principle architecture


MN1780EU08MN_00015

1.1 Traffic Channel Switching

The BSC is connected to the TRAU via the Asub interface, to the SGSN via the Gbinterface and to the BTSE via the Abis interface.

BTSE

BTSE

TRAULink

Interface

Link

Interface

SN-1BSC

SGSNLink

Interface

Link

Interface

.

.

.

.

.

.

SN-0Asub

Abis

PCM 30 PCM 30

Gb

Frame

Relay

Fig. 2 Asub, Abis and Gb interfaces


MN1780EU08MN_00016

One of the functions of the BSC is to switch the traffic channels from the MSC via theTRAU to the appropriate BTSE. This is accomplished by the Switching Network (SN)in the BSC.

The duplicated Switching Network (SN) switches the individual traffic channels(16 kbit/s = 13 kbit/s + 3 kbit/s) from the MSC to the BTSE and vice versa.

TRAU

BSC

SGSN

.

.

.

.

.

.

Asub

Abis

Link

Interface

Link

Interface

SN-1

Link

Interface

Link

Interface

SN-0

3 2 1 0 3 2 1 0

4x16 kbit/s

Traffic Channels

4x16 kbit/s

Traffic Channels

Gb

Permanent Virtual

Connection in

Frame RelayPacket Data

Channel

Fig. 3 BSC traffic channel switching


MN1780EU08MN_00017

1.1.1 Packet Control Unit

In the SBS, the realization of GPRS requires the functional element PCU to beintroduced into BSC and the CCUs (Channel Codec Units) to be implemented in theBTSs. The PCU assumes central GPRS tasks in the SBS such as radio channelmanagement and protocol conversion between Gb and Abis interface. The CCUsserve to extend PCU functions in the individual BTSs; however, functions arerestricted to channel coding, radio channel measurements and mapping of GPRSinformation via the Abis interface.

For packet-transmitted data and signaling, the PCU performs the same tasks asthose formerly performed by the BSC for transmission-oriented information. It alsofulfils additional functions for packet data transmission, such as the PDCH RLC ARQfunctions (including buffering and re-transmission of RLC blocks in case of data loss).

Owing to the fact that the CCU does not know the radio resources assigned to theindividual MS, a large number of functions, which for the classical GSM serviceswere formerly performed in the BTS, have now been removed to the PCU. Onetypical example of this is the power control function.

An important task of the PCU is the channel access control function.

1.1.1.1 Data Format Conversion between Gb and Abis Interfaces

While the Gb interface has been specified as interface with multivendor-capabilities,the transport mechanism on the Abis interface represents a proprietary solution. Thetransport mechanism is a proprietary PCU frame format (an extension of existingTRAU frames). The PCU frames have a uniform length of 320 Bit and are transferred

every 20 ms via the Abis interface (�16 kbit/s). In the BSC the PCU acts as astatistical multiplexer and router. The protocol layers are handled and interworkingfunctions are performed.


MN1780EU08MN_00018

Gb:standard interface

multi-vendor capabilities

PCU is responsible for central GPRS-tasks in the SBS

• Management of GPRS radio resources

• Protocol conversion (packet data Interworking)

• Tasks comparable to “classical” BSC

• Remote (until now BTS-tasks): PC, TA,...

CCUs only:• Channel Coding

• Radio Channel Measurement

CCU

CCU

P

C

U

BTS BSC

SGSN

Abis Gb

TDPC

PCU

Abis:proprietary

LAPD

SGSNBSC

Frame Relay

Data transport:

• proprietary PCU frame format

• (extension of TRAU frame)

• PCU frames: 320 Bit / 20 ms

PCU

Functions

TRAU FrameTRAU Frame

TRAU FrameTRAU Frame

PCU as

Multiplexer & Router

each 16 kbit/s

TDPC: Telephony

Distribution Processor Circuit

Fig. 4 PCU functions


MN1780EU08MN_00019

1.2 Signaling Information Processing

There are two signaling paths in the SBS each with a different protocol:

� Traffic channel signaling between MSC and BSC (CCSS7 protocol)

� Signaling between BSC and SGSN (BSSGP)

� O&M information exchange and traffic channel signaling within the SBS (LAPDprotocol)

BTSE

BTSE

BSC TRAU MSC

LAPD

LAPD

LAPD

4x16 kbit/s TCH

CCSS 7

64 kbit/s

CCSS 764 kbit/s

1x16 kbit/s TCH

Abis Asub A

SBS

SGSN

Gb

BSS GPRS ProtocolFrame Relay

PCU

Fig. 5 Signaling in the SBS


MN1780EU08MN_000110

The signaling channel (CCSS7) passes through the TRAU transparently (notranscoding) and is evaluated by the BSC.

BTSE

BTSE

BSC TRAU MSC

CCSS 7

64 kbit/s

CCSS 7

64 kbit/s

Abis Asub A

SBS

Fig. 6 CCSS7signaling


MN1780EU08MN_000111

The timeslot used on the Asub interface for LAPD signaling cannot be used on the Ainterface.

Since the CCSS7 signaling on the Asub interface uses the entire 64 kbit/s, the sametimeslot on the remaining A interface links cannot be used.

BTSE

BTSE

BSC TRAU MSC

LAPD

CCSS 7

64 kbit/s

CCSS 7

64 kbit/s

Abis Asub A

SBS

not used

Fig. 7 CCSS7 and LAPD signaling


MN1780EU08MN_000112

The following types of signaling timeslots must be assigned to the Abis and Asubinterfaces:

� Timeslots carrying O&M signaling data for the control of the BTSE by the BSC.The O&M signaling on the Abis uses the LAPD protocol and is referred to asLPDLM in the BSC database.

� Timeslots carrying traffic channel signaling. The traffic channel signaling on theAbis interface uses the LAPD protocol and is called LPDLR in the BSC database.(LPDLM and LPDLR are always put together into the same timeslot.)

� Timeslots carrying O&M signaling data for the control of the TRAU by the BSC.The O&M signaling on the Asub uses the LAPD protocol and is referred to asLPDLS in the BSC database.

� Timeslots carrying traffic channel signaling. The traffic channel signaling on the Aand Asub interfaces uses CCSS7 protocol and is referred to as SS7L in the BSCdatabase.

The BSSGP is carried on the same Permanent Virtual Circuit between BSC andSGSN that carries the packet data traffic.

PCMB PCMSUm

Abis AsubPCMA

A

LPDLM&LPDLR LPDLS SS7L

BTSE BSC TRAU MSC

SGSN

PCMG

Gb

BSSGP

Fig. 8 Interfaces and signaling


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2 Functions of the BSC Modules


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The different modules of the BSC are shown in the figure below:

DK 40

Line TerminationQTLP/DTLP


Line TerminationQTLP/DTLP Switching

Network

SN16/SN64

Clock

PLLH




LA

PD

PP

LD

LA

PD

PP

LD

BS

SG

P

PP

CU

CC

S 7

PP

CC

CC

S 7

PP

CC

MEMT TDPC

Telephony Processors

O&MInterface

IXLT

AdministrativeProcessor

(ME2M) UBEX

MPCCDK 40

to OMC

to LMT

. . . PeriphalProcessors

Fig. 9 BSC internal architecture


MN1780EU08MN_000115

The following table summarizes the BSC modules:

Abbreviation Full Module Name

SN16 or 64 Switching Network at 16 or 64 kbit/s

PPCC Peripheral Processor for CCSS7

PPLD Peripheral Processor for LAPD

PPCU Processor for Packet Control Unit

TDPC Telephony and Distributor Processor Circuit

MEMT Memory of the TDPC

MPCC Main Processor Control Circuit

(ME2M) (Memory Board 2 Mbyte)

UBEX Universal Bus Extender Board

QTLP or DTLP Quad or Dual Trunk Line Peripheral Board

DK40 Disk 40 Mbyte

IXLT Interface to LMT/OMC

PLLH Phase Locked Loop High Performance

PWRD Power Distributor

EPWR Expansion Power Supply


MN1780EU08MN_000116

2.1 Switching Network (SN16 or SN64)

The Switching Network (SN16 or SN64):

� switches, under the control of the Administrative Processor, the traffic channelsfrom the TRAU to the BTSE and from the BTSE to the TRAU

� routes the signaling timeslots (LAPD and CCSS7) to/from the peripheralprocessors (PPLD and PPCC) via semipermanent connections (nailed-upconnections).

� comprises a single stage switching matrix for 4 x 3072 x 16 kbit/s (SN16) orrespectively 3072 x 64 kbit/s (SN64) time slots.

� is protected by 2n redundancy (n=1).

BTSE

BTSE

LAPD

TRAU

SGSNLine

Termination

Line

Termination

Line

Termination

Line

Termination

L

A

P

D

B

S

S

G

P

C

C

S

7

C

C

S

7

Switching

Network

Telephony

Processor

Peripheral Processors

LAPD

CCS7

BSC

BSSGP

Fig. 10 Switching network


MN1780EU08MN_000117

2.2 Peripheral Processor for CCSS7 (PPCC)

The Peripheral Processor for CCSS7 (PPCC):

� handles CCSS7 MTP layer 2 for the signaling towards the MSC (A interface, via Asub interface). The layer 2 defines the functions such as:- error detection- error correction- recovery of a link failure

� handles up to 4 x 64 kbit/s signaling links

� is protected by n+1 redundancy (n=1).

DK 40




Network

SN16/SN64

Clock

PLLH




L

A

P

D

P

P

L

D

L

A

P

D

P

P

L

D

B

S

S

G

PO

P

P

C

U

C

C

S

7

P

P

C

C

C

C

S

7

P

P

C

C

MEMT TDPC


O&M

Interface

IXLT

Administrative

Processor

(ME2M) UBEX

MPCCDK 40

to OMC

to LMT

. . . Periphal

Processors

Fig. 11 Peripheral processor for CCSS7 (PPCC)


MN1780EU08MN_000118

2.3 Peripheral Processor for LAPD (PPLD)

The Peripheral Processor for LAPD (PPLD):

� is responsible for handling the level 2 LAPD protocol (used for signaling on theAbis and Asub interfaces):

- O&M signaling between BSC and TRAU: LPDLS

- O&M signaling between BSC and BTSE: LPDLM

- Radio signaling between BSC and BTSE (TRX): LPDLR

� handles up to 8 physical signaling links, both for 16 kbit/s or 64 kbit/s, and up to 64Terminal Endpoint Identifiers (TEI)

� is protected by n+1 redundancy.

DK 40




Network

SN16/SN64

Clock

PLLH




L

A

P

D

P

P

L

D

L

A

P

D

P

P

L

D

B

S

S

G

P

P

P

C

U

C

C

S

7

P

P

C

C

C

C

S

7

P

P

C

C

MEMT TDPC


O&M

Interface

IXLT

Administrative

Processor

(ME2M) UBEX

MPCCDK 40

to OMC

to LMT

. . . Periphal

Processors

Fig. 12 Peripheral processor for LAPD (PPLD)


MN1780EU08MN_000119

2.4 Telephony Processor (TDPC, MEMT)

The hardware structure of the Telephony Processor is based on two circuit boards:

� TDPC: Telephony and Distributor Processor Circuit which includes a 4 Mbytememory

� MEMT: Memory of the Telephony Processor which is a memory expansion for theTDPC and behaves as a mail box for MPCC - TDPC messages interchange.

The Telephony Processor:

� handles all signaling functions above MTP layer 2 (except for measurementpreprocessing, which is performed in the BTSE) and all application processesrelated to call control, radio resource management, and mobility management

� is connected via an internal bus (Telephony System Bus) to the PPCC and PPLD


DK 40




Network

SN16/SN64

Clock

PLLH




L

A

P

D

P

P

L

D

L

A

P

D

P

P

L

D

B

S

S

G

P

P

P

C

U

C

C

S

7

P

P

C

C

C

C

S

7

P

P

C

C

MEMT TDPC


O&M

Interface

IXLT

Administrative

Processor

(ME2M) UBEX

MPCCDK 40

to OMC

to LMT

. . . Periphal

Processors

Fig. 13 Telephony processor (TDPC, MEMT)


MN1780EU08MN_000120

2.5 Administrative Processors (MPCC, ME2M, UBEX)

The Administrative Processor circuit is comprised of three boards:

� MPCC: Main Processor Control Circuit which includes a 2 Mbyte memory

� ME2M: Memory Board 2 Mbyte which is a memory expansion for the MPCC(ME2M is not used in release BR5.0 or higher)

� UBEX: Universal Bus Extender board which interfaces MPCC to switchingnetwork, clock, peripheral processors, and line terminations.

The administrative processor:

� controls the connections of the Switching Network (SN) on the basis of theTelephony Processor messages

� handles traffic and performance measurements

� is responsible for hardware configuration

� is responsible for diagnostic and maintenance management

� controls the DK40

� performs software downloading



MN1780EU08MN_000121

DK 40




Network

SN16/SN64

Clock

PLLH




L

A

P

D

P

P

L

D

L

A

P

D

P

P

L

D

B

S

S

G

P

P

P

C

U

C

C

S

7

P

P

C

C

C

C

S

7

P

P

C

C

MEMT TDPC


O&M

Interface

IXLT

Administrative

Processor

(ME2M) UBEX

MPCCDK 40

to OMC

to LMT

. . . Periphal

Processors

Fig. 14 Administrative processor (MPCC, ME2M, UBEX)


MN1780EU08MN_000122

2.6 Line Termination (QTLP or DTLP)

The Quad or Dual Trunk Line Peripheral boards (QTLP or DTLP) provide theconnections to the BTSE (Abis interface) and TRAU (Asub interface) via standard2 Mbit/s digital lines. Both type of modules are referred to as XTLP or LICD.

The QTLP or DTLP are distributed between Abis and Asub interfaces. QTLP must beassociated to SN16 as well as DTLP must be associated to SN64. The QTLP/SN16association features the Dual Rate (Half Rate/Full Rate) capability for the SBSwhereas the DTLP/SN64 features the normal Full Rate capability for traffic channels.

DK 40




Network

SN16/SN64

Clock

PLLH




L

A

P

D

P

P

LD

L

A

P

D

P

P

LD

B

S

S

G

P

P

P

CU

CC

S 7

P

P

C

C

CC

S 7

P

P

C

C

MEMT TDPC


O&MInterface

IXLT


ME2M UBEX

MPCCDK 40

to OMC

to LMT

. . . PeriphalProcessors

Fig. 15 Line termination (QTLP or DTLP)


MN1780EU08MN_000123

Selection Mode

Each QTLP (DTLP) handles four (two) active 2 Mbit/s PCM lines and contains four(two) ports.

Each port consists of two physical interfaces (terminal A and terminal B). One ofthese terminals is chosen for the active line, the second one can be used for aredundant line or as loop terminal 2.

Port 0

Port 1

Port 2

Port 3

Port 0

Port 1

DTLP

QTLP

terminal A

terminal B

terminal A

terminal B

terminal A

terminal B

terminal A

terminal B

terminal A

terminal B

terminal A

terminal B

2 Mbit/s

(TRAU or BTSE)

2 Mbit/s

(TRAU or BTSE)

Fig. 16 QTLP and DTLP


MN1780EU08MN_000124

Transparent Mode

In order to support the increased capacity of the BSC a flexible PCM lineconfiguration to the TRAU is provided, i.e. without changing the number of QTLPboards, the number of PCMS connected is increased.

The QTLP board can be configured with all 4 PCM couples either in selection mode(the line keeps 2 trunks busy even if it is not terminated) or in transparent mode (theline keeps busy only one trunk, it can be configured only in simplex). Thus, it ispossible to connect up to 8 TRAU to a single QTLP board, leaving more cardsavailable for the Abis connection.

Up to 16 PCMS + 28 PCMB or 20 PCMS + 26 PCMB (i. e. 46 PCM lines)configurations are possible.

Q T L P

T R A U 1

T R A U 2

T R A U 3

T R A U 4

Fig. 17 Selection mode (duplicated line) TRAU connected to a single QTLP


MN1780EU08MN_000125

QTLP

TRAU 1

TRAU 2

TRAU 3

TRAU 4

TRAU 5

TRAU 6

TRAU 7

TRAU 8

Fig. 18 PCM lines in transparent mode (simplex line), 8 TRAU connected to a single QTLP

QTLP

TRAU 1

TRAU 2

TRAU 3

TRAU 4

BTSE 1

BTSE 2

Fig. 19 Mixed configuration of PCM lines in transparent mode (simplex line) and selection mode (duplicated line: 4 Asub andAbis links are connected to 1 QTLP)


MN1780EU08MN_000126

2.7 Mass Storage (DK40)

The Disk 40 Mbyte (DK40) consists of a hard disk with copies of all software in theSBS and all configuration data to allow a fast restart without downloading from theOMC. The hard disk is customary in trade, the name DK40 is historical.

The DK40 is updated every time a database change is made via the LMT or theOMC.

The DK40 is duplicated and data are written by the MPCC on both copiessimultaneously.

DK 40




Network

SN16/SN64

Clock

PLLH




L

A

P

D

PP

L

D

L

A

P

D

PP

L

D

B

S

S

G

P

PP

C

U

C

C

S

7

P

P

C

C

C

C

S

7

P

P

C

C

MEMT TDPC


O&M

Interface

IXLT

Administrative

Processor

(ME2M) UBEX

MPCCDK 40

to OMC

to LMT

. . . Periphal

Processors

Fig. 20 Mass storage (DK40)


MN1780EU08MN_000127

System directories

The DK40 is used for storing the BSC database and the software load files. Usually,there are three system directories:

� SYS_BACKUP: Here the running software version is stored.

� SYS_FALLBACK: For security, here the most reliable software version is stored.

� SYS_NEW: This directory is intended for the download in case of softwareupgrades.

DK 40

New

Fallback

Backup

Fig. 21 System directories of DK 40


MN1780EU08MN_000128

2.8 O&M Interface (IXLT)

The Interface X.25 and Local Terminal (IXLT) allows the administrative processor tobe connected to the operation and maintenance center (OMC) and to the localmaintenance terminal (LMT).

DK 40




Network

SN16/SN64

Clock

PLLH




L

A

P

D

P

P

L

D

L

A

P

D

P

P

L

D

L

A

P

D

P

P

L

D

C

C

S

7

P

P

C

C

C

C

S

7

P

P

C

C

MEMT TDPC


O&M

Interface

IXLT

Administrative

Processor

(ME2M) UBEX

MPCCDK 40

to OMC

to LMT

. . . Periphal

Processors

Fig. 22 O&M interface (IXLT)


MN1780EU08MN_000129

The interconnection between the LMT and the BSC is realized by a X.21/V.11interface using the LAPB and HDLC protocol.

BTSE

BSC

TRAUMSC

LMT

IXLT

X.21/V11

SBS

Fig. 23 Interconnection BSC - LMT


MN1780EU08MN_000130

The interconnection to the OMC can be realized either by a dedicated physical link(X.25) via a public (or private) packet switched data network or by a 64 kbit/s PCMtime slot extracted from a 2 Mbit/s line towards the MSC (nailed-up connection). TheO-Link can be set up redundantly.

BTSE

BSC

IXLT

TRAUMSC

SIEMENS

NIXDORF SIEMENS

NIXDORF SIEMENS

NIXDORF

PSDN

dedicated line

nailed-upconnection

OMC for SBS

SBSNo transcoding

64 kbit/s

64 kbit/s

64 kbit/s

Fig. 24 Interconnection BSC - OMC


MN1780EU08MN_000131

2.9 Clock Unit (PLLH)

The Phase Locked Loop High Performance (PLLH) clock:

� is based on a high stability quartz oscillator that provides all of the timing signalsnecessary to the system

� can work in free running mode, or synchronized to external clock sources

� is based on two identical redundant boards (PLLH) working in master/slaveconfiguration.

DK 40




Network

SN16/SN64

Clock

PLLH




L

A

P

D

P

P

L

D

L

A

P

D

P

P

L

D

B

S

S

G

P

P

P

C

U

C

C

S

7

P

P

C

C

C

C

S

7

P

P

C

C

MEMT TDPC


O&M

Interface

IXLT

Administrative

Processor

(ME2M) UBEX

MPCCDK 40

to OMC

to LMT

. . . Periphal

Processors

Fig. 25 Clock (PLLH)


MN1780EU08MN_000132

2.10 Packet Control Unit (PCU)

Hardware implementation of a PCU into the SBS requires extension of the BSC bytwo cards, termed Peripheral Packet Control Unit PPCU. One card provides GPRS,while the second card is on cold standby.

A BSC may comprise one or two PCUs (and consequently 2 or 4 PPCUs, two active,two cold standby).If there are two PCUs in a BSC, the packet traffic is distributedstatically to both units. From the point of view of SGSN the BSC then consists of twoareas. A specific cell is always explicitly assigned to a certain PCU.

The functions of the PPCUs supporting the interworking of packet data between theAbis and Gb interfaces may be divided as follows:

� Channel handling via the Abis interface

� Implementation of the BSS GPRS protocol and the network service (frame relay)functions on the Gb interface.

Cells are assigned to an individual PPCU statically (by configuration).

2.10.1 PPCU

The new PPCU boards are built into the BSC rack instead of PPLDs (peripheralprocessors for LAPD). For two PCUs (with two PPCUs each), nine of the 16 PPLDsneed to be removed. The PPCUs of the first PCU substitute PPLDs 15 and 12,additionally, PPLDs 14 and 13 need to be removed. The PPCUs of a second PCUsubstitute PPLDs 9 and 8, while PPLDs 11, 10 and 7 have to be removed.

The PPCU board is structured into three blocks:

� PCU controller

� Abis interface controller

� Gb interface controller

Communication between these blocks is possible by the use of a PCI bus.


MN1780EU08MN_000133

PCU

Implementation

PPCU

Peripheral Packet

Control Unit:

Interworking packet data

between Gb & A bis

BSC

PCU

PPCUPeripheral Packet

Control Unit

Providing

Service

PPCU

Cold

Standby

PCU

PPCU

Providing

Service

PPCU

Cold

Standby

max. 2 PCUs

cell 1

cell 2

cell 3

cell n� � �

cell n+1

cell n+2

cell n+1

cell n+x� � �

SGSN

regards BSC (2 PCUs) as 2 areas

PCU Controller

RLC /MAC (PCUC)

Abis Interface

Controller A bIC

Gb Interface

Controller GbIC PCI bus

PPCU board

structure

Fig. 26 PCU implementation


MN1780EU08MN_000134

3 Bus Systems

Three bus systems are implemented on the BSC backplane:

� Telephony System Bus:

Connects the peripheral processors PPCC and PPLD, PPCU with the TDPC.

� Administrative System Bus:

Connects the TDPC to the MPCC and the MPCC to the IXLT and DK40.

� Administrative Extended Bus:

Used as an O&M connection between MPCC (via UBEX) and PPCC, PPLD,PPCU, SNXX, PLLH and XTLP.


MN1780EU08MN_000135

DK 40




Network

SN16/SN64

Clock

PLLH




L

A

P

D

P

P

L

D

L

A

P

D

P

P

L

D

B

S

S

G

P

P

P

C

U

C

C

S

7

P

P

C

C

C

C

S

7

P

P

C

C

MEMT TDPC


O&M

Interface

IXLT

Administrative

Processor

(ME2M) UBEX

MPCCDK 40

to OMC

to LMT

. . .

Telephony

System Bus

Administrative

System Bus

Administrative

Extended Bus

Fig. 27 Bus systems


MN1780EU08MN_000136


MN1780EU08MN_000137

4 Rack Configuration


MN1780EU08MN_000138

The BSC consists of the Base and Expansion Subracks:

� The Base Subrack represents the minimum configuration.

� The Expansion Subrack provides capability to increase the number of XTLP andPPLD or PPCU.

Lamp Panel

X

T

L

P

8

X

T

L

P

7

X

T

L

P

6

P

P

L

D

14

P

P

L

D

13

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1

EXPANSION

Fuse and Alarm

Panel

Base

XTLP = QTLP or DTLP; SNXX = SN16 or SN64

Fig. 28 BSC rack (without PCU)


MN1780EU08MN_000139

L I C

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FUSE & ALARM

PANEL

P P

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Removed

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P P

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2

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Removed

Fig. 29 BSC rack (with 4 PPCU)


MN1780EU08MN_000140

4.1 Base Subrack

For reasons of reliability, certain modules are duplicated (2n redundancy) orcombined to a pool with one spare module (n+1 redundancy).

Module Redundancy Quantity Numbering

XTLP n+1 2+1 XTLP-0,-1; XTLP-S0

PPCC n+1 1+1 PPCC-0,-1

PPLD n+1 3 PPLD-0,-1,-2

PLLH 2n 2 PLLH-0,-1

PWRS 2n 2 PWRS-0,-1

DK40 2n 2 DK40-0,-1

IXLT 2n 2 IXLT-0,-1

SNXX 2n 2 SN16-0,-1

TelephonyProcessor

2n 2 TDPC-0,-1

MEMT-0,-1


2n 2 MPCC-0,-1

ME2M-0,-1

UBEX-0,-1


MN1780EU08MN_000141

The base subrack accommodates two power supplies PWRS-0 and PWRS-1:

� input voltage: -48 V

� output voltage: +5.3 V and +12.3 V

The two power supplies PWRS-0/PWRS-1 provide power to the following modules:

� PWRS-0 is responsible for all of the modules on side 0 and all XTLP, PPCC, andPPLD.

� PWRS-1 is responsible for all of the modules on side 1 and all XTLP, PPCC, andPPLD.

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Fig. 30 DC power distribution in the base subrack


MN1780EU08MN_000142

4.2 Expansion Subrack

The expansion subrack has additional space for the following:

� 7 + 1 XTLP

� 12 PPLD or 4 PPLD + 4 PPCU

� 2 PWRS, called EPWR in the BSC database.

Module Redundancy Quantity Numbering

XTLP n+1 7+1 QTLP-2...-8

QTLP-S1

PPLD n+1 12 PPLD-3...-14

PPCU n+1 2 x (1+1) PPCU-0...-3

PWRS 2n 2 PWRS-0,-1

Each EPWR supplies all of the modules.

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Fig. 31 DC power distribution in the expansion subrack


MN1780EU08MN_000143

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Fig. 32 Expansion subrack fully equipped with four PPCU


MN1780EU08MN_000144


MN1780EU08MN_000145

5 BSC Capacity

The capacity of a BSC is limited by the following four factors:

� Quantity of DTLP boards with SN64 or QTLP boards with SN16.

� Capacity of the switching network: 1500 Erl.

� Number of available LAPD signaling links (112, PPLD).

� Maximum number of BTSE, BTS and TRX handled by the database:max. 100 BTSE, max. 150 BTS and max. 250 TRX.

� Maximum 75 GPRS cells per PCU, max 64 GPRS physical channels per cell.


MN1780EU08MN_000146


MN1780EU08MN_000147

6 Exercises

� List the major functions of the BSC.

� List the processors used in the BSC and state the purpose of each.

� State the purpose of the switching network.

� State the purpose of the DK40.

� Name the main directories of the DK40.

� In which directory is stored the running software?

� State the purpose of the IXLT.

� State the purpose of the PLLH.

� State the purpose of the QTLP.

� If MPCC-1 becomes defective, will the entire BSC be out of service?

� If EPWR-1 becomes defective, which modules will not be powered?

� How many QTLP, PPCC, and PPLD are in the base subrack?

� How many QTLP, PPCC, and PPLD are in the expansion subrack?


MN1780EU08MN_000148

bsc architecture

Documents

administrative

packet control

traffic channel

power supplies

administrative

telephony

administrative

traffic channels