bruce mayer, pe registered electrical & mechanical engineer [email protected]

[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx1

Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

Bruce Mayer, PERegistered Electrical & Mechanical Engineer

[email protected]

Engineering 43

Diodes-2



Learning Goals Understand the Basic Physics of

Semiconductor PN Junctions which form most Diode Devices

Sketch the IV Characteristics of Typical PN Junction Diodes

Use the Graphical LOAD-LINE method to determine the “Operating Point” of Nonlinear (includes Diodes) Circuits



Learning Goals Analyze diode-containing Voltage-

Regulation Circuits Use various math models for Diode

operation to solve for Diode-containing Circuit Voltages and/or Currents

Learn The difference between LARGE-signal and SMALL-Signal Circuit Models

IDEAL and PieceWise-Linear Models

http://en.wikipedia.org/wiki/File:Diode_Modelling_Image10.jpg



Diode Models LoadLine Analysis

works well when the ckt connected to a SINGLE Diode can be “Thevenized”

However, for NONLinear ckts, such as those containing multiple diodes, construction of the LOAD-Curve Eqn may be difficult, or even impossible.

Many such ckts can be analyzed by Idealizing the diode

http://en.wikipedia.org/wiki/File:Load_line_diode.png



Diode Models Consider an Electrical Diode

→ We can MODEL the V-I Behavior of this Device in Several ways

V

I

REALBehavior

IDEALModel

OFFSETModel

LINEARModel



Ideal Model (Ideal Rectifier) Analyze Ckts containing Ideal Diodes1. Assume (or Guess) a “state” for each

diode. Ideal Diodes have Two states1. ON → a SHORT Ckt when Fwd Biased2. OFF →an OPEN Ckt if Reverse Biased

2. Check the Assumed Opens & Shorts• Should have Current thru the SHORTS• Should have ∆V across the OPENS

Dio

de O

N

Diode OFF

http://en.wikipedia.org/wiki/File:Diode_Modelling_Image5.png



Ideal Model (Ideal Rectifier)3. Check to see if guesses for i-flow, ∆V,

and BIAS-State are consistent with the Ideal-Diode Model

4. If i-flow, ∆V, and bias-V are consistent with the ideal model, then We’re DONE.• If we arrive at even a SINGLE

Inconsistency, then START OVER at step-1

Dio

de O

N

Diode OFF

http://en.wikipedia.org/wiki/File:Diode_Modelling_Image5.png



Example Ideal Diode Find For Ckt Below find:• Use the

IdealDiodeModel

od VI &1

1dI

2dI

A



Example Ideal Diode

Assume BOTH Diodes are ON or Conducting

In this Case VD1 = VD2 = 0

Thus D2 Anode is connected to GND

Then Find by Ohm

Next use KCL at Node-A (in = out)

1dI

2dI

mA 1k 10

V 0102

dI

A

k 9.9V 100

21 dd II



Example Ideal Diode

Using ID2 = 1 mA

Thus Now must Check

that both Diodes are indeed conducting

From the analysis

Thus the current thru both Diodes is positive which is consistent with the assumption

1dI

2dI

A

mA 1k 9.9

V 1001

dI

mA 0101.01 dI

mA 1µA 10 21 dd II



Example Ideal Diode

Since both Diodes conduct the Top of Vo is connected to GND thru D2 & D1

Another way to think about this is that since VD2 = 0 and VD1 = 0 (by Short Assumption) Find Vo = GND+VD2+VD1

= GND + 0 + 0 = 0 Thus the Answer

1dI

2dI

A

V 0µA 101 od VI



Example Ideal Diode Find For Ckt Below find:• Use the

IdealDiodeModel• Note the

differentvalues onR1 & R2–Swapped

od VI &1

1dI

2dI

B



Example Ideal Diode

Again Assume BOTH Diodes are ON, or Conducting

As Before VD1 = VD2 = 0

Again VB shorted to GND thru D1

Then Find by Ohm

Now use KCL at Node-B (in = out)

mA 01.1k 9.9

V 0102

dI

k 01V 100

21 dd II

1dI

2dI

B



Example Ideal Diode

Using ID2 = 1.01 mA

Thus Now must Check

that both Diodes are indeed conducting

From the analysis

We find and INCONSISTENCY and our Assumption is WRONG

1dI

2dI

B

mA 01.1k 01

V 1001

dI

mA 01.01 dI

mA 01.1µA 10 21 dd II



Example Ideal Diode

Must Iterate Assume • D1 → OFF

D2 → ON

In this Case D1 is an OPEN → ID1 =0

Current ID2 must flow thru BOTH Resistors

Then Find by Ohm

mA 005.1

k 9.910V 1010

2

dI

1dI

2dI

B



Example Ideal Diode

Must Check that D1 is REVERSE Biased as it is assumed OFF

By KVL & Ohm

Thus D1 is INDEED Reverse-Biased, Thus the Ckt operation is Consistent with our Assumption

1dI

2dI

B

mV 50 V 05.0mA005.1kΩ10V10

B

B

VV



Example Ideal Diode

Calculate Vo by noting that:

D2 is ON → VD2 = 0D1 is OFF → Current can only flow thru D2

In this case Vo = VB

By the Previous Calculation, Find

1dI

2dI

B

mV 50A 01 od VI



Offset & Linear Models The Offset Model

Better than Ideal, but no account of Forward-Slope

The Linear Model

The model eqn:

Yet moreaccurate, but also does not account for Rev-Bias Brk-Down

V6.0 DbD iRv



Point Slope Line Eqn When constructing

multipiece-wise linear models, the Point-Slope Equation is extremely Useful

• Where

– (x1, y1) & (x2, y2) are KNOWN Points

Example: Find Eqn for line-segment:

2 4 6 8 10 12 14 16 18 204

6

8

10

12

14

16

18

x

y

11 xxmyy

12

12

xxyy

xym

(3,17)

(19,5)

43

1612

319175

m

xym



Point Slope Line Eqn Using the 2nd Point

Can easily convert to y = mx+b

Multiply by m, move −5 to other side of =

2 4 6 8 10 12 14 16 18 204

6

8

10

12

14

16

18

x

y

19435 xy

(3,17)

(19,5)

477

43

420

457

43

54

5743

457

435

19435

xy

xy

xy

xy

xy



Slopes on vi Curve With Reference to

the Point-Slope eqn v takes over for x, and i takes over for y

The Slope on a vi Curve is a conductance

If the curve is NONlinear then the local conductance is the first Derivative

Recall the Op-Pt is also the Q-Pt

GmVIm

vi

vi

iemens SVolt

Amps

gdvdim

dvdim

OpOpvi

OpOpvi

,

, SiemensVolt

Amps

gdvdimm

QQviOpvi ,,



Slopes on vi Curve Finally recall that

conductance & resistance are Inverses

Example: Find the RESISTANCE of the device associated with the VI curve that follows

2 4 6 8 10 12 14 16 18 204

6

8

10

12

14

16

18

V (volts)

I (am

ps)

Linear VI Curve

RGmvi

1

Siemens 43

V16A12

Volts319Amps517

Gm

VIm

vi

vi



Slopes on vi Curve Since R = 1/G Find

the Device Resistance as

For a NONlinear vi curve the local slope then: r = 1/g

The General Reln2 4 6 8 10 12 14 16 18 20

4

6

8

10

12

14

16

18

V (volts)

I (am

ps)

Linear VI Curve

S 0.751

RGmvi

1.333 1 Rmvi

Ohms 34

A12V16

Amps517Volts319

R

IVR

QQ

OpOp

Op

Op

didvr

didvr

dvdig

r

elyalternativor 11



Example PieceWise Linear Model Construct a

PieceWise Linear Model for the Zener vi curve shown at Right



PieceWise Linear Zener

m for Segment A

Us Pt-Slp eqn with (0.6V,0mA) for Pt-1

Segment- B is easy

101mS 100

V0.61.6mA01001

A

AA

m

VI

Rm

mA60mS100 :OR

V6.0mS1000

DD

DD

vivi

0Di



PieceWise Linear Zener

m for Segment C

Us Pt-Slp eqn with (−6V,0mA) for Pt-1

Thus the PieceWise Model for the Zener

121mS 33.83

1.2VmA100

V2.76mA10001

C

CC

m

VI

Rm

mA500mS3.83 :OR

V6mS3.830

DD

DD

vivi

V6ifmA5003.3mS8V6.0V6if0

V6.0ifmA60mS100

DD

D

DD

D

vvv

vvi



Example PieceWise Linear Model Alternatively in

terms of Resistances

ADVICE: remember the Pt-Slope Line-Eqn

V6ifmA50012

V6.0V6if0

V6.0ifmA6010

DD

D

DD

D

vvv

vv

i



Half-Wave Rectifier Ckt Consider an Sinusoidal V-Source, such

as an AC socket in your house, supplying power to a Load thru a Diode

Power Input Load Voltage



HalfWave Rectifier Note that the Doide

is FWD-Biased during only the POSITIVE half-cycle of the Source

Using this simple ckt provides to the load ONLY positive-V; a good thing sometimes

However, the positive voltage comes in nasty PULSES which are not well tolerated by positive-V needing loads



Smoothed HalfWave Rectifier Adding a Cap to the

Circuit creates a Smoothing effect

In this case the Diode Conducts ONLY when vs>vC and vC=vL

This produces vL(t) and iL(t) curves

Note that iL(t) is approx. constant

LCD

LC

iiidtdvCi



Smoothed HalfWave Rectifier The change in

Voltage across the Cap is called “Ripple”

Often times the load has a Ripple “Limit” from which we determine Cap size

From the iL(t) curve on the previous slide note:• Cap Discharges for

Almost the ENTIRE Cycle time, T (diode Off)

• The Load Current is approx. constant, IL

Recall from EARLY in the Class

Ripple

TIQ :lysymbolical Or,

Time Current Charge



Smoothed HalfWave Rectifier Also from Cap

Physics (chp3)

In the Smoother Ckt the Cap charges during the “Ripple” portion of the curve

Equating the Charge & Discharge “Q’s find

Note that both these equations are Approximate, but they are still useful for initial Ckt Design

Solving the equations for the Cap Value needed for a given Vr

capcap VCQ

TIVCQ Lrcap Charge Discharge

r

L

VTIC



Smoothed HalfWave Rectifier Find the Approximate Average Load

Voltage

22,,

,r

mloLhiL

mavgLVV

VVVV

avgLV ,

VL,hiVL,lo



Capacitor-Size Effect Any load will discharge the

capacitor. In this case, the output will depend on how the RC time constant compares with the period of the input signal.

The plots at right consider the various cases for the simple circuit above with a 1kHz, 5V sinusoidal input

mS 1 TRC



Full Wave Rectifier The half-wave ckt

will take an AC-Voltage and convert it to DC, but the rectified signal has gaps in it.

The gaps can be eliminated thru the use of a Full-Wave rectifier ckt

The Diodes are• Face-to-Face (right)• Butt-to-Butt (left)

Thisrectifiedoutput hasNO Gaps



Full Wave Rectifier Operation

D1 Supplies V to Load

D4 Supplies V to Load



Full Wave Rectifier Smoothing The Ripple on the

FULL wave Ckt is about 50% of that for the half-wave ckt

Since the Cap DIScharges only a half-period compared to the half-wave ckt, the size of the “smoothing” cap is then also halved:

r

L

VTIC

2



Small Signal Models Often we use NonLinear Circuits to

Amplify, or otherwise modify, non-steady Signals such as ac-sinusoids that are small compared to the DC Operating Point, or Q-Point of the Circuit.

Over a small v or i range even NonLinear devices appear linear. This allows us to construct a so-called small signal Linear Model

http://www.tootoo.com/s-ps/ce-led-traffic-signal-light-nbjd112f-2-c--p-2909275.html



Small Signal Analysis Small signal Analysis is usually done in

Two Parts:1. Large-Signal DC Operating Point (Q-Pt)2. Linearize about the Q-Pt using calculus

Recall from Calculus

This approximation become more accrate as ∆y & ∆x become smaller

xy

dxdy



Small Signal Analsyis Now let y→iD, and x→ vD

Use a DC power Supply to set the operating point on the diode curve as shown at right• This could be done using LoadLine methods

From Calculus

Next Take derivative about the Q-Pt Siemensor A/V of units DDDD vidvdi



Small Signal Analysis About Q-Pt

Now if we have a math model for the vi curve, and we inject ON TOP of VDQ a small signal, ∆vD find

The derivative is the diode small-signal Conductance at Q

Qnear D

D

QD

D

vi

dvdi

DdDQD

DD vgv

dvdii



Small Signal Analysis In the large signal

Case: R = 1/G By analogy In the

small signal case: r = 1/g Also since small

signal analysis is associated with small amounts that change with time…

Define the Diode’s DYNAMIC, small-signal Conductance and Resistance

QD

D

QD

D

dd

QD

Dd

didv

dvdi

gr

dvdig

1

1



Small Signal Analysis Note Units for rd

Recall the approximation for iD

Change Notation for Small Signal conditions

Find rd for a “Shockley” Diode in majority FWD-Bias

Recall Shockley Eqn

Then the Large-signal Operating Point at vD = VDQ

AmpVolt

VoltAmp 1

1

QD

Dd dv

dir

d

DD

QD

DD r

vvdvdii

dD

dD

vvii

1

T

D

nVv

sD eIi

T

DQ

T

DQ

nVV

snVV

sDQ eIeII 1



Small Signal Analysis Taking the derivative

of the Shockely Eqn

Recall from last sld

Sub this Reln into the Derivative Eqn

Recall

Subbing for diD/dvD

T

D

T

D

nVv

STT

nVv

SQD

D eInVnV

eIdvdi 11

DQnVV

s IeI T

DQ

T

DQDQ

TQD

D

nVI

InVdv

di

1

1

QD

Dd dv

dir

DQ

T

T

DQ

QD

Dd I

nVnVI

dvdir

11



Notation: Large, Small, Total VDQ and IDQ are the LARGE Signal

operating point (Q-Pt) DC quantities• These are STEADY-STATE values

vD and iD are the TOTAL and INSTANTANEQOUS quantities• These values are not necessarily steady-

state. To emphasize this we can write vD(t) and iD(t)



Notation: Large, Small, Total vd and id are the SMALL, AC quantities• These values are not necessarily steady-

state. To emphasize this we can write vd(t) and id(t)

AnExamplefor DiodeCurrentnotation



Effect of Q-Pt Location From

Analysis

DQ

Td

ddd

InVr

rvi

and

ppdi ,2

ppdi 1

ppdv 1ppdv 2



DC Srcs SHORTS in Small-Signal In the small-signal equivalent circuit DC

voltage-sources are represented by SHORT CIRUITS; since their voltage is CONSTANT, they exhibit ZERO INCREMENTAL, or SIGNAL, voltage

Alternative Statement: Since a DC Voltage source has an ac component of current, but NO ac VOLTAGE, the DC Voltage Source is equivalent to a SHORT circuit for ac signals



Setting Q, Injecting v Consider this ckt with AC & DC V-srcs

Sets Q

Sets vd



Large and Small Signal Ckts Recall from Chps 3

and 5 for Caps:• OPENS to DC• SHORTS to fast AC

Thus if C1 is LARGE it COUPLES vin(t) with the rest of the ckt

Similarly, Large C2 couples to the Load

To Find the Q-point DEcouple vin and vo to arrive at the DC circuit

CjZC 1



Large and Small Signal Ckts Finding the Large

signal Model was easy; the Caps acts as an OPENS

The Small Signal Ckt needs more work• Any DC V-Supply is

a SHORT to GND• The Diode is

replaced by rd (or gd)• The Caps are Shorts

Thus the Small Signal ckt for the above



Example: Small Signal Gain Find the Small

Signal Amplification (Gain), Av, of the previous circuit

Using the Small Signal Circuit

Note that RC, rd, and RL are in Parallel

And vo(t) appears across this parallel combination

The equivalent ckt

LdCp RRRR1111

tvo



Example: Small Signal Gain Thus for this Ckt the

Large, Small, and small-Equivalent ckts

Then the Amplification (Gain) by Voltage Divider

p

p

in

ov RR

RvvA

tvo

LdCp RRRR1111



All Done for Today

SmallSignal

BJT Amp

Common Collector Amplifier

LARGESignalModel

SMALLSignalModel



Bruce Mayer, PERegistered Electrical & Mechanical Engineer

[email protected]

Engineering 43

Appendix



tvo

tvo



Small Signal Analysis In the large signal

Case: R = 1/G By analogy In the

small signal case: r = 1/g Also since small

signal analysis is associated with small amounts that change with time…

Define the Diode’s DYNAMIC Conductance and Resistance

QD

D

QD

D

dd

QD

Dd

didv

dvdi

gr

dvdig

1

1



P10.67 Graph vo vs. vi for vi: −5V to +5V

-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6

file =XY_Plot_0211.xls

bruce mayer, pe registered electrical & mechanical engineer [email protected]

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