bruce mayer, pe registered electrical & mechanical engineer bmayer@chabotcollege

[email protected] • ENGR-43_Lec-06-4_RC_OpAmps.ppt1

Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

Bruce Mayer, PERegistered Electrical & Mechanical Engineer

[email protected]

Engineering 43

Chp 6.4Chp 6.4RC OpAmps RC OpAmps

CktsCkts



RC OpAmp CircuitsRC OpAmp Circuits Introduce Two Very

Important Practical Circuits Based On Operational Amplifiers

Recall the OpAmp

The “Ideal” Model That we Use• RO = 0

• Ri = ∞

• Av = ∞

Consequences of Ideality• RO = 0 vO = Av(v+−v−)

• Ri = ∞ i+ = i− = 0

• Av = ∞ v+ = v−



RC OpAmp Ckt RC OpAmp Ckt Integrator Integrator

KCL At v- node By Ideal OpAmp• Ri = ∞ i+ = i- = 0

• Av = ∞ v+ = v- = 0

0v



RC OpAmp Integrator contRC OpAmp Integrator cont

By the Ideal OpAmp Assumptions

Separating the Variables and Integrating Yields the Solution for vo(t)

A simple Differential Eqn

Thus the Output is a (negative) SCALED TIME INTEGRAL of the input Signal



RC OpAmp Ckt RC OpAmp Ckt Differentiator Differentiator

By Ideal OpAmp• v- = GND = 0V

• i- = 0

KCL at v-

2i

1i

KVL

iii 21 Now the KVL

01111 CviRv

1R

0v

1C

v



RC OpAmp Differentiator cont.RC OpAmp Differentiator cont.

Recall Ideal OpAmp Assumptions• Ri = ∞ i+ = i- = 0

• Av = ∞ v+ = v- = 0

Then the KCL

Recall the Capacitor Integral Law

Thus the KVL

02

121 Rviii O

t

C dxxiC

tv 1

t

dxxiC

iRtv )(1)( 11

111

Taking the Time Derivative of the above

)(111

111 t

dtdvCi

dtdiCR

1i

1R 2i



RC OpAmp Differentiator contRC OpAmp Differentiator cont

In the Previous Differential Eqn use KCL to sub vO for i1• Using

Examination of this Eqn Reveals That if R1 were ZERO, Then vO would be Proportional to the TIME DERIVATIVE of the input Signal• in Practice An Ideal

Differentiator Amplifies Electrical Noise And Does Not Operate

• The Resistor R1 Introduces A Filtering Action. – Its Value Is Kept As Small

As Possible To Approximate A Differentiator

02

1 Rvi O

)(11211 tdtdvCRv

dtdvCR o

o

1i

1R



Aside → Electrical NoiseAside → Electrical Noise ALL electrical signals

are corrupted by external, uncontrollable and often unmeasurable, signals. These undesired signals are referred to as NOISE

The Signal-To-Noise Ratio

Simple Model For A Noisy 1V, 60Hz Sinusoid Corrupted With One MicroVolt of 1GHz Interference

)102sin(10)120sin()( 96 ttty

Signal Noise

V1V10

amplitude noiseamplitude signalSN 6

Use an Ideal Differentiator)102cos(2000)120cos(120)( 9 ttt

dtdy

The SN is Degraded Due to Hi-Frequency Noise

Signal Noise

503

2000120

amplitude noiseamplitude signalSN



Class Exercise Class Exercise Ideal Differen. Ideal Differen.

Given Input v1(t)• SAWTOOTH Wave

Let’s Turn on the Lites for 10 minutes for YOU to Differentiate

Given the IDEAL Differentiator Ckt and INPUT Signal

Find vo(t) over 0-10 ms

F 2

k 1

F 2

k 1

Recall the Differentiator Eqn

)(11211 tdtdvCRv

dtdvCR o

o

R1 = 0; Ideal ckt



RC OpAmp Differentiator Ex.RC OpAmp Differentiator Ex.

Given Input v1(t)

The Slope from 0-5 mSF 2

k 1

F 2

k 1

sV

dtdvm 3

1

10510

For the Ideal Differentiator

)(112 tdtdvCRvo

Units Analysis

sFVQF

QsV

sQV

AV



RC OpAmp Differentiator cont.RC OpAmp Differentiator cont.

Derivative Scalar PreFactor

A Similar Analysis for 5-10 mS yields the Complete vO

F 2

k 1

F 2

k 1

mSin 50:4520

10510102 3

3112

tVVv

SVS

dttdvCRv

o

o

sCR 36312 102F102101

Apply the Prefactor Against the INput Signal Time-Derivative (slope)

InPutOutPut



RC OpAmp RC OpAmp IntegratorIntegrator Example Example

Given Input v1(t)• SQUARE Wave

For the Ideal Integrator

Units Analysis Again

t

ioo dxxvCR

vtv021

)(1)0()(

sFVQF

QsV

sQV

AV

μF 0.2

k 5



RC OpAmp Integrator Ex. cont.RC OpAmp Integrator Ex. cont.

The Integration PreFactor

0<t<0.1 S• v1(t) = 20 mV (Const)

1

21

1000001.0

12.05

11

S

SFkCR

Next Calculate the Area Under the Curve to Determine the Voltage Level At the Break Points

1.0

0

3121 21.01020)()( SmVSVdttvtvCR o

0.1t<0.2 S• v1(t) = –20 mV (Const)

01.010202

)()1.0()(

3

2.0

1.012121

SVSmV

dttvvCRtvCR oo

Integrate In Similar Fashion over• 0.2t<0.3 S• 0.3t<0.4 S



RC OpAmp Integrator Ex. cont.1RC OpAmp Integrator Ex. cont.1 Apply the 1000/S PreFactor and Plot Piece-Wise



Practical ExamplePractical Example Simple Circuit Model For a

Dynamic Random Access Memory Cell (DRAM)

Also Note the TINY Value of the Cell-State Capacitance (50x10-15 F)

Note How Undesired Current Leakage is Modeled as an I-Src



Practical Example contPractical Example cont

The Criteria for a Logic “1”• Vcell >1.5 V

Now Recall that V = Q/C• Or in terms of Current

During a WRITE Cycle the Cell Cap is Charged to 3V for a Logic-1• Thus The TIME PERIOD

that the cell can HOLD the Logic-1 value

t

CCC dxxiC

vv0

)(1)0(

VtCI

CtIV

cell

leak

cell

leakcell 5.15.13

sA

FVtH3

12

15

105.11050

)(1050)(5.1

Now Can Calculate the DRAM “Refresh Rate”

Hzt

fH

R 6671



Practical Example cont.2Practical Example cont.2 Consider the Cell at the

Beginning of a READ Operation fCoulfCoulfCoulQ

fCoulfFVQfCoulfFVQ

total

out

cell

8256751506754505.1

150503

fFCtotal 50045050 Then The Output

VfFfCoul

CQV OI 65.1

500825

/ Calc the Change in VI/O

at the READ

When the Switch is Connected Have Caps in Parallel



Design ExampleDesign Example Design an OpAmp ckt to implement in

HARDWARE this Math Relation

t

vdyyvv0

210 25

Examine the Reln to find an

Integrator Adder



Design ExampleDesign Example The Proposed

Solution The by Ideal

OpAmps & KCL & KVL &Superposition

t

vdyyvv0

210 25

t

vdyyvv0

210 25



Design ExampleDesign Example

3

4

21

4 2;5RR

CRRR

Then the Design Eqns

t

vdyyvv0

210 25

The Ckt Eqn

TWO Eqns in FIVE unknowns

This means that we, as ckt designers, get to PICK 3 values

For 1st Cut Choose• C = 20 μF• R1 = 100 kΩ

• R4 = 20 kΩ



Design ExampleDesign Example In the Design Eqns

t

vdyyvv0

210 25

kRFRk

k

2020100

205

2

2

kRRk

10

202

3

3

If the voltages are <10V, then all currents should be the in mA range, which should prevent over-heating

20μ

100k

20k

10k

20k

Then the DESIGN



WhiteBoard WorkWhiteBoard Work Let’s Work These Probs

Find Energy Stored on Cx

choose C such that

dttvvo 110

80k



APPENDIXAPPENDIX

IC GROUND BOUNCE



LEARNING EXAMPLE

IC WITH WIREBONDS TO THE OUTSIDE

FLIP CHIP MOUNTING

GOAL: REDUCE INDUCTANCE IN THE WIRING AND REDUCE THE“GROUND BOUNCE” EFFECT A SIMPLE MODEL CAN BE USED TO

DESCRIBE GROUND BOUNCE



MODELING THE GROUND BOUNCE EFFECT

)()( tdtdiLtV G

ballGB

IF ALL GATES IN A CHIP ARE CONNECTED TO A SINGLE GROUND THE CURRENTCAN BE QUITE HIGH AND THE BOUNCE MAY BECOME UNACCEPTABLE

USE SEVERAL GROUND CONNECTIONS (BALLS) AND ALLOCATE A FRACTION OFTHE GATES TO EACH BALL

nHLball 1.0 sAm 9

3

10401040

bruce mayer, pe registered electrical & mechanical engineer bmayer@chabotcollege

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