bruce mayer, pe registered electrical & mechanical engineer bmayer@chabotcollege

[email protected] • ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx1

Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

Bruce Mayer, PERegistered Electrical & Mechanical Engineer

[email protected]

Engineering 43

FETs-2(Field Effect Transistors)



Learning Goals

Understand the Basic Physics of MOSFET Operation

Describe the Regions of Operation of a MOSFET

Use the Graphical LOAD-LINE method to analyze the operation of basic MOSFET Amplifiers

Determine the Bias-Point (Q-Point) for MOSFET circuits



Load Line: Common Source Amp Shown below is

typical “Common-Source” Amplifier circuit

THE DC sources, VDD & VGG bias the MOSFET for Amp operation

That is, the two DC sources set The Operating, or Q, Pt

Now apply KVL to left loop

GGinGS

GGGSin

Vtvvor

Vvtv

0



Load Line: Common Source Amp Using the values

given the Schematic

Now KVL on Right Loop

Rearranging

Of form: y = mx + b Using given values

V421000sin1V tvGS

DSDDDD

DSDDDD

viRVor

viRV

0

D

DDDS

DD R

Vv

Ri

1

mA 20mS 1k 1

V 20

k 1

1

DSD

DSD

vi

orvi



Load Line: Common Source Amp Thus the LoadLine

Equation

Plot this on the FET vi Curve to determine the Operating Point

Since this is a LINE need only 2-points• Intercepts are easy

Making a T-Table

k 1

V 20

k 1

1DSD vi

vDS iD

0 20 mA20V 0



Draw LoadLine on FET vi Curve

VGG = VGS sets Q-Pt



Max and Min Opp-Points The common source

Amp is designed to Operate in the SATURATION Region. Recall the vGS Eqn

By sin behavior

Reading the vi-LL graph find (vDS,iD) co-ords• (vDSmin,iD) = (4V,16mA)

– vGS = 5V

• (vDSmax,iD) = (16V,4mA)– vGS = 3V

V42000sin1V tvGS

B-Pt3VV41V

A-Pt5VV41V

min,

max,

GS

GS

v

v



Voltage Swing The common source

Amp is must stay in Saturation. For this nFET that means max & min vGS values of 5V & Vto give the 1V amplitude of the sin

From Last Slide We calculated corresponding

Xmax/min values for vDS

• vDS,min = 4V (vGS = 5)

• vDS,max = 16V (vGS = 3)

Note that the output direction is Opposite the Input direct

The ckt produces a SATURATED output Voltage Swing of 4V−16V = −12V



Input and OutPut Compared Note that OUTput

peaks occur at INput Valleys → Inversion

The ratio of the V-swings

This is NOT the Gain

Gate Excitation

vDS Response

6V 2

V 12

SA



LoadLine Gain Notice

• vGS: 4→3– VDS: 11→16 (∆ = 5)

• vGS: 4→5– VDS: 11→4 (∆ = 7)

Unequal ∆’s due to the NONlinear nature of MOSFETS; they are “Square-Law” devices• The iD lines in SAT are

NOT evenly Spaced

Input

Output



LoadLine Gain Since the FET is NOT

linear, is NOT directly proportional to , so we can NOT Define a true Gain

“Small Signal” methods WILL allow us to define a true grain for the AC part of the voltage input• Requires Calculus

– To “Linearize” ckt

Input

Output



Common-Source Amp Analysis

To analyze The Common-Source Amplifier we will do the following:

1. Perform DC analysis to find the bias, or Q, point; i.e., find the DC drain current and check that the transistor is in the saturation region)

2. Find circuit small-signal AC model (based on the bias point obtained)

3. Perform AC (small signal) analysis



Saturation Slippery-Slope

Must also take care that the small-signal input does NOT push the FET Out of Saturation at ANY Time.

The vin-Amplitude and Bias-Pt Selection could• Drive the FET out of SAT

and into TRIODE Operation• Drive the FET into CutOff

(vGS < Vto)



One-Supply Bias Circuit Usually only ONE

supply voltage is available. In this case set VG with a voltage divider

Use ThéveninAt Gate

Using Thévenin Analysis at VG to relative to GND

DDGG

GGthgndG

VRR

RV

VVV

21

1

21

21

21||

RR

RRR

RRRR

G

Gth



Bias-Pt Analysis by Thévenin

)



Digression: RG by Src DeActA

lternative



One-Supply Bias Circuit Replacing

the left side of the ckt with its Thévenin equivalent

Then theKVL Eqn for the Gate Loop

The is NO V-Drop across RG as iG = 0

Thus Recall the CS amp

is designed to operate in Saturation which produces iD at this level

DSGSGG iRvRV 00

GSDSG viRV

2toGSD VvKi

Di



One-Supply Bias Circuit If the Circuit has

been properly Biased the FET is in SATURATION

In Saturation iD is INdependent of vDS and equals, at the operating , or Q, point

Recall theKVL eqnon theGATELoop (nowAssumed at the “Q” point):

Sub into SAT eqn

Di

2toGSQDQ VvKi

S

GSQGDQ R

vVi

2toGSQS

GSQG VvKR

vV



One-Supply Bias Circuit

Solve for vGSQ:

Or: Introduce new Constant: Yields quadratic Eqn in vGSQ:

Now Solve by MATLAB’s MuPAD

2toGSQS

GSQG VvKR

vV

2toGSQSGSQG VvKRvV KRU S

021 22 GtoGSQtoGSQ VUVvUVUv



vG

SQ b

y Mu

PA

D



One-Supply Bias Circuit

Discarding the Negative Root find

Then Find iDQ by subbing vGSQ from above into the gate KVL Eqn:

U

VVUUVv toGtoGSQ 2

1412

S

GSQGDQ R

vVi



One-Supply Bias Circuit Solving the last two

eqns yields iDQ and vGSQ • Beware that the

parabolic iD eqn will produce an extraneous root– Discard the

SMALLER root as SAT requires: vGS−Vto ≥ 0

The KVL eqn on cktRight-Side

ReArranging

Then with iDQ from before (MuPAD)

DS

DSDD

DD

iR

viR

V

0

DSDDDDS iRRVv

DQSDDDDSQ iRRVv KiVv DtoGS

Di



Small Signal FET Model At the Operating

Point the quantities are DC, and should be Noted in Upper case letters:

If a small-amplitude ac signal is injected into the circuit the instantaneous quantity Eqns:

Where id and vgs are the small signal quantities

A conceptual Diagram

DQDSQ IV ,Pt-Q

tvVtv

tiIti

gsGSQGS

dDQD



Small Signal FET Model Recall iD in SAT

From last slide

Subbing for iD & vGS

Now the Q-Pt is also in Saturation so,

Using this reln and expanding the IDQ+id eqn yields

Where gm is called the “small signal transconduce” for an nMOSFET

Again for IGFET0gi

tvVtv

tiIti

gsGSQGS

dDQD

2togsGSQdDQ VvVKiI

2toGSQDQ VVKI

gsmgstoGSQd vgvVVKi 2

2toGSD VvKi



Small Signal FET Model

These eqns describe the linear small signal operation in the Saturation region

A graphical representation of the model

0and ggsmd ivgi



gm(Q)

Usually a greater value of gm is better than a smaller one

gm is a function of the Device “K” Parameter and the Q-Pt values

Recall

Also recall at Q-Pt

Or: Thus Simplifying: Recall from our

MOSFET Construction Discussion

• “KP” is singlequantity

toGSQm VVKg 2

2toGSQDQ VVKI

KIVV DQtoGSQ KIKg DQm 2

DQm KIg 2

2

KP

L

WK



gm(Q)

Using And

Find

Simplifying

Thus to increase the transconductance of a KP-fixed MOSFET• Increase IDQ

– Remember, Vswing must be entirely in the SATURATION region

• Increase the W/L ratio– But this makes the

transistor BIGGER; usually NOT desired

DQm KIg 2

2

KP

L

WK

DQm IKP

L

Wg

22

DQm IL

WKPg 2



Refined Small Signal Model The previous model

assumed CONSTANT iD in Saturation

Real MOSFETs exhibit an upward Slope in SAT:

Recall that a SLOPE on a vi Curve is effectively• A Conductance;

G or g• An inverse

Resistance 1/R or 1/r

On a MOSFET this slope is called the “Drain Resistance, rd



Refined Small Signal Model

The KCL Equation for the model that accounts for the upward iD Slope in SAT

The Graphical Representation d

dsgsmd r

vvgi

dsv



gm & rd by Calculus

Start with Refined Model Equation

ReCall

• G & g in Siemens (amps per volt)

Now let the ∆’s approach ZERO to make derivatives

Specifically find the slope of model eqn when vds = 0

Thus gm:

Note that the FET operates at the Q-Pt

ddsgsmd rvvgi

v

ig

V

IG

Δ&

Δdgsmd rvgi 0

m

vgs

d gdv

di

ds

0

0 DSQdsDSQDS VvVv



gm & rd by Calculus

Again use approx:

In the this case vds = 0 implies vDS = VDSQ

so can approximate:

This Eqn is an approximation of a derivation amongst iD, vGS and vDS

• G & g in Siemens (amps per volt)

Now let the ∆’s approach ZERO to make derivatives

Again letting the ∆’s go to zero

Recall

Now in the small-signal eqn let vgs = 0

x

y

dx

dy

DSQDS VvGS

Dm v

ig

Δ

PtQGS

Dm v

ig

i

vr

I

VR

Δ&

Δ

0

0

gsvddsd

ddsmd

rvior

rvgi



gm & rd by Calculus

Solving this Eqn for rd

In this Case

Again use approx:

Thus similar to before

Thus we can write a partial derivative for rd

Or, as stated in the Text Book

0

gsvd

dsd i

vr

0 GSQgsGSQGS VvVv

x

y

dx

dy

GSQGS VvD

DSd i

vr

Δ

PtQDSD

PtQD

DSd vi

i

vr

1

d

PtQDS

D

d

gv

i

r

1



Example 12.3: Find gm & rd

Q-Pt → (VDSQ, IDQ)

= (10 V, 7.4 mA)

Also VGSQ = 3.5 V




Recall approx.

In This Example VDSQ = 10 V

Make a t-Table when vDS = 10V• See vi Graph

Thus • ∆vGS = (4 − 3) V = 1V

• ∆iD = (10.7 − 4.7) mA = 6mA

Then gm:

DSQDS VvGS

Dm v

ig

Δ

VvGS

Dm

DSv

ig

10

Δ

vGS iD

4V 10.7mA3V 4.7mA

mSiemens 6V 1

mA 6mg




Recall approx.

In This Example VGSQ = 3.5 V

Make a t-Table when vGS = 3.5V• See vi Graph

Thus • ∆vDS = (14 − 4) V = 10V

• ∆iD = (8 − 6.7) mA = 1.3mA

Then rd:

k 7.69mA 3.1

V 01dr

GSQGS VvD

DSd i

vr

Δ

VvD

DSd

GSi

vr

5.3

Δ

vDS iD

4V 6.7mA14V 8mA




Q-Pt → (VDSQ, IDQ)

= (10 V, 7.4 mA)

Also VGSQ = 3.5 V

ΔvDS

ΔiD



All Done for Today

Large ScaleResistanceChallenge



All Done for Today

3 & 4Connection

nFET



Bruce Mayer, PERegistered Electrical & Mechanical Engineer

[email protected]

Engineering 43

Appendix



DC Srcs SHORTS in Small-Signal

In the small-signal equivalent circuit DC voltage-sources are represented by SHORT CIRUITS; since their voltage is CONSTANT, the exhibit ZERO INCREMENTAL, or SIGNAL, voltage

Alternative Statement: Since a DC Voltage source has an ac component of current, but NO ac VOLTAGE, the DC Voltage Source is equivalent to a SHORT circuit for ac signals

bruce mayer, pe registered electrical & mechanical engineer bmayer@chabotcollege

Documents

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