bruce mayer, pe licensed electrical & mechanical engineer bmayer@chabotcollege

[email protected] • ENGR-43_Lec-05c_Thevenin_AC_Power.pptx1

Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

Bruce Mayer, PELicensed Electrical & Mechanical Engineer

[email protected]

Engineering 43

Sequential (FlipFlop)

Logic



But First… WhiteBoard Work For the Truth Table

Shown at right• Construct the Karnaugh

Map• Write The Minimized

Function Q(A,B,C,D)• Draw the Logic Circuit

Notice “1’s” in Rows• 1, 5, 9, 13, 14, 15

– Need only put “1’s” in these locations; other cells Assumed to be Zero

Row A B C D Q0 0 0 0 0 01 0 0 0 1 12 0 0 1 0 03 0 0 1 1 04 0 1 0 0 05 0 1 0 1 16 0 1 1 0 07 0 1 1 1 08 1 0 0 0 09 1 0 0 1 110 1 0 1 0 011 1 0 1 1 012 1 1 0 0 013 1 1 0 1 114 1 1 1 0 115 1 1 1 1 1



Blank Map (NonStretching)

AB\CD 00 01 11 10

00

01 1

11

10

AB\CD 00 01 11 10

00 A’B’C’D’ A’B’C’D A’B’CD A’B’CD’

01 A’BC’D’ A’BC’D A’B’CD A’B’CD’

11 ABC’D’ ABC’D ABCD ABCD’

10 AB’C’D’ AB’C’D AB’CD AB’CD’



Stretchable Blank Map

AB\CD 00 01 11 10

00

01

11

10



More… WhiteBoard Work Implement This Function using ONLY

NAND Gates

An Example of NAND-Gate Synthesis• NANDS are easier to construct than

ANDs, ORs, NORs – NANDs are the preferred gate for logic circuits

BADCBADCAF



“Memory Filled” Logic The Invert/AND/OR Combinatorial

Logic Circuits depended ONLY on the Current Inputs; previous states did Not affect the Current State• Combinatorial Logic is MEMORYLESS

In SEQUENTIAL Logic the Circuit Output CAN Depend on the Previous condition of the Circuit• Sequential Logic has MEMORY



Sequential Circuit A sequential circuit

consists of a feedback path, and employs some memory elements

[Sequential circuit] = [Combinational logic] + [Memory Elements]

Combinational logic

Memory elements

Combinational outputs Memory outputs

External inputs



Synchronous vs Asynchronous Almost all Logic “Chips” Include a Clock The Clock helps to “Synchronize” the

Operation of the Circuits. The “Clock” is simply a very regular Hi/Lo

Pulse train Logic Forms are divided into two groups:

• SYNCHRONUS → Depend on Clock• Asynchronous → NO Clock-Dependency



Asynchronous S-R FlipFlop Cross-coupled NOR gates

• Similar to inverter pair, with capability to force Q to 0 (reset=1) or 1 (set=1)

R

S

Q

Q'RS

Q01

0 1

R

S

Q

Q'

10

1 0

R

S

Q

Q'

n-10

0 n-1

R

S

Q

Q'

??1

1 ??



NAND based SR FlipFlop Cross-coupled NAND gates

• Similar to inverter pair, with capability to force Q to 0 (reset=0) or 1 (set=0)

R'S' Q Q

Q'

S'

R'

NOR notes Any HI input → LO output

• Any HI → LO All LO inputs → HI output

• All LO → HI

Any LO input → HI output• Any LO → HI

All HI inputs → LO output• All HI → LO

NAND notes



State Behavior of SR FlipFlop Transition Table

Sequential (output depends on history when inputs R=0, S=0) but asynchronous

R

S

Q

Q'

S R Qn-1 Qn 0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 X1 1 1 X

hold

reset

set

not allowed

characteristic equationQn = S + R’ Q∙ n-1

Qn-1\SR 00 01 11 10

0 0 0 X 1

1 1 0 X 1

SETREset



SR FlipFlop Timing Behavior

Reset Hold Set SetReset Race

R

S

Q

Q’

100

R

S

Q

Q'

“Races” Produce UnPredictable OutPuts

Any HI input → LO output• Any HI → LO

All LO inputs → HI output• All LO → HI



Clocked SR FlipFlop Control times when

R and S inputs matter• Otherwise, the slightest glitch on R or S while

enable is low could cause change in value stored• Ensure R & S stable before utilized (to avoid

transient R=1, S=1)

enable'S' Q'

QR' R

S

Set Reset

S'R'enable'QQ'

100



Clocked SR FlipFlops NOR-NOR

Implementation

TruthTable

• For NOR: any-Hi→LO; ALL-LO→Hi

enable'S' Q'

QR' R

S

R’ S’ En’ R S Qn

0 0 0 1 1 NotAllowed0 1 0 1 0 Reset to 01 0 0 0 1 Set to 11 1 x 0 0 Qn−1

x x 1 0 0 Qn−1

x → Don’t Care



Clocked SR FlipFlops NAND-NOR

Implementation

TruthTable

R S C Qn

0 0 x Qn−1

0 1 1 Set to 11 0 1 Reset to 01 1 1 NotAllowedx x 0 Qn−1

x → Don’t Care

Circuit Symbol



SR FlipFlop Clock-Overide Sometimes Need to Set or Reset the

FlipFlop withOUT Regard to the Clock

Note the position of Pr & Cl on the 3rd-Stage ORs (any Hi→Hi)• Ensures Pr & Cl OverRide R, S, & C



Edge Triggered D FlipFlop sensitive to

inputs only near edge of clock signal (not while steady )

Q

D

Clk=1

R

S0

D’

0

D’ D

Q’

holds D' whenclock goes low

holds D whenclock goes low



Edge-Triggered FlipFlop Flavors POSITIVE edge-triggered

• Inputs sampled on RISING edge; outputs change after RISING edge

NEGATIVE edge-triggered flip-flops• Inputs sampled on falling edge; outputs change

after falling edge

positive edge-triggered FF

negative edge-triggered FF

DCLK

QposQpos'QnegQneg'

100



Edge Triggered D FlipFlop 4-NAND,

1-NOTimplementation

Truth Table for All Postive-GoingEdge D-FF’s• NAND:

– any LO → Hi– All HI → LO

CLK D Qn

0 x Qn−1

1 x Qn−1

↑ 0 0↑ 1 1

http://upload.wikimedia.org/wikipedia/commons/6/69/D-FlipFlop_(4-NAND,_1-NOT).PNG



Edge Triggered JK FlipFlop A “Toggling” Flip Flop

• Under A certain Control-Set: Q → Q’– Notice that Q does NOT go HI-for-sure or

LO-for-sure, and it does NOT remain STEADY

A NAND Nest:• Circuit Symbol



JK FlipFlop Toggle TruthTable The Simplified Ckt

Note that the outputs feed back to the enabling NAND gates. This is what gives the toggling action when J=K=1

ReCall NAND• Any LO → Hi• ALL Hi → LO

C J K Qn Notes0 x x Qn−1 No Chg1 x x Qn−1 No Chg↓ 0 0 Qn−1 No Chg↓ 0 1 0 Reset to 0↓ 1 0 1 Set to 1↓ 1 1 Q’n−1 TOGGLE



Cascading FF → Shift Register Serial-in/Parallel-out Shift register

• New value goes into first stage• While previous value of 1st stg goes into 2nd stg• The QN can be SAMPLED any time

CLK

INQ0 Q1

D Q D Q OUT

IN

Q0

Q1

CLK

100



Example: Eliminate Inconsistency

D Q

D Q

Q0

Clock

Clock

Q1

Async Input

Clocked Synchronous

System

is asynchronous and fans out to D0 and D1

one FF catches the signal, one does not

inconsistent state may be reached!

In

Q0

Q1

CLK

D Q

D Q

Q0

Clock

Clock

Q1

Async Input D Q

Synchronizer

Want to Send SAME

Input Value to

TWO Places



FlipFlops Summarized Development of D-FF

• Level-sensitive used in custom integrated circuits– can be made with 4 pairs of gates– Usually follows multiphase non-overlapping

clock discipline• Edge-triggered used in programmable logic

devices– Good choice for data storage register



FlipFlops Summarized Historically J-K FF was popular but now

never used• Similar to R-S but with 1-1 being used to

toggle output (complement state)• Same Operation Can always be

implemented using D FlipFlops Preset and Clear inputs are highly

desirable on flip-flops• Used at start-up or to reset system to a

known state



FlipFlops Summarized Reset (set state to 0) R

• Synchronous: Dnew = R' • Dold – Transition only when next clock edge arrives

• Asynchronous: doesn't wait for clock, – quick but dangerous

Preset or Set (set state to 1) S• Synchronous: Dnew = Dold + S

– Transition only when next clock edge arrives)• Asynchronous: doesn't wait for clock

– quick but dangerous



WhiteBoard Work Use Gates and a D-

FF to Implement the JK-FF operation

C J K Qn Notes0 x x Qn−1 No Chg1 x x Qn−1 No Chg↓ 0 0 Qn−1 No Chg↓ 0 1 0 Reset to 0↓ 1 0 1 Set to 1↓ 1 1 Q’n−1 TOGGLE



All Done for Today

IEEE91-1984Gates



Bruce Mayer, PELicensed Electrical & Mechanical Engineer

[email protected]

Engineering 43

AppendixLogic Syn



RowA

BC

DQ

00

00

00

10

00

11

20

01

00

30

01

10

40

10

00

50

10

11

60

11

00

70

11

10

81

00

00

91

00

11

101

01

00

111

01

10

121

10

00

131

10

11

141

11

01

151

11

11



NAND Gate Synthesis With the expression in SOP form

1. After any need inversions; In the first logic level there are as many logic gates as terms in the SOP expression

2. Each gate corresponds to a SINGLE Term, and has, as inputs, the variables in that term

3. The outputs of the First Logic-Level are ALL inputs to a SINGLE (multi-input if needed) NAND gate

bruce mayer, pe licensed electrical & mechanical engineer bmayer@chabotcollege

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