broadband gateway processor data...

821xx-DSH-002-GMarch 2008

Comcerto® M821xxBroadband Gateway ProcessorData Sheet

M821xx Data Sheet.

821xx-DSH-002-G Mindspeed Technologies®

Mindspeed Proprietary and Confidential

Revision HistoryRevision Date Description

G March 2008 First release as “Final”. See Section Appendix A: Revision Summary.

F October 2007 First release as “Preliminary”.

E September 2007 Fith release as “Advance Information”.

D March 2007 Fourth release as “Advance Information”.

C December 2006 Third release as “Advance Information”.

B May 2006 Second release as “Advance Information”.

A April 2006 Initial release as “Advance Information”.

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821xx-DSH-002-G Mindspeed Technologies® 3Mindspeed Proprietary and Confidential

Contents

1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

1.1.1 M821xx Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431.1.2 M821xx Feature by Device Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

1.2 Applicable Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441.3 RoHs Advisory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.0 Technical Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462.1 Hardware Application Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.1.1 Reference Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462.1.2 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462.1.3 UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472.1.4 Packet over Sonet (PoS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472.1.5 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472.1.6 HOST Microprocessor (uP) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482.1.7 TDM Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482.1.8 DDR2 SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482.1.9 Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482.1.10 USB PHY Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492.1.11 Inter-IC Bus (I2C) Master/Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492.1.12 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492.1.13 General Purpose IO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502.1.14 UART Serial Interface Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502.1.15 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502.1.16 Internal Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502.1.17 IPSec Security Co-Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.2 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522.3 Software Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

2.3.1 Embedded Host Controller Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532.3.2 Voice Channel Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.0 Applications and Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.2 Comcerto M821xx Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553.3 Comcerto APB Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563.4 Applicable ARM Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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4.0 Pin List and Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584.1 Overview of this Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584.2 Hardware Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594.3 Device to Package Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594.4 Interface Regions — 4-Row Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604.5 Pinout — 4-Row Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614.6 Pin List — 4-Row Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.7 Interface Regions — 6-Row Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754.8 Pinout — 6-Row Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764.9 Pin List — 6-Row Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784.10 Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904.11 I/O PAD Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914.12 Quick Signal Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.12.1 Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924.12.2 DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934.12.3 WAN (Ethernet0) and LAN (Ethernet0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

4.12.3.1 GMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .934.12.3.2 RGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .944.12.3.3 MII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .944.12.3.4 RMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

4.12.4 UTOPIA / PoS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954.12.5 PCI / mP Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974.12.6 TDM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984.12.7 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984.12.8 Universal Asynchronous Receiver Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994.12.9 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994.12.10 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994.12.11 General Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994.12.12 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004.12.13 JTAG Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004.12.14 Test and Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004.12.15 Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.13 Unused Interface Termination Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024.13.1 Unused PCI / mP Bus Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024.13.2 Unused TDM Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044.13.3 Unused JTAG Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044.13.4 Unused I2CTermination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054.13.5 Unused SPI Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054.13.6 Unused UART Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064.13.7 Unused USB Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064.13.8 Unused GPIO Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074.13.9 Unused Timers Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084.13.10 Unused Test and Miscellaneous Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.0 Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.2.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105.2.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105.2.3 Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

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5.3 Clock Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115.3.1 Clock Activation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.3.2 Reset Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.3.3 Functional Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145.3.4 Loop-back Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.3.4.1 PUI Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1145.3.4.2 TDM Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1145.3.4.3 GEMAC Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

5.3.5 Device PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155.3.5.1 ARM and AHB PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1155.3.5.2 USB PHY PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

5.3.6 Rates Generation and Change Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165.3.6.1 ARM and AHB Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1165.3.6.2 Rate Change Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1165.3.6.3 APB Bridge Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1175.3.6.4 USB Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1175.3.6.5 External EPHY Reference Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

5.3.7 Interface Clocks Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185.3.7.1 TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1185.3.7.2 FSYNC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1195.3.7.3 PUI Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1205.3.7.4 PCI Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1215.3.7.5 DDR2 Interface Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1215.3.7.6 Expansion Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

5.4 Reset Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235.4.1 External Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235.4.2 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235.4.3 Global Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235.4.4 Block Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

5.5 Random Number Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6.0 Clock and Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266.2 Clock Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

6.2.1 ARM Clock Control (ARM_CLK_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276.2.2 AHB Clock Control (AHB_CLK_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286.2.3 Clock Dividers Control (CLKDIV_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296.2.4 TDM Clock Control (TDMCLK_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306.2.5 FSync Control (FSYNC_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306.2.6 Clocks Power Down (CLK_PWR_DWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316.2.7 Random Number Control (RNG_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326.2.8 ARM Clk Control 2 (ARM_CLK_CNTRL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336.2.9 PLL Status (PLL_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336.2.10 Random Number Status (RNG_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

6.3 Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356.3.1 Register: Block Reset (BLK_RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356.3.2 CSP Reset (CSP_RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

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7.0 Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377.2 Expansion Bus Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

7.2.1 NAND Flash Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397.2.2 AHB Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.3 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7.4.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1427.4.2 ALE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457.4.3 Strobe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477.4.4 NAND Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

7.5 Examples for Boot Flash Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527.6 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527.8 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527.9 Expansion Interface AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537.10 Notes Regarding Asynchronous Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

8.0 Expansion Bus Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

8.2.1 Expansion Soft-Reset (EX_SW_RST_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568.2.2 Expansion Chip-Select Enable (EX_CS_EN_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578.2.3 Expansion Memory Segment Size (EX_CSx_SEG_R); Where x = 0 – 4 . . . . . . . . . . . . . . . . . . . . . 1578.2.4 Chip Select x Configuration (EX_CSx_CFG_R); Where x = 0 – 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 1588.2.5 Chip Select x Timing Configuration (EX_CSx_TMG1_R); Where x = 0 - 4 . . . . . . . . . . . . . . . . . . . 1598.2.6 Chip Select x Timing Configuration (EX_CSx_TMG2_R); Where x = 0 - 4 . . . . . . . . . . . . . . . . . . . 1608.2.7 Chip Select x Timing Configuration (EX_CSx_TMG3_R); Where x = 0 - 4 . . . . . . . . . . . . . . . . . . . 1608.2.8 Clock Divider Configuration (EX_CLOCK_DIV_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

8.3 Register Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

9.0 DDR2 SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629.1 DDR2 SDRAM Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639.3 DDR2 SDRAM Interface Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639.4 DDR2 SDRAM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

10.0 DDR2 SDRAM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16510.1 Alternative Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16510.2 Changing DDR2 SDRAM Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16610.3 System-Dependent Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

10.3.1 Memory Size Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16710.3.2 DRIVE_DQ_DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16710.3.3 POWER_DOWN, SREFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16710.3.4 CS_MAP, ODT_WR_MAP_CS0, ODT_WR_MAP_CS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16810.3.5 RTT, RTT_PAD_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16910.3.6 CASLAT_LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

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10.3.7 CASLAT_LIN_GATE, INT_ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17010.3.8 INT_MASK, INT_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17010.3.9 REDUC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17110.3.10 Device-Dependent Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17210.3.11 Auto_Refresh_Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17210.3.12 Eight_Bank_Mode, NO_CMD_INT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17210.3.13 WRITEINTERP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17310.3.14 ADDR_PINS, CASLAT, COLUMN_SIZE, TCKE, TEMRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17310.3.15 TPDEX, TRRD, TRTP, TWTR, WRLAT. APREBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17410.3.16 TFAW, TMRD, TRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17410.3.17 TRFC, TCPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17510.3.18 TRAS_MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17510.3.19 TREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17510.3.20 TRAS_MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17510.3.21 TWR_INT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17510.3.22 TRCD_INT, TDLL, TXSNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17610.3.23 TXSR, TINIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

11.0 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17711.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17711.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17711.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

11.3.1 MII Mode Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17811.3.2 RMII Mode Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17811.3.3 GMII Mode Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17911.3.4 RGMII Mode Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

11.4 Ethernet Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18111.5 MDIO Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18311.6 MII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18411.7 RMII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18511.8 GMII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18611.9 RGMII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

12.0 Ethenet Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19012.1 GMAC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.1.1 GEMAC to PHY interface and clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19012.2 HICORE Packet FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.2.1 GEM FIFO Control Register [0xD000] (read/write) default 0x1B . . . . . . . . . . . . . . . . . . . . . . . . . 19212.2.2 TXFHTH [0xD024] (read/write) default 0xC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.3 GigE MAC Configuration, Control, and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19312.3.1 Network Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19412.3.2 Network Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19512.3.3 Network Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19612.3.4 Transmit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19712.3.5 Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19712.3.6 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19812.3.7 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19912.3.8 Interrupt Disable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20012.3.9 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

M821xx Data Sheet


12.3.10 PHY Maintenance Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20212.3.11 Received Pause Quantum Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20312.3.12 Transmit Pause Quantum Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20312.3.13 Hash Bottom [31:0] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20312.3.14 Hash Top [63:32] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20312.3.15 Specific Address 1 Bottom [31:0] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20412.3.16 Specific Address 1 Top [47:32] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20412.3.17 Specific Address 2 Bottom [31:0] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20412.3.18 Specific Address 2 Top [47:32] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20412.3.19 Specific Address 3 Bottom [31:0] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20512.3.20 Specific Address 3 Top [47:32] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20512.3.21 Specific Address 4 Bottom [31:0] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20512.3.22 Specific Address 4 Top [47:32] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20512.3.23 Type ID Match 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20612.3.24 Type ID Match 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20612.3.25 Type ID Match 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20612.3.26 Type ID Match 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20712.3.27 IPG Stretch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20712.3.28 Module ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20712.3.29 Specfic Address Top and Bottom Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

12.3.29.1Specific Address (5 — 32) Bottom [31:0] Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20912.3.29.2Specific Address (5—32) Top [47:32] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

12.3.30 Statistics Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20912.3.31 BytesTransmitted [31:0] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21112.3.32 Bytes Transmitted [47:32] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21112.3.33 Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21212.3.34 Broadcast Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21212.3.35 Multicast Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21212.3.36 Pause Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21212.3.37 64 Byte Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21312.3.38 65 to 127 Byte Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21312.3.39 128 to 255 Byte Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21312.3.40 256 to 511 Byte Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21312.3.41 512 to 1023 Byte Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21412.3.42 1024 to 1518 Byte Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21412.3.43 Greater than 1518 Byte Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21412.3.44 Transmit Under Runs Frames Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21412.3.45 Single Collision Frames Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21512.3.46 Multiple Collision Frames Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21512.3.47 Excessive Collisions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21512.3.48 Late Collisions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21512.3.49 Deferred Tansmission Frames Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21612.3.50 Carrier Sense Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21612.3.51 Bytes Received [31:0] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21612.3.52 Bytes Received [47:32] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21712.3.53 Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21712.3.54 Broadcast Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21712.3.55 Multicast Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21712.3.56 Pause Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21812.3.57 64 Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21812.3.58 65 to 127 Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21812.3.59 128 to 255 Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21812.3.60 256 to 511 Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

M821xx Data Sheet


12.3.61 512 to 1023 Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21912.3.62 1024 to 1518 Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21912.3.63 1519 to Maximum Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21912.3.64 Undersize Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22012.3.65 Oversize Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22012.3.66 Jabbers Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22012.3.67 Frame Check Sequence Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22112.3.68 Length Field Frame Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22112.3.69 Receive Symbol Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22112.3.70 Alignment Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22212.3.71 Receive Overruns Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22212.3.72 IP Header Checksum Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22212.3.73 TCP Checksum Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22312.3.74 UDP Checksum Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

12.4 GEM IF, Tx, Rx, Col and STS FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22312.4.1 GEM Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22412.4.2 TX Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22512.4.3 TX Collision FIFO Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22512.4.4 RX Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22612.4.5 RX Status Pack Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22612.4.6 RX Status FIFO Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22612.4.7 RX Status FIFO Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

12.5 GEM External FIFO Interface Registers (IDMA-Side Control Registers) . . . . . . . . . . . . . . . . 22712.5.1 HCSM FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22712.5.2 HCSM FIFO Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22812.5.3 HCSM FIFO Interrupt Acknowledge Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22812.5.4 RXFF DEPTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22812.5.5 TXFF DEPTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22912.5.6 TXFF HTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22912.5.7 TXFF LTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

12.6 FIFO Threshold Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

13.0 UTOPIA/Packet over Sonet (PoS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23113.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23113.2 UTOPIA / PoS Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23113.3 Multiple-PHY Mode Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

13.3.1 TX Master Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23213.3.2 RX Master Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23213.3.3 Processor Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23313.3.4 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

13.4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23413.4.1 Utopia Interface to PHY Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23513.4.2 Utopia Interface to Link Layer Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23613.4.3 PoS Interface to PHY Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23713.4.4 PoS Interface to Link Layer Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

13.5 UTOPIA ATM-PHY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24013.6 PoS-PHY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24313.7 UTOPIA / PoS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

13.7.1 PUI Timing (PoS and UTOPIA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24713.7.2 UTOPIA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24813.7.3 PoS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

M821xx Data Sheet


14.0 PoS / UTOPIA Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25214.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25214.2 PoS / UTOPIA Interface-Side Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

14.2.1 TX and RX Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25214.2.2 Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25214.2.3 PoS-UTOPIA Interface Side Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

14.3 Interface-Side Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25414.3.1 PUI FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25414.3.2 PUI TX FIFO High Threshold (TXFHTH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25414.3.3 PUI TX FIFO Low Threshold (TXFLTH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25514.3.4 PUI Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25514.3.5 PUI RX FIFO High Threshold (RXFHTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25614.3.6 PUI RX FIFO Low Threshold (RXFLTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25614.3.7 TX Master Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25614.3.8 TX Master Polling Calendar0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25714.3.9 TX Master Polling Calendar1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25814.3.10 TX Master Polling Calendar Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25814.3.11 TX Master Ready Service Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25814.3.12 TX Master Select Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25914.3.13 RX Slave Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25914.3.14 RX Master Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25914.3.15 RX Master Polling Calendar0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26014.3.16 RX Master Polling Calendar1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26014.3.17 RX Master Polling Calendar Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26014.3.18 RX Master Ready Service Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26114.3.19 RX Master Select Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26114.3.20 TX Slave Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26114.3.21 PUI ATM Cell Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26114.3.22 PUI ATM Cell Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26214.3.23 PUI UDMA Pack Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26214.3.24 PUI Frame Max Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26214.3.25 PUI STATUS FIFO Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26314.3.26 PUI STATUS FIFO Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26314.3.27 PUI STATUS FIFO Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26314.3.28 PUI INT Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26414.3.29 PUI INT Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26514.3.30 PUI INT Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

14.4 PoS / UTOPIA IDMA-Side Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26614.5 IDMA-Side Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

14.5.1 HCSM FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26714.5.2 HCSM FIFO Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26714.5.3 HCSM FIFO Interrupt Acknowledge Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26814.5.4 HCSM TX FIFO SIZE (TXFFDEPTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26814.5.5 HCSM TX FIFO High Threshold (TXHTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26814.5.6 HCSM TX FIFO Low Threshold (TXLTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26914.5.7 HCSM RX FIFO Size (RXFF Depth) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26914.5.8 HCSM RX FIFO High Threshold (RXHTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26914.5.9 HCSM RX FIFO Low Threshold (RXLTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

M821xx Data Sheet


15.0 PCI/µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27015.1 PCI/µP Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27015.2 PCI/µP Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27115.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27215.4 PCI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

15.4.1 PCI Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27515.5 PCI DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

15.5.1 Mailbox and FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27715.5.2 Mailbox Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

15.6 PCI – SDRAM Windowing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27915.6.1 PCI Host Memory Bridge (HMB) Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

15.6.1.1 HMB Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28015.6.1.2 HMB Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28115.6.1.3 HMB Interface Registers (Including HICORE Host Side Register) . . . . . . . . . . . . . . . . . . . . . .281

15.7 PCI – AHB Direct Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28215.7.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28215.7.2 APBB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

15.8 PCI Host Mode Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28315.8.1 PCI Host Configuration Programming Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

15.8.1.1 Example 1: Configuration Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28415.8.1.2 Example 2: Configuration Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284

15.8.2 PCI Bus Configuration Registers and Allocation Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28515.8.3 PCI Host Mode Bus Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

15.8.3.1 PCI Arbiter Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28515.8.3.2 PCI Host Mode Arbiter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

15.9 Microprocessor (µP) Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28715.9.1 8-bit, 16-bit, and 32-bit µP Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28715.9.2 mP Bus General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28815.9.3 µP Interface FIFO / Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28915.9.4 Microprocessor Bus Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28915.9.5 mP Bus AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

16.0 PCI/µP Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30016.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30016.2 Mailbox and FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

16.2.1 FIFO Control Register (Address 0x00, R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30316.2.2 FIFO Status Register (Address 0x04, R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30516.2.3 FIFO Interrupt Acknowledge Register (Address 0x04, W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30616.2.4 TX_FIFO Size[15:0] (Address 0x10, R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30716.2.5 TX_FIFO High Threshold[15:0] (Address 0x14, R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30716.2.6 TX_FIFO Low Threshold[15:0] (Address 0x18, R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30716.2.7 RX_FIFO Size[15:0] (Address 0x20, R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30716.2.8 RX_FIFO High Threshold[15:0] (Address 0x24, R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30716.2.9 RX_FIFO Low Threshold[15:0] (Address 0x28, R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30716.2.10 Bus Configuration [7:0] (Address 0x070, R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30816.2.11 RX_FIFO Data[15:0] (Address 0x100-0x7FF, R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30816.2.12 TX_FIFO Data[15:0] (Address 0x100-0x7FF, W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

16.3 PCI Bus Configuration Registers and Allocation Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30916.3.1 PCI Device IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31016.3.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

M821xx Data Sheet


16.3.3 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31016.3.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31016.3.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31116.3.6 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31216.3.7 Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31216.3.8 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31316.3.9 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31316.3.10 Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31316.3.11 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31316.3.12 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31316.3.13 Cap_Ptr Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31316.3.14 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31416.3.15 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31416.3.16 Min Grant Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31416.3.17 Max Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31416.3.18 Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31416.3.19 Next Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31416.3.20 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31416.3.21 PME Polarity Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

16.4 HMB Interface Registers (Including HICORE Host Side Register) . . . . . . . . . . . . . . . . . . . . 31616.4.1 HMB FIFO Interface Registers (ARM Processor Side Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

16.4.1.1 HMB Control Register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31816.4.1.2 Memory BIST Register (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31916.4.1.3 HMB TX FIFO Data Byte Mode – Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31916.4.1.4 HMB RX FIFO DATA Byte Mode – Write only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32016.4.1.5 HMB TX FIFO Data 16 Bit Mode – Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32016.4.1.6 HMB RX FIFO DATA 16 Bit Mode – Write only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32016.4.1.7 HMB TX FIFO Data 32 Bit Mode – Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32016.4.1.8 HMB RX FIFO DATA 32 Bit Mode – Write only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

16.4.2 HBM Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32116.4.3 HMB Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32116.4.4 HMB Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32116.4.5 PCI Base Address1/PCI Base Address2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32216.4.6 System Base Address 1/ System Base Address2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32216.4.7 Size Mask 1 / Size Mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32216.4.8 PCI Arbiter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

16.5 APB Accessible Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32316.5.1 APB TX FIFO Data Byte Mode – Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32416.5.2 APB RX FIFO DATA Byte Mode – Write only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32416.5.3 APB TX FIFO Data 16 Bit Mode – Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32416.5.4 APB RX FIFO DATA 16 Bit Mode – Write only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32516.5.5 APB TX FIFO Data 32 Bit Mode – Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32516.5.6 APB RX FIFO DATA 32 Bit Mode – Write only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32516.5.7 APB FIFO Control Register – Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32516.5.8 APB FIFO Interrupt Status Register – Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32716.5.9 APB FIFO Interrupt Acknowledge Register – Write only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32716.5.10 BIST Status Register – Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32816.5.11 APB TX FIFO Size – Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32816.5.12 APB TX FIFO High Threshold – Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32916.5.13 APB TX FIFO Low Threshold – Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32916.5.14 APB RX FIFO Size – Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32916.5.15 APB RX FIFO High Threshold – Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33016.5.16 APB RX FIFO Low Threshold – Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

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16.5.17 PCI DMA Engine Interface Control Register – Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33116.5.18 PCI DMA Engine Interrupt Status & Bus Status Register - Read only . . . . . . . . . . . . . . . . . . . . . . 33216.5.19 PCI DMA Engine Interface Interrupt Acknowledge Register - Write only . . . . . . . . . . . . . . . . . . . 33316.5.20 PCI TX/RX DMA Starting Address – Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33316.5.21 PCI TX/RX Transfer Burst Size – Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33316.5.22 PCI TX/RX DMA Transfer Length – Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33416.5.23 APBB Interrupt Enable – Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33416.5.24 APBB Interrupt Status – Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33416.5.25 APBB Control – Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

17.0 IPSec Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33617.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33617.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33717.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

17.3.1 Packet Formating and Transformations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33917.3.1.1 Transforms for Tunnel and Transport Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

17.3.2 IPSec Packet Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34017.3.3 Offload Interface Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

17.3.3.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34117.3.4 Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34217.3.5 External Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

17.3.5.1 Security Association Database (SAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34317.3.5.2 Time Based TTL (Time to Live) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34617.3.5.3 Extended Sequence Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34617.3.5.4 Data Descriptor Table (DDT) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

17.4 IPSec Engine Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

18.0 IPSec Engine Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34818.1 Register Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34818.2 ESP/AH Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34818.3 ESP/AH Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

18.3.1 Interrupt Enable (INT_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34918.3.2 Interrupt Status (INT_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35018.3.3 Security Bus Arbiter Request (SEC_REQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35018.3.4 Security Bus Arbiter Grant (SEC_GNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35018.3.5 Security Resource Manager Start (SRM_GO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35118.3.6 Security Resource Manager (SRM_RDY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35118.3.7 Endian Control (ENDIAN_CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35118.3.8 Outgoing Packet Source Pointer (OUT_SRC_PTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35118.3.9 Outgoing Packet Destination Pointer (OUT_DST_PTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35218.3.10 Outgoing Offset (OUT_OFFSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35218.3.11 Outgoing Security Database Pointer (OUT_SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35218.3.12 Outgoing Status (OUT_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35218.3.13 Incoming Packet Source Pointer (IN_SRC_PTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35318.3.14 Incoming Packet Destination Pointer (IN_DST_PTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35318.3.15 Incoming Offset (IN_OFFSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35318.3.16 Incoming Security Database Pointer (IN_SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35318.3.17 Incoming Status (IN_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

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18.4 ESP/AH Access FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35418.4.1 Security Resource Manager Command Registers (SRM_CMD[2:0]) . . . . . . . . . . . . . . . . . . . . . . . 35418.4.2 Security Resource Manager Return Registers (SRM_CMD[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . 35418.4.3 Security Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

18.5 Offload Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35518.6 Offload Interface Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

18.6.1 Interrupt Enable (INT_EN_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35618.6.2 Threshold Configuration (THRSH_CFG_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35618.6.3 Process loop disable configuration (PL_DISABLE_CFG_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

18.7 Offload Interface Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35818.7.1 Event status (EV_STAT_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35818.7.2 Fill level status (FILL_LVL_STAT_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35918.7.3 Process loop disable status (PL_DISABLE_STAT_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

18.8 Offload Interface FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36018.8.1 FIFO holding OUT_SRC_PTR entries (OUT_SRC_PTR_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36018.8.2 FIFO holding OUT_DST_PTR entries (OUT_DST_PTR_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36018.8.3 FIFO holding OUT_SAI entries (OUT_SAI_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36018.8.4 FIFO holding OUT_STAT entries (OUT_STAT_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36118.8.5 FIFO holding IN_SRC_PTR entries (IN_SRC_PTR_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36118.8.6 FIFO holding IN_DST_PTR entries (IN_DST_PTR_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36118.8.7 FIFO holding IN_SAI entries (IN_SAI_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36218.8.8 FIFO holding IN_STAT entries (IN_STAT_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

19.0 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36319.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36319.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36319.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36519.4 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36719.5 Transmit and Receive FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36819.6 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36819.7 Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

19.7.1 Transmit and Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36919.7.2 Transmit Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36919.7.3 Receive Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

19.8 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37019.9 SPI Clock Polarity and Phase Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37419.10Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37619.11SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

20.0 Serial Peripheral Interface (SPI) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37720.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

20.1.1 CTRLR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37920.1.2 CTRLR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38120.1.3 SSIENR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38220.1.4 MWCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38220.1.5 SER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38320.1.6 BAUDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38320.1.7 TXFTLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38420.1.8 RXFTLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

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20.1.9 TXFLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38520.1.10 RXFLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38620.1.11 SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38620.1.12 IMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38720.1.13 ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38820.1.14 RISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38920.1.15 TXOICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

21.0 TDM Bus Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39021.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39021.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39121.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39121.4 TDM Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39221.5 TDM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39721.6 TDM Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39821.7 H.100 TDM Timing Example Using TDM_CK = 2 Cycles per Bit . . . . . . . . . . . . . . . . . . . . . . 398

22.0 TDM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39922.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39922.2 TDM Bus Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

22.2.1 Network Frame Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39922.2.2 Transmitter Operating Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40022.2.3 Transmitter Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40022.2.4 Transmitter Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40022.2.5 Transmitter Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40122.2.6 Transmitter Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40122.2.7 Receiver Operating Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40222.2.8 Receiver Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40222.2.9 Receiver Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40222.2.10 Receiver Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40322.2.11 Receiver Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

22.3 TDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40422.3.1 Memory Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40422.3.2 Rx DMA Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40422.3.3 Tx DMA Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40422.3.4 IRQ2TDMA Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40522.3.5 IRQ2TDMA Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40522.3.6 TDM Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40522.3.7 Interrupt Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40622.3.8 Rx Word Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40622.3.9 Tx Word Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40622.3.10 Backward Compatibility Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40722.3.11 TDM Rx Channel Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40722.3.12 TDM Tx Channel Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40722.3.13 Channel 0 to 127 Receive Base Memory Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40822.3.14 Channel 0 to 127 Transmit Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40922.3.15 Rx Look-up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40922.3.16 Tx Look-up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41022.3.17 Base Address RAM BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41022.3.18 TDM RX Buffer RAM BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

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22.3.19 TDM TX Buffer RAM BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41122.3.20 Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

23.0 Universal Asynchronous Receiver Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . 41323.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41323.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41323.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41423.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41423.5 Register Address Map and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

24.0 Universal Asynchronous Receiver Transmitter (UART) Registers . . . . . . . . . . . . . . 41524.1 Register Address Map and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

24.1.1 Register Bitmap Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41724.1.2 Receive Buffer Register (RBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41724.1.3 Transmit Holding Register (THR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41724.1.4 Divisor Latch High and Low (DLH, DLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41724.1.5 Interrupt Enable Register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41824.1.6 Interrupt Identity Register (IIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41824.1.7 FIFO Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41924.1.8 Line Control Register (LCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41924.1.9 Modem Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41924.1.10 Line Status Register (LSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42024.1.11 Modem Status Register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42124.1.12 Scratchpad Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

25.0 Inter-IC (I2C) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42225.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42225.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42225.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42225.4 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42325.5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42425.6 High Speed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42425.7 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42425.8 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42425.9 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42425.10Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

25.10.1 Master Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42525.10.2 Master Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42725.10.3 Slave Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42825.10.4 Slave Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42925.10.5 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

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26.0 I2C Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43126.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

26.1.1 Resetting the Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43126.1.2 Addr Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

26.1.2.1 7-bit addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43226.1.2.2 10-bit addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .432

26.1.3 XADDR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43226.1.4 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43326.1.5 CNTR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

26.1.5.1 IEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43326.1.5.2 ENAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43326.1.5.3 STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43426.1.5.4 STP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43426.1.5.5 IFLG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43426.1.5.6 AAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .434

26.1.6 STAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43526.1.7 CCRFS and CCRH Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

26.2 High Speed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43826.2.1 Master Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44026.2.2 Slave Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44126.2.3 Slave Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44226.2.4 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

27.0 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44427.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44427.2 USB Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44527.3 USB Design and Layout Requirments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44527.4 Device Operational Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

27.4.1 Device Controller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44627.4.2 Port State and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44727.4.3 Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44827.4.4 Suspend/Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

27.4.4.1 Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .449Suspend Description ............................................................................................................. 449Suspend Operational Model .................................................................................................. 449

27.4.4.2 Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44927.4.5 Managing Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

27.4.5.1 Endpoint Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45027.4.6 Stalling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45127.4.7 Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

27.4.7.1 Data Toggle Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45227.4.7.2 Data Toggle Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .452

27.4.8 Operational Model For Packet Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45227.4.9 Priming Transmit Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

27.4.9.1 Priming Receive Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45327.4.10 Interrupt/Bulk Endpoint Operational Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

27.4.10.1Interrupt/Bulk Endpoint Bus Response Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45527.4.11 Control Endpoint Operation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

27.4.11.1Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .455Setup Packet Handling (Pre-2.3 hardware) ........................................................................... 455Setup Packet Handling (2.3 hardware and later) ................................................................... 456

M821xx Data Sheet


27.4.11.2Data Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45727.4.11.3Status Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45727.4.11.4Control Endpoint Bus Response Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457

27.4.12 Isochronous Endpoint Operational Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45827.4.12.1Isochronous Pipe Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .459

27.4.13 Isochronous Endpoint Bus Response Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46027.4.14 Managing Queue Heads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46027.4.15 Queue Head Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46127.4.16 Operational Model For Setup Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46227.4.17 Managing Transfers with Transfer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

27.4.17.1Software Link Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46327.4.18 Building a Transfer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46327.4.19 Executing A Transfer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46427.4.20 Transfer Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46427.4.21 Flushing/De-priming an Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46527.4.22 Device Error Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46527.4.23 Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

27.4.23.1High-Frequency Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46627.4.23.2Low-Frequency Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46727.4.23.3Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467

27.5 EHCI Deviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46727.5.1 Embedded Transaction Translator Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

27.5.1.1 Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46827.5.1.2 Operational Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46827.5.1.3 Discovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46827.5.1.4 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46927.5.1.5 Operational Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .469

Micro-frame Pipeline ............................................................................................................. 469Split State Machines .............................................................................................................. 470Asynchronous Transaction Scheduling and Buffer Management .......................................... 470Periodic Transaction Scheduling and Buffer Management .................................................... 470

27.5.1.6 USB 2.0 – 11.18.6.[1-2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47027.5.1.7 USB 2.0 – 11.18.[7-8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471

Multiple Transaction Translators ........................................................................................... 47127.5.2 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

27.5.2.1 USBMODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47127.5.2.2 Non-Zero Fields the register file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47127.5.2.3 SOF Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471

27.5.3 Embedded Design Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47227.5.3.1 Frame Adjust Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .472

27.5.4 Miscellaneous variations from EHCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47227.5.4.1 Programmable Physical Interface Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47227.5.4.2 Discovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .472

6.4.2.1 Port Reset ................................................................................................................. 472Port Speed Detection ............................................................................................................ 473

27.5.4.3 Port Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47327.6 Device Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

27.6.1 Endpoint Queue Head (dQH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47527.6.1.1 Endpoint Capabilities/Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47627.6.1.2 Transfer Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477

27.6.2 Current dTD Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47727.6.3 Set-up Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47727.6.4 Endpoint Transfer Descriptor (dTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

M821xx Data Sheet


27.7 USB Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48127.7.1 USB Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48127.7.2 Device Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48127.7.3 Host Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

28.0 USB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48428.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48428.2 Register Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

28.2.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48428.2.2 Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

28.3 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48728.3.1 ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48728.3.2 HWGENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48828.3.3 HWHOST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48928.3.4 HWDEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48928.3.5 HWTXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48928.3.6 HWRXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

28.4 Device/Host Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49028.4.1 CAPLENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49028.4.2 HCIVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49028.4.3 HCSPARAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49128.4.4 HCCPARAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49228.4.5 DCIVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49328.4.6 DCCPARAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

28.5 Device/Host Timer Registers (Non-EHCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49428.5.1 GPTIMER0LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49428.5.2 GBTIMER0CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49428.5.3 GBTIMER1LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49528.5.4 GBTIMER1CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

28.6 Device/Host Operational Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49528.6.1 USBCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49528.6.2 USBSTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49828.6.3 USBINTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50128.6.4 FRINDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50328.6.5 PERIODICLISTBASE; DEVICEADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

28.6.5.1 Host Controller (PERIODICLISTBASE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50428.6.5.2 Device Controller (USB DEVICEADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .504

28.6.6 ASYNCLISTADDR, ENDPOINTLISTADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50528.6.6.1 Host Controller (ASYNCLISTADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50528.6.6.2 Device Controller (ENDPOINTLISTADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .505

28.6.7 TTCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50628.6.8 BURSTSIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50628.6.9 TXFILLTUNUNG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50728.6.10 ENDPTNAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50828.6.11 ENDPTNAKEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50928.6.12 PORTSCx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

28.6.12.1Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50928.6.12.2Device Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .510

28.6.13 USBMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51628.6.14 ENDPTSETUPSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51728.6.15 ENDPTPRIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

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28.6.16 ENDPTFLUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51928.6.17 ENDPTSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51928.6.18 ENDPTCOMPLETE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52028.6.19 ENDPTCTRL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52128.6.20 ENDPTCTRL1 – ENDPTCTRL15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

29.0 General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52629.1 GPIO Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52729.2 General Purpose Boot Option Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52729.3 GPIO Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

30.0 General Purpose I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52930.1 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

30.1.1 GPIO Output Register and GPIO Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53030.1.2 GPIO Interrupt Enable Register (Rising Edge and Falling Edge) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53030.1.3 GPIO Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53030.1.4 APB Bus Access Wait State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53230.1.5 TDM Mux Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53230.1.6 TDM_FS Control and Version ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53330.1.7 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53330.1.8 IO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53430.1.9 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53630.1.10 System Configuration Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53730.1.11 ARM ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53830.1.12 [0x040 R] Bootstrap Pin Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

31.0 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53931.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53931.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

31.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53931.2.2 Interrupt Generation Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

31.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

32.0 Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54232.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54232.2 IRQ Status and Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54332.3 ARM1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54632.4 ARM0 and ARM1 IRQ STATUS0 Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54632.5 ARM0 and ARM1 IRQ Winner Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54832.6 IRQ Self-Clear Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54832.7 FIQ Priority Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54932.8 TDMA Status, Control and Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54932.9 ARM0 and ARM1 IRQ Status0 Vector Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

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33.0 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55233.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55233.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

33.2.1 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55433.2.2 TDM Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55533.2.3 Counting or Driving TIM_EVNT0 and TIM_EVNT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

33.3 Timer Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55633.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

34.0 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

35.0 Test and Debug Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56035.1 Test and Debug Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

35.1.1 JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56035.1.2 Test Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

35.2 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56135.3 Tri-state Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

36.0 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56236.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56236.2 Programmable Stop-Clock Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

36.2.1 Stop-Clock Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56236.2.1.1 Stopping Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56236.2.1.2 Holding Logic Blocks in Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .563

36.2.2 Output Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56436.3 Automatic Stop-Clock Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56536.4 ARM Clock Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

36.4.1 Reducing the Clock Frequency of Both ARM Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56536.4.2 Reducing the Clock Frequency of an ARM Procesor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

36.5 ARM Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56536.6 DDR2 Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

36.6.1 Memory Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56636.6.2 Memory Self-Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

36.7 USB Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

37.0 AHB – APB Bus Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56737.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56737.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56737.3 APB Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56737.4 AHB–APB Bus Bridge Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569

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38.0 I/O DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57038.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57038.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57038.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

38.3.1 I/O Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57238.3.2 I/O DMA Transfers with Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

38.3.2.1 I/O DMA — Ethernet Operating Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .574TX DMA Operation Sequence (Outbound) .............................................................................. 574RX DMA Operation Sequence (Inbound) ................................................................................ 574

38.3.2.2 I/O DMA — Ethernet Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .575Next Field Bit Description ....................................................................................................... 575System Field Bit Description .................................................................................................. 576Frame Status Field Bit Description ......................................................................................... 576Frame Control Field Bit Description (Both directions) ............................................................ 576Buffer Pointer Field Bit Description. ....................................................................................... 577Buffer Control Field Bit Description. ....................................................................................... 577

38.3.3 I/O DMA Transfers with POS/UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57838.3.3.1 I/O DMA — POS/UTOPIA Operating Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .578

Tx DMA Operation Sequence (Outbound) .............................................................................. 578RX DMA Operation Sequence (Inbound) ................................................................................. 579

38.3.3.2 I/O DMA — POS/UTOPIA Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .579Next Field Bit Description ....................................................................................................... 579System Field Bit Description. ................................................................................................. 580Frame Status Field Bit Description ......................................................................................... 580Frame Control Field Bit Description (Both Directions) ............................................................ 580Buffer Pointer Field Bit Description. ....................................................................................... 581Buffer Control Field Bit Description. ....................................................................................... 581

38.3.4 VPI/VCI Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58238.3.4.1 VPI/VCI Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58238.3.4.2 VPI/VCI Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .584

39.0 I/O DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58539.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58539.2 I/O DMA Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58539.3 HDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

39.3.1 HDMA Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58839.3.2 Transmit DMA Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58839.3.3 Receive DMA Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58839.3.4 Transmit Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58939.3.5 Receive Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58939.3.6 Tx Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58939.3.7 Rx Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58939.3.8 Locked Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

39.4 Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59039.4.1 Priority assignment 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59039.4.2 Priority assignment 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59039.4.3 NSEQ Drive Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

39.5 HMDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59139.5.1 Host Mem Bridge: Soft Reset (write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59139.5.2 Host Mem Bridge Locked Transfer Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

39.6 VPI/VCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

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39.6.1 1st VPI/VCI Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59239.6.2 1st Corresponding Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59239.6.3 2nd VPI/VCI Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59239.6.4 2nd Corresponding Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59239.6.5 3rd VPI/VCI Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59339.6.6 4th Corresponding Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59339.6.7 5th VPI/VCI Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59439.6.8 5th Corresponding Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59439.6.9 6th VPI/VCI Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59439.6.10 6th Corresponding Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59439.6.11 7th VPI/VCI Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59539.6.12 7th Corresponding Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59539.6.13 8th VPI/VCI Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59539.6.14 8th Corresponding Value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59539.6.15 Programmable Mask: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59639.6.16 VPI/VCI Enable: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

39.7 GEMAC0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59739.7.1 Mem to GEMAC0 Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59739.7.2 Mem to GEMAC0: Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59739.7.3 Mem to GEMAC0: Locked Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59739.7.4 Mem to GEMAC0: IDMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59839.7.5 Mem to GEMAC0: IRQ Status Register (read transaction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59839.7.6 Mem to GEMAC0: IRQ Clear Register (write transaction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59939.7.7 Mem to GEMAC0: Soft Reset (write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59939.7.8 GEMAC0 to Mem: Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59939.7.9 GEMAC0 to Mem: Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60039.7.10 GEMAC0 to Mem: Locked Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60039.7.11 GEMAC0 to Mem: IDMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60139.7.12 GEMAC0 to Mem: IRQ Status Register (read transaction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60139.7.13 GEMAC0 to Mem: IRQ Clear (write transaction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60239.7.14 GEMAC0 to Mem: Soft Reset (write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

39.8 PU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60239.9 GMAC1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

40.0 Memory DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60340.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60340.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60340.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

40.3.1 CRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60440.3.2 Data Scattering And Gathering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

40.3.2.1 Memory To Memory DMA Operation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .605Read Memory DMA ................................................................................................................ 605Write Memory DMA ............................................................................................................... 605

40.3.2.2 Memory To Memory DMA Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606Frame and Buffer Descriptors - Memory to FIFO (Outbound) ................................................. 606Frame and Buffer Descriptors - FIFO to Memory (Inbound) ................................................... 608

M821xx Data Sheet


41.0 Memory DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61041.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61041.2 MDMA Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61041.3 MDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

41.3.1 MDMA NSEQ Drive Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61141.3.2 Mem to FIFO: Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61141.3.3 Mem to FIFO: Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61141.3.4 Mem to FIFO: Locked Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61141.3.5 Mem to FIFO: Soft Reset (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61241.3.6 FIFO to Mem: Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61241.3.7 FIFO to Mem: Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61241.3.8 FIFO to Mem: Locked Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61241.3.9 FIFO to Mem: Soft Reset (write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

42.0 Hardware Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61442.1 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

42.1.1 Power Sequencing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61542.1.2 Power Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61542.1.3 Power Down Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

42.2 Power Rail Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61642.3 Reset Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

42.3.1 RESET# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61742.3.2 Latching of Configuration Inputs after Rest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

42.4 Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61942.4.1 Boot Source Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61942.4.2 Boot Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

42.4.2.1 External Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61942.4.2.2 Internal Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .621

43.0 Electrical and Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62243.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62243.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62343.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62443.4 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

43.4.1 LVCMOS Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62543.4.2 SSTL18 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

43.5 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62743.6 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

44.0 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

M821xx Data Sheet


Appendix A Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

Appendix B Device Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

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Figures

Figure 1-1 M821xx Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 1-2 M821xx Voice-Only Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Figure 2-1 Top Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 2-2 S/W Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 3-1 M828xx Convergence Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 3-2 ACP Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 4-1 M821xx Hardware Interface Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Figure 4-2 Interface Regions — 4-Row Package (Top View Looking Through Package) . . . . . . . . . . . . 60Figure 4-3 Interface Regions — 6-Row Package (Top View Looking Through Package) . . . . . . . . . . . . 75Figure 5-1 EPHY Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Figure 5-2 PUICLK Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Figure 5-3 PCI Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Figure 5-4 Expansion Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Figure 7-1 Expansion Bus Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Figure 7-2 Expansion Bus Chip Select Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139Figure 7-3 Normal Mode Timing Diagram (RDY_EN = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144Figure 7-4 Normal Mode Timing Diagram (RDY_EN = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145Figure 7-5 ALE Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147Figure 7-6 Strobe Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149Figure 7-7 NAND Command Latch Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Figure 7-8 NAND Addrss Latch Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151Figure 7-9 NAND Data Latch Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151Figure 7-10 Expansion Bus AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153Figure 9-1 DDR2 Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Figure 9-2 DDR2 Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164Figure 11-1 MDIO Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183Figure 11-2 MII Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184Figure 11-3 RMII Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185Figure 11-4 GMII Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186Figure 11-5 RGMII Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188Figure 13-1 Polling & Selection Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233Figure 13-2 End and Restart of Cell Transmission at Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . 240

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Figure 13-3 Transmission to PHY paused for Three Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240Figure 13-4 Polling Phase and Selection Phase at Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 241Figure 13-5 End and Restart of Cell Transmission at Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . 241Figure 13-6 Unexpected Receipt of Two Back-to-Back Cells from the Same PHY . . . . . . . . . . . . . . . . . 242Figure 13-7 Two Subsequent Cells from the Same PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242Figure 13-8 Single-PHY and Byte Level-Multi-PHY Transmit Logical Timing . . . . . . . . . . . . . . . . . . . . . 243Figure 13-9 Packet-Level Multi-PHY Addressing Transmit Logical Timing . . . . . . . . . . . . . . . . . . . . . . 244Figure 13-10Single PHY Receive Logical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245Figure 13-11Packet Level Multi-PHY Logical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246Figure 13-12UTOPIA Interface Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247Figure 13-13UTOPIA Interface Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248Figure 13-14PoS Interface Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250Figure 15-1 PCI/µP Interface Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271Figure 15-2 PCI Bus Output Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275Figure 15-3 PCI Bus Input Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275Figure 15-4 PCI-DMA Operations Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277Figure 15-5 FIFO / Mailbox Register Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278Figure 15-6 PCI-SDRAM Windowing Operations Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279Figure 15-7 HMB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280Figure 15-8 PCI-SDRAM Windowing Operations Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282Figure 15-9 PCI Host Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284Figure 15-10PCI Host Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285Figure 15-11FIFO Burst Read With No Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289Figure 15-12FIFO Burst Read With Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290Figure 15-13FIFO Burst Write With No Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291Figure 15-14FIFO Burst Write With Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292Figure 15-15Non-Burst Read From FIFO or Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293Figure 15-16Non-Burst Write To FIFO or Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294Figure 15-17Burst Read With HBBLAST# Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295Figure 15-18Microprocessor Bus Synchronous AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 296Figure 15-19Microprocessor Bus Asynchronous AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 298Figure 16-1 FIFO / Mailbox Register Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301Figure 17-1 IPsec Engine Operations Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337Figure 17-2 IPv4 Tranform for Transport Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339Figure 17-3 IPv4 Transform for Tunnel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340Figure 17-4 IDDT Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347Figure 19-1 Block Diagram of SPI block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364Figure 19-2 Hardware/Software Slave Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365Figure 19-3 Example SPI Bus Connection to SLIC Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366Figure 19-4 SPI Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367Figure 19-5 M821xx Configured as Master Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

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Figure 19-6 SPI block Master Transfer Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373Figure 19-7 SPI Serial Format (SCPH = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374Figure 19-8 SPI Serial Format Continuous Transfers (SCPH = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374Figure 19-9 SPI Serial Format (SCPH = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375Figure 19-10SPI Serial Format Continuous Transfer (SCPH = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375Figure 19-11Maximum sclk_out/AHB Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376Figure 21-1 Transmit Timing (FE = 1, CMSX = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392Figure 21-2 Transmit Timing (FE = 0, CMSX = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393Figure 21-3 Received Timing (FE = 1, CMSR = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393Figure 21-4 Received Timing (FE = 0, CMSR = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394Figure 21-5 Transmit Timing (FE = 1, CMSX = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394Figure 21-6 Transmit Timing (FE = 0, CMSX = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395Figure 21-7 Received Timing (FE = 1, CMSR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395Figure 21-8 Received Timing (FE = 0, CMSR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396Figure 21-9 TDM Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397Figure 21-10TDM Loopback Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398Figure 25-1 I2C Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423Figure 25-2 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430Figure 26-1. State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443Figure 27-1 Device Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447Figure 27-2 Endpoint Queue Head Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461Figure 27-3 Software Link Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463Figure 27-4 End Point Queue Head Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474Figure 27-5 End Point Queue Head (dQH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476Figure 27-6 Endpoint Transfer Descriptor (dTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478Figure 27-7 Device Power State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482Figure 27-8 Host Power State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483Figure 31-1 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540Figure 33-1 Timer Top-level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554Figure 33-2 TDM Timer Top Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555Figure 38-1 I/O DMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571Figure 38-2 DMA Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573Figure 38-3 VPI/VCI Comparison Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583Figure 40-1 Memory DMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604Figure 42-1 S/W Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614Figure 42-2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617Figure 43-1 Reference Clock Waveform Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

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Tables

Table 1-1 Features by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 3-1 APB Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Table 4-1 Device to Package Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Table 4-2 M821xx Pins — 4-Row Package (Top View – Left Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Table 4-3 M821xx Pins — 4-Row Package (Top View – Right Side) . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 4-4 Pin List — 4-Row — M82104, M82108, M82152, M82154, M82170, M82172, M82174. . 63Table 4-5 M821xx Pins — 6-Row Package (Top View – Left Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Table 4-6 M821xx Pins — 6-Row Package (Top View – Right Side) . . . . . . . . . . . . . . . . . . . . . . . . . . 77Table 4-7 Pin List — 6-Row — M82190, M82192, M82194. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Table 4-8 I/O Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Table 4-9 Expansion Bus Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Table 4-10 DDR SDRAM Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 4-11 GMII Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 4-12 RGMII Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Table 4-13 MII Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Table 4-14 RMII Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Table 4-15 UTOPIA / PoS Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Table 4-16 PCI / mP Bus Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Table 4-17 TDM Bus Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Table 4-18 SPI Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Table 4-19 UART Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Table 4-20 I2C Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Table 4-21 USB Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Table 4-22 GPIO Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Table 4-23 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Table 4-24 JTAG Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Table 4-25 Test and Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Table 4-26 Power and Ground Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Table 4-27 Unused PCI or uP Bus Interface Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Table 4-28 Unused TDM Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Table 4-29 Unused JTAGTermination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Table 4-30 Unused I2C Interface Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Table 4-31 Unused PCI or uP Bus Interface Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Table 4-32 Unused UART Interface Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Table 4-33 Unused USB Bus Interface Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Table 4-34 Unused GPIO Interface Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Table 4-35 Unused PCI or uP Bus Interface Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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Table 4-36 Unused PCI or uP Bus Interface Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Table 5-1 M821xx Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Table 5-2 821xx PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Table 5-3 Needed Configuration Value for Each TDM Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118Table 5-4 Number of TDM Clocks versus Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Table 6-1 Offload Register Interface Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Table 6-2 Fields of ARM Clock Control (ARM_CLK_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127Table 6-3 Fields of AHB Clock Control (AHB_CLK_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Table 6-4 Fields of Clock Dividers Control (CLKDIV_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129Table 6-5 Fields of TDM Clock Control (TDMCLK_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Table 6-6 Fields of FSync Control (FSYNC_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Table 6-7 Fields of Clocks Power Down (CLK_PWR_DWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Table 6-8 Fields of Rndm Nbr Control (RNG_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132Table 6-9 Fields of ARM Clk Control 2 (ARM_CNTRL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Table 6-10 Fields of PLL Status (PLL_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Table 6-11 Fields of Rndm Nbr Status (RNG_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Table 6-12 Offload Register Interface Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Table 6-13 Fields of Block Reset (BLK_RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Table 6-14 Fields of CSP Reset (CSP_RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Table 7-1 Expansion Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140Table 7-2 Normal Mode Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143Table 7-3 ALE Mode Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Table 7-4 Command Strobe Mode Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148Table 7-5 NAND Mode Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Table 7-6 AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153Table 8-1 Register Map for Expansion Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Table 8-2 Fields of Expansion Soft-Reset (EX_SW_RST_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156Table 8-3 Fields of Chip Select Enable (EX_CS_EN_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157Table 8-4 Fields of Memory Segment Size Control (EX_CSx_SEG_R) . . . . . . . . . . . . . . . . . . . . . . . 157Table 8-5 Fields of Chip Select Control (EX_CSx_CFG_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158Table 8-6 Fields of Chip Select Control (EX_CSx_TMG1_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159Table 8-7 Fields of Chip Select Control (EX_CSx_TMG2_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160Table 8-8 Fields of Segment Size Control (EX_CSx_TMG3_R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160Table 8-9 Fields of Chip Select Control (EX_CLOCK_DIV_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Table 8-10 Register Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Table 9-1 DDR2 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Table 9-2 DDR2 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164Table 10-1 Alternative Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165Table 10-2 Memory Size Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167Table 11-1 Features by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177Table 11-2 MII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178Table 11-3 RMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178Table 11-4 GMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179Table 11-5 RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180Table 11-6 Ethernet0 (WAN) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181Table 11-7 Ethernet1 (LAN) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182Table 11-8 MDIO Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

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Table 11-9 MII Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184Table 11-10 RMII Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185Table 11-11 GMII Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186Table 11-12 RGMII Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188Table 12-5 GEMAC Conifg, Control and Status Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193Table 12-6 Network Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194Table 12-7 Network Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195Table 12-8 Network Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Table 12-9 Transmit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197Table 12-10 Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197Table 12-11 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198Table 12-12 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199Table 12-13 Interrupt Disable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200Table 12-14 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201Table 12-15 PHY Maintenance Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202Table 12-16 Received Pause Quantum Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203Table 12-17 Transmit Pause Quantum Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203Table 12-18 Hash Bottom Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203Table 12-19 Hash Top Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203Table 12-20 Specific Address 1 Bottom Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204Table 12-21 Specific Address 1 Top Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204Table 12-22 Specific Address 2 Bottom Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204Table 12-23 Specific Addres 2 Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204Table 12-24 Specific Address 3 Bottom Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205Table 12-25 Specific Address 3 Top Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205Table 12-26 Specific Address 4 Bottom Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205Table 12-27 Specific Address 4 Top Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205Table 12-28 Type ID Match 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206Table 12-29 Type ID Match 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206Table 12-30 Type ID Match 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206Table 12-31 Type ID Match 4 Registeer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Table 12-32 IPG Stretch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Table 12-33 Module ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Table 12-34 Specific Address Top and Bottom Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Table 12-35 Specific Address Bottom Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209Table 12-36 Specific Address Top Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209Table 12-37 Statistics Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210Table 12-38 Bytes Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211Table 12-39 Bytes Tramsmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211Table 12-40 Frmaes Tramsmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212Table 12-41 Broadcast Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212Table 12-42 Multicast Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212Table 12-43 Pause Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212Table 12-44 64 Byte Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213Table 12-45 65 to 127 Byte Frames Tramsmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213Table 12-46 128 to 255 Byte Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213Table 12-47 256 to 511 Byte Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

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Table 12-48 512 to 1023 Byte Frames Tranmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214Table 12-49 1024 to 1518 Byte Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214Table 12-50 Greater than 1518 Byte Frames Transmitted Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214Table 12-51 Transmit Under Runs Frames Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214Table 12-52 Singe Collision Frames Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215Table 12-53 Multipe Collision Frames Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215Table 12-54 Excessive Collisions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215Table 12-55 Late Collisions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215Table 12-56 Deferred Transmission Frames Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216Table 12-57 Carrier Sense Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216Table 12-58 Bytes Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216Table 12-59 Bytes Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217Table 12-60 Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217Table 12-61 Broadcast Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217Table 12-62 Multicast Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217Table 12-63 Pause Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218Table 12-64 64 Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218Table 12-65 65 to 127 Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218Table 12-66 128 to 255 Bytes Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218Table 12-67 256 to 511 Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219Table 12-68 512 to 1023 Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219Table 12-69 1024 to 1518 Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219Table 12-70 1519 to Maximum Byte Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219Table 12-71 Undersixe Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220Table 12-72 Oversize Frames Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220Table 12-73 Jabber Received Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220Table 12-74 Frame Check Sequence Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221Table 12-75 Length Field Frame Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221Table 12-76 Receive Symbol Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221Table 12-77 Alignment Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222Table 12-78 Receive Overruns Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222Table 12-79 IP Header Checksum Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222Table 12-80 TCP Checksum Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223Table 12-81 UDP Checksum Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223Table 12-82 GEM IF, Tx, Rx, Col and STS FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223Table 12-83 GEM Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224Table 12-84 TX Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225Table 12-85 TX Collission FIFO Depth Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225Table 12-86 RX Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226Table 12-87 RX Status Pack Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226Table 12-88 RX Status FIFO Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226Table 12-89 RX Staus FIFO Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226Table 12-90 GEM External FIFO Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227Table 12-91 HCSM FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227Table 12-92 HCSM FIFO Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228Table 12-93 HCSM FIFO Interrupt Acknowledge Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228Table 12-94 RXFF Depth Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

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Table 12-95 TXFF DEPTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229Table 12-96 TXFF HTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229Table 12-97 TXFF LTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229Table 13-1 UTOPIA Level 2 Modes Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232Table 13-2 PoS Level 2 Modes Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232Table 13-3 M8219x UTOPIA/POS Signal Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234Table 13-4 UTOPIA TX ATM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235Table 13-5 UTOPIA RX ATM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235Table 13-6 UTOPIA RX PHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236Table 13-7 UTOPIA TX PHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236Table 13-8 PoS TX Link Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Table 13-9 PoS RX Link Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Table 13-10 PoS RX PHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238Table 13-11 PoS TX PHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239Table 13-12 PUI Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247Table 13-13 UTOPIA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249Table 13-14 PUI Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250Table 14-1 M8219x UTOPIA/PoS Signal Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252Table 14-2 Register Map for Interface-Side Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253Table 14-3 PUI FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254Table 14-4 PUI TX FIFO High Theshold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254Table 14-5 PUI TX FIFO Low Threshold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255Table 14-6 PUI Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255Table 14-7 PUI RX FIFO High Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256Table 14-8 PUI RX FIFO Low Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256Table 14-9 TX Master Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256Table 14-10 TX Master Polling Calendat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257Table 14-11 TX Master Polling Calendar1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258Table 14-12 TX Master Polling Cakendar Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258Table 14-13 TX Master Ready Service Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258Table 14-14 TX Master Select Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259Table 14-15 RX Slave Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259Table 14-16 RX Master Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259Table 14-17 RX Master Polling Calendar0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260Table 14-18 RX Master Polling Calendar1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260Table 14-19 RX Master Polling Calendar Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260Table 14-20 RX Master Ready Service Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261Table 14-21 RX Master Select Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261Table 14-22 TX Slave Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261Table 14-23 PUI ATM Cell Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261Table 14-24 PUI ATM Cell Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262Table 14-25 PUI UDMA Pack Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262Table 14-26 PUI Frame Max Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262Table 14-27 PUI Status FIFO Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263Table 14-28 PUI Status FIFO Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263Table 14-29 PUI Status FIFO Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263Table 14-30 PUI INT Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

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Table 14-31 PUI INT Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265Table 14-32 PUI INT Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265Table 14-33 Register Map for Processor-Side Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266Table 14-34 HCSM FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267Table 14-35 HCSM FIFO Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267Table 14-36 USCM FIFO Inerrupt Acknowledge Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268Table 14-37 HCSM TX FIFO Size (TXFFDEPTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268Table 14-38 HCSM TX FIFO HIgh Threshold (TXHTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268Table 14-39 HCSM TX FIFO Low Threshold (TXLTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269Table 14-40 HCSM RX FIFO Size (RXFF Depth) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269Table 14-41 HCSM RX FIFO High Threshold (RXHTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269Table 14-42 HSXM RX FIFO Low Threshold (RXLTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269Table 15-1 PCI/mProcessor Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272Table 15-2 PCI Bus Input and Output Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276Table 15-3 Microprocessor Bus Connection to Host Processor Bus . . . . . . . . . . . . . . . . . . . . . . . . . . 287Table 15-4 Microprocessor Bus Synchronous AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 297Table 15-5 Microprocessor Bus Asynchronous AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . 298Table 16-1 Mailbox and FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302Table 16-2 FIFO Control Register [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303Table 16-3 FIFO Control Register [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303Table 16-4 FIFO Control Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303Table 16-5 FIFO Status Register [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305Table 16-6 FIFO Status Register [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305Table 16-7 FIFO Status Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305Table 16-8 FIFO Interrupt Acknowledge Register [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306Table 16-9 FIFO Interrupt Acknowledge Register [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306Table 16-10 FIFO Interrupt Acknowledge Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 306Table 16-11 Bus Configuration [7:0] Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308Table 16-12 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309Table 16-13 PCI Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310Table 16-14 Command Register [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310Table 16-15 Command Register [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310Table 16-16 Command register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311Table 16-17 Status Register [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311Table 16-18 Status Register [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311Table 16-19 Status Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312Table 16-20 PME Polarity Control Register [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315Table 16-21 PME Polarity Control Register [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315Table 16-22 HMB Interface Registers (Including HICORE Host Side Register) . . . . . . . . . . . . . . . . . . . 316Table 16-23 HMB Controll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318Table 16-24 Memory BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319Table 16-25 HMB TX FIFO Data Byte Mode - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319Table 16-26 HMB RX FIFO Data Byte Mode - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320Table 16-27 HMB TX FIFO Data 16 Bit Mode - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320Table 16-28 HMB RX FIFO Data 16 Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320Table 16-29 HMB TX FIFO Data 32 Bit Mode - Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320Table 16-30 HMB RX FIFO Data 32 Bit Mode - Write Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

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Table 16-31 HMB Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321Table 16-32 HMB Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321Table 16-33 HMB Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321Table 16-34 PCI Base Address1/PCI Base Address2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322Table 16-35 System Base Address1/System Base Address2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322Table 16-36 Size Mask1/Size Mask2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322Table 16-37 PCI Arbiter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322Table 16-38 APB Accessible Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323Table 16-39 APB TX FIFO Data Byte Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324Table 16-40 APB RX FIFO Data Byte Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324Table 16-41 APB TX FIFI Data 16 Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324Table 16-42 APB RX FIFO DATA 16 Bit ode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325Table 16-43 APB TX FIFO DATA 32 Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325Table 16-44 APB RX FIFO DATA 32 Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325Table 16-45 APB FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326Table 16-46 APB FIFO Interrupt Status Regiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327Table 16-47 APB FIFO Interrupt Acknowledge Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327Table 16-48 BIST Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328Table 16-49 APB TX FIFO Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328Table 16-50 APB TX FIFO High Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329Table 16-51 APB TX FIF Low Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329Table 16-52 APB RX FIFO Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329Table 16-53 APB RX FIFO High Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330Table 16-54 APB RX FIFO Low Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330Table 16-55 PCI DMA Engine Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331Table 16-56 PCI DMAEngine Interrupt Status & Bus Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 332Table 16-57 PCI DMA Engine Interface Interrupt Acknowledge Register . . . . . . . . . . . . . . . . . . . . . . . . 333Table 16-58 PCI TX/RX DMA Starting Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333Table 16-59 PCI TX/RX Transfer Burst Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333Table 16-60 PCI TX/RX DMA Transfer Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334Table 16-61 APBB Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334Table 16-62 APBB Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334Table 16-63 APBB Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335Table 17-1 Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342Table 17-2 Security Association Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343Table 18-1 ESP/AH Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348Table 18-2 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349Table 18-3 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350Table 18-4 Security Bus Arbiter Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350Table 18-5 Security Bus Arbiter Grant Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350Table 18-6 Security Resource Manager Start Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351Table 18-7 Security Resource Manager Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351Table 18-8 Endisn Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351Table 18-9 Outgoing Packet Source Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351Table 18-10 Outgoing Packet Destination Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352Table 18-11 Outgoing Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352Table 18-12 Outgoing Security Database Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

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Table 18-13 Outgoing Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352Table 18-14 Incoming Packet Source Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353Table 18-15 Incoming Packet Destination Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353Table 18-16 Incoming Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353Table 18-17 Incoming Security Database Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353Table 18-18 Incoming Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354Table 18-19 Security Resource Manager Command Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354Table 18-20 Security Resource Manager Return Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354Table 18-21 Security Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355Table 18-22 Offload Register Interface Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355Table 18-23 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356Table 18-24 Threshold Configutration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356Table 18-25 Process Loop Disable Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357Table 18-26 Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358Table 18-27 Fill Level Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359Table 18-28 Process Loop Disable Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359Table 18-29 FIFO holding OUT_SRC_PTR entries Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360Table 18-30 FIFO holding OUT_DST_PTR entries Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360Table 18-31 FIFO holding OUT_SAI entries Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360Table 18-32 FIFO holding OUT_STAT entries Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361Table 18-33 FIFO holding IN_SRC_PTR entries Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361Table 18-34 FIFO holding IN_DST_PTR enteries Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361Table 18-35 FIFO holding IN_SAI entries (IN_SAI_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362Table 18-36 FIFO holding IN_STAT entries (IN_STAT_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362Table 19-1 M821xx SPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365Table 19-2 SPI Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367Table 20-1 Memory Map of SPI block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377Table 20-2 Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379Table 20-3 DFS Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380Table 20-4 Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381Table 20-5 SSIENR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382Table 20-6 MWCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382Table 20-7 Slave Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383Table 20-8 Baud Rate Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383Table 20-9 Transmit FIFO Threshold Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384Table 20-10 TXFTLR Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384Table 20-11 Receive FIFO Threshold Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385Table 20-12 RXFTLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385Table 20-13 Transmit FIFO Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385Table 20-14 Receive FIFO Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386Table 20-15 SSI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386Table 20-16 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387Table 20-17 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388Table 20-18 Raw Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389Table 20-19 Transmit FIFO Overflow Interrupt Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389Table 21-1 M821xx TDM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391Table 21-2 TDM Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

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Table 21-3 TDM Loopback Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398Table 22-1 Network Frame Parameter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399Table 22-2 Transmitter Operating Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400Table 22-3 Transmitter Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400Table 22-4 Transmitter Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400Table 22-5 Transmitter Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401Table 22-6 Transmitter Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401Table 22-7 Receiver Operating Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402Table 22-8 Receiver Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402Table 22-9 Receiver Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402Table 22-10 Receiver Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403Table 22-11 Receiver Active Slot Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403Table 22-12 Memory Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404Table 22-13 Rx DMA Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404Table 22-14 Tx DMA Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404Table 22-16 IRQ2TDMA Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405Table 22-17 TDM Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405Table 22-18 Interrupt Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406Table 22-19 Rx Word Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406Table 22-20 Tx Word Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406Table 22-21 Backward Compatibility Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407Table 22-22 TDM Rx Channel Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407Table 22-23 TDM Tx Channel Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407Table 22-24 Channel 0 to 127 Receive Base Memory Address Registers . . . . . . . . . . . . . . . . . . . . . . . . 408Table 22-25 Transmit Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409Table 22-26 Rx Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409Table 22-27 Tx Look-up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410Table 22-28 Base Address RAM BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410Table 22-29 RDM RX Buffer RAM BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411Table 22-30 TDM TX Buffer RAM BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411Table 22-31 Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412Table 23-1 M821xx UART Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414Table 24-1 Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415Table 24-2 UART 0 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416Table 24-3 UART 1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416Table 24-4 Interrupt Identity Register IIR Bit Map Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418Table 25-1 M821xx SPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422Table 25-2 I2C Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423Table 25-3 STAT Register Contents 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425Table 25-4 STAT Register Contents 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426Table 25-5 STAT Register Contents 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426Table 25-6 STAT Register Contents 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427Table 25-7 STAT Register Contents 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428Table 25-8 State Diagram Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430Table 26-1 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431Table 26-2 ADDR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432Table 26-3 XADDR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

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Table 26-4 CNTR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433Table 26-5 TSTAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436Table 26-6 CCRFS and CCRH Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437Table 26-7 STAT Register Contents 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439Table 26-8 STAT Register Contents 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439Table 26-9 STAT Register Contents 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440Table 26-10 STAT Register Contents 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441Table 26-11 State Diagram Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443Table 27-1 USB Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445Table 27-2 Device Controller State Information Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447Table 27-3 Device Controller Endpoint Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450Table 27-4 Device Controller Stall Response Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451Table 27-5 Variable Length Transfer Protocol (ZLT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454Table 27-6 Variable Length Transfer Protocol (ZLT = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454Table 27-7 Interrupt/Bulk Endpoint Bus Response Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455Table 27-8 Control Endpoint Bus Response Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457Table 27-9 Isochronous Encpoint Bus Response Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460Table 27-10 Device Error Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465Table 27-11 Error Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466Table 27-12 Execution Interrupt Action Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466Table 27-13 USBMODE— USB Device Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476Table 27-14 Next dTD Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477Table 27-15 Multiple Mode Control (HCCPARAMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478Table 27-16 Next dTD Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478Table 27-17 dTD Tolken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479Table 27-18 dTD Buffer Page Pointer List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480Table 28-1 Memory DMA Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485Table 28-2 ID — Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487Table 28-3 HWGENERAL — General Hardware Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488Table 28-4 HWHOST — Hardware Host Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489Table 28-5 HWDEVICE — Device Hardware Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489Table 28-6 ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489Table 28-7 ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490Table 28-8 CAPLENGTH — Capability Register Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490Table 28-9 HCIVERSION — Host Interface Version Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490Table 28-10 IHCSPARAMS — Host Control Structural Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491Table 28-11 HCCPARAMS — Host Control Capability Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492Table 28-12 DCIVERSION — Device Interface Version Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493Table 28-13 DCIVERSION — Device Control Capability Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 493Table 28-14 GPTIMER0LD — General Purpose Timer #0 Load Register . . . . . . . . . . . . . . . . . . . . . . . . 494Table 28-15 GPTIMER0CTRL — General Purpose Timer #0 Control Register . . . . . . . . . . . . . . . . . . . . 494Table 28-16 USBCMD — USB Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495Table 28-17 USBSTS — USB Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498Table 28-18 USBINT — USB Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501Table 28-19 FRINDEX— USB Frame Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503Table 28-20 DEVICEADDR – Device Controller USB Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 504Table 28-21 ASYNCLISTADDR — Host Controller Next Asyn Address . . . . . . . . . . . . . . . . . . . . . . . . . 505

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Table 28-22 ENDPOINTLISTADDR— Device Controller Endpoint List Address . . . . . . . . . . . . . . . . . . . 505Table 28-23 TTCTRL— Host Controller Embedded TT Async Buffer Status . . . . . . . . . . . . . . . . . . . . . . 506Table 28-24 BURSTSIZE— Bust Size Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506Table 28-25 TXFILLTUNNING — Transmit Buffer Fill Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507Table 28-26 ENDPTNAK — Endpoint NAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508Table 28-27 ENDPTNAKEN— Endpoint NAK Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509Table 28-28 PORTSCx — Port Status Control[1:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510Table 28-29 USBMODE— USB Device Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516Table 28-30 ENDPOINTSETUPSTAT— Endpoint Setup Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517Table 28-31 ENDPTPRIME— Endpoint Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518Table 28-32 ENDPTFLUSH— Endpoint De-Initialize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519Table 28-33 ENDPTSTAT— Endpoint Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519Table 28-34 ENDPTCOMPLETE— Endpoint Complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520Table 28-35 ENDPTCTRL0— Endpoint Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521Table 28-36 ENDPTCTRL1 – ENDPTCTRL15 — Endpoint Control 1 – Endpoint Control 15 . . . . . . . . . 523Table 29-1 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526Table 30-1 Description of Control Registers and Associated Offset Values . . . . . . . . . . . . . . . . . . . . . 529Table 30-2 GPIO Input Register: Bit Number, SIgnal Name, and Description . . . . . . . . . . . . . . . . . . . . 530Table 30-3 APB Bus Access Wait State Register Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532Table 30-4 TDM Mux Control Register Field Definitons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532Table 30-5 TDM_FS Control and Version ID Register Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . 533Table 30-6 Lock Register Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533Table 30-7 IO Control Register Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534Table 30-8 General Control Register Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536Table 30-9 System Configuration Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537Table 30-10 ARM ID Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538Table 30-11 Bootstrap Pin Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538Table 32-1 Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542Table 32-2 IRQ STATUS_0, IRQ_MASK_0, and FIQ MASK_0 Register Bit Definition . . . . . . . . . . . . . . 543Table 32-3 IRQ STATUS_1, IRQ_MASK_1, and FIQ MASK_1 Register Bit Definition . . . . . . . . . . . . . . 545Table 32-4 ARM1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546Table 32-5 ARM0 and ARM1 IRQ STATUS0 Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547Table 32-6 ARM0 and ARM1 IRQ Winner Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548Table 32-7 IRQ Self-Clear Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548Table 32-8 IFIQ Priority Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549Table 32-9 TDMA Status and Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549Table 33-1 TIM_EVNT0 Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555Table 33-2 TIM_EVNT1 Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556Table 33-3 Timer Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556Table 34-1 Timer Block Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557Table 35-1 JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560Table 35-2 Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561Table 36-1 Clocks Power Down Bits (CLK_PWR_DWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563Table 36-2 Block Reset (BLK_RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563Table 37-1 APB Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567Table 38-1 Next Field Bit Data Structure Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575Table 38-2 System Field Bit Data Structure Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

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Table 38-3 Memory to GMAC (Outbound) Data Structure Description . . . . . . . . . . . . . . . . . . . . . . . . . 576Table 38-4 GMAC to Memory (Inbouned) Data Structure Descritpion . . . . . . . . . . . . . . . . . . . . . . . . . 576Table 38-5 Frame Control Field Bit Description (Both directions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576Table 38-6 Buffer Pointer Field Bit Data Structure Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577Table 38-7 Memory to GMAC (Outboud) Data Structure Description . . . . . . . . . . . . . . . . . . . . . . . . . . 577Table 38-8 GMAC to Memory Data Structure Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577Table 38-9 Next Field Bit Data Structure Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579Table 38-10 System Field Bit Data Structure Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580Table 38-11 PU to Memory Frame Status Field Bit Data Structure Description . . . . . . . . . . . . . . . . . . . 580Table 38-12 Frame Control Field Bit Data Structure Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580Table 38-13 Buffer Pointer Field Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581Table 38-14 Memory to PU Data Structure Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581Table 38-15 PU to Memory Data Structure Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581Table 38-16 VPI / VCI Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582Table 39-1 I/O DMA Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585Table 39-2 HDMA Soft Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588Table 39-3 Transmit DMA Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588Table 39-4 Receive DMA Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588Table 39-5 Transmit Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589Table 39-6 Receive Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589Table 39-7 Tx Block Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589Table 39-8 Rx Block Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589Table 39-9 Locked Transfer Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590Table 39-10 Priority Assignment Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590Table 39-11 Priority Assignment Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590Table 39-12 NSEQ Drive Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591Table 39-13 Host Mem Bridge: Soft Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591Table 39-14 Host Mem Bridge Locked Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591Table 39-15 VPI/VCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592Table 39-16 1st Corresponding Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592Table 39-17 2nd VPI/VCI Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592Table 39-18 2nd Corresponding Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592Table 39-19 3rd VPI/VCI Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593Table 39-20 3rd Corresponding Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593Table 39-21 4th VPI/VCI Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593Table 39-22 4th Corresponding Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593Table 39-23 5th VPI/VCI Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594Table 39-24 5th Corresponding Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594Table 39-25 6th VPI/VCI Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594Table 39-26 6th Corresponding Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594Table 39-27 7th VPI/VCI Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595Table 39-28 7th Corresponding Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595Table 39-29 8th VPI/VCI Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595Table 39-30 8th Corresponding Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595Table 39-31 Programmable Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596Table 39-32 VPI/VCI Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596Table 39-33 Mem to GEMAC0 Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

M821xx Data Sheet


Table 39-34 Mem to GEMAC0: Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597Table 39-35 Mem to GEMAC0: Locked Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597Table 39-36 Mem to GEMAC0: IDMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598Table 39-37 Mem to GEMAC0: IRQ Status Register (read transaction) . . . . . . . . . . . . . . . . . . . . . . . . . 598Table 39-38 Mem to GEMAC0: IRQ Clear Register (write transaction) . . . . . . . . . . . . . . . . . . . . . . . . . . 599Table 39-39 Mem to GEMAC0: Soft Reset (write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599Table 39-40 GEMAC to Mem: Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599Table 39-41 GEMAC0 to Mem: Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600Table 39-42 GEMAC to Mem; Locked Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600Table 39-43 GEMAC0 to Mem: IDMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601Table 39-44 GEMAC0 to Mem: IRQ Status Register (read transaction) . . . . . . . . . . . . . . . . . . . . . . . . . 601Table 39-45 GEMAC0 to Mem: IRQ Clear (write transaction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602Table 39-46 GEMAC to Mem: Soft Reset (write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602Table 40-1. Frame Next Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606Table 40-2. Frame System (Fsystem) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606Table 40-3. Frame Status (Fstatus) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607Table 40-4. Frame Control (FControl) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607Table 40-5. Buffer Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607Table 40-6. Buffer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608Table 40-7. Frame Next Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608Table 40-8. Frame System (Fsystem) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608Table 40-9. Frame Status (Fstatus) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608Table 40-10. Frame Control (FControl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609Table 40-11. Buffer Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609Table 40-12. Buffer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609Table 41-1 Memory DMA Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610Table 41-2 MDMA NSEQ Drive Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611Table 41-3 Mem to FIFO: Start Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611Table 41-4 Mem to FIFO: Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611Table 41-5 Mem to FIOF: Locked Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611Table 41-6 Mem to FIFO: Soft Reset (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612Table 41-7 FIFO to Mem: Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612Table 41-8 FIFO to Mem: Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612Table 41-9 FIFO to Mem: Locked Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612Table 41-10 FIFO to Mem: Soft Reset (write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613Table 42-1 Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618Table 42-2 Boot Configuration Lands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619Table 43-1 Voltage Requirments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622Table 43-2 Temperature Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622Table 43-3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623Table 43-4 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624Table 43-5 LVCMOS Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625Table 43-6 SSTL2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626Table 43-7 Reference Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

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1.0 Introduction

1.1 SummaryThe M821xx Comcerto®100 series of Integrated Services Platform products provides a new level of integration and performance for Residential Gateway, Small Office / Home Office (SOHO) VoIP router, Small Medium Business (SMB) and enterprise VPN router, and Passive Optical Network (PON) ONT products.

The M821xx supports enterprise-class data routing performance (with NIST Certified security) and has enough bandwidth to support multiple HDTV IPTV streams while guaranteeing up to 4 simultaneous carrier-class VoIP channels.

The M821xx’s performance stems from its unique dual-ARM11 (450MHz each) architecture (see Figure 1-1) which separates the real-time traffic processed on the Media Stream Processor (MSP) from the non-real-time processes on the Applications and Control Processor (ACP).

Figure 1-1 M821xx Device Block Diagram

M821xx Data Sheet


An embedded high-speed bus management system utilizes a Multi-Layer Advanced High Performance Bus for non-blocking data transfer between the high-speed GMII/RGMII (GbE), USB 2.0, PCI, Utopia, TDM physical interfaces and memories.

The following diagram shows a voice-only M821xx application.

1.1.1 M821xx ApplicationsTypical Data/Voice applications include:

• Cable or DSL Broadband Customer Premises Equipment (CPE)

• Small Office / Home Office VoIP Router

• Small Medium Business and Enterprise VPN Router

• Residential Gateway

• Integrated Access Device (IAD)

• Passive Optical Network Single Family Unit (SFU) Optical Network Termination (ONT)

• Passive Optical Network Small Business Unit (SBU) Optical Network Termination (ONT)

• Passive Optical Network Multi-Dwelling Unit (MDU) Optical Network Termination (ONT)

Figure 1-2 M821xx Voice-Only Device Block Diagram

M821xx Data Sheet


1.1.2 M821xx Feature by Device SummaryFor overview of the interfaces described below, refer to Section 2.1 Hardware Application Interfaces.

Table 1-1 Features by Part Number

1.2 Applicable DocumentsDocuments supporting Comcerto 100 devices are available at www.mindspeed.com upon non-disclosure agreement (NDA) and registration.

Feature M82104 M82108 M82152 M82154 M82170 M82172 M82174 M82190 M82192 M82194

Applications Voice Voice Data + Voice

Data + Voice

Data Data + Voice

Data + Voice

Data Data + Voice

Data + Voice

WAN: GMII / RGMII/ MII/ RMII

only MII / RMII

LAN: RGMII / MII / RMII

only MII / RMII

Complex Voice Channels 4 8 2 4 0 2 4 0 2 4

PoS-II / UTOPIA-II

PCI 2.1

2x USB 2.0

Expansion Bus width 16 16 16 16 16 16 16 16 / 32 16 / 32 16 / 32

Temp: 0 — +70 °C

Temp: -40 — +85 °C

NOTE: Registered users are automatically updated when documents are added or updated. To get update notifications, contact your Mindspeed representatives and they will handle registration. An e-mail will arrive indicating the Login ID and pass-word for the Mindspeed website.

M821xx Data Sheet


1.3 RoHs Advisory

For additional guidance on avoiding RoHS-related assembly problems, please refer to:

• IPC-7095B Design and Assembly Process Implementation for BGAs Revision B. April 2007. IPC, www.ipc.org

WARNING: Mixing BGA leaded and unleaded (RoHS) parts on the same electronic assembly can result in reliability and manufacturability problems.

The consensus from the Industry is that mixing Lead and RoHS parts / boards in the same process is not a High Reliability process that can be used for Telecom applications. This is why Mindspeed offers leaded and RoHS options to allow customers to choose one or the other for their manufacturing process. We also must follow our Manufacturing partners recommendations on how to properly use our components in the assembly process.Customers are urged to follow most recent industry recommendations if they have to mix leaded and unleaded (RoHS) components.

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.


2.0 Technical Overview

2.1 Hardware Application InterfacesThe M821xx has the following interfaces:

2.1.1 Reference Clock InterfaceA 24 MHz clock oscillator drives the reference clock interface. The single-clock requirement reduces EMI and system design complexity. For detailed requirements see Section 43.5 Reference Clock on page 627.

2.1.2 Ethernet InterfaceEthernet implementation varies across the M821xx family. All of the devices have at least one Ethernet interface. These interfaces support auto-negotiation, and promiscuous mode operation. RMII supports +2.5V signaling levels while the other Ethernet interfaces support +3.3V signaling levels.

The voice-only M82104 and M82108 devices support only one Ethernet interface (Ethenet0) which can be configured in MII, rMII, GMII, or rGMII modes. All of the data-handling M821xx devices support two Ethernet interfaces.

Both Ethernet interfaces on the M82152 and M82154 devices support only MII and RMII standards. M8217x and M8219x devices support a WAN-oriented Ethernet interface (Ethernet0) and a LAN-ori-ented one (Ethernet1). One port (Ethernet1) supports RMII, RGMII and MII and the other port (Ethernet 0) supports RMII, RGMII, GMII and MII.

For additional information, see Section 11.0 Ethernet Interface on page 177.

NOTE: The Mindspeed Comcerto Device is a multi-core system-on-chip (SOC) device operating above 400 MHz. Appropriate power supply and layout considerations are required to guarantee optimum performance.

Mindspeed provides schematic and layout review. Mindspeed HIGHLY RECOMMENDS customers submit their designs to Mindspeed for a complete and confidential review.

Customer designs MUST meet the Power Supply, Thermal, and Layout considerations described in the:• M821xx Hardware Requirements App Note (821xx-APP-002)

• M821xx Thermal Application Note (821xx-APP-001)

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M821xx Data Sheet


2.1.3 UTOPIA InterfaceM8219x devices support the UTOPIA Level 2 interface.

The ATM physical interface communicates with and controls the ATM link interface chip, which carries out all transmission convergence and physical media dependent functions. It supports:

• UTOPIA L2 Master

• UTOPIA L2 Slave

The UTOPIA L2 Master supports up to 8 ATM PHY devices, while the Slave UTOPIA interface is used to connect to an ATM switching fabric.

The UTOPIA Interface supports 8 and 16 bits of data, and supports frequencies of 25 — 50 MHz.

For additional information, see Section 13.2 UTOPIA / PoS Overview on page 231.

2.1.4 Packet over Sonet (PoS) InterfaceM8219x devices support the PoS Level 2 interface.

The Packet over Sonet (PoS) physical interface communicates with and controls the PoS-PHY layer. It supports:

• PoS L2 Master and

• PoS L2 Slave

The PoS L2 Master supports up to 8 PoS-PHY devices.

The PoS Interface can be configured for a data bus widths of 8 or 16 bits, and it supports a frequencies of 25 — 50 MHz.

For additional information, see Section 13.2 UTOPIA / PoS Overview on page 231.

2.1.5 PCI Bus InterfaceThe 32-bit, 33 MHz, PCI Bus Interface conforms to the PCI Local Bus Specification, Production Version, Revision 2.1. The PCI Bus Interface supports both Host Mode and Peripheral Mode.

In Host Mode, the M821xx can configure and access peripherals on the PCI Bus. The Host Mode includes a Bus Arbiter for multiple masters. A maximum of 3 masters are supported (M821xx + 2 external masters). Host Mode provides a PCI Bridge to allow external PCI bus masters to access 821xx SDRAM. PCI Host Mode can be used to add high bandwidth devices to the system such as Wi-Fi wireless LAN devices.

In Peripheral Mode, the M821xx is a memory slave and a bus master for memory accesses. Configuration is by PCI configuration protocol. For more information, see Section 15.1 PCI/µP Interface Features on page 270.

NOTE: The UTOPIA interface signals are multiplexed with the PoS interface signals.

NOTE: The PoS interface signals are multiplexed with the UTIOPIA interface signals.

NOTE: The PCI interface signals are multiplexed with the Host Microprocessor Interface signals.

M821xx Data Sheet


2.1.6 HOST Microprocessor (uP) InterfaceThe Microprocessor Bus Interface may be used in the External Host Controller configuration. The purpose of the Host Microprocessor Interface is to allow efficient data transfer between the memory within the M821xx device and an external host processor. The Host Microprocessor Interface supports a glue-less connection to Intel or Motorola 8, 16, or 32-bit microprocessor busses. For more information, see Section 15.5 PCI DMA Operation on page 277.

2.1.7 TDM Bus InterfaceThe TDM Bus interface provides one full-duplex, serial time-division multiplexed (TDM) bus providing a maximum of 24/32/64/128 timeslots (running at 1.5444 MHz, 2.048 MHz, 4.096 MHz, or 8.192 MHz, accordingly) for digital data transfer between the Network Interface Device (e.g., T1/E1 Framer, Time Slot Interchanger, etc) and the M821xx.

The TDM Interface timing parameters are programmable, and can be configured for H.100, H110, and H-MVIP bus standards (Also, see section H.100 TDM Timing Example Using TDM_CK = 2 Cycles Per Bit.)

For more information, see Section 21.0 TDM Bus Interface Description on page 390.

2.1.8 DDR2 SDRAM InterfaceThe M821xx devices provide address, data, and control lines for connection to DDR2 Synchronous Dynamic RAM (SDRAM).

The DDR2 Interface includes the following:

• 32-bit or 16-bit data bus interfacing to x8 and x16 memories (x4 not supported).

• Address bus supports up to 1 GByte of memory.

• Support for clock frequencies from 125 MHz to 165 MHz.

• Support for DDR power down.

• Support for 4 cycle bursts length.

• Support for 4 and 8 memory banks.

• 1.8V I/O (SSTL_18 compatible).

For more information, see Section 9.0 DDR2 SDRAM Interface on page 162.

2.1.9 Expansion Bus InterfaceThe M821xx Expansion Bus (EXP_) provides address, data, and control lines for connection to system peripheral devices. The EXP Bus provides Chip Selects for system peripheral devices such as Flash memory, Boot ROM, etc. All M821xx devices support 16 data bits on the Expansion bus. The bus width may vary from 8 to 16 bits per chip select.The M8219x devices are 16/32-bits bus width-capable. For more information, see Section 7.0 Expansion Bus Interface on page 137.

NOTE: The Host Microprocessor Interface signals are multiplexed with the PCI interface signals.

M821xx Data Sheet


2.1.10 USB PHY Host InterfaceExcept for the voice-only M8210x devices, all the M821xx devices provide two USB 2.0 Host/Device Interfaces. Each USB 2.0 PHY Host Interface supports HS (480 Mbps) mode, and is backward compatible with USB1.1.

The controller for each Universal Serial Bus interface handles all of the USB 2.0 protocol and provides a simple Read/Write protocol to the application software. Some of the features of the USB Controller are:

• USB 2.0 compliance

• Low speed (LS, 1.5 Mbps)

• Full speed (FS, 12 Mbps)

• High speed (HS, 480 Mbps)

• Line interface: UTMI+ Level 3

• HUB support

For more information, see Section 27.0 USB Interface on page 444.

2.1.11 Inter-IC Bus (I2C) Master/Slave InterfaceAll of the M821xx devices support I2C and can be configured to load boot code over it. The Inter-IC Bus, or I2C, is a low-bandwidth, short distance protocol for on board communications. All devices are connected through two wires: serial data (SDA) and serial clock (SCL).

All devices must have a unique address to identify it on the bus. Slave devices have a predefined address, but the lower bits of the address can be assigned to allow for multiples of the same devices on the bus.

The I2C Bus supports multiple data speeds: standard (100 kbps), fast (400 kbps) and high speed (3.4 Mbps) communications.

Other features include:

• Built in collision detection,

• Support for 7- and 10-bit addressing,

• Multi-master support,

• Data broadcast (general call).

For more information, see Section 25.0 Inter-IC (I2C) Interface on page 422.

2.1.12 SPI InterfaceA Multi-Chain Serial Peripheral Interface (SPI) provides a common interface mechanism for controlling peripheral devices. For example, SLICs (Subscriber Line Interface Circuits) from multiple vendors can be controlled on the SPI Bus, which is used to setup such parameters as µ-law/a-law PCM conversion, Off-Hook Indication, Ringing Generation, etc. The SPI interface operates at up to 4MHz, master mode. The number of slave select outputs varies among M821xx devices.

All M821xx devices support SPI and can be configured to boot from it.

SPI features include:

• Dedicated hardware slave select lines can be used or software can be used to select the target slave device.

• Software can dynamically control the bit rate of the data transfer.

M821xx Data Sheet


• Independent masking of interrupts: master collision, transmit FIFO overflow, transmit FIFO empty, receive. FIFO full, receive FIFO underflow, and receive FIFO overflow.

• Data frame size (4 to 16 bits): the frame size of each data transfer is under the control of the programmer.

• FIFO depth: The depth of both transmit and receive buffers is fixed at 16 bits. FIFO width is fixed at 16 bits.

For more information, see Section 19.0 Serial Peripheral Interface (SPI) on page 46.

2.1.13 General Purpose IO InterfaceThe M821xx devices provides up to 32 GPIO signals; the exact number varies among devices. The first 8 GPIO lines support interrupts to the Applications and Control Processor (ACP). In addition, M821xx devices allow four Expansion Bus address line inputs to be latched at reset as boot configuration straps.

For details, see Section 29.0 General Purpose I/O on page 526.

2.1.14 UART Serial Interface Port The M821xx devices provide one or two UART interfaces, with FIFOs. Only the Rx and Tx signals are provided which can be connected to an RS232 driver for standard serial port operation. The UART Interfaces provide a useful Console Port and can also be used as a software debug port. It is recommended to connect the UART pins to RS232 drivers and standard connectors (e.g. RJ45, 9-pin DIN, etc.) for easy access.

For more information, see Section 23.0 Universal Asynchronous Receiver Transmitter (UART) on page 413.

2.1.15 JTAG Interface The M821xx provides two JTAG interfaces, one for each ARM core. The JTAG interface provides access to the ARM11 embedded ICE (in-circuit emulation) unit and supports IEEE 1149.1 Boundary Scan for manufacturing and test. The JTAG signals should be routed to a JTAG connector footprint, such as the 3M #2520-6002UB.

For more information, see Section 35.0 Test and Debug Interface Description on page 560.

2.1.16 Internal TimersM821xx devices support real-time systems design with several timing facilities:

• Six 32 bit-wide general purpose timers, each capable of generating an interrupt.Of these, two 32-bit timer/counters are capable of driving external event pins or counting events through those pins.

• Two 16-bit TDM timers driven by TDM frame synch, each capable of generating an interrupt.

• One 32-bit watchdog timer capable of generating an internal reset.

• Several pairs of the general purpose timers can be chained together to form x2 wide timers.

M821xx Data Sheet


2.1.17 IPSec Security Co-Processor The IPSec co-processor enables support of NIST-certified VPN technology. As a co-processor, the main advantage this logic core offers over simple cryptographic accelerators is that it can perform crypto operation (cipher + digest) as well as processes IPSec ESP and AH protocols for IPv4 and IPv6.

The co-processor’s capabilities include:

• Performs AES128/192/256, DES, 3DES, cipher operation.

• Performs MD5, SHA-1, SHA-256 digest operation.

• Insets or removes ESP/AH headers and trailers.

• Updates IP header (protocol, length, checksum).

• Manages Security Association Database.

• Performs TTL (time to live) update and anti-replay checks.

• Inbound and outbound operation fully processed in parallel

• Uses DMA for packets and contexts (SA).

The co-processor's DMA can be configured to handle up to 64 packets for ciphering and 64 more for deciphering without any processor intervention.

The Security Co-Processor can also perform “raw cryptographic” processing through the AHB slave interface and an internal Security Resource Manager (SRM). This feature can be used to encrypt/decrypt any non IPSec block of data (e.g.: AES or SHA1 for voice cipher) in parallel with any IPSec task.

The M821xx dual-processor architecture allows the IPSec core to be used by both the Media Stream Processor (MSP) or the Applications and Control Processor (ACP). For example, the MSP can use the IPSec co-processor for a raw cryptographic task such as SRTP helper, while the ACP uses it for IPSec off-loading.

For more information on security co-processor capabilities, contact your Mindspeed representative.

M821xx Data Sheet


2.2 Top-Level Block DiagramFigure 2-1 Top Level Block Diagram

MSPARM1

ARM 1136J-S@ 450 MHz

32k Prog Cache32k Data Cache

DDR2Controller

1GB

Expansion Bus

InternalBotot ROM

HIF/PCI

USB2.0CTRLR1 / PHY1

ACPARM0

ARM 1136J-S@ 450 MHz

16k Prog Cache16k Data Cache

128KBLevel2Cache

LAN2 ports

1 port

2 cnt/wvfrm

MII1/RMII1/RGMII1

MII0/RMII0/GMII0/RGMII0

16 data

PCI 2.1HIF

HS/FS/LSUSB PHY1

HS/FS/LSUSB PHY0

2-8 MHz1 port

4+1 CS22 addr8/16/32data

16/32 data14 addr3 BA

32

32

32

32

WAN

AHB master (64 bitsunless o.w. stated)

APB slave (32 bits)

AHB slave (64 bitsunless o.w. stated)

Multi-Level AMBA High Performance Bus (64 bits)@ 165 MHz

3232

USB2.0CTRLR0 / PHY0

TDM DMA /TDM Interface

AHB to APBBus Bridge

PoS / UTOPIA/Interface

10 / 100 / 1000EMAC1

MemoryDMA

10 / 100 / 1000EMAC0Clock /

Reset

InterruptController

I/O DMA

GPIO

I2C

SPI

UART

Timers

1 port

32

ARAM64KB

I/O DMA Channel

Standard ARM block

Internal-only block

Block with externalinterface

IPsecEngine

M821xx Data Sheet


2.3 Software InterfacesThe M821xx user applications interface to the hard real time voice code by means of a shared memory interface within the device. This partitioning allows deterministic performance of the voice processing channels, at the same time providing the flexibility and power of a high level operating system to applications. A typical arrangement is shown in Figure 2-2, the top half being code running on the Embedded Host Controller, the bottom half being the voice channel firmware (MSP).

2.3.1 Embedded Host Controller FirmwareThe M821xx device is provided with a Board Support Package (BSP) for popular operating systems (OS) that provide the kernel operating environment for the host application OS (contact Mindspeed sales office for details). Applications are built and debugged on this device using standard third party ARM tool chains and debuggers.

2.3.2 Voice Channel FirmwareThis is provided in ARM AXF format for downloading to SDRAM, at boot time. This image contains code for packet processing, signal processing and encryption (if applicable).

Figure 2-2 S/W Block Diagram

.


3.0 Applications and Control Processor

This chapter presents essential facts about the Applications and Control Processor (ACP) along with directions to other sources of information on this industry-standard architecture. It also presents a detailed map of the device’s internal memory space along with customer-accessible register space.

3.1 OverviewThe Comcerto M821xx Integrated Service Platform devices are centered on two ARM1136 processor cores running at 450 MHz. One processor, ARM1, serves as the Media Stream Processor (MSP) and performs voice and packet processing. The other processor core, ARM0, serves as the Applications and Control Processor (ACP) and functions as an embedded host processor for the device and associated peripherals in a CPE application.

Applications programmers have full access to the ACP The ACP can boot from external or internal memories ranging from remote servers via Ethernet to internal code stores and local EEPROM via I2C or SPI. Once executing, software on the ACP communicates with the MSP and the external network through the “Virtual Ethernet Interface”. Applications running on the ACP access other SoC cores over the multi-layer Advanced Host Bus (AHB) and the Advanced Peripheral Bus (APB).

Figure 3-1 M828xx Convergence Processor

M821xx Data Sheet


3.2 Comcerto M821xx Memory MapThe following memory map shows the 4 GB of memory space accessible to the ACP over the AHB.

Figure 3-2 ACP Memory Map

IBR / NOR remapor external SDRAM(7)

(Default)(2)

ARAM

~~ ~~

~~~~

0000_0000

0000_FFFF0001_000009FF_FFFF0A00_0000

0A07_FFFF

32 x 16 MB

(1) This memory space will be mapped to DDR2SDRAM base, taking configured DDR2

L2 Cache(6)

~~

~~

~~

SDRAM configuration

IPSEC configuration

USB0 configuration

USB1 configuration

APB(5)

Internal Boot ROM

Expansion bus(4)

(NOR, NAND, peripherals)

(Default)(2)~~(Default)(2)

(Default)(2)~~

PCI / HIF

(Default)(2)

SDRAM(3)

(Default)(2)

(High Mem)SDRAM(1)

~~

~~ ~~

64 KB

512 KB

64 KB

16 MB

16 MB

8 MB

8 MB

16 MB

4 MB

256 MB

1 GB

64 KB

0A08_FFFF0A09_FFFF0A0A_0000

0A0A_FFFF0A0B_00000CFF_FFFF

0DFF_FFFF

0D00_0000

0E00_0000

0F00_00000EFF_FFFF

0F7F_FFFF0F80_0000

0FFF_FFFF1000_0000

10FF_FFFF1100_0000

13FF_FFFF1400_00001FFF_FFFF

3FFF_FFFF

2000_0000

4000_0000

4FFF_FFFF5000_00007FFF_FFFF8000_0000

BFFF_FFFFC000_0000FFFE_FFFFFFFF_0000

FFFF_FFFF

(2) Memory space marked ‘Default’ will returnAHB error message when addressed.Addressing of empty memory space withindefined space such as ‘SDRAM’ will not return an AHB error message.

(3) The SDRAM controller will be accessed when the address is within this range even when the configured external SDRAM size is smaller.

(4) Only five 16 MB aperatures with in this

(5) For details, see section 4.3.

(6) This cache is addressable only by ARM0.

(7) After reset, this 64 KB memory space will bemapped to the Internal Boot ROM or toexternal NOR flash depending on thestatus of bootstrap inputs (TM_BOOTOP[1:0]).The rest of the address space is unchanged.When ROM re-map is cleared, accesses to the lowest 64 KB of memory space will be mapped to the lowest 64 KB of external SDRAM.

SDRAM memory size into consideration.

space support expansion bus peripherals.They start at 0x2000_0000 and are interspersed with Default areas of 48 MB. See Figure 7-2,

M821xx Data Sheet


3.3 Comcerto APB MemoryAll of the registers mapped in the APB bus are word address aligned. The APB addresses range from hex 1000 0000 to hex 101F FFFF. Table 3-1 shows the address mapping for the peripheral registers within each block.

Table 3-1 APB Memory Map

Select Address (hex) Memory Size (KB) Description

PSEL31 101F 0000 64 Reserved.

PSEL30 101E 0000 64 MDMA.

PSEL29 101D 0000 64 TDMA2.

PSEL28 101C 0000 64 Reserved.

PSEL27 101B 0000 64 Reserved.

PSEL26 101A 0000 64 Expansion Bus.

PSEL25 1019 0000 64 EMAC1.

PSEL24 1018 0000 64 Reserved. PSEL17 through PSEL24 are currently reserved.

PSEL23 1017 0000 64

PSEL22 1016 0000 64

PSEL21 1015 0000 64

PSEL20 1014 0000 64

PSEL19 1013 0000 64

PSEL18 1012 0000 64

PSEL17 1011 0000 64

PSEL16 1010 8000 32 AHB Arbiter.

1010 0000 32

PSEL15 100F 0000 64 ARAM.

PSEL14 100E 0000 64 IDMA.

PSEL13 100D 0000 64 EMAC0.

PSEL12 100C 0000 Utopia / PoS Interface.

PSEL11 100B 0000 Clock (PLL configuration).

PSEL10 100A 0000 Interrupt Controller.

PSEL91009 C000 16 I2C Interface.

1009 8000 16 SPI Interface.

1009 4000 16 UART1.

1009 0000 16 UART0.

M821xx Data Sheet


3.4 Applicable ARM Document• ARM 1136JF-S and ARM 1136JS Technical Reference Manual. DDI0211H, Issued: 14 Oct 2005.

PSEL8 1008 0000 64 Reserved.

PSEL7 1007 0000 64 GPIO.

PSEL6 1006 0000 64 AHB Decoder.

PSEL5 1005 0000 64 TIMER.

PSEL4 1004 8000 32 ASA_ARAM and ASA_DDR. Arbiter for external SCRAM and ARAM.

1004 0000 32

PSEL3 1003 0000 64 Reserved.

PSEL2 1002 0000 64 TDMA.

PSEL1 1001 0000 64 PCI / Host Interface.

PSEL0 1000 0000 64 TDM.

Select Address (hex) Memory Size (KB) Description

.


4.0 Pin List and Signal Summary

4.1 Overview of this SectionThis section presents pin, or contact, information for M821xx devices:

• Hardware Interface Overview (Section 4.2)

• Device to Package Assignments (Section 4.3)

• Interface Regions diagrams (4-Row: Figure 4-2; 6-Row: Figure 4.4)

• Pinout (4-Row: Section 4.5; 6-Row: Section 4.8)

• Pin List (4-Row: Section 4.6; 6-Row: Section 4.9)

• I/O Pad Definitions (Section 4.11 I/O PAD Types)

• Quick Signal Reference (Section 4.12)

• Unused Interface Termination Recommendaations (Section 4.13)

For detailed signal descriptions, refer to specific interface sections.

For power requirements, refer to Section 42.0 Hardware Initialization on page 614, and Section 43.0 Electrical and Environmental Specifications on page 622.

For a M821xx pin list as in ‘.txt’ or ‘.xls’ format, contact your Mindspeed sales representative or FAE.

For additional package details, see Section 44.0 Package Dimensions.

M821xx Data Sheet


4.2 Hardware Interface OverviewFigure 4-1 M821xx Hardware Interface Summary

4.3 Device to Package AssignmentsThe M821xx devices include similar packages with different pinouts:

– 4-Row where the signal pins are concentrated in the outermost 4 rows– 6-Row where the signal pins are concentrated in the outermost 6 rows (includes UTOPIA interface)

Table 4-1 Device to Package Assignments

Package Type M82104 M82108 M82152 M82154 M82170 M82172 M82174 M82190 M82192 M82194

4- Row

6-Row

GMII, RGMIIMII, RGMII

Ethernet0

Ethernet1

RGMII, MII, RMII

USB 2.0 x2

I2C

SPI

JTAG x2

TDM

32 GPIOs

2 Timer /Counters

UART x2

PCI 2.1 / µP Bus

Expansion Bus8 / 16 / 32

DDR2 SDRAM1GB (x32 bits)

M821xxIntegrated Services Platform

UTOPIA,PoS L2

M821xx Data Sheet


4.4 Interface Regions — 4-Row PackageFigure 4-2 Interface Regions — 4-Row Package (Top View Looking Through Package)

USB Signals

TDM

UART

SPI

PCI / HostBus

Ground

Expansion Bus

JTAGDDR2

GMII

MII

GPIO[5:0]

Ground

VI/O

VDD

Ground

VDD

VI/O

M821xx Data Sheet


4.5 Pinout — 4-Row PackageThese devices include: M82104, M82108, M82152, M82154, M82170, M82172, M82174.

For a visual summary of interface regions, refer to Table 4-2 on page 61.

For pin list, see Table 4-4 on page 63.

Table 4-2 M821xx Pins — 4-Row Package (Top View – Left Side)1 2 3 4 5 6 7 8 9 10 11 12 13

A VDDO_DDR2

DDR_DATA_0

DDR_DATA_5

DDR_DATA_15

VSS DDR_DATA_13

DDR_DATA_23

DDR_DATA_18

VDD0_DDR2

DDR_CLKN

DDR_DQS_3

DDR_DATA_24

B VSS DDR_DQS_0

DDR_DATA_7

DDR_DATA_2

DDR_DQS_1

DDR_DATA_8

DDR_DATA_10

DDR_DQS_2

DDR_DATA_16

DDR_DATA_21

DDR_CLK

DDR_DATA_31

DDR_DATA_26

C VDDO_GMII0

DDR_CS_N_0

DDR_ODT_0

VDDO_DDR2

DDR_DATA_1

DDR_DATA_4

DDR_DATA_14

VSS DDR_DATA_12

DDR_DATA_22

DDR_DATA_19

VDDO_DDR2

DDR_DATA_30

D GMII0_TXD7

GMII0_TXD6 VSS DDR_DM_0 DDR_

DATA_6DDR_

DATA_3DDR_DM_1

DDR_DATA_9

DDR_DATA_11

DDR_DM_2

DDR_DATA_17

DDR_DATA_20

DDR_DM_3

E VSS GNII0_TXD5

GMII0_MDIO

GMII0_MDC VSS VSS VSS VSS VSS VSS VSS VSS VSS

F GMII0_TXD4

GMII0_TXD3

GMIIO_TX_EN

GMII0_GTX_

REFCLKVSS VSS VSS VSS VSS VSS VSS VSS VSS

GGMII0_TXD2

GMII0_TXD1 VDDO_

GMII0

GMII0_GTX_CLK

VSS VSS VSS VSS VSS VSS VSS VSS VSS

H GMII0_TXD0

GMII0_RXD0

GMII0_TX_CLK

GMII0_TX_ER VSS VSS VSS VDD_

PREVDD_REF

VDD0_DDR2

VDD0_DDR2

VDD0_DDR2

VDD0_DDR2

J VDDO_GMII0

GMII0_RXD1

GMII0_RX_CLK

GMII0_RX_ER VSS VSS VSS VDDO_

GMII0 VDD VDD VDD VDD VDD

K GMII0_RXD2

GMII0_RXD3

GMII0_CRS

GMII0_RX_DV

VSS VSS VSS VDDO_GMII0_0

VDD VSS VSS VSS VSS

L GMII0_RXD4

GMII0_RXD5

VDDO_GMII0

GMII0__COL VSS VSS VSS VDDO_

GMII0VDD VSS VSS VSS VSS

MGMII0_RXD6

GMII0_RXD7

MII1_MDC

TM_ETH_REFCL

KO

VSS VSS VSS VDDO_MII1 VDD VSS VSS VSS VSS

N VSS MII1_TXD3

MII1_MDIO

MII1_TX_CLK

VSS VSS VSS VDDO_MII1

VDD VSS_PLL_0

VSS VSS VSS

P MII1_TXD2 MII1_TXD1 MII1_COL MII1_TX_EN

VSS VSS VSS VDDO_MII1

VDD VSS_PLL_1

VSS VSS VSS

R MII1_TXD0 MII1_RXD0 VSS MII1_TX_ER VSS VSS VSS VDDO_

EXPVDD VSS VSS VSS VSS

T MII1_RXD1

MII1_RXD2

MII1_RX_ER

MII1_RX_CLK

VSS VSS VSS VDDO_EXP

VDD VSS VSS VSS VSS

U VDDO_MII1

MII1_RXD3

MII_RX_DV VSS VSS VSS VSS VDDO_EXP

VDD VSS VSS VSS VSS

V MII1_CRS VDD_PLL_0

VDD_PLL_1

PLL_XO VSS VSS VSS VDDO_EXP VDD VDD VDD VDD VDD

W TRISTATE_N

GPIO_0 VSS PLL_XI VSS VSS VSS VSS VDDO_EXP

VDDO_EXP

VDDO_EXP

VDDO_EXP

VDDO_EXP

Y GPIO_1 GPIO_2 VSS GPIO_3 VSS VSS VSS VSS VSS VSS VSS VSS VSS

AA VDDO_EXP GPIO_4 GPIO_5 EXP_DQ_15 VSS VSS VSS VSS VSS VSS VSS VSS VSS

AB EXP_CLK VSS VDDO_EXP

EXP_DQ_5 VSS VSS VSS VSS VSS VSS VSS VSS VSS

AC EXP_DQ_14

EXP_DQ_13

EXP_DQ_8

EXP_DQ_4

EXP_DQ_0

EXP_NAND_RE_N

EXP_NAND_RDY

EXP_CS_N_0

EXP_CS_N_3

EXP_A_L_2

EXP_A_L_5

EXP_A_L_9

EXP_A_L_12

AD EXP_DQ_12

EXP_DQ_11

EXP_DQ_7

EXP_DQ_3

VSS EXP_IRQ EXP_NAND_CS

EXP_ALE

VDDO_EXP

EXP_A_L_1

EXP_A_L_4

EXP_A_L_8 VSS

AE VSS EXP_DQ_10

EXP_DQ_6

EXP_DQ_2

EXP_DM_0 EXP_NAND_WE_N

EXP_NAND_CLE

EXP_WE_N

EXP_CS_N_2

EXP_A_L_0

EXP_A_L_3

EXP_A_L_7

EXP_A_L_11

AF EXP_DQ_9

VDDO_EXP_0

EXP_DQ_1

EXP_DM_1

EXP_NAND_ALE VSS EXP_

RE_NEXP_CS

_N_1EXP_RDY

_BYSNVDDO_

EXPEXP_A_

L__6EXP_A_L__10

1 2 3 4 5 6 7 8 9 10 11 12 13

M821xx Data Sheet


Table 4-3 M821xx Pins — 4-Row Package (Top View – Right Side)14 15 16 17 18 19 20 21 22 23 24 25 26

VSS DDR_A_11

DDR_A_6

DDR_A_2

VDD0_DDR2

DDR_A_10

DDR_A_12

DDR_ODT_1

VSS JTAG1_TMS

JTAG1_TRST_N

JTAG0_TCK A

DDR_DATA_29

DDR_A_5

DDR_A_1

DDR_A_3

DDR_BA_2

DDR_BA_0

DDR_CS_N_1

DDR_A_0

DDR_A_9

JTAG0_TDI

JTAG0_TDO

JTAG0_TMS VDDO_PCI B

DDR_DATA_27

DDR_RAS_N

VSS DDR_CAS_N

DDR_A_8

DDR_A_7

VDDO_DDR2

DDR_A_4

JTAG1_TDO

JTAG0_TRST_N

SPI_TXD SPI_RXD SPI_SS0_N C

DDR_DATA_25

DDR_DATA_28

DDR_WE_N

DDR_CLKE

DDR_BA_1

DDR_A_13

JTAG1_TCK

JTAG1_TDI

TM_BSCN_JTAG

SPI_SS1_N

SPI_SS2_N

SPI_SS3_N

UART1RX D

VSS VSS VSS VSS VSS VSS VSS VSS VSS UART0RX UART0TX UART1TX VSS E

VSS VSS VSS VSS VSS VSS VSS VSS VSS TIM_EVNT1

TIM_EVNT0

PCI_AD_2

PCI_AD_0 F

VSS VSS VSS VSS VSS VSS VSS VSS VSS PCI_AD_1

VDDO_PCI

PCI_AD_3

PCI_AD_4 G

VDDO_DDR2

VDDO_DDR2

VDDO_DDR2

VDDO_DDR2

VDD_REF

VDD_PRE VSS VSS VSS PCI_AD_9

PCI_PAR

PCI_CBE_N_0

PCI_AD_5 H

VDD VDD VDD VDD VDD VDDO_PCI

VSS VSS VSS PCI_AD_7

PCI_AD_8

PCI_STOP_N

VDDO_PCI J

VSS VSS VSS VSS VDD VDDO_PCI

VSS VSS VSS I2C_SDA

SPI_SCLK

PCI_AD_13

PCI_AD_15 K



VSS I2C_SCL

PCI_TRDY_N L



PCI_AD_11

PCI_CBE_N_1

PCI_AD_12 M


VSS VSS VSS PCI_IRDY_N

PCI_AD_14

PCI_SER_N VSS N

VSS VSS VSS VSS VDD VDDO_PCI VSS VSS VSS PCI_

AD_29PCI_

AD_23PCI_

FRAME_NPCI_

PERR_N P

VSS VSS VSS VSS VDD VDDO_PCI VSS VSS VSS RESET_N VDDO_

PCIPCI_CLK

PCI_DEVSEL_N R

VSS VSS VSS VSS VDD VSSA_USB0

VSS VSS VSS TDM_CKTM_PCI_

REFCLKO

PCI_AD_16

PCI_CBE_N_2 T

VSS VSS VSS VSS No Connect

VDDA_USB_0

VSS VSS VSS TM_EXT_RESET

PCI_INTB_N

PCI_AD_21

VDDO_PCI U

VDD VDD VDD VDD No Connect

VSSA_USB1 VSS VSS VSS PCI_

REQ2_NPCI_

INTA_NPCI_

CBE_N_3PCI_

AD_19 V

VDDO_EXP

VDDO_EXP

VDDO_EXP

VDDO_EXP

VDDO_EXP

VDDA_USB_1 VSS VSS VSS PCI_

GNT1_NVSS PCI_

AD_27PCI_

AD_17 W


PCI_AD_24

PCI_AD_20

PCI_AD_18 Y


PCI_IDSEL

PCI_REQ1_N VSS AA

VSS VSS VSS VSS VSS VSS VSS VSS VSS PCI_AD30

PCI_GNT2_N

PCI_AD_22

PCI_AD_25 AB

EXP_A_U_16

EXP_A_U_19

PullLow

No Connect

No Connect VSS VSS VSS VSS

USB0_VBUS_STA

T

VDDO_PCI

TDM_FS PCI_AD_31 AC

EXP_A_U_15

EXP_A_U_18

No Connect

VDDO_EXP VSS VSS USB1_REF VSS VSS USB0

_REF No Connect TDM_DR TDM_DX AD

EXP_A_L_14

EXP_A_U_17

EXP_A_U_21

No Connect

VDDA_USB_1

VSSA_USB1

VDD_USB1_P

VDDA_USB_0

VSSA_USB0

VDD_USB0_P

NoConnect

USB1_VBUS_STAT

VDDO_PCI AE

EXP_A_L_13 VSS EXP_A

_U_20No

Connect USB1_DM USB1_DP VSS_USB_P_0 USB0_DM USB0_DP VSS_USB_

P_1No

Connect VSS AF

14 15 16 17 18 19 20 21 22 23 24 25 26

M821xx Data Sheet

821xx-DSH-002-G Mindspeed Technologies™ 63Advance Information / Mindspeed Proprietary and Confidential

4.6 Pin List — 4-Row PackageThese devices include: M82104, M82108, M82152, M82154, M82170, M82172, M82174.

Table 4-4 Pin List — 4-Row — M82104, M82108, M82152, M82154, M82170, M82172, M82174.

Location Signal Symbol Dir. I/O Type

A1 Unused corner — —

A2 VDDO_DDR2 — PWR

A3 DDR_DATA_0 B MEMIO



A6 VSS — GND





A11 DDR_CLKN O MEMIODIF

A12 DDR_DQS_3 B MEMIO


A14 VSS — GND

A15 DDR_A_11 O MEMIO

A16 DDR_A_6 O MEMIO

A17 DDR_A_2 O MEMIO




A21 DDR_ODT_1 O MEMIO

A22 VSS — GND

A23 JTAG1_TMS I Ihu

A24 JTAG1_TRST_N I Ihu

A25 JTAG0_TCK I Ihu


B1 VSS — GND

B2 DDR_DQS_0 B MEMIO

B3 DDR_DATA_7 B MEMIO








B11 DDR_CLK O MEMIODIF




B15 DDR_A_5 O MEMIO

B16 DDR_A_1 O MEMIO

B17 DDR_A_3 O MEMIO

B18 DDR_BA_2 O MEMIO


B20 DDR_CS_N_1 O MEMIO

B21 DDR_A_0 O MEMIO

B22 DDR_A_9 O MEMIO

B23 JTAG0_TDI I Ihu

B24 JTAG0_TDO O Ots8

B25 JTAG0_TMS I Ihu

B26 VDDO_PCI — PWR

C1 VDDO_GMII0 — PWR

C2 DDR_CS_N_0 O MEMIO

C3 DDR_ODT_0 O MEMIO

C4 VDDO_DDR2 — PWR

C5 DDR_DATA_1 B MEMIO



C8 VSS — GND




M821xx Data Sheet

Continued Table 3-6 Pin List — 4-Row — M82104, M82108, M82152, M82154, M82170, M82172, M82174.






C15 DDR_RAS_N O MEMIO

C16 VSS — GND

C17 DDR_CAS_N O MEMIO

C18 DDR_A_8 O MEMIO

C19 DDR_A_7 O MEMIO


C21 DDR_A_4 O MEMIO

C22 JTAG1_TDO O Ots8

C23 JTAG0_TRST_N I Ihu

C24 SPI_TXD /GPIO_25

B Ihu/Ots8

C25 SPI_RXD /GPIO_26

B Ihd/Ots8

C26 SPI_SS0_N /GPIO_27

B Ihu/Ots8

D1 GMII0_TXD7 O Ot16


D3 VSS B GND

D4 DDR_DM_0 O MEMIO

D5 DDR_DATA_6 B MEMIO


D7 DDR_DM_1 O MEMIO



D10 DDR_DM_2 O MEMIO






D16 DDR_WE_N O MEMIO


D17 DDR_CLKE O MEMIOPL

D18 DDR_BA_1 O MEMIO

D19 DDR_A_13 O MEMIO

D20 JTAG1_TCK I Ihu

D21 JTAG1_TDI I Ihu

D22 TM_BSCN_JTAG I Id

D23 SPI_SS1_N /GPIO_28

B Ihu/Ots8

D24 SPI_SS2_N O Ots8

D25 SPI_SS3_N O Ots8

D26 UART1RX /GPIO_22

B Ihu/Ots8

E1 VSS O GND

E2 GMII0_TXD5 O Ot16

E3 GMII0_MDIO /RMII0_MDIO /

RGMII0_MDIO /MII0_MDIO

B I/Ots8

E4 GMII0_MDC /RMII0_MDC /

RGMII0_MDC /MII0_MDC

O Ots8

E5 VSS — GND

E6 VSS — GND

E7 VSS — GND

E8 VSS — GND

E9 VSS — GND

E10 VSS — GND

E11 VSS — GND

E12 VSS — GND

E13 VSS — GND

E14 VSS — GND

E15 VSS — GND

E16 VSS — GND

E17 VSS — GND

E18 VSS — GND


M821xx Data Sheet



E19 VSS — GND

E20 VSS — GND

E21 VSS — GND

E22 VSS — GND

E23 UART0_RX /GPIO_20

B Ihu/Ots8

E24 UART0_TX /GPIO_21

B Ihu/Ots8

E25 UART1_TX /GPIO_23

B Ihu/Ots8

E26 VSS — GND

F1 GMII0_TXD4 O Ot16

F2 GMII0_TXD3 /RGMII0_TXD3

MII0_TXD3

O Ot16

F3 GMII0_TX_ENRMII0_TX_ENRGMII0_TXCMII0_TX_EN

O Ot16

F4 GMII0_GTX_REFCLK

I I

F5 VSS — GND

F6 VSS — GND

F7 VSS — GND

F8 VSS — GND

F9 VSS — GND

F10 VSS — GND

F11 VSS — GND

F12 VSS — GND

F13 VSS — GND

F14 VSS — GND

F15 VSS — GND

F16 VSS — GND

F17 VSS — GND

F18 VSS — GND

F19 VSS — GND

F20 VSS — GND


F21 VSS — GND

F22 VSS — GND

F23 TIM_EVNT1GPIO_16

B Ihu/Ots8

F24 TIM_EVNT0 /GPIO_15

B Ihu/Ots8

F25 PCI_AD_2 /HBD_2

B PCI

F26 PCI_AD_0 /HBD_0

B PCI

G1 GMII0_TXD2 / RGMII0_TXD2 /

MII_TXD2

O Ot16

G2 GMII0_TXD1 / RMII0_TXD1 /

RGMII0_TXD1 / MII0_TXD1

O Ot16

G3 VDDO_GMII0 — PWR

G4 GMII0_GTX_CLK O Ot16

G5 VSS — GND

G6 VSS — GND

G7 VSS — GND

G8 VSS — GND

G9 VSS — GND

G10 VSS — GND

G11 VSS — GND

G12 VSS — GND

G13 VSS — GND

G14 VSS — GND

G15 VSS — GND

G16 VSS — GND

G17 VSS — GND

G18 VSS — GND

G19 VSS — GND

G20 VSS — GND

G21 VSS — GND

G22 VSS — GND


M821xx Data Sheet



G23 PCI_AD_1 /HBD_1

B PCI

G24 VDDO_PCI — PWR

G25 PCI_AD_3 /HBD_3

B PCI

G26 PCI_AD_4 /HBD_4

B PCI

H1 GMII0_TXD0 /RMII0_TXD0 /

RGMII0_TXD0 /MII0_TXD0

O Ot16

H2 GMII0_RXD0 /RMII0_RXD0 /

RGMII0_RXD0 /MII0_RXD0

I I

H3 GMII0_TX_CLK /RGMII0_REFCLK /

MII0_TX_CLK

I I

H4 GMII0_TX_ER /RGMII0_CTL /MII0_TX_ER

O Ot16

H5 VSS — GND

H6 VSS — GND

H7 VSS — GND

H8 VDD_PRE — PWR

H9 VDDO_REF — PWR

H10 VDDO_DDR2 — PWR








H18 VDD_REF — PWR

H19 VDD_PRE — PWR

H20 VSS — GND

H21 VSS — GND


H22 VSS — GND

H23 PCI_AD_9 /HBD_9

B PCI

H24 PCI_PAR /HBA_2

B PCI

H25 PCI_CBE_N_0 /HBBE_N0

B PCI

H26 PCI_AD_5 /HBD_5

B PCI

J1 VDDO_GMII0 — PWR

J2 GMII0_RXD1 /RMII0_RXD1 /


I I

J3 GMII0_RX_CLK /RMII0_REFCLK /RGMII0_RXC /MII0_RX_CLK

I I

J4 GMII0_RX_ER /RMII0_RX_ER /

MII0_RX_ER

I I

J5 VSS — GND

J6 VSS — GND

J7 VSS — GND


J9 VDD — PWR

J10 VDD — PWR

J11 VDD — PWR

J12 VDD — PWR

J13 VDD — PWR

J14 VDD — PWR

J15 VDD — PWR

J16 VDD — PWR

J17 VDD — PWR

J18 VDD — PWR

J19 VDDO_PCI — PWR

J20 VSS — GND

J21 VSS — GND


M821xx Data Sheet



J22 VSS — GND

J23 PCI_AD_7 /HBD_7

B PCI

J24 PCI_AD_8 /HBD_8

B PCI

J25 PCI_STOP_N /HBFIFO

B PCI


K1 GMII0_RXD2 /RMII0_PHY_DPXRGMII0_RXD2 /

MII0_RXD2 /

I I

K2 GMII0_RXD3 /RMII0_PHY_SPEED


I I

K3 GMII0_CRS /RMII0_PHY_LINK /

MII0_CRS

I I

K4 GMII0_RX_DV /RMII0_CRS_DV /

RGMII0_RX_CTL /MII0_RX_DV

I I

K5 VSS — GND

K6 VSS — GND

K7 VSS — GND

K8 VDDO_GMII0 — PWR

K9 VDD — PWR

K10 VSS — GND

K11 VSS — GND

K12 VSS — GND

K13 VSS — GND

K14 VSS — GND

K15 VSS — GND

K16 VSS — GND

K17 VSS — GND

K18 VDD — PWR

K19 VDDO_PCI — PWR


K20 VSS — GND

K21 VSS — GND

K22 VSS — GND

K23 I2C_SDA /GPIO_19

B Ihu/Ots8

K24 SPI_SCLK /GPIO_24

B Ihu/Ots8

K25 PCI_AD_13 /HBD_13

B PCI

K26 PCI_AD_15 /HBD_15

B PCI

L1 GMII0_RXD4 I I

L2 GMII0_RXD5 I I

L3 VDDO_GMII0 — PWR

L4 GMII0_COL /MII0_COL

I I

L5 VSS — GND

L6 VSS — GND

L7 VSS — GND


L9 VDD — PWR

L10 VSS — GND

L11 VSS — GND

L12 VSS — GND

L13 VSS — GND

L14 VSS — GND

L15 VSS — GND

L16 VSS — GND

L17 VSS — GND

L18 VDD — PWR

L19 VDDO_PCI — PWR

L20 VSS — GND

L21 VSS — GND

L22 VSS — GND

L23 PCI_AD_6 /HBD_6

B PCI


M821xx Data Sheet



L24 VSS — GND

L25 I2C_SCL /GPIO_18

B Ihu/Ots8

L26 PCI_TRDY_N /HBCS_N

B PCI

M1 GMII0_RXD6 I I

M2 GMII0_RXD7 I I

M3 MII1_MDC /RMII1_MDC /RGMII1_MDC

O Ots8

M4 TM_ETH_REFCLK0 O Ot16

M5 VSS — GND

M6 VSS — GND

M7 VSS — GND

M8 VDDO_MII1 — PWR

M9 VDD — PWR

M10 VSS — GND

M11 VSS — GND

M12 VSS — GND

M13 VSS — GND

M14 VSS — GND

M15 VSS — GND

M16 VSS — GND

M17 VSS — GND

M18 VDD — PWR

M19 VDDO_PCI — PWR

M20 VSS — GND

M21 VSS — GND

M22 VSS — GND

M23 PCI_AD_10 /HBD_10

B PCI


B PCI

M25 PCI_CBE_N_1 / HBBE_N1

B PCI



B PCI

N1 VSS — GND

N2 MII1_TXD3 /RGMII1_TXD3

O Ot16

N3 MII1_MDIO /RMII1_MDIO /RGMII1_MDIO

B I/Ots8

N4 MII1_TX_CLK /RGMII1_REFCLK

I I

N5 VSS — GND

N6 VSS — GND

N7 VSS — GND

N8 VDDO_MII1 — PWR

N9 VDD — PWR

N10 VSS_PLL_0 — GND

N11 VSS — GND

N12 VSS — GND

N13 VSS — GND

N14 VSS — GND

N15 VSS — GND

N16 VSS — GND

N17 VSS — GND

N18 VDD — PWR

N19 VDDO_PCI — PWR

N20 VSS — GND

N21 VSS — GND

N22 VSS — GND

N23 PCI_IRDY_N /HBA_6

B PCI

N24 PCI_AD_14 /HBD_14

B PCI

N25 PCI_SERR_N /HBW_N

B PCI

N26 VSS — GND

P1 MII1_TXD2 / RGMII1_TXD2

O Ot16


M821xx Data Sheet



P2 MII1_TXD1 / RMII1_TXD1 / RGMII1_TXD1

O Ot16

P3 MII1_COL I I/Ot8

P4 MII1_TX_EN /RMII1_TX_EN /RGMII1_TXC

O Ot16

P5 VSS — GND

P6 VSS — GND

P7 VSS — GND

P8 VDDO_MII1 — PWR

P9 VDD — PWR

P10 VSS_PLL_1 — GND

P11 VSS — GND

P12 VSS — GND

P13 VSS — GND

P14 VSS — GND

P15 VSS — GND

P16 VSS — GND

P17 VSS — GND

P18 VDD — PWR

P19 VDDO_PCI — PWR

P20 VSS — GND

P21 VSS — GND

P22 VSS — GND

P23 PCI_AD_29 /HBD_29

B PCI


B PCI

P25 PCI_FRAME_N /HBA_4

B PCI

P26 PCI_PERR_N /HBWAIT_N

B PCI

R1 MII1_TXD0 /RMII1_TXD0 /RGMII1_TXD0

O Ot16


R2 MII1_RXD0 /RMII1_RXD_0

RGMII1_RXD_0

I I

R3 VSS — GND

R4 MII1_TX_ERRGMII1_TX_CTL

O Ot16

R5 VSS — GND

R6 VSS — GND

R7 VSS — GND

R8 VDDO_EXP — PWR

R9 VDD — PWR

R10 VSS — GND

R11 VSS — GND

R12 VSS — GND

R13 VSS — GND

R14 VSS — GND

R15 VSS — GND

R16 VSS — GND

R17 VSS — GND

R18 VDD — PWR

R19 VDDO_PCI — PWR

R20 VSS — GND

R21 VSS — GND

R22 VSS — GND

R23 RESET_N I Ih


R25 PCI_CLK /HBCLK

I PCI

R26 PCI_DEVSEL_N /HBA_3

B PCI

T1 MII1_RXD1 /RMII1_RXD1 /RGMII1_RXD1

I I

T2 MII1_RXD2 /RMII1_PHY_DPX /

RGMII1_RXD2

I I


M821xx Data Sheet



T3 MII1_RX_ER /RMII1_RX_ER

I I

T4 MII1_RX_CLK /RMII1_REFCLK /

RGMII1_RXC

I I

T5 VSS — GND

T6 VSS — GND

T7 VSS — GND

T8 VDDO_EXP — PWR

T9 VDD — PWR

T10 VSS — GND

T11 VSS — GND

T12 VSS — GND

T13 VSS — GND

T14 VSS — GND

T15 VSS — GND

T16 VSS — GND

T17 VSS — GND

T18 VDD — PWR

T19 VSS_USB0 — GND

T20 VSS — GND

T21 VSS — GND

T22 VSS — GND

T23 TDM_CK /TM_TDM_REFCLK

B Ih/Ot16

T24 TM_PCI_REFCLKO O Ot16

T25 PCI_AD_16 /HBD_16

B PCI

T26 PCI_CBE_N_2HBBE_N2

B PCI

U1 VDDO_MII1 — PWR

U2 MII1_RXD3 /RMII1_PHY_SPEED /

RGMII1_RXD3

I I

U3 MII1_RX_DV /RMII1_CRS_DV /RGMII1_RX_CTL

I I


U4 VSS — GND

U5 VSS — GND

U6 VSS — GND

U7 VSS — GND

U8 VDDO_EXP — PWR

U9 VDD — PWR

U10 VSS — GND

U11 VSS — GND

U12 VSS — GND

U13 VSS — GND

U14 VSS — GND

U15 VSS — GND

U16 VSS — GND

U17 VSS — GND

U18 No Connect — USBANLG

U19 VDDA_USB_0 — PWR

U20 VSS — GND

U21 VSS — GND

U22 VSS — GND

U23 TM_EXT_RESET /GPIO_17

B Ihd/Ots8

U24 PCI_INTB_N O PCI

U25 PCI_AD_21 / HBD_21

B PCI

U26 VDDO_PCI — PWR

V1 MII1_CRS /RMII1_PHY_LINK

I I

V2 VDD_PLL_0 — PWR

V3 VDD_PLL_1 — PWR

V4 PLL_XO O OSCL

V5 VSS — GND

V6 VSS — GND

V7 VSS — GND

V8 VDDO_EXP — PWR

V9 VDD — PWR


M821xx Data Sheet



V10 VDD — PWR

V11 VDD — PWR

V12 VDD — PWR

V13 VDD — PWR

V14 VDD — PWR

V15 VDD — PWR

V16 VDD — PWR

V17 VDD — PWR

V18 No Connect — USBANLG

V19 VSSA_USB1 — GND

V20 VSS — GND

V21 VSS — GND

V22 VSS — GND

V23 PCI_REQ2_N I PCI

V24 PCI_INTA_N /HBINT_N

O PCI

V25 PCI_CBE_N_3 /HBBE_N3

B PCI

V26 PCI_AD_19 /HBD_19

B PCI

W1 TRISTATE_N I Iu

W2 GPIO_0 B Ihu/Ots16

W3 VSS — GND

W4 PLL_XI I OSCL

W5 VSS — GND

W6 VSS — GND

W7 VSS — GND

W8 VSS — GND

W9 VDDO_EXP — PWR

W10 VDDO_EXP — PWR










W19 VDDA_USB_1 — PWR

W20 VSS — GND

W21 VSS — GND

W22 VSS — GND

W23 PCI_GNT1_N /HBLAST_N

B PCI

W24 VSS — GND

W25 PCI_AD_27 /HBD_27

B PCI

W26 PCI_AD_17 /HBD_17

B PCI

Y1 GPIO_1 B Ihu/Ots16


Y3 VSS — GND


Y5 VSS — GND

Y6 VSS — GND

Y7 VSS — GND

Y8 VSS — GND

Y9 VSS — GND

Y10 VSS — GND

Y11 VSS — GND

Y12 VSS — GND

Y13 VSS — GND

Y14 VSS — GND

Y15 VSS — GND

Y16 VSS — GND

Y17 VSS — GND

Y18 VSS — GND

Y19 VSS — GND

Y20 VSS — GND

Y21 VSS — GND


M821xx Data Sheet



Y22 VSS — GND

Y23 PCI_AD_26 /HBD_26

B PCI


B PCI


B PCI


B PCI

AA1 VDDO_EXP — PWR

AA2 GPIO_4 B Ihu/Ots16

AA3 GPIO_5 B Ihu/Ots16

AA4 EXP_DQ_15 B I/Ots8

AA5 VSS — GND

AA6 VSS — GND

AA7 VSS — GND

AA8 VSS — GND

AA9 VSS — GND

AA10 VSS — GND

AA11 VSS — GND

AA12 VSS — GND

AA13 VSS — GND

AA14 VSS — GND

AA15 VSS — GND

AA16 VSS — GND

AA17 VSS — GND

AA18 VSS — GND

AA19 VSS — GND

AA20 VSS — GND

AA21 VSS — GND

AA22 VSS — GND

AA23 PCI_AD_28 /HBD_28

B PCI

AA24 PCI_IDSEL /HBA_5

I PCI

AA25 PCI_REQ1_N B PCI


AA26 VSS — GND

AB1 EXP_CLK O Ot8

AB2 VSS — GND

AB3 VDDO_EXP — PWR

AB4 EXP_DQ_5 B I/Ots8

AB5 VSS — GND

AB6 VSS — GND

AB7 VSS — GND

AB8 VSS — GND

AB9 VSS — GND

AB10 VSS — GND

AB11 VSS — GND

AB12 VSS — GND

AB13 VSS — GND

AB14 VSS — GND

AB15 VSS — GND

AB16 VSS — GND

AB17 VSS — GND

AB18 VSS — GND

AB19 VSS — GND

AB20 VSS — GND

AB21 VSS — GND

AB22 VSS — GND

AB23 PCI_AD_30 /HBD_30

B PCI

AB24 PCI_GNT2_N O PCI


B PCI


B PCI

AC1 EXP_DQ_14 B I/Ots8






M821xx Data Sheet



AC6 EXP_NAND_RE_N O Ots8

AC7 EXP_NAND_RDY/BSYN /GPIO_6

B Ihu/Ots16

AC8 EXP_CS_N_0 O Ots8


AC10 EXP_A_L_2 /TM_MII1_MODE0

B Id/Ots8

AC11 EXP_A_L_5 /TM_GBPT_OP3

B Iu/Ots8

AC12 EXP_A_L_9 /HBBUSSIZE_0

B Iu/Ots8


B Id/Ots8

AC14 EXP_A_U_16 /GPIO_9

B Ihd/Ots8


B Ihd/Ots8

AC16 Pull Low — Ihd

AC17 No Connect — Id/Ot8

AC18 No Connect — Id/Ot8

AC19 VSS — GND

AC20 VSS — GND

AC21 VSS — GND

AC22 VSS — GND

AC23 USB0_VBUS_STAT I I

AC24 VDDO_PCI — PWR

AC25 TDM_FS / TM_TDM_FSO

B I/Ot8

AC26 PCI_AD_31 /HBD_31

B PCI

AD1 EXP_DQ_12 B I/Ots8




AD5 VSS — GND

AD6 EXP_IRQ / GPIO_7

B Ihu/Ots16


AD7 EXP_NAND_CS / GPIO_29

B Ihu/Ots8

AD8 EXP_ALE O Ots8

AD9 VDDO_EXP — PWR

AD10 EXP_A_L_1 /TM_MII0_MODE0

B Id/Ots8

AD11 EXP_A_L_4 /TM_BOOT_OP0

B Id/Ots8

AD12 EXP_A_L_8 /TDM_TM_CLKSRC_

EN

B Id/Ots8

AD13 VSS — GND

AD14 EXP_A_U_15 / GPIO_8

B Ihd/Ots8

AD15 EXP_A_U_18 /GPIO_11

B Ihd/Ots8

AD16 No Connect — Ot16


AD18 VSS — GND

AD19 VSS — GND

AD20 USB1_REF B USBANLG

AD21 VSS — GND

AD22 VSS — GND

AD23 USB0_REF B USBANLG

AD24 No Connect I Iu

AD25 TDM_DR I Ihd

AD26 TDM_DX O Ihd/Ots8

AE1 VSS — GND

AE2 EXP_DQ_10 B I/Ots8



AE5 EXP_DM_0 O Ots8

AE6 EXP_NAND_WE_N /EXP_CS_4

O Ots8

AE7 EXP_NAND_CLE / GPIO_31

B Ihu/Ots8


M821xx Data Sheet

Continued Table 3-6 Pin List — 6-Row — M82190, M82192, M82194.


AE8 EXP_WE_N /EXP_RW_N

O Ots8

AE9 EXP_CS_N_2 O Ots8

AE10 EXP_A_L_0 /TM_MII0_MODE1

B Iu/Ots8

AE11 EXP_A_L_3 / TM_BOOT_OP1

B Id/Ots8

AE12 EXP_A_L_7 / PCIHOST_N /

HBBURSTEN_N

B Id/Ots8

AE13 EXP_A_L_11 /TM_GPBT_OP0 (on

reset)

B Id/Ots8

AE14 EXP_A_L_14 /TM_MII1_MODE1 (on

reset)

B Iu/Ots8

AE15 EXP_A_U_17 / GPIO_10

B Ihd/Ots8

AE16 EXP_A_U_21 / GPIO_14

B Ihd/Ots8

AE17 No Connect — Id/Ot8

AE18 VDDA_USB_1 — PWR

AE19 VSSA_USB1 — GND

AE20 VDD_USB1_P — PWR

AE21 VDDA_USB_0 — PWR

AE22 VSSA_USB0 — GND

AE23 VDD_USB0_P — PWR

AE24 No Connect — O

AE25 USB1_VBUS_STAT I I

AE26 VDDO_PCI — PWR

AF1 Unused corner — —

AF2 EXP_DQ_9 B I/Ots8

AF3 VDDO_EXP_0 — PWR

AF4 EXP_DQ_1 B I/Ots8

AF5 EXP_DM_1 O Ots8

AF6 EXP_NAND_ALE /GPIO_30

B Ihu/Ots8

AF7 VSS — GND


AF8 EXP_RE_N /EXP_STRB_N

O Ots8

AF9 EXP_CS_N_1 O Ots8

AF10 EXP_RDY_BSYN I Iu

AF11 VDDO_EXP — PWR

AF12 EXP_A_L_6 /PCIMODE / HBMODE_N

(on reset)

B Iu/Ots8

AF13 EXP_A_L_10 /HBBUSSIZE_1 (on

reset)

B Iu/Ots8

AF14 EXP_A_L_13 /TM_GPBT_OP2 (on

reset)

B Id/Ots8

AF15 VSS — GND

AF16 EXP_A_U_20 / GPIO_13

B Ihd/Ots8

AF17 No Connect — Id/Ot8

AF18 USB1_DM B USBDATA

AF19 USB1_DP B USBDATA

AF20 VSS_USB_P_0 B GND

AF21 USB0_DM B USBDATA

AF22 USB0_DP B USBDATA

AF23 VSS_USB_P_1 — GND

AF24 No Connect — O

AF25 VSS O GND

AF26 Unused Corner — —


M821xx Data Sheet


4.7 Interface Regions — 6-Row PackageFigure 4-3 Interface Regions — 6-Row Package (Top View Looking Through Package)

PCI / HostBus

VSS

DDR2

GMII

MII

VI/O

VDD

Ground

VDD

VI/O

Expansion Bus

VSSUSB

PoS / UTOPIA

VSS

GPIO

TDM

JTAGUARTSPII2C

M821xx Data Sheet


4.8 Pinout — 6-Row PackageThese devices include: M82190, M82192, M82194.

For a visual summary of interface regions, refer to Table 4-3 on page 62. For pin list, see Table 4-7 on page 78.

Table 4-5 M821xx Pins — 6-Row Package (Top View – Left Side)1 2 3 4 5 6 7 8 9 10 11 12 13

A VDDO_DDR_2

DDR_DATA_0

DDR_DATA_5

DDR_DATA_15

VSS DDR_DATA_13

DDR_DATA_23

DDR_DATA_18

VDDO_DDR2

DDR_CLKN

DDR_DQS_3

DDR_DATA_24

B DDR_CS_N_0

DDR_DQS_0

DDR_DATA_7

DDR_DATA_2

DDR_DQS_1

DDR_DATA_8

DDR_DATA_10

DDR_DQS_2

DDR_DATA_16

DDR_DATA_21

DDR_CLK

DDR_DATA_31

DDR_DATA_26

C GMII0_TXD7

GMII0_TXD6

DDR_DATA_1

VDDO_DDR2

DDR_ODT_0

DDR_DATA_4

DDR_DATA_14

VSS DDR_DATA_12

DDR_DATA_22

DDR_DATA_19

VDDO_DDR2

DDR_DATA_30

D VSS GMII0_TXD5

GMII0_MDC

DDR_DM_0

DDR_DATA_6

DDR_DATA_3

DDR_DM_1

DDR_DATA_9

DDR_DATA_11

DDR_DM_2

DDR_DATA_17

DDR_DATA_20

DDR_DM_3

E GMII0_TXD4

GNII0_TXD3

GMII0_TX_EN

GMII0_GTX_MDIO VSS VSS VSS VSS VSS VSS VSS VSS VSS

F GMII0_RXD0

GMII0_TXD2

VDDO_GMII0

GMII0_TX_ER VSS VSS VSS VSS VSS VSS VSS VSS VSS

GGMII0_RXD2

GMII0_RXD3

GMII0_RX_ER

GMII0_TX_D1

GMII0_GTX_CLK

GMII0_GTX_

REFCLKVSS VSS VSS VSS VSS VSS VSS

H VDDO_GMII0

GMII0_RXD6

GMII0_TXD0

GMII0_RXD1 VSS GMII0_

TX_CLK VSS VDD_PRE

VDD0_REF

VDD0_DDR2

VDD0_DDR2

VDD0_DDR2

VDD0_DDR2

J GMII0_RXD7

MII1_MDC

GMII0_RXD5

GMII0_RXD4

GMII0_RX_DV

GMII0_RX_CLK VSS VDDO_

GMII0_0 VDD VDD VDD VDD VDD

K MII1_MDIO

MII1_TXD2

VDDO_GMII0

MII1_TXD3

GMIIO_COL

GMIIO_CRS VSS VDDO_

GMII0 VDD VSS VSS VSS VSS

L MII1_RXD0

MII1_TX_EN

MII1_TXD1

MII1_TXD0

MII1_TX_CLK

TM_ETH_REFCLKO VSS VDDO_

GMII0 VDD VSS VSS VSS VSS

M VSS MII1_RXD3 MII1_COL

MII1_RXD2 VSS MII1_

RXD1 VSS VDDO_MII1 VDD VSS VSS VSS VSS

N MII1_RX_ER

MII1_RX_DV

MII1_TX_ER

MII1_CRS PLL_XI MII1_

RX_CLK VSS VDDO_MII1 VDD VSS_PLL

_0 VSS VSS VSS

P GPIO_1 GPIO_0 VDDO_MII1

VDD_PLL_0 GPIO_2 PLL_

XO VSS VDDO_MII1 VDD VSS_PLL

_1 VSS VSS VSS

R GPIO_3 EXP_DQ_31

TRISTATE_N

VDD_PLL_1

EXP_DQ_26 EXP_CLK VSS VDDO_

EXP VDD VSS VSS VSS VSS

T VDDO_EXP

EXP_DQ_30 GPIO_5 GPIO_4 VSS EXP_

DQ_21 VSS VDDO_EXP VDD VSS VSS VSS VSS

U EXP_DQ_27

EXP_DQ_25

EXP_DQ__29

EXP_DQ_28

EXP_DQ_11

EXP_DQ_15 VSS VDDO_

EXP VDD VSS VSS VSS VSS

V EXP_DQ_23

EXP_DQ22

VDDO_EXP

EXP_DQ_24

EXP_DQ_3 EXP_DQ_4 VSS VDDO_EXP VDD VDD VDD VDD VDD

W EXP_DQ_18

EXP_DQ_17

EXP_DQ_20

EXP_DQ_19

EXP_DM_0 EXP_DQ_1 VSS VDDO_EXP VDDO_EXP VDDO_EXP VDDO_EXP VDDO_EXP VDD0_EXP

Y VSS EXP_DM_3 EXP_DQ_16

EXP_DM_2 EXP_DM_1 EXP_DQ_0 VSS VSS VSS VSS VSS VSS VSS

AA EXP_DQ_12

EXP_DQ_10

EXP_DQ_14

EXP_DQ_13 VSS VSS EXP_NAND

_RE_NEXP_NAND

_WE_NEXP_NAND

_CLEEXP_A_L_5 EXP_A_U_

15PUI_ADR_

4PUI_DAT_

10

AB EXP_DQ_7

EXP_DQ_6

EXP_DQ_9

EXP_DQ_8 VSS VSS EXP_IRQ EXP_NAND

_ALEEXP_A_L_1 EXP_A_L

_10VSS PUI_DAT_

15 PUI_DAT_3

AC EXP_NAND_CS

EXP_NAND_RDY

EXP_DQ_5

EXP_DQ_2

EXP_CS_N_2 EXP_A_L_3 EXP_A_L_9 EXP_A_

_L_12EXP_A_U_17

PUMSTMODE_N

PUI_DAT_14

PUI_DAT_8

PUI_DAT_5

AD VSS EXP_RE_N

EXP_CS_N_1

EXP_CS_N_3

VDDO_EXP EXP_A_L_4 EXP_A_L_ 11

EXP_A_L_13 VDDO_EXP PUI_ADR

_3PUI_DAT_

13 PUI_DAT_9 VSS

AE EXP_WE_N EXP_ALE EXP_RDY_BYSN

EXP_A_L_0

EXP_A_L_6 EXP_A_L_ 14

EXP_A_U_16

EXP_AU_18

EXP_AU_21

PUI_ADR_2

PUI_ADR_0

PUI_DAT_11

PUI_DAT_6

AF EXP_CS_N_0

VDDO_EXP

EXP_A_L_2

EXP_A_L_7

EXP_A_L_8 VSS EXP_

A_U_19EXP_A_U_20

PUI_ADR_1

VDDO_EXP

PUI_DAT_12

PUI_DAT__7

1 2 3 4 5 6 7 8 9 10 11 12 13

M821xx Data Sheet


Table 4-6 M821xx Pins — 6-Row Package (Top View – Right Side)14 15 16 17 18 19 20 21 22 23 24 25 26

VSS DDR_A_11 DDR_A_6 DDR_A_2VDD0_DDR2

DDR_A_10

DDR_A_12

DDR_ODT_1 VSS TIM_

EVNT1PCI_AD_9

PCI_PAR A

DDR_DATA_29

DDR_A_5

DDR_A_1

DDR_A_3

DDR_BA_2

DDR_BA_0

DDR_CS_N_1

DDR_A_0

DDR_A_9 UART1TX PCI_

AD_4VDDO_

PCIPCI_

CBE_N_0 B

DDR_DATA_27

DDR_RAS_N VSS DDR_

CAS_NDDR_A_8

DDR_A_7

VDDO_DDR2

DDR_A_4 UART1RX UART0TX TIM_EVNT

0PCI_AD_5

PCI_AD_7 C

DDR_DATA_25

DDR_DATA_28

DDR_WE_N

DDR_CLKE

DDR_BA_1

DDR_A_13

JTAG0_TCK

TM_BSCN_JTAG

JTAG0_TDI

JTAG0_TDO

PCI_AD_3

PCI_AD_8

PCI_STOP_N D

VSS VSS VSS VSS VSS JTAG1_TMS

JTAG1_TRST_N VSS VSS UART0RX PCI_AD_1 PCI_AD_15 VSS E

VSS VSS VSS VSS JTAG1_TDO

JTAG1_TCK

JTAG1_TDI VSS VSS SPI_TXD PCI_AD_2 PCI_

TRDY_NPCI_

AD_14 F

VSS VSS VSS VSS VSS VSS VSS JTAG0_TMS

SPI_SS3_N SPI_RXD VDDO_PCI PCI_

AD_13PCI_

CBE_N_1 G

VDDO_DDR2

VDDO_DDR2

VDDO_DDR2

VDDO_DDR2

VDD_REF

VDD_PRE VSS JTAG0_TRST_N

SPI_SS1_N

SPI_SS2_N

PCI_AD_0

PCI_AD_12

PCI_SERR_N H

VDD VDD VDD VDD VDD VDDO_PCI VSS SPI_

SS0_N VSS VSS VSS PCI_PERR_N

VDDO_PCI J

VSS VSS VSS VSS VDD VDDO_PCI VSS I2C_

SDASPI_SCLK VSS PCI_

CBEN_N_2PCI_

DEVSEL_NPCI_

FRAME_N K

VSS VSS VSS VSS VDD VDDO_PCI VSS PCI_

AD_6I2C_SCL

PCI_AD_16

VSS PCI_AD_21

PCI_CBE_N_3 L


AD_10PCI_

AD_11PCI_

AD_17PCI_

AD_19PCI_

AD_18PCI_

AD_25 M


IRDY_N VSS PCI_AD_27

PCI_AD_20

PCI_AD_31 VSS N


AD_29PCI_

AD_23PCI_

INTB_NPCI_

INTA_NPCI_

REQ1_NPCI_

PCI_AD_22 P

VSS VSS VSS VSS VDD VDDO_PCI VSS RESET_N PCI_CLK PCI_

AD_30VDDO_

PCIPCI_

REQ2_NPCI_

GNT2_N R

VSS VSS VSS VSS VDD VDDO_PCI VSS TDM_CK

TM_PCI

_REFCLKO

PCI_AD_26

PCI_IDSEL

PCI_GNT1_N

PCI_AD_24 T

VSS VSS VSS VSS No Connect VSS VSS VSS VDDO

_PCITDM_

FSTDM_

DXPCI_

AD_28VDDO_

PCI U

VDD VDD VDD VDD No Connect

VDDA_USB_1

VDDA_USB_0

VSSA_USB0 VSS NoConnect

USB1_VBUS_STAT

TDM_DRUSB0_VBUS_STAT

V

VDD0_EXP VDD0_EXP VDD0_EXP VDD0_EXP VDD0_EXP VSSA_USB1

VSS VSS VSS VDD_USB0_P

VSS_USB_P_1

TM_EXT_RESET No Connect W

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS USB0_REF

No Connect VSS Y

PUI_SOCP PUO_CLK PUO_DAT_15

PUO_DAT_6

Pull Low

No Connect

No Connect VSS VSS VSS_USB

_P_OVDD_USB1

_PVSSA_USB0 USB0_DP AA

PUI_CLK VDDO_EXP PUO_DAT_10

TM_PUI_REFCLKO

No Connect VSS No

Connect VSS VSS VSS USB1_REF

VDDA_USB_0

USB0_DM AB

PUI_DAT_0 PUI_CTRL1

PUO_CTRL2

PUO_SOCP

PUO_DAT_11

PUO_DAT_7

PUO_DAT_1

PUO_DAT_0

PUO_ADDR_2 VSS VSS VSSA_

USB1USB1_DP AC

PUI_DAT_1 PUI_CTRL2

PUO_CTRL1

VDD0_EXP

PUO_DAT_12

PUO_DAT_8

PUO_DAT_2 VSS PUO

_ADR_3 VSS VSS VDDA_USB_1 USB1_DM AD

PUI_DAT_2

PUI_PRTY

PUI_MOD PUI_CTRL3 PUO_ERR PUO_MOD PUO_PRTY PUO_DAT

_13PUO_DAT

_5PUO_DAT_4

PUO_ ADR_4

PUO_ ADR_0 VDDO_EXP AE

PUI_DAT_4 VSS PUI_

EOPPUI_ERR

PUO_CTRL3

VDDO_EXP

PUO_EOP PUO_DAT_14

PUO_DAT_9 VSS PUO_

DAT_3PUO_ADR_1 AF

14 15 16 17 18 19 20 21 22 23 24 25 26

M821xx Data Sheet


4.9 Pin List — 6-Row PackageThese devices include: M82190, M82192, M82194.

Table 4-7 Pin List — 6-Row — M82190, M82192, M82194.


A1 Unused corner. — —





A6 VSS — GND





A11 DDR_CLKN O MEMIODIF

A12 DDR_DQS_3 B MEMIO


A14 VSS — GND


A16 DDR_A_6 O MEMIO

A17 DDR_A_2 O MEMIO




A21 DDR_ODT_1 O MEMIO

A22 VSS — GND

A23 TIM_EVNT1 /GPIO_16

B Ihu/Ots8

A24 PCI_AD_9 /HBD_9

B PCI

A25 PCI_PAR /HBA_2

B PCI












B11 DDR_CLK O MEMIODIF




B15 DDR_A_5 O MEMIO

B16 DDR_A_1 O MEMIO

B17 DDR_A_3 O MEMIO




B21 DDR_A_0 O MEMIO

B22 DDR_A_9 O MEMIO

B23 UART1TX / GPIO_23 B Ihu/Ots8

B24 PCI_AD_4 /HBD_4

B PCI

B25 VDDO_PCI — PWR

B26 PCI_CBE_N_0 / HBBE_N0

B PCI

C1 GMII0_TXD7 O Ot16

C2 GMII0_TXD6 O Ot16



M821xx Data Sheet




C5 DDR_ODT_0 O MEMIO



C8 VSS — GND







C15 DDR_RAS_N O MEMIO

C16 VSS — GND

C17 DDR_CAS_N O MEMIO

C18 DDR_A_8 O MEMIO

C19 DDR_A_7 O MEMIO


C21 DDR_A_4 O MEMIO

C22 UART1RX / GPIO_22

B Ihu/Ots8

C23 UART0_TX / GPIO_21

B Ihu/Ots8

C24 TIM_EVNT0 / GPIO_15

B Ihu/Ots8

C25 PCI_AD_5 /HBD_5

B PCI

C26 PCI_AD_7 /HBD_7

B PCI

D1 VSS O GND


D3 GMII0_MDC /RMII0_MDC /

RGMII0_MDC /MII0_MDC

O Ots8

D4 DDR_DM_0 O MEMIO




D7 DDR_DM_1 O MEMIO









D16 DDR_WE_N O MEMIO

D17 DDR_CLKE O MEMIOPL

D18 DDR_BA_1 O MEMIO

D19 DDR_A_13 O MEMIO

D20 JTAG0_TCK I Ihu

D21 TM_BSCN_JTAG I Id

D22 JTAG0_TDI I Ihu

D23 JTAG0_TDO O Ots8

D24 PCI_AD_3 /HBD_3

B PCI

D25 PCI_AD_8 /HBD_8

B PCI

D26 PCI_STOP_N /HBFIFO

B PCI

E1 GMII0_TXD4 O Ot16

E2 GMII0_TXD3 /RGMII0_TXD3 /

MII0_TXD3

O Ot16

E3 GMII0_TX_EN /RMII0_TX_EN /RGMII0_TXC /MII0_TX_EN

O Ot16

E4 GMII0_MDIO /RMII0_MDIO /

RGMII0_MDIO /MII0_MDIO

B I/Ots8

E5 VSS — GND

E6 VSS — GND

E7 VSS — GND


M821xx Data Sheet



E8 VSS — GND

E9 VSS — GND

E10 VSS — GND

E11 VSS — GND

E12 VSS — GND

E13 VSS — GND

E14 VSS — GND

E15 VSS — GND

E16 VSS — GND

E17 VSS — GND

E18 VSS — GND

E19 JTAG1_TMS I Ihu

E20 JTAG1_TRST_N I Ihu

E21 VSS — GND

E22 VSS — GND

E23 UART0_RX /GPIO_20

B Ihu/Ots8

E24 PCI_AD_1 /HBD_1

B PCI

E25 PCI_AD_15 /HBD_15

B PCI

E26 VSS — GND

F1 GMII0_RXD0 /RMII0_RXD0 /


I I

F2 GMII0_TXD2 / RGMII0_TXD2 /

MII_TXD2

O Ot16

F3 VDDO_GMII0 — PWR

F4 GMII0_TX_ER /RGMII0_TX_CTL /

MII0_TX_ER

O Ot16

F5 VSS — GND

F6 VSS — GND

F7 VSS — GND

F8 VSS — GND


F9 VSS — GND

F10 VSS — GND

F11 VSS — GND

F12 VSS — GND

F13 VSS — GND

F14 VSS — GND

F15 VSS — GND

F16 VSS — GND

F17 VSS — GND

F18 JTAG1_TDO O Ots8

F19 JTAG1_TCK I Ihu

F20 JTAG1_TDI I Ihu

F21 VSS — GND

F22 VSS — GND

F23 SPI_TXD / GPIO_25

B Ihu/Ots8

F24 PCI_AD_2 /HBD_2

B PCI

F25 PCI_TRDY_N /HBCS_N

B PCI

F26 PCI_AD_14 /HBD_14

B PCI

G1 GMII0_RXD2 /RMII0_PHY_DPX /


I I

G2 GMII0_RXD3 /RMII0_PHY_SPEED /


I I

G3 GMII0_RX_ER /RMII0_RX_ER /

MII0_RX_ER

I I

G4 GMII0_TXD1 /RMII0_TXD1 /


O Ot16

G5 GMII0_GTX_CLK O Ot16


M821xx Data Sheet



G6 GMII0_GTX_REFCLK

I I

G7 VSS — GND

G8 VSS — GND

G9 VSS — GND

G10 VSS — GND

G11 VSS — GND

G12 VSS — GND

G13 VSS — GND

G14 VSS — GND

G15 VSS — GND

G16 VSS — GND

G17 VSS — GND

G18 VSS — GND

G19 VSS — GND

G20 VSS — GND

G21 JTAG0_TMS I Ihu

G22 SPI_SS3_N O Ots8

G23 SPI_RXD /GPIO_26

B Ihd/Ots8

G24 VDDO_PCI — PWR

G25 PCI_AD_13 /HBD_13

B PCI

G26 PCI_CBE_N_1 /HBBE_N1

B PCI

H1 VDDO_GMII0 — PWR

H2 GMII0_RXD6 I I

H3 GMII0_TXD0 /RMII0_TXD0 /


O Ot16

H4 GMII0_RXD1 /RMII0_RXD1 /


I I

H5 VSS — GND


H6 GMII0_TX_CLK /RGMII0_REFCLK /

MII0_TX_CLK

I I

H7 VSS — GND

H8 VDD_PRE — PWR

H9 VDD_REF — PWR









H18 VDD_REF — PWR

H19 VDD_PRE — PWR

H20 VSS — GND

H21 JTAG0_TRST_N I Ihu

H22 SPI_SS1_N /GPIO_28

B Ihu/Ots8

H23 SPI_SS2_N O Ots8

H24 PCI_AD_0 /HBD_0

B PCI

H25 PCI_AD_12 /HBD_12

B PCI

H26 PCI_SERR_N /HBW_N

B PCI

J1 GMII0_RXD7 I I

J2 MII1_MDC /RMII1_MDC /RGMII1_MDC

O Ots8

J3 GMII0_RXD5 I I

J4 GMII0_RXD4 I I

J5 GMII0_RX_DV /RMII0_CRS_DV /

RGMII0_RX_CTL /MII0_RX_DV

I I


M821xx Data Sheet



J6 GMII0_RX_CLK /RMII0_REFCLK /RGMII0_RXC /MII0_RX_CLK

I I

J7 VSS — GND


J9 VDD — PWR

J10 VDD — PWR

J11 VDD — PWR

J12 VDD — PWR

J13 VDD — PWR

J14 VDD — PWR

J15 VDD — PWR

J16 VDD — PWR

J17 VDD — PWR

J18 VDD — PWR


J20 VSS — GND

J21 SPI_SS0_N /GPIO_27

B Ihu/Ots8

J22 VSS — GND

J23 VSS — GND

J24 VSS — GND

J25 PCI_PERR_N /HBWAIT_N

B PCI


K1 MII1_MDIO /RMII1_MDIO /RGMII1_MDIO

B I/Ots8

K2 MII1_TXD2 /RGMII1_TXD2

O Ot16


K4 MII1_TXD3RGMII1_TXD3

O Ot16

K5 GMII0_COL /MII0_COL

I I


K6 GMII0_CRS /RMII0_PHY_LINK /

MII0_CRS

I I

K7 VSS — GND


K9 VDD — PWR

K10 VSS — GND

K11 VSS — GND

K12 VSS — GND

K13 VSS — GND

K14 VSS — GND

K15 VSS — GND

K16 VSS — GND

K17 VSS — GND

K18 VDD — PWR

K19 VDDO_PCI — PWR

K20 VSS — GND

K21 I2C_SDA /GPIO_19

B Ihu/Ots8

K22 SPI_SCLK /GPIO_24

B Ihu/Ots8

K23 VSS B GND

K24 PCI_CBE_N_2 /HBBE_N2

B PCI

K25 PCI_DEVSEL_N /HBA_3

B PCI

K26 PCI_FRAME_N /HBA_4

B PCI

L1 MII1_RXD0 /RMII1_RXD0 /RGMII1_RXD0

I I

L2 MII1_TX_EN /RMII1_TX_EN /RGMII1_TXC

O Ot16

L3 MII1_TXD1 / RMII1_TXD1 /RGMII1_TXD1

O Ot16


M821xx Data Sheet



L4 MII1_TXD0 /RMII1_TXD0 /RGMII1_TXD0

O Ot16

L5 MII1_TX_CLK /RGMII1_REFCLK

I I

L6 TM_ETH_REFCLKO O Ot16

L7 VSS — GND


L9 VDD PWR

L10 VSS — GND

L11 VSS — GND

L12 VSS — GND

L13 VSS — GND

L14 VSS — GND

L15 VSS — GND

L16 VSS — GND

L17 VSS — GND

L18 VDD — PWR

L19 VDDO_PCI — PWR

L20 VSS — GND

L21 PCI_AD_6 /HBD_6

B PCI

L22 I2C_SCL /GPIO_18

B Ihu/Ots8

L23 PCI_AD_16 /HBD_16

B PCI

L24 VSS — GND

L25 PCI_AD_21 /HBD_21

B PCI

L26 PCI_CBE_N_3 /HBBE_N3

B PCI

M1 VSS — GND

M2 MII1_RXD3 /RMII1_PHY_SPEED /

RGMII1_RXD3

I I

M3 MII1_COL I I/Ot8


M4 MII1_RXD2 /RMII1_PHY_DPX /

RGMII_RXD2

I I

M5 VSS — GND

M6 MII1_RXD1 /RMII1_RXD1 /RGMII1_RXD1

I I

M7 VSS — GND

M8 VDDO_MII1 — PWR

M9 VDD — PWR

M10 VSS — GND

M11 VSS — GND

M12 VSS — GND

M13 VSS — GND

M14 VSS — GND

M15 VSS — GND

M16 VSS — GND

M17 VSS — GND

M18 VDD — PWR

M19 VDDO_PCI — PWR

M20 VSS — GND


B PCI


B PCI


B PCI


B PCI


B PCI


B PCI

N1 MII1_RX_ER /RMII1_RX_ER

I I

N2 MII1_RX_DV /RMII1_CRS_DV /RGMII1_RX_CTL

I I


M821xx Data Sheet



N3 MII1_TX_ER //RGMII1_TX_CTL

O Ot16

N4 MII1_CRS /RMII1_PHY_LINK

I I

N5 PLL_XI I OSCL

N6 MII1_RX_CLK /RMII1_REFCLK /

RGMII1_RXC

l I

N7 VSS — GND

N8 VDDO_MII1 — PWR

N9 VDD — PWR

N10 VSS_PLL_0 — GND

N11 VSS — GND

N12 VSS — GND

N13 VSS — GND

N14 VSS — GND

N15 VSS — GND

N16 VSS — GND

N17 VSS — GND

N18 VDD — PWR

N19 VDDO_PCI — PWR

N20 VSS — GND

N21 PCI_IRDY_N /HBA_6

B PCI

N22 VSS — GND


B PCI


B PCI


B PCI

N26 VSS — GND

P1 GPIO_1 B Ihu/Ots16



P4 VDD_PLL_0 — PWR



P6 PLL_XO O OSCL

P7 VSS — GND


P9 VDD — PWR

P10 VSS_PLL_1 — GND

P11 VSS — GND

P12 VSS — GND

P13 VSS — GND

P14 VSS — GND

P15 VSS — GND

P16 VSS — GND

P17 VSS — GND

P18 VDD — PWR

P19 VDDO_PCI — PWR

P20 VSS — GND


B PCI


B PCI

P23 PCI_INTB_N O PCI

P24 PCI_INTA_N /HBINT_N

O PCI

P25 PCI_REQ1_N B PCI


B PCI

R1 GPIO_3 B Ihu/Ots16

R2 EXP_DQ_31 B I/Ots8

R3 TRISTATE_N I Iu

R4 VDD_PLL_1 O PWR

R5 EXP_DQ_26 B I/Ots8

R6 EXP_CLK O Ot8

R7 VSS — GND

R8 VDDO_EXP — PWR

R9 VDD — PWR

R10 VSS — GND


M821xx Data Sheet



R11 VSS — GND

R12 VSS — GND

R13 VSS — GND

R14 VSS — GND

R15 VSS — GND

R16 VSS — GND

R17 VSS — GND

R18 VDD — GND

R19 VDDO_PCI I PWR

R20 VSS — GND

R21 RESET_N I Ih

R22 PCI_CLK / HBCLK

I PCI

R23 PCI_AD_30 /HBD_30

B PCI


R25 PCI_REQ2_N I PCI

R26 PCI_GNT2_N O PCI

T1 VDDO_EXP — PWR

T2 EXP_DQ_30 B I/Ots8

T3 GPIO_5 B Ihu/Ots16

T4 GPIO_4 B Ihu/Ots16

T5 VSS — GND

T6 EXP_DQ_21 B I/Ots8

T7 VSS — GND

T8 VDDO_EXP — PWR

T9 VDD — PWR

T10 VSS — GND

T11 VSS — GND

T12 VSS — GND

T13 VSS — GND

T14 VSS — GND

T15 VSS — GND

T16 VSS — GND

T17 VSS — GND


T18 VDD — PWR

T19 VDDO_PCI — PWR

T20 VSS — GND

T21 TDM_CK / TM_TDM_REFCLKO

B Ih/Ot16

T22 TM_PCI_REFCLKO O Ot16


B PCI

T24 PCI_IDSEL /HBA_5

I PCI

T25 PCI_GNT1_N /HBLAST_N

B PCI


B PCI

U1 EXP_DQ_27 B I/Ots8






U7 VSS — GND

U8 VDDO_EXP — PWR

U9 VDD — PWR

U10 VSS — GND

U11 VSS — GND

U12 VSS — GND

U13 VSS — GND

U14 VSS — GND

U15 VSS — GND

U16 VSS — GND

U17 VSS — GND

U18 No Connect — USBANLG

U19 VSS — GND

U20 VSS — GND

U21 VSS — GND



M821xx Data Sheet



U23 TDM_FS /TM_TDM_FSO

B I/Ot8

U24 TDM_DX O Ihd/Ots8

U25 PCI_AD_28 /HBD_28

B PCI


V1 EXP_DQ_23 B I/Ots8


V3 VDDO_EXP — PWR




V7 VSS — GND

V8 VDDO_EXP — PWR

V9 VDD — PWR

V10 VDD — PWR

V11 VDD — PWR

V12 VDD — PWR

V13 VDD — PWR

V14 VDD — PWR

V15 VDD — PWR

V16 VDD — PWR

V17 VDD — PWR

V18 No Connect — USBANLG

V19 VDDA_USB1 — PWR

V20 VDDA_USB_0 — PWR

V21 VSSA_USB0 — GND

V22 VSS — GND

V23 No Connect I Iu

V24 USB1_VBUS_STAT I I

V25 TDM_DR I Ihd

V26 USB0_VBUS_STAT I I

W1 EXP_DQ_18 B I/Ots8





W5 EXP_DM_0 O Ots8


W7 VSS — GND

W8 VDDO_EXP — PWR

W9 VDDO_EXP — PWR










W19 VDDA_USB_1 — PWR

W20 VSS — GND

W21 VSS — GND

W22 VSS — GND

W23 VDD_USB0_P B PWR

W24 VSS_USB_P_1 — GND

W25 TM_EXT_RESET /GPIO_17

B Ihd/Ots8

W26 No Connect — O

Y1 VSS — GND

Y2 EXP_DM_3 O Ots8

Y3 EXP_DQ_16 B I/Ots8

Y4 EXP_DM_2 O Ots8

Y5 EXP_DM_1 O Ots8

Y6 EXP_DQ_0 B I/Ots8

Y7 VSS — GND

Y8 VSS — GND

Y9 VSS — GND

Y10 VSS — GND


M821xx Data Sheet



Y11 VSS — GND

Y12 VSS — GND

Y13 VSS — GND

Y14 VSS — GND

Y15 VSS — GND

Y16 VSS — GND

Y17 VSS — GND

Y18 VSS — GND

Y19 VSS — GND

Y20 VSS — GND

Y21 VSS — GND

Y22 VSS — GND

Y23 VSS — GND

Y24 USB0_REF B USBANLG

Y25 No Connect — O

Y26 VSS — GND





AA5 VSS — GND

AA6 VSS — GND

AA7 EXP_NAND_RE_N O Ots8

AA8 EXP_NAND_WE_N /EXP_CS_4_N

O Ots8

AA9 EXP_NAND_CLE /GPIO_31

B Ihu/Ots8

AA10 EXP_A_L_5 /TM_GBPT_OP3

B Iu/Ots8

AA11 EXP_A_U_15 /GPIO_8

B Ihd/Ots8

AA12 PUI_ADR_4 B Ih/Ots12

AA13 PUI_DAT_10 I Ih

AA14 PUI_SOCP I Ih

AA15 PUO_CLK I Ih


AA16 PUO_DAT_15 O Ih/Ots12

AA17 PUO_DAT_6 O Ih/Ots12

AA18 Pull Low — Ihd

AA19 No Connect — Id/Ot8

AA20 No Connect — Id/Ot8

AA21 VSS — GND

AA22 VSS — GND

AA23 VSS_USB_P_0 — GND

AA24 VDD_USB1_P — PWR

AA25 VSSA_USB0 — GND

AA26 USB0_DP B USBDATA





AB5 VSS — GND

AB6 VSS — GND

AB7 EXP_IRQ /GPIO_7

B Ihu/Ots16

AB8 EXP_NAND_ALE /GPIO_30

B Ihu/Ots8

AB9 EXP_A_L_1 /TM_MII0_MODE0

B Id/Ots8

AB10 EXP_A_L_10 / HBBUSSIZE_1 (on

reset)

B Iu/Ots8

AB11 VSS — GND

AB12 PUI_DAT_15 I Ih

AB13 PUI_DAT_3 I Ih

AB14 PUI_CLK I Ih

AB15 VDDO_EXP — PWR

AB16 PUO_DAT_10 O Ih/Ots12

AB17 TM_PUI_REFCKO O Ot16

AB18 No Connect — Id/Ot8

AB19 VSS — GND

AB20 No Connect — Id/Ot8


M821xx Data Sheet



AB21 VSS — GND

AB22 VSS — GND

AB23 VSS — GND

AB24 USB1_REF B USBANLG

AB25 VDDA_USB_0 — PWR

AB26 USB0_DM B USBDATA

AC1 EXP_NAND_CS /GPIO_29

B Ihu/Ots8

AC2 EXP_NAND_RDY / BSYN /GPIO_6

B Ihu/Ots16




AC6 EXP_A_L_3 /TM_BOOT_OP1

B Id/Ots8

AC7 EXP_A_L_9 /HBBUSSIZE_0

B Iu/Ots8


B Id/Ots8


B Ihd/Ots8

AC10 PU_MSTMODE_N I Ihu

AC11 PUI_DAT_14 I Ih

AC12 PUI_DAT_8 I Ih

AC13 PUI_DAT_5 I Ih

AC14 PUI_DAT_0 I Ih

AC15 PUI_CTRL1 I Ih

AC16 PUO_CTRL2 I Ih

AC17 PUO_SOCP O Ots12

AC18 PUO_DAT_11 O Ih/Ots12




AC22 PUO_ADR_2 B Ih/Ots12

AC23 VSS — GND


AC24 VSS — GND

AC25 VSSA_USB1 — GND

AC26 USB1_DP B USBDATA

AD1 VSS — GND

AD2 EXP_RE_N /EXP_STRB_N

O Ots8

AD3 EXP_CS_N_1 O Ots8

AD4 EXP_CS_N_3 O Ots8


AD6 EXP_A_L_4 /TM_BOOT_OP0

B Id/Ots8

AD7 EXP_A_L_11 /TM_GPBT_OP0 (on

reset)

B Id/Ots8

AD8 EXP_A_L_13TM_GPBT_OP2 (on

reset)

B Id/Ots8


AD10 PUI_ADR_3 B Ih/Ots12

AD11 PUI_DAT_13 I Ih

AD12 PUI_DAT_9 I Ih

AD13 VSS — GND

AD14 PUI_DAT_1 I Ih

AD15 PUI_CTRL2 O Ih/Ots12

AD16 PUO_CTRL1 O Ih/Ots12


AD18 PUO_DAT_12 O Ih/Ots12



AD21 VSS — GND

AD22 PUO_ADR_3 B Ih/Ots12

AD23 VSS — GND

AD24 VSS — GND

AD25 VDDA_USB_1 — PWR

AD26 USB1_DM B USBDATA


M821xx Data Sheet



AE1 EXP_WE_N /EXP_RW_N

O Ots8

AE2 EXP_ALE B Ots8

AE3 EXP_RDY_BSYN I Iu

AE4 EXP_A_L_0 /TM_MII0_MODE1

B Iu/Ots8

AE5 EXP_A_L_6 :PCIMODE / HBMODE_N

(on reset)

B Iu/Ots8

AE6 EXP_A_L_14 / TM_MII1_MODE1

B Iu/Ots8

AE7 EXP_A_U_16 /GPIO_9

B Ihd/Ots8


B Ihd/Ots8


B Ihd/Ots8

AE10 PUI_ADR_2 B Ih/Ots12

AE11 PUI_ADR_0 B Ih/Ots12

AE12 PUI_DAT_11 I Ih

AE13 PUI_DAT_6 I Ih

AE14 PUI_DAT_2 I Ih

AE15 PUI_PRTY I Ih

AE16 PUI_MOD I Ih

AE17 PUI_CTRL3 B Ih/Ots12

AE18 PUO_ERR O Ots12

AE19 PUO_MOD O Ots12

AE20 PUO_PRTY O Ots12

AE21 PUO_DAT_13 O Ots12



AE24 PUO_ADR_4 B Ih/Ots12

AE25 PUO_ADR_0 B Ih/Ots12

AE26 VDDO_EXP — PWR


AF2 EXP_CS_N_0 O Ots8



AF4 EXP_A_L_2 /TM_MII1_MODE0

B Id/Ots8

AF5 EXP_A_L_7 /PCIHOST_N /

HBBURSTEN_N

B Id/Ots8

AF6 EXP_A_L_8 /TDM_TM_CLKSRC_

EN

B Id/Ots8

AF7 VSS — GND

AF8 EXP_A_U_19 /GPIO_12

B Ihd/Ots8

AF9 EXP_A_U_20 /GPIO_13

B Ihd/Ots8

AF10 PUI_ADR_1 B Ih/Ots12


AF12 PUI_DAT_12 I Ih

AF13 PUI_DAT_7 I Ih

AF14 PUI_DAT_4 I Ih

AF15 VSS — GND

AF16 PUI_EOP I Ih

AF17 PUI_ERR I Ih

AF18 PUO_CRTL3 B Ih/Ots12


AF20 PUO_EOP O Ots12

AF21 PUO_DAT_14 O Ih/Ots12


AF23 VSS — GND


AF25 PUO_ADR_1 B Ih/Ots12



M821xx Data Sheet


4.10 Design Notes

No Connect pins must remain unconnected. Pull Low pins must be connected to ground.

For reliable operation, connect unused inputs to an appropriate signal level.

M821xx devices require four DC power levels. External to the device they share a common ground plane. Analog power and ground connections to USB and PLL pins require separate treatment. For details on power sequencing, refer to Section 42.1 Power Supply Sequencing.

NOTE: The Mindspeed Comcerto Device is a multi-core system-on-chip (SOC) device operating above 400 MHz. Appropriate power supply and layout considerations are required to guarantee optimum performance.

Mindspeed provides schematic and layout review. Mindspeed HIGHLY RECOMMENDS customers submit their designs to Mindspeed for a complete and confidential review.

Customer designs MUST meet the Power Supply, Thermal, and Layout considerations described in the:

• M821xx Hardware Requirements App Note (821xx-APP-002)

• M821xx Thermal Application Note (821xx-APP-001)

M821xx Data Sheet


4.11 I/O PAD TypesNOTE: Mindspeed provides IBIS files for M821xx devices. Contact your FAE or sales

representative.

Table 4-8 I/O Type Descriptions

I/O Type Description

USBDATA USB 2.0 compliant analog data

USBANALOG USB 2.0 compliant analog

I Digital input, CIN = 8pF

Id/Ots8 Digital Input, 75 kΩ pull-down, CIN = 8pF / Digital output, 3-State, slew rate, 8mA

Ihd/Ots8 Digital Input with hysterisis, 75 kΩ pull-down, CIN = 8pF / Digital output, 3-State, slew rate, 8mA

Iu/Ots8 Digital Input, 75 kΩ pull-up, CIN = 8pF / Digital output, 3-state, slew rate, 8mA

Ihu/Ots8 Digital Input with hysterisis, 75 kΩ pull-up, CIN = 8pF / Digital output, 3-state, slew rate, 8mA

Ihu/Ots16 Digital Input with hysterisis, 75 kΩ pull-up. CIN = 8pF / Digital output, 3-state, slew rate, 16mA

I/Ot8 Digital input, CIN = 8pF / Digital output, 3-State, 8mA

Ih/Ot16 Digital input with hysteresis, CIN = 8pF / Digital output, 3-State, 16mA

I/Ots8 Digital input, CIN = 8pF / Digital output, 3-State, Slew Rate, 8mA

Ih/Ots12 Digital input,CIN = 8pF / Digital output, 3-State, Slew Rate, 12mA

Id/Ot8 Digital input, 75 kΩ pull-down, CIN = 8pF / Digital output, 3-State, 8mA

Id Digital input

Ihd Digital input with hysteresis, 75 kΩ pull-down, CIN = 8pF

Iu Digital input, 75 kΩ pull-up, CIN = 8pF

Ihu Digital input with hysteresis, 75 kΩ pull-up, CIN = 8pF

I Digital input, CIN = 8pF

Ih Digital input with hysteresis, CIN = 8pF

Ot8 Digital output, 3-State. 8mA

Ot16 Digital output, 3-State, 16mA

Ots8 Digital output, 3-State, slew control, 8m

O Digital output

Oscl Oscillator I/O

PCI PCI compatible, input with hysterisis, CIN = 8pF / output with 3-state, slew control, 66MHz capable

MEMIOPL STTL 1.8 I/O with 75 kΩ pull-down; 6.7 mA/ 13.4 mA

MEMIO STTL 1.8 I/O 6.7 mA/ 13.4 mA

MEMIODIF STTL 1.8 I/O differential 6.7 mA/ 13.4 mA

M821xx Data Sheet


4.12 Quick Signal Reference

4.12.1 Expansion BusFor more on this topic, refer to Section 7.0 Expansion Bus Interface.

Table 4-9 Expansion Bus Signal Summary

Symbol Dir. Name//Function

EXP_CLK O Expansion Bus Clock to peripheral devices.

EXP_CS#[3:0] O Expansion Bus Chip Selects enable or disable targeted peripheral devices. Chip select 0 dedicated to external boot flash when used.

EXP_RE# /EXP_STRB#

O Expansion Bus Read Enable asserted to indicate read operation.Expansion Bus Strobe indicates command.

EXP_NAND_RE# O NAND Flash Read Enable goes low to indicate a read operation from flash device.

EXP_WE# /EXP_RW#

O Expansion Bus Write Enable indicates a writer operation to a peripheral, Read/Write Enable supports Strobe Mode.

EXP_NAND_WE#/EXP_CS#[4]

O Expansion Bus NAND Flash Write Enable goes low to indicate a write to NAND flash. When NAND flash not used, may be sued as Chip Select. NOTE: NAND Flash selected through GPIO.

EXP_DM[3:0] O Expansion Bus Data Mask indicates active bytes to peripheral during a write.

EXP_RDY / BSY# I Expansion Bus Ready / Busy Status. When low indicates transaction in process. When high indicates ready for next transaction.

EXP_A(21:0) O Expansion Bus Address Bus specifies memory location along with EXP_DM[3:0]. Selects 16M of memory per chip select. Internally 24 address bits are supported but only 22 are outputted.

EXP_ALE O Expansion Bus Address Latch Enable used to control address latching on peripheral bus when multiplexed address/data bus in use.

EXP_DQ B Expansion Bus Data Bus.Configured to 8, 18 or 32 active bits. (32 bits not supported in all versions of M821xx)

M821xx Data Sheet


4.12.2 DDR2 SDRAMFor more on this topic, refer to Section 9.0 DDR2 SDRAM Interface.

Table 4-10 DDR SDRAM Signal Summary

4.12.3 WAN (Ethernet0) and LAN (Ethernet0)For more on this topic, refer to Section 11.0 Ethernet Interface.

4.12.3.1 GMII ModeTable 4-11 GMII Signal Summary

Symbol Dir, Name/Function

DDR_CLKDDR_CLK#

O Differential clock outputs to memory.

DDR_CKE O Enables memory clock.

DDR_CS#[1:0] O Goes low to enable memory device.

DDR_RAS# O Memory row address strobe.

DDR_CAS# O Memory column address strobe.

DDR_WE# O Memory write enable.

DDR_DM[3:0] O Data byte mask to memory.

DDR_BA[4:0 O Memory bank select.

DDR_A[13:0] O Memory address bus (fewer bits may be used).

DDR_DATA[31:0] B Memory data bus. (optionally,16 bits may be used)

DDR_DQS[3:0] B Data strobe used to latch reads and sample writes from memory device.

DDR_ODT O On-Die termination for DDR2 SDRAMs.

Symbol Dir. Name/Function

GMII_GTX_CLK O Gigabit transfer bit clock. 125 MHz in 1000-Base mode.

GMII_GTX_REFCLK I Gigabit reference clock. 125 MHz.

GMII_TX_CLK I Transmit clock. 25 MHz in100-Base node, and 2,5 MHz in 10-Base mode.

GMII_TXD[7:0] O GMII transmit data.

GMII_TX_EN O GMII transmit enable. Indicates valid data on GMII_TXD.

GMII_TX_ER O GMII transmit error. Request out for transmit error condition.

GMII_RX_CLK I GMII Receive clock. 125 MHz in 1000-Base Mode, 25 MHz in 100-Base Mode, and 2.5 MHz in 10-Base Mode.

GMII_RXD[7:0] I GMII receive data.

GMII_RX_DV I GMII receive data valid.

GMII_RX_ER I GMII receive error detected.

GMII_CRS I GMII carrier sense.

M821xx Data Sheet


4.12.3.2 RGMII ModeTable 4-12 RGMII Signal Summary

4.12.3.3 MII ModeTable 4-13 MII Signal Summary

GMII_COL I GMII collision detect.

GMII_MDC O Serial management interface clock.

GMII_MDIO B Serial management interface data.


RGMII_REFCLK I 125 MHz reference clock.

RMII_TXC RGMII transmit clock: 125 MHz, 25 MHz, or 2.5 MHz.

RGMII_TXD[3:0] O RGMII transmit data.

RGMII_RXC O RGMII receive clock.

RGMII_RX_CTL I RGMII receive control.

RGMII_RXD[3:0] I RGMII receive data.

RGMII_TX_CTL I RGMII transmit control.

RGMII_MDC O Serial management interface clock.

RGMII_MDIO B Serial management interface data.


MII_TX_CLK I Transmit clock. 25 MHz in 100-Base Mode, and 2.5 MHz in 10-Base Mode.

MII_TXD[3:0] O MII transmit data.

MII_TX_EN O MII transmit enable.

MII_TX_ER O MII transmit error.

MII_RX_CLK I MII receive clock

MII_RXD[3:0] I MII receive data.

MII_RX_DV I MII receive data valid.

MII_RX_ER I MII receive error detected.

MII_CRS I MII carrier sense.

MII_COL I MII collision detect.

MII_MDC O Serial management interface clock.

MII_MDIO B Serial management interface data.


M821xx Data Sheet


4.12.3.4 RMII ModeTable 4-14 RMII Signal Summary

4.12.4 UTOPIA / PoSFor more on this topic, refer to Section 11.0 Ethernet Interface

Table 4-15 UTOPIA / PoS Signal Summary


RMII_REFCLK I Reference clock. Continuous 50 MHz reference clock.

RMII_TX_EN O Transmit enable.

RMII_TXD[1:0] O Transmit data.

RMII_CRS_DV I Carrier sense / Receive data valid. Asserted by PHY when medium is non-idle.

RMII_RX_ER I Receive error detected.

RMII_RXD[1:0] I Receive data.

RMII_PHY_LINK I Receive PHY link detect.

RMII_PHY_DPX I Receive PHY duplex.

RMII_PHY_SPEED I PHY speed.

RMII_MDC O Serial management interface clock.

RMII_MDIO B Serial management interface data.

Symbol Dir. Name /Function

PU_MSTMODE# I Master# or Slave Mode Select.

PUO_CLK I Master Mode Data Transfer / Synchronization Clock

Slave Mode Data Transfer / Synchronization Clock

PUO_ADR[4:0] B Master Mode Address

Slave Mode Address

PUO_DAT[15:0] O Master Mode Data

Slave Mode Data

PUO_PRTY O Master Mode Parity

Slave Mode Parity

PUO_SOCP O Master Mode Start of Cell/Packet

Slave Mode Start of Cell/Packet

PUO_EOP O End of Packet

PUO_MOD O Modulo

PUO_ERR O Error

PUO_CTRL1 O Master Mode Multifunction Signal

Slave Mode Multifunction Signal

M821xx Data Sheet


PUO_CTRL2 I Master Mode Multifunction Signal.

Slave Mode Multifunction Signal.

PUO_CTRL3 B Master Mode Multifunction Signal.

Slave Mode Multifunction Signal.

PUI_CLK I Master Mode Data Transfer / Synchronization Clock

Slave Mode Data Transfer / Synchronization Clock

PUI_ADR B Master Mode Address

Slave Mode Address

PUI_DAT I Master Mode Data Signal

Slave Mode Data Signal

PUI_PRTY I Master Mode Parity

Slave Mode Parity

PUI_SOCP I Master Mode Start of Cell or Packet

Slave Mode Start of Cell or Packet

PUI_EOP I End of Packet

PUI_MOD I Modulo

PUI_ERR I Error (not used in Utopia mode)

PUI_CTRL1 I Master Mode Multifunction Signal


PUI_CTRL2 O Master Mode Multifunction Signal


PUI_CTRL3 B Master Mode Multifunction Signal


Symbol Dir. Name /Function

M821xx Data Sheet


4.12.5 PCI / µP BusFor more on this topic, refer to Section 15.0 PCI/µP Interface

Table 4-16 PCI / µP Bus Signal Summary


PCIMODE /HBMODE#

I Microprocessor Bus Mode Select.

PCI_HOST# /HBBURSTEN#

I PCI Host Mode Select.

Microprocessor Bus Burst Enable.

Reserved /HBBUSSIZE[1:0]

I Reserved.

Microprocessor Bus Size.

PCIREQ2 /Reserved

I Request 2

Reserved.

PCIGNT2 /Reserved

O Grant 2

Reserved

PCI_PERR# /HBWAIT#

B Parity Error

Microprocessor Bus Wait

PCI_CLK /HBCLK

I PCI Bus Clock

Microprocessor Bus Clock

PCI_STOP# /HBFIFO

B Stop

Microprocessor Bus FIFO Select

PCI_IRDY# /HBA6

B Initiator Ready

Microprocessor Bus Address

PCI_IDSEL /HBA5

I Initialization Device

Microprocessor Bus Address Bit 5

PCI_FRAME# /HBA4

B Cycle Frame


PCI_DEVSEL# /HBA3

B Device Select


PCI_PAR /HBA2

B Parity


PCI_AD[31:0] /HBD[31:0]

B PCI Address and Data

Microprocessor Data

PCI_CBE#[3:0] /HBBE#[3:0]

B PCI Command and Byte Enable

Microprocessor Bus Byte Enable or Address Bit 0

PCI_TRDY# /HBCS#

B Target Ready

Microprocessor Bus Chip Select

M821xx Data Sheet


4.12.6 TDM BusFor more on this topic, refer to Section 21.0 TDM Bus Interface Description

Table 4-17 TDM Bus Signal Summary

4.12.7 Serial Peripheral Interface (SPI)For more on this topic, refer to Section 19.0 Serial Peripheral Interface (SPI)

Table 4-18 SPI Signal Summary

PCI_SERR# /HBW#

B System Error

Microprocessor Bus Write

PCI_GNT1# /HBLAST#

B Grant

Microprocessor Bus Burst Last Indicator

PCI_INTA# /HBINT#

O Interrupt A

Microprocessor Bus Interrupt

PCI_INTB# /Reserved

O Interrupt B (Optional)

Reserved.

PCIREQ1 /Reserved

B Request.

Reserved.


TDM_CK B Data clock input from network, or from device, if it is the source of the clock.

TDM_FS B Frame synchronization input from network.

TDM_DX I Data transmit lead output from device.

TDM_DR O Data receive lead input from network.


SPI_SCLK O Serial bit-rate clock

SPI_TXD O Transmit data signal.

SPI_RXD i Receive data signal.

SPI_SS# O Slave select output.


M821xx Data Sheet


4.12.8 Universal Asynchronous Receiver Transmitter (UART)For more on this topic, refer to Section 23.0 Universal Asynchronous Receiver Transmitter (UART),

M821xx devices all support two UART interfaces.

Table 4-19 UART Signal Summary

4.12.9 I2C InterfaceFor more on this topic, refer to Section 25.0 Inter-IC (I2C) Interface

Table 4-20 I2C Signal Summary

4.12.10 USB InterfaceFor more on this topic, refer to Section 27.0 USB Interface.

The M82104 and M82108 devices do not support USB. Other M821xx devices support two USB ports.

Table 4-21 USB Signal Summary

4.12.11 General Purpose I/O (GPIO)For more on this topic, refer to Section 29.0 General Purpose I/O.

Table 4-22 GPIO Signal Summary


UART_RX I Receive input.

UART_TX O Transmit output.


I2C_SCL B I2C input/output clock line.

I2C_SDA B I2C input/output data line


USB_DP B Positive channel connected to USB cable.

USB_DM B Negative channel connected to USB cable.

USB_REF B External resistor connection for current reference.

USB_VBUS_STAT I VBUS Status. As a host, this signal indicates a power fault condition. As a device this signal indicates if the voltage on the received VBUS is at a valid level for operation.


GPIO[7:0] B General Purpose I/Os. These pins can generate interrupts. GPIO_07 is multiplexed with EXP_IRQ.

GPIO[31:8] B General Purpose I/Os. Multiplexed with other signals.

M821xx Data Sheet


4.12.12 TimersTable 4-23 Timers

4.12.13 JTAG InterfacesFor more on this topic, refer to Section 35.0 Test and Debug Interface Description. There are two JTAG ports. JTAG0 supports debug of ARM0 and boundary scan. JTAG1 supports debug of ARM1.

Table 4-24 JTAG Signal Summary

4.12.14 Test and MiscellaneousTable 4-25 Test and Miscellaneous Signals


TM_EVNT B Timer event. These pins can be configured as output, to generate an external clock by the timer, or as an input, to count external events.


JTAG_TCK I Clock.

JTAG_TDI I Input data.

JTAG_TDO O Output data.

JTAG_TMS I Mode select.

JTAG_TRST# I Reset


RESET I Device reset.

PLL_XI O Reference clock in.

PLL_XO I Reference clock out.

TM_PUI_REFCLKO O Utopia/PoS reference clock.

TM_PCI_REFCLKO O PCI reference clock.

TM_ETH_REFCLKO O Ethernet reference clock. Two modes: MII/RGMII or RMII reference.

TM_TDM_FSO O TDM frame synchronization output.

TM_TDM_REFCLKO O TDM clock output.

TM_MII0_MODE[1:0] I Ethenet0 configuration. See Section 11.4 Ethernet Signal Multiplexing.

TM_MII1_MODE[1:0] I Ethernet1 configuration. See Section 11.4 Ethernet Signal Multiplexing..

TM_BOOT_OP[1:0] I Boot option configurations.See Section 42.4.1 Boot Source Options.

TM_TDM_CLKSRC_EN I TDM source enable configuration.

TM_GBPT_OP[3:0] I General purpose boot option inputs. Section 29.0 General Purpose I/O.

TM_BSCN_JTAG I Indicates if JTAG0 used for debug or boundary scan. Low = ARM0 debug. High = boundary scan. See Section 29.0 General Purpose I/O.

TM_EXT_RESET O External reset pin; used to hold external devices in reset until all clocks are up.

TRISTATE# I Tristates all outputs.

M821xx Data Sheet


4.12.15 Power and GroundFor information on power application, see Section 42.1 Power Supply Sequencing.

For information on consolidation of power inputs and connection of reference inputs, see Section 42.2 Power Rail Assignments.

Table 4-26 Power and Ground Contacts

Symbol(s) Name/Function

Power Inputs

VDD Vcore (+1.2 V)

VDD_PRE Vpre-drivers (+1.2 V)

VDDO_PCI PCI Interface (+3.3 V)

VDDO_EXP Expansion Bus Interface (+3.3 V)

VDDO_GMII0 WAN Interface — Ethernet0 (+3.3 or +2.5 V)

VDDO_MII1 LAN Interface — Ethernet1 (+3.3 or + 2.5 V)

VDDO_DDR2 External Memory Interface (+1.8 V)

VDDO_REF SSTL reference voltage (+0.9 V)

VDDA_USB_0, VDDA_USB_1

USB Interface Analog Supply (+3.3V)

VDD_USB0_P, VDD_USB1_P

USB Digital Supply (+1.2 V)

VDDA_PLL_0, VDDA_PLL_1

PLL Supply (1.2 V)

Grounds

VSS Ground

VSSA_USB0, VSSA_USB1

USB Analog Grounds

VSS_USB_P_0, VSS_USB_P_1

USB Digital Grounds

VSS_PLL_0, VSS_PLL_1

PLL Grounds

M821xx Data Sheet


4.13 Unused Interface Termination Recommendations

4.13.1 Unused PCI / µP Bus TerminationNOTE: When the PCI/µP is unused, strap it into mP (HBMODE or host bus) mode and

setup host bus read (pull HBW# high) to put data and address I/Os into output mode.

Table 4-27 Unused PCI or uP Bus Interface Termination

Pin(8210x,

8215x, and8217x)

Pin(8219x) Signal Name Signal Description Signal

Type Termination

AF12 AE9 PCIMODE /HBMODE#

Microprocessor Bus Mode Select

I Pull down through 4.7 KΩ..

AE12 AF5 PCI_HOST# /HBBURSTEN#

PCI Host Mode Select I Pull up through 4.7 K Ω..

Microprocessor Bus Burst Enable

AF13, AC12 AB10, AC7 Reserved /HBBUSSIZE[1:0]

Reserved I Pull up through 4.7 K Ω..

Microprocessor Bus Size

V23 R25 PCIREQ2 /Reserved

Request 2 I Pull down.

Reserved

AB24 R26 PCIGNT2 /Reserved

Grant 2 O No connect.

Reserved

P26 J25 PCI_PERR# /HBWAIT#

Parity Error B Pull Up.

Microprocessor Bus Wait

R25 R22 PCI_CLK /HBCLK

PCI Bus Clock I Connect to TM_PCI_REFCLK.

Microprocessor Bus Clock

J25 D26 PCI_STOP# /HBFIFO

Stop B Pull down.

Microprocessor Bus FIFO Select

N23 N21 PCI_IRDY# /HBA6

Initiator Ready B Pull down.

Microprocessor Bus Address

AA24 T24 PCI_IDSEL /HBA5

Initialization Device I Pull down.


P25 K26 PCI_FRAME# /HBA4

Cycle Frame B Pull down.


M821xx Data Sheet


R26 K25 PCI_DEVSEL# /HBA3

Device Select B Pull down.


H24 A25 PCI_PAR /HBA2

Parity B Pull down.


AC26, AB23,P23, AA23, W25, Y23, AB26, Y24, P24, AB25,U25, Y25,V26, Y26, W26, T25, K26, N24, K25, M26,M24, M23, H23, J24, J23, L23, H26, G26, G25, F25, G23, F26

N25, R23, P21, U25, N23, T23, M26, T26, P22, P26,L25, N24,M24, M25, M23, L23, E25, F26, G25, H25,M22, M21, A24, D25, C26, L21, C5, B24, R23, F24, E24, H24

PCI_AD[31:0] /HBD[31:0]

PCI Address and Data B No connect.

Microprocessor Data

V25, T26, M25, H25

L26, K24, G26, B26

PCI_CBE#[3:0] /HBBE#[3:0]

PCI Command and Byte Enable

B Pull down.

Microprocessor Bus Byte Enable or Address Bit 0

L26 F25 PCI_TRDY# /HBCS#

Target Ready B Pull down.

Microprocessor Bus Chip Select

N25 H26 PCI_SERR# /HBW#

System Error B Pull up.

Microprocessor Bus Write

W23 T25 PCI_GNT1# /HBLAST#

Grant B Pull up.

Microprocessor Bus Burst Last Indicator

V24 P24 PCI_INTA# /HBINT#

Interrupt A O No connect.

Microprocessor Bus Interrupt

Table 4-27 Unused PCI or uP Bus Interface Termination (Continued)

Pin(8210x,

8215x, and8217x)


Type Termination

M821xx Data Sheet


4.13.2 Unused TDM Termination

4.13.3 Unused JTAG Termination

U24 P23 PCI_INTB# /Reserved

Interrupt B (Optional) O No connect.

Reserved

AA25 P25 PCIREQ1 /Reserved

Request B Pull down.

Reserved

Table 4-28 Unused TDM Termination

Pin(8210x,

8215x, and8217x)


Type Termination

T23 T21 TDM_CK Data clock input from network, or from device, if it is the source of the clock.

B Pull-down through 10K Ω.

AC25 U23 TDM_FS Frame synchronization input from network.

B Pull-down through 10K Ω.

AD26 U24 TDM_DX Data transmit lead output from device.

O No connect.

AD25 V25 TDM_DR Data receive lead input from network.

I No connect.

Table 4-29 Unused JTAGTermination

Pin(8210x,

8215x, and8217x)


Type Termination

A25 D20 JTAG0_TCK Clock. I No connect.

B23 D22 JTAG0_TDI Input data. I No connect.

B24 D23 JTAG0_TDO Output data. O No connect.

B25 G21 JTAG0_TMS Mode select. I No connect.

C23 H21 JTAG0_TRST# Reset. I No connect.

D20 F19 JTAG1_TCK Clock. I No connect.

D21 F20 JTAG1_TDI Input data. I No connect.

C22 F18 JTAG1_TDO Output data. O No connect.

Table 4-27 Unused PCI or uP Bus Interface Termination (Continued)

Pin(8210x,

8215x, and8217x)


Type Termination

M821xx Data Sheet


4.13.4 Unused I2CTermination

4.13.5 Unused SPI Termination

A23 E19 JTAG1_TMS Mode select. I No connect.

A24 E20 JTAG1_TRST# Reset I No connect.

Table 4-30 Unused I2C Interface Termination

Pin(8210x,

8215x, and8217x)


Type Termination

L25 L22 I2C_SCL I2C input/output clock line

B No connect.

K23 K21 I2C_SDA I2C input/output data line B No connect.


Pin(8210x,

8215x, and8217x)


Type Termination

K24 K22 SPI_SCLK Serial bit-rate clock O No connect.

C24 F23 SPI_TXD Transmit data signal. O No connect.

C25 G23 SPI_RXD Receive data signal. I No connect.

C26 J21 SPI_SS0_N Slave select output. O No connect.

D23 H22 SPI_SS1_N Slave select output. O No connect.

D24 H23 SPI_SS2_N Slave select output. O No connect.

D25 G22 SPI_SS3_N Slave select output. O No connect.

Table 4-29 Unused JTAGTermination (Continued)

Pin(8210x,

8215x, and8217x)


Type Termination

M821xx Data Sheet


4.13.6 Unused UART Termination

4.13.7 Unused USB Termination

Table 4-32 Unused UART Interface Termination

Pin(8210x,

8215x, and8217x)


Type Termination

E23 E23 UART0_RX Receive input. I No connect.

E24 C23 UART0_TX Transmit output. O No connect.

D26 C22 UART1_RX Receive input. I No connect.

E25 B23 UART1_TX Transmit output. O No connect.

Table 4-33 Unused USB Bus Interface Termination

Pin(8210x,

8215x, and8217x)


Type Termination

AF22 AA26 USB0_DP Positive channel connected to USB cable.

B No connect.

AF21 AB26 USB0_DM Negative channel connected to USB cable.

B No connect.

AD23 Y24 USB0_REF External resistor connection for current reference.

I Pull-down with 6.04 KΩ..

AC23 V26 USB0_VBUS_STAT VBUS Status. As a host, this signal indicates a power fault condition.

I Pull-up.

AF19 AC26 USB1_DP Positive channel connected to USB cable.

B No connect.

AF18 AD26 USB1_DM Negative channel connected to USB cable.

B No connect.

AD20 AB24 USB1_REF External resistor connection for current reference.

B Pull-down with 6.04K.

AE25 V24 USB1_VBUS_STAT VBUS Status. As a host, this signal indicates a power fault condition.

I Pull-up.

M821xx Data Sheet


4.13.8 Unused GPIO TerminationTable 4-34 Unused GPIO Interface Termination

Pin(8210x,

8215x, and8217x)


Type Termination

W2 P2 GPIO_0 General Purpose I/O 0 B No connect.

Y1 P1 GPIO_1 General Purpose I/O 1 B No connect.

Y2 P5 GPIO_2 General Purpose I/O 2 B No connect.

Y4 R1 GPIO_3 General Purpose I/O 3 B No connect.

AA2 T4 GPIO_4 General Purpose I/O 4 B No connect.

AA3 T3 GPIO_5 General Purpose I/O 5 B No connect.

AC7 AC2 GPIO_6 General Purpose I/O 6 (EXP_NAND_RDY/BSYN)

B No connect.

AD6 AB7 GPIO_7 General Purpose I/O 7(EXP_IRQ )

B No connect.

AD14 AA11 GPIO_8 General Purpose I/O 8(EXP_A_U_15)

B No connect.

AC14 AE7 GPIO_9 General Purpose I/O 9(EXP_A_U_16)

B No connect.

AE15 AC9 GPIO_10 General Purpose I/O 10(EXP_A_U_17)

B No connect.

AD15 AE8 GPIO_11 General Purpose I/O 11(EXP_A_U_18)

B No connect.

AC15 AF8 GPIO_12 General Purpose I/O 12(EXP_A_U_19)

B No connect.

AF16 AF9 GPIO_13 General Purpose I/O 13(EXP_A_U_20)

B No connect.

AE16 AE9 GPIO_14 General Purpose I/O 14(EXP_A_U_21)

B No connect.

F24 C24 GPIO_15 General Purpose I/O 15(TIM_EVNT0)

B No connect.

F23 A23 GPIO_16 General Purpose I/O 16(TIM_EVNT1)

B No connect.

U23 W25 GPIO_17 General Purpose I/O 17(TM_EXT_RESET)

B No connect.

L25 L22 GPIO_18 General Purpose I/O 18(I2C_SCL)

B No connect.

K23 K21 GPIO_19 General Purpose I/O 19 (I2C_SDA)

B No connect.

M821xx Data Sheet


4.13.9 Unused Timers Termination

E23 E23 GPIO_20 General Purpose I/O 20(UART0_RX)

B No connect.

E24 C23 GPIO_21 General Purpose I/O 21(UART0_TX)

B No connect.

D26 C22 GPIO_22 General Purpose I/O 22(UART1RX)

B No connect.

E25 B23 GPIO_23 General Purpose I/O 23(UART1_TX)

B No connect.

K24 K22 GPIO_24 General Purpose I/O 24(SPI_SCLK)

B No connect.

C24 F23 GPIO_25 General Purpose I/O 25(SPI_TXD)

B No connect.

C25 G23 GPIO_26 General Purpose I/O 26(SPI_RXD)

B No connect.

C26 J21 GPIO_27 General Purpose I/O 27(SPI_SS0_N)

B No connect.

D23 H22 GPIO_28 General Purpose I/O 28(UART1_TX)

B No connect.

AD7 AC1 GPIO_29 General Purpose I/O 29(UART1_TX)

B No connect.

AF6 AB8 GPIO_30 General Purpose I/O 30(EXP_NAND_ALE)

B No connect.

AE7 AA9 GPIO_31 General Purpose I/O 31(EXP_NAND_CLE)

B No connect.


Pin(8210x,

8215x, and8217x)


Type Termination

F24 C24 TIM_EVNT0 Timer Event 0 B No connect.

F23 A23 TIM_EVNT1 Timer Event 1 B No connect.

Table 4-34 Unused GPIO Interface Termination (Continued)

Pin(8210x,

8215x, and8217x)


Type Termination

M821xx Data Sheet


4.13.10 Unused Test and Miscellaneous Termination

NOTE: Unused output clocks can be configured off. See Section 36.2.2 Output Clock Control.


Pin(8210x,

8215x, and8217x)


Type Termination

— AB17 TM_PUI_REFCLKO Utopia / PoS reference clock.

O No connect.

T24 T22 TM_PCI_REFCLKO PCI reference clock. O No connect.

M4 L6 TM_ETH_REFCLKO Ethernet reference clock. Two modes: MII/RGMII or RMII reference.

O No connect.

W1 R3 TRISTATE Tristates outputs. I No connect.

.


5.0 Clock and Reset

5.1 IntroductionThis section provides functional details on the Clock / Reset block which includes Random Number Generation capabilities.

For use of this block related to power management, see Section 36.0 Power Management.

For register-level details, see Section 6.0 Clock and Reset Registers.

5.2 Features

5.2.1 Clock• All generated clocks (with the exception of TDM_CK), outputs or internal, will be active during

reset, running at the external reference clock (Refclk) frequency.

• TDM, PCI, PUI and GEMAC Input Interface Clocks are bypassed by reference clock during reset, and automatically switch to the external input clocks, two reference clock rising edges after reset is de-activated. The switch is done in the blocks.

• Internal generated TDM clock is not active during reset. After reset it is reference clock divided by 16 and the switching between the divided reference clock and the generated TDM clock is done through glitch-less configuration.

• All generated interface clocks have a programmable rate, divided down from the ARM or AHB clock.

5.2.2 Reset• Active low external hardware reset globally resets the device.

• A software reset resets the device except the PCI / µP (HIF) Interface block, which is accessible through the PCI / µP (HIF) interface and through the APB Bus Interface.

• ARM0 reset by hardware reset and a software reset in the PCI / µP block, and is active after power up and reset.

• ARM1 controlled by software reset in the ARM APB address space (see Interrupt Controller block registers Section 32.0). It defaults to active, holding ARM1 in reset until configured otherwise.

• Peripherals including PHYs controlled by software reset, with a default value of being in reset. These include: PoS / UTOPIA (PUI), PCI / µP, TDM, Ethernet0, Ethernet1, USB0, and USB1.

M821xx Data Sheet


5.2.3 Random Number Generator• 16-bit random numbers generator

• Handshaking request mechanism between the Random Number Generator and the system for new number generation

• Compliant (by simulation only) with FIPS PUB 140 statistical random number generator tests

• Detection of pair-wise consistency or lock-up error

• Run at 12 MHz (reference clock divided by 2)

5.3 Clock Functional DescriptionThis programmable phase-locked loop (PLL) analog macro-cell can be used for frequency generation. The block is intended for use in digital or analog/mixed-signal designs that operate from a nominal +/- 10% core logic supply.

The PLL block is ideal for clock generation where the reference frequency may be set for a wide variety of possible values. It can also be used for generating a low-jitter clock referenced to a variable or fixed-reference frequency. Typical applications include frequency synchronization, clock recovery / regeneration and frequency synthesis.

Application of this PLL in mixed-signal circuits requires power and ground isolation and a robust isolation approach from digital noise to function at its full low-jitter performance.

The PLL is designed for standard, digital CMOS processing along with being compatible with the 0.13um, 1.0V TSMC CL013LV process, this design is fully implemented in standard CMOS single poly/silicide processes with poly resistors offered by most CMOS foundries.

The relationship of clock out to the input frequency is: Fout=Fin*[ Y/ (W*X*2) ]

The relationship of the VCO to the input frequency is: Fvco=Fin*Y/W

Table 5-1 lists M821xx clocks.

Table 5-1 M821xx Clocks

Clock Name Description Direction Rate (MHz) Clock Spec

Crystal_In Input From Crystal Input 24 MHz +/- 50 ppm

Crystal_Out Output to Crystal Output 24 MHz +/- 50 ppm

Ddrclk DDR2 Clock Output 165 MHz

ddrclkn Inverted DDR2 clock Output 165 MHz

Expclk Expansion bus clock Output 33 MHz

Pciclk_out Locally generated PCI and Host Processor Interface Clock. Bypassed by Refclk in Reset.

Output =< 33 MHz

Pciclk_in PCI and Host Processor Interface Clock. Bypassed by Refclk in ResetNot Available in all Packages

Input 33 MHz

Puiclk_out Locally generated Pos/Utopia Transmit Clock. Bypassed by Refclk in Reset

Output 25, 33, 50 MHz

M821xx Data Sheet


Txpuiclk PoS/Utopia Transmit Clock. Bypassed by Refclk in Reset Not Available in all Packages

Input 25, 33, 50 MHz

Rxpuiclk PoS/Utopia Receive Clock. Bypassed by Refclk in ResetNot Available in all Packages

Input 25, 33, 50 MHz

Tdmclk TDM Clock.Could be input or locally generated.Bypassed by Refclk in Reset (in TDM block)

Input/Output 1.536, 1.544, 2.048, 4.096,

8.192, 16.384 MHz

Spitxclk SPI Transmit Clock Output =< 4 MHz

I2ctxclk I2C Transmit Clock Input/Output =< 3.4 MHz

eephyrefclk External Giga Ethernet PHY reference clock Output 25/50 MHz +/- 50 ppm

Gmac0refclk RMII0, GMII0 Reference Clock.Bypassed by Refclk in Reset

Input 125 MHz

Gmac0txclk RGMII0 Transmit Clock. Bypassed by Refclk in Reset

Output 125 MHz

Gmac0rxclk RGMII0 Receive Clock.Bypassed by Refclk in Reset

Input 125 MHz

Gmac0mdclk GEMAC0 Management Data Clock Output 2.5 MHz

Gmac1refclk RMII1, RGMII1 Reference Clock.Bypassed by Refclk in Reset

Input 125 MHz

Gmac1txclk RGMII1 Transmit Clock.Bypassed by Refclk in Reset

Output 125 MHz

Gmac1rxclk RGMII1 Receive Clock.Bypassed by Refclk in Reset

Input 125 MHz

Gmac1mdclk GEMAC1 Management Data Clock Output 2.5 MHz

Dqs0 DDR Data Strobe 0 Input/Output 165 MHz




TCK0 JTAG Port 0 Test Clock Input

TCK1 JTAG Port 1 Test Clock Input

FSYNC Frame SYNCCould be input or locally generated.

Input/Output 8 KHz

Table 5-1 M821xx Clocks (Continued)

M821xx Data Sheet


5.3.1 Clock Activation SequenceAfter power up, clocks are activated based on the following sequence:

1. During hardware reset, the outputs from the PLLs are not used and bypassed by Refclk (default value of a configuration bit). Thus, ARM and AHB clocks are running at Refclk rate. All clock dividers used for clock generation are also in reset and bypassed by Refclk (default value of a configuration bit). TDM generated clock is not active in hard reset and PCI / µP, PoS / UTOPIA, TDM and GEMAC input external clocks are bypassed by Refclk.

2. After hardware reset, the two PLLs are active using their default parameters, but still not used and in bypass mode (default value of a configuration bit), and their outputs are still Refclk. All clock dividers are out of reset and clocked but still bypassed by Refclk, except in the Expansion Bus block, where, the output clock is the divided clock.

3. The downloaded code programs the PLLs with the required frequencies (see section Rate Change Procedure for needed sequence). Meanwhile, all peripheral blocks and USB internal PHYs are to be held in reset through software control (the default value of a configuration bit). External PHYs and peripherals are to be held in reset though a GPIO’s pull down pad.

4. The downloaded code programs the clock dividers with the appropriate ratios. Their output clocks are still bypassed by Refclk.

5. Once the PLLs are locked (35µs max), software can use the PLL clock outputs. The switching of the clock is glitch-free done by synchronization circuitry.

6. The software then selects to use the clock outputs from the clock dividers. The switching of the clock is glitch-free done by synchronisation circuitry.

7. Outputs from clock dividers becomes: PLL / Divide Ratio.

8. Once their reset requirements are met, the software brings the internal peripheral blocks and PHYs out of reset, as well as the external PHYs and peripherals.

5.3.2 Reset Clocking ModeDuring reset, internally generated clocks are bypassed by reference clock, and manual switching is required to use them after reset de-activation.

External Clock Inputs are also bypassed by Refclk while the corresponding blocks are held in reset. Automatic switching to the external interface clock is done upon reset de-activation.

NOTE: The MDC clock is zero unless the Maintenance interface is enabled and then it’s AHB/X when X is a configure number. MDC can’t be more than 2.5 MHz.The clock to the TDM block can be an external one or the generated one, selected by bootstrap.

M821xx Data Sheet


5.3.3 Functional Clocking ModesThe following clocking modes are defined.

• PLL Bypass: Selected PLL output is bypassed by its Reference Clock. Bypass for PLL0 and PLL1 are not mutually exclusive

• Sync Mode: Ahbclk is in sync with Fclk, divided by a programmable ratio.

• Div Bypass: In SYNC mode, AHB clock is PLL0 clock or divided PLL0 clock.

• ARM AHB Bypass: PLL0 clock can be bypassed by PLL1 clock.

• ARM0 Div Bypass: ARM0 clock can be divided by a programmable ratio or divider can be bypassed.

• ARM1 Div Bypass: ARM1 clock can be divided by a programmable ratio or divider can be bypassed.

• Fclk for ARM0 PD: Power down Fclk to ARM0.

• Fclk for ARM1 PD: Power down Fclk to ARM1.

5.3.4 Loop-back Clocking Modes

5.3.4.1 PUI Loop-Back

In PUI Loop-Back Mode, Tx PUI external input clock (txpuiclk) is bypassed by Ahbclk divided by four. The same applies for Rx PUI external input clock (rxpuiclk). The bypass is done inside the PUI block.

5.3.4.2 TDM Loop-Back

The TDM has 3 types of loopback:

1. Inside the TDM block itself: In this Mode, TDM clock, internally generated or externally provided, is bypassed by Ahbclk divided by four. The bypass is done inside the TDM block.

2. External loopback: The Rx direction is loopbacked into the Tx direction as is. No change in clocks.

3. Internal loopback; The Tx direction is loopbacked into the Rx direction as is. No change in clocks.

NOTE: The select whether to divide the FCLK or not (div_bypass) used in the SYNC mode should be done before the switch to SYNC mode, otherwise a glitch can occur on the AHB clock.

M821xx Data Sheet


5.3.4.3 GEMAC Loop-Back

Two loop-back modes are available:

• Local Loop-Back: Tx and Rx clocks of the Giga Ethernet block are bypassed with Ahbclk divided by two. Clock bypass is done outside the Ethernet IP, the rest of the loop-back muxing is done inside the IP block.

• Giga Ethernet Loop-Back: input Rx clock is bypassed by input Tx clock.

5.3.5 Device PLLsTable 5-2 lists the M821xx PLLs.

5.3.5.1 ARM and AHB PLLs

One PLL is used to generate the ARM Fast Clock (450 MHz), and one for the AHB Bus clock (165 MHz).

The two PLL shall be running from the same 24 MHz reference clock input Refclk.

The PLL output frequency is programmable using:

PLL Out = REFCLK * (Y) / [(W+1) * (X+1) * 2]Where 4Y<128, 0X<32, 0W< 4.

A Bypass mode is provided to switch glitch-free from the PLL VCO clock to the reference clock internally to the PLL, and the clock output becomes Refclk/2. This mode shall not be used in the device.

5.3.5.2 USB PHY PLLs

The USB IP block has one PLL requiring a reference clock of 24 MHz +/- 100 ppm and generating a 480 MHz clock.

The ARM PLL reference clock can be used if it meets the ppm requirements. Tighter ppm tolerance increases cost however.

The PHY PLL output is divided down by 16 or 8 to generate the USB controller 30 or 60 MHz Clock. The lowest frequency (30) shall be selected in this device.

Table 5-2 821xx PLLs

Required Actual

PLL Description Reference Clock Rate

Reference Clock Spec

ReferenceClock

OutputClock Rate

OutputClock Spec

ARM ARM Fast Clock PLL 24 MHz +/- 100ppm 24 MHz +/- 50 ppm 450 MHz 25 pSec

AHB AHB Bus Clock PLL 24 MHz +/- 100ppm 24 MHz +/- 50 ppm 165 MHz 25 pSec

USB USB IP Block PLL 12, 24 MHz +/-100ppm 24 MHz +/- 50 ppm 480 MHz

M821xx Data Sheet


5.3.6 Rates Generation and Change Procedures

5.3.6.1 ARM and AHB Clock

Two PLLs in the ClockCore block are used to generate the ARMs Fast Clock (Fclk) and the AHB Bus Clock (Hclk), from the reference clock Refclk. Refclk can be the oscillator output or driven from one of the crystal pins in oscillator bypass mode.

Each PLL can be programmed with a multiplier and two divider values to come up with the required rate. It takes a maximum of 35us for the PLL to lock. Details on the PLL can be found under the ARM PLL section.

Given the PLL output clock is:

PLL Output = REFCLK * (Y) / [( W + 1) * (X+1) * 2 ], (Where 4 Y < 128, X < 32, W < 4),

And starting with a 24 MHz Reference clock, the values for Y, W and X would be:

FCLK = 24MHz*(75) / [(2)*(1)*2] = 450 MHz, Y=75, W=1, X=0

AHBCLK = 24MHz*(55) / [(2)*(2)*2] = 165 MHzY=55, W=1, X=1

The above values put the PLL VCOs (Refclk*Y/(W+1)) in the recommended range of 400 MHz – 1GHz to keep the jitter low.

The following control bits are needed for each PLL:

• PLL Disable: Disables the PLL when active high. No output clock is generated. PLL Bypass would not be able to switch after the PLL is disabled. Default value is 0.

• PLL Bypass Control : Pypass the PLL internally when active high. PLL output clock is Refclk.

• PLL Clock Bypass: Bypasses the PLL when active high. Output clock is Refclk. Has no effect after PLL is disabled.

• Y <6:0>: Y Multiplier bits.

• W <1:0>: W Divider bits.

• X <4:0>: X Divider bits.

5.3.6.2 Rate Change Procedure

Changing the ARM or AHB clock rates can be done on the fly but have to follow a defined procedure:

1. Put the relevant PLL in Bypass Mode using the clock MUX. The output clock frequency will switch to Refclk.

2. Do an internal PLL bypass (inside the PLL)

3. Wait for 500us

4. Disable the PLL.

NOTE: Due to the fact that the two clocks will be used to generate some of the interface clocks the following restrictions apply if the clocks are in use:

• ARM clock shall be a multiple of 25 MHz, required by the PUI and EPHY clock generation schemes.

• AHB clock shall be fixed to 165 MHz, required by the PCI clock generation scheme.

M821xx Data Sheet


5. Wait for 500us

6. Enable the PLL

7. Wait for 500us

8. Set Multiplier (Y) and Divider (W,X) values.

9. Wait for PLL to lock

10. Remove the internal PLL bypass (inside the PLL)

11. Remove the PLL from Bypass Mode using the clock MUX. The output clock frequency will be the new programmed rate

5.3.6.3 APB Bridge Strobe

For power reduction, configuration registers sitting on the APB bus shall be clocked using a strobe signal Pstbn. Timing and waveform diagrams can be found in the AAB block HDD.

All the new blocks will use PSTBL and not PSTBN.

5.3.6.4 USB Reference Clock

The USB IP requires a Reference clock for its PHY interface, with the following requirements:

•12, 24 MHz, +/- 100 ppm. A 24 MHz reference clock will be provided.

•Clock should be active during reset

The Reference Clock output from the oscillator could be used as the USB reference clock if it meets the above requirements. In previous devices, the input reference clock had +/- 100 ppm. Tolerance can be tightened on it at the expense of cost.

5.3.6.5 External EPHY Reference Clock Generation

The External EPHY requires a reference clock with the following requirements:

• 25/50 MHz, +/- 50 ppm, 200ps max jitter

• Clock should be active during reset

A clock divider is used to generate it from FCLK. The division ratio is to be programmable to support multiple FCLK frequencies up to 500 MHz. For the target frequency of 450 MHz, the division ration is 18 for 25 MHz and 9 for 50 MHz. The clock divider shall be able to generate a 50% duty cycle output clock for odd number division ratios. A Clock Switch selects, glitch-free, between Refclk and the divider output clock, and default’s to Refclk upon reset. Power down logic shall be default to activate the clock.

Figure 5-1 EPHY Clock Generation

ClockDivderFCLK

ratio[4:0]

eephyclk pwr dwn

EEPHYCLKPWRDWN

Divide Ratio

ClockSwitch

sel

clk switch

0

1REFCLK

M821xx Data Sheet


Changing the rate for the EPHY clocks can be done on the fly by writing a new value to the divide ratio register. The new value will take place once the divider loads the ratio value into its counters.

5.3.7 Interface Clocks Generation

5.3.7.1 TDM Clock Generation

The TDM clock can be configured to be an external input clock or an internally generated one. When internally generated, the rates supported are 1.536, 1.544, 2.048, 4.096, 8.192 and 16.384 MHz. TDM clock direction is selected through a bootstrap pin (a functional pin is pulled up or down on the board and latched during reset only). If it is generated internally, the TDM clock shall be active during reset and will equal reference clock divided by 16 (1.5 MHz). Therefore the divider will not be reset during hard reset and the option to reset it is for test mode only. To provide a clock to the TDM block during Reset, a Clock Switch shall select, glitch-free, between Refclk and the TDM input clock, and shall default to Refclk upon reset (implemented in the block itself). The input TDM clock to the TDM block can be the internal generated clock or the external input when externally generated.

The clock generation can be disabled and thus, no clock will be output.

While in reset, the generated TDM clock is not active. After reset it is 1.5 MHz (reference/16).

After reset one needs to switch to the generated TDM clock in order to stop outputting the 1.5 MHz and start outputting the TDM clock. The default frequency for the TDM clock is 1.536 MHz.

The TDM clock can also be powered down through configuration.

TDM frequency can be changed by configuring different R values in the TDM clock control register.Table 5-3 shows the R value for each clock rate.

Because of the way the TDM clock is generated from the 165 MHz clock the duty cycle of the TDM clock will be between 40% to 60%.

In case one needs to change the frequency, the R value should be changed. The change is always done at the end of the TDM clock cycle and not at the moment the R value was changed. The counter will also be reset in order to get a clean start for the new R value accumulation.

Table 5-3 Needed Configuration Value for Each TDM Clock Rate

Clock rate (MHz) (decimal) (ppm)

1.536 39982241 0.025

1.544 40190482 0.0249

2.048 53309655 0.0187

4.096 106619309 0.0094

8.192 213238619 0.0047

16.384 426477237 0.0023

NOTE: The TDM clock is derived from the AHB clock based on the following formula:

TDM_clock = (R/2^32) * AHB Clock

Where R is read from bits 29:0 of the TDM Clock Control register (see Section 6.2.4 TDM Clock Control (TDMCLK_CNTRL).

of R of∆

M821xx Data Sheet


5.3.7.2 FSYNC Generation

The device supports an external input TDM FSYNC or can generate one internally. FSync and TDM Clock directions can be coupled i.e. both inputs or both outputs, or the TDM clock can be input while the FSYNC is an output. Because the FSYNC and the TDM clock can have different direction, their direction can’t be selected using the same bootstrap. Therefore the direction of the FSYNC will be set by a configuration bit in the GPIO with a default direction of input. One can switch from input to output direction and this switch is not a glitch-free switch.

FSYNC will be generated using the TDM clock (the generated internally or the external, when the clock is an input).

When generated internally, FSYNC is configured to change on the rising or falling edge of the TDM clock, with a programmable period (=< 2048 TDM clocks), and a programmable Duty Cycle in which the High phase can be anywhere between 1 to (2047) TDM clock cycles.

There is no restriction on the delay between the rise/fall edge of TDM clock and the rise/fall edge of FSYNC, as long as timing requirements are met at the receiver’s interface. FSYNC is usually sampled on the opposite edge of TDM clock.

The FSYNC generation can be disabled and thus, no FSYNC will be generated. The default is enabled.

Once enabled, the FSYNC will be asserted for the amount of TDM cycles configured to be high and then will be deasserted for the amount of TDM cycles configured low.

The FSYNC should be an 8 KHz signal, therefore the number of TDM clocks needed to generate one period of FSYNC will change according to the TDM clock frequency. The following table summarize the number of TDM clock cycles needed for each TDM clock frequency.

Table 5-4 Number of TDM Clocks versus Clock Frequency

TDM Clock Frequency Number Of TDM Clock Cycles

1.536 192

1.544 193

2.048 256

4.096 512

8.192 1024

16.384 2048

M821xx Data Sheet


5.3.7.3 PUI Clock Generation

Three PUI clock rates are supported: 25MHz, 33 MHz and 50MHz. The Duty cycle is 45% to 55% but a target of 50% is desired. A clock shut down is required.

The 25 and 50 MHz can be generated from FCLK, using a clock division ratio of 18 or 9 respectively. The 33 MHz rate can be generated from the AHBCLK, similarly to the PCI Interface clock, by dividing it by 5.

One divider can be used, and a clock switch shall select between the AHBCLK and FCLK to be the divider’s clock source, with the later being the default value. The division ratio is programmable in order to produce the relevant frequancies.

A Clock Switch selects, glitch-free, between Refclk and the divider output clock, and shall default to Refclk upon reset.

Power down logic shall be default to activate the clock.

The default value of the PUICLK will be 50 MHz.

Changing the rate for the PUI clocks can be done on the fly by following a defined procedure:

To switch from Fast (Fclk) to Slow (Ahbclk)/Fast (Fclk) clock:

1. Change the divider Clock Source if needed

2. Change Divider Ratio value

To switch from Slow (Ahbclk) to Fast (Fclk) clock:

1. Change Divider Ratio value

2. Change the divider Clock Source

The switch from Fast to Slow and vise-versa are different in order to avoid outputting a clock with frequency grater then 50 MHz at any time.

Figure 5-2 PUICLK Generation

ClockDivder

FCLK ClockSwitch

sel

clk source

10

puiclk pwr dwn

PUICLKPWRDWN

ratio[4:0]

Divide Ratio

AHBCLK ClockSwitch

sel

clk switch

0

1REFCLK

M821xx Data Sheet


5.3.7.4 PCI Clock Generation

The PCI clock rate supported is, 33 MHz. The Duty cycle is 37% to 63% but a target of 50% is desired. A clock power-down down is required.

The 33 MHz can be generated from AHBCLK, using a clock division ratio of 5. However the ratio is kept programmable for more flexibility.

A Clock Switch selects, glitch-free, between Refclk and the divider output clock, and shall default to Refclk upon reset.


Changing the rate for the PCICLK clocks can be done on the fly by writing a new value to the divide ratio register. The new value will take place once the divider loads the ratio value into its counters.

5.3.7.5 DDR2 Interface Clock

The two DDR clocks have the same rate as the Bus clock. One is in phase and one is an inverted version.

The inverted version is generated in the pad.

5.3.7.6 Expansion Bus Clock

The expansion bus requires a programmable clock rate, with a maximum of 33 MHz clock for this device. It shall be generated from the AHBCLK. It is generated and controlled in the Expansion block.

A clock switch selects, glitch-free, between Refclk and the divider output, and shall default to Refclk upon reset and will switch to the divided AHB clock right after reset ends.


When reset is asserted, output clock might have glitches when switching to reference clock.

Figure 5-3 PCI Clock Generation

AHBCLK

pciclk pwr dwn

PCICLKPWRDWN

ratio[4:0]

Divide Ratio

ClockSwitch

sel

clk switch

0

1REFCLK

ClockDivder

M821xx Data Sheet


Changing the rate for the EXPCLK clocks can be done on the fly by writing a new value to the divide ratio register. The new value will take place once the divider loads the ratio value into its counters.

Figure 5-4 Expansion Bus Clock

expclk pwr dwn

EXPCLK

AHBCLKPWRDWN

ratio[4:0]

Divide Ratio

ClockSwitch

sel

clk switch

0

1

ClockDivder

REFCLK

M821xx Data Sheet


5.4 Reset Functional Description

5.4.1 External Hardware ResetAn asynchronous input resets the whole device. Once activated, it reaches all flops without any synchronisation.

5.4.2 Watchdog ResetWhen the watchdog timer expires, it resets all the blocks, including itself after some synchronization delay in the reset block. It behaves similarly to the External Hard Reset. For Watchdog Reset register controls see Section 33.0 Timers, or for the exact register locations, see Table 34-1, “Timer Block Register Map,” on page 557.

5.4.3 Global Software ResetTwo register bits in the PCI/µP (HIF) address space are available for software reset. One is accessible from the host (external) side and one from the ARM side.

Software Reset clears all the blocks except the PLLs, blocks in the Pciclk clock domain, and the USB PHYs.

For software reset from the ARM side, see bit 8 in Table 16-47, “APB FIFO Interrupt Acknowledge Register,” on page 327.

For software reset from the host side, see bit 8 in Table 16-10, “FIFO Interrupt Acknowledge Register Bit Descriptions,” on page 306.

Note also that Watchdog Reset provides a global software reset effect.

NOTE: Do not use the Global Software Reset when the Internal Boot ROM supports boot. Instead use the Watchdog Reset to effect a software reset.When the Global Software Reset bit is set, blocks are reset but clock settings remain the same. Without default clock frequencies normally present after a hardware reset, the code in the Internal Boot ROM cannot pass the boot process on to external ROMs accessible through the I2C or SPI interfaces.If the boot process invovles going directly to external NOR Flash without reference to the Internal Boot ROM, then Global Software Reset will work OK.

M821xx Data Sheet


5.4.4 Block ResetsThe following blocks have a block level Software Reset. Their reset control bit is not self clear, and the software controls its activation and deactivation.

• USB0 PHY: Internal USB0 PHY block reset. Defaults to reset active.

• USB1 PHY: Internal USB1 PHY block reset. Default to reset active.

• PCI IF: PCI IF block reset. Only resets Pciclk domain in the HIF block. Defaults to reset active

• HIF: HIFCO block reset. Resets the HI block except Pciclk domain. Defaults to reset active

• PUI: PoS/Utopia block reset. Defaults to reset active

• TDM: TDM block reset. Defaults to reset active

• GEMAC0: GEMAC0 block reset. Defaults to reset active

• GEMAC1: GEMAC1 block reset. Defaults to reset active

• USB0: USB0 Controller block reset. Defaults to reset active

• USB1: USB1 Controller block reset. Defaults to reset active

• DDR: DDR controller block reset. Defaults to reset active.

• IPSEC: IPSEC block reset. Defaults to reset active.

• ARM1: ARM1 Reset. Defaults to reset active. (not done in this block)

• ARM0: ARM0 Reset. Defaults to reset not active.

M821xx Data Sheet


5.5 Random Number Functional DescriptionThe RNG block receives reference clock divided by 2. The block will be reset in HW and SW reset received from the reset core block. The RNG configuration are in AHB clock domain, nevertheless they are not synchronized to RNG clock domain because there is an internal synchronization inside the RNG.

The 3 indications, output by the RNG, will be synchronized to AHB clock, by synchronizing the RNG clock divided by 2 to the AHB as a SYNC pulse. Once that SYNC pulse is asserted at AHB clock domain, the indications will be latched at AHB clock domain.

The RNG clock divider will be reset at HW reset only.

The LFSR is a 24-stage shift chain with XNOR feedback from tap-points located at stages eighteen and twenty-three. This LFSR configuration has been shown to pass all FIPS statistical number testing with sufficient margin. A third input to the XNOR gate is the random noise input from the ring oscillator. The LFSR output is taken from between registers eight and twenty-three and is conditionally loaded into an intermediate pipeline register when the shift count reaches sixteen and the pair-wise consistency test passes. The LFSR module also contains the logic required to detect a lock-up condition of either all ones or all zeroes. Such a condition would create an error condition for the number generated during the request.

A ring sub-module is intended to provide noise into the pseudo-random LFSR chain. It is a thirty-three-stage ring oscillator with a gating feature to freeze the ring into a known state for pseudo-random operation of the LFSR. The ring is sampled with the same clock used to shift the LFSR so as to create a new noise sample upon each shift. The ring is designed to top out at 1 GHz at the fast process corner and hence oscillates numerous times between each sample edge.

Handshaking is provided for request of a new number, and acknowledge of the request. If during the generation of a new number the RNG detects a pair-wise consistency failure or LFSR lock-up, the RNG will alert the system to the failure. The system can either use the “clear” or “flush” mechanisms to return to normal operation if and when an error state is reached. The “clear” operation is only intended to resolve the error state by producing another number (16 bit LFSR shift) for the intermediate pipeline register in the hope that it will be devoid of the previous error characteristics relative to the previous error-free number provided by the RNG. The “flush” operation resets the LFSR contents to a known value and performs 256 consecutive shifts to prime the intermediate pipeline register followed by a self generated single request which provides a new random number at the output.

.


6.0 Clock and Reset Registers

6.1 IntroductionFor details on Clock/Reset block operations, see Section 5.0 Clock and Reset. This section presents both clock control (Section 6.2 ) and reset registers (Section 6.3 ).

6.2 Clock Control RegistersThe clock configuration registers are summarized in Table 6-1..

NOTE: The memory addressing of the clock configuration registers is offset from the base address: 0x 100B 0000.

Table 6-1 Offload Register Interface Map

Register Address DescriptionARM_CLK_CNTRL 0x0 ARM Clock Control

AHB_CLK_CNTRL 0x4 AHB Clock Control

PLL_STATUS 0x8 PLL Status

CLKDIV_CNTRL 0xC Clock Dividers Control

TDMCLK_CNTRL 0x10 TDM Clock Control

FSYNC_CNTRL 0x14 FSync Configuration

CLK_PWR_DWN 0x18 Clocks Power Down

RNG_CNTRL 0x1C Random Number Control

RNG_STATUS 0x20 Random Number Status

ARM_CLK_CNTRL2 0x24 TDM Clock Jitter Control

NOTE: Dynamic Access: Writing to registers that have write permission may be restricted to times when a channel (or other functional sub-block) is in a specific state (e.g., disabled). This is documented in the register description tables through the value of the Dynamic (abbreviated "Dyn") column for the field. Some writes may be permitted at any time, but will not take effect until a short time later. In such a situation, the exact behavior is explained in the register description text.

M821xx Data Sheet


6.2.1 ARM Clock Control (ARM_CLK_CNTRL)Default Value: 0x5000004Table 6-2 Fields of ARM Clock Control (ARM_CLK_CNTRL)

Bits Name Description Reset Value

Dyn Acc

31 ARM_PLL_BY_CTRL Controls PLL internal bypass.• 0 — PLL output is generated clock• 1 — PLL output is REF clock

0 Yes RW

30:27 RSVD N/A N/A N/A

26 ARM_AHB_BYP ARM FCLK bypass with AHB PLL clock output• 0 — ARM clock is AHB clock• 1— ARM clock is FCLK

1 Yes RW

25 PLL_Disable Disables and Powers Down PLL.• 0 — VCO output is active.• 1— VCO output is 0. If PLL Bypass is not set

before disabling the PLL, its output will be stuck at 0 and Bypass will no longer take effect.

0 Yes RW

24 PLL_Clk_Bypass PLL Clock Bypass• 0 — PLL output is Reference Clock*Y/((W+1)*(X+1)*2)• 1— PLL output is Reference Clock

1 Yes RW


20:16 X_Divider PLL X Divider value. Internally X+1 is used 0 Yes RW


9:8 W_Divider VCO W Divider value. Internally W+1 is used 0 Yes RW

7 RSVD N/A N/A N/A

6:0 Y_Multipler VCO Y Multiplier. Minimum is 4. If less than 4 is programmed the value of 4 will be used internally

0x4 Yes RW

M821xx Data Sheet


6.2.2 AHB Clock Control (AHB_CLK_CNTRL)Default Value: 0x11000004

Table 6-3 Fields of AHB Clock Control (AHB_CLK_CNTRL)


Dyn Acc

31 AHB_PLL_BY_CTRL Controls PLL internal bypass.• 0 — PLL output is generated clock• 1— PLL output is REF clock

0 Yes RW

30 DIV_BYPASS Divider bypass Mode Enable. Selects between Fclk/Sync Divider to Fclk

• 0 — Bypass Mode Disabled• 1— Bypass Mode Enabled

0 Yes RW

29 SYNC_MODE SYNC Mode Enable. AHB = (Fclk/Sync Divider) or Fclk depends on DIV_BYPASS configuration.

• 0 — Sync Mode Disabled• 1— Sync Mode Enabled

0 Yes RW

28:26 SYNC_DIVIDER AHB Clock Sync mode divider. AHB = Fclk/Divider 0x4 Yes RW

25 PLL_Disable Disables and Powers Down PLL.• 0 — VCO output is active.• 1 — VCO output is 0. If PLL Bypass is not set

before disabling the PLL, its output will be stuck at 0 and Bypass will no longer take effect.

0 Yes RW

24 PLL_Clk_Bypass PLL Clock Bypass• 0 — PLL output is Reference Clock

*Y/((W+1)*(X+1)*2)• 1 — PLL output is Reference Clock

1 Yes RW


20:16 X_Divider PLL X Divider value. Internally X+1 is used 0 Yes RW


9:8 W_Divider VCO W Divider value. Internally W+1 is used 0 Yes RW

7 RSVD N/A N/A N/A

6:0 Y_Multipler VCO Y Multiplier. Minimum is 4. If less than 4 is programmed the value of 4 will be used internally

0x4 Yes RW

M821xx Data Sheet


6.2.3 Clock Dividers Control (CLKDIV_CNTRL)Default Value: 0x226922

Table 6-4 Fields of Clock Dividers Control (CLKDIV_CNTRL)


Dyn Acc


21 EPHY_ClkDiv_Bypass EPHY Generated Clock Bypass• 0 — EPHY Clock Output is from Clock Divider• 1 — EPHY Clock Output is Reference Clock

1 Yes RW

20:16 EPHY_ClkDiv_Ratio EPHY Clock Divider Ratio. This is a 1-base value. 2 Yes RW

15 RSVD N/A N/A N/A

14 PUI_ClkDiv_Bypass PUI Generated Clock Bypass• 0 — PUI Clock Output is from Clock Divider• 1 — PUI Clock Output is Reference Clock

1 Yes RW

13 PUI_ClkDiv_SrcClk PUI Clock Divider Source Clock• 0 — PUI Clock Divider uses AHB Clock as its clock

source• 1 — PUI Clock Divider uses ARM Fast Clock as its

clock source

1 Yes RW

12:8 PUI_ClkDiv_Ratio PUI Clock Divider Ratio. This is a 1-base value. 9 Yes RW


5 PCI_ClkDiv_Bypass PCI Generated Clock Bypass• 0 — PCI Clock Output is from Clock Divider• 1 — PCI Clock Output is Reference Clock

1 Yes RW

4:0 PCI_ClkDiv_Ratio PCI Clock Divider Ratio. This is a 1-base value. 2 Yes RW

M821xx Data Sheet


6.2.4 TDM Clock Control (TDMCLK_CNTRL)Default Value: 0xC26214A1

6.2.5 FSync Control (FSYNC_CNTRL)Default Value: 0x20BF0001

Table 6-5 Fields of TDM Clock Control (TDMCLK_CNTRL)


Dyn Acc

31 TDM_CLK_EN TDM clock generation enable. 1 Yes RW

30 TDM_GEN_BYP TDM Generated Clock Bypass

0 — TDM Clock Output is from TDM Clock Generation Logic

1—TDM Clock Output is Divided Reference Clock

1 Yes RW

29:0 INC_VALUE Counter increment value. According to the desired TDM clock output frequency, this field should be cofigured.

0x26214a1 Yes RW

Table 6-6 Fields of FSync Control (FSYNC_CNTRL)


Dyn Acc


29 FSYNC_EN FSYNC generation enable 1 Yes RW

28 FSYNC_FALL_EDGE FSYNC sampling edge

0 — FSYNC Output is in reference to TDM clock rising edge

1— FSYNC Output is in reference to TDM clock falling edge

0 Yes RW

27 RSVD N/A N/A N/A

26:16 Low_Phase_Width TDM FSync Low Phase Pulse Width in TDM Clock units. A 1-base value. Should be configured according to TDM clock frequency in order to receive 8 KHz. In 16.38 MHz TDM clock the maximum value is 0x7FF. Can’t be configured to 0.

0xBF Yes RW


10:0 High_Phase_Width TDM FSync High Phase Pulse Width in TDM Clock units. A 1-base value. Should be configured according to TDM clock frequency in order to receive 8 KHz. In 16.38 MHz TDM clock the maximum value is 0x7FF. Always configured to ((Maximum number of cycles) - Low_Phase_Width ). Can’t be configured to zero.

1 Yes RW

M821xx Data Sheet


6.2.6 Clocks Power Down (CLK_PWR_DWN)Default Value: 0x0

Table 6-7 Fields of Clocks Power Down (CLK_PWR_DWN)


Dyn Acc


21 ARM0_Clk_PD ARM 0 Generated Clock Power Down. Active High. 0x0 Yes RW

20 ARM1_Clk_PD ARM 1 Generated Clock Power Down. Active High. 0x0 Yes RW

19 EEPHY_Clk_PD External EPHY Generated Clock Power Down. Active High.

0x0 Yes RW

18 TDM_Clk_PD TDM IF Generated Clock Power Down. Active High. 0x0 Yes RW

17 PUI_Clk_PD PUI IF Generated Clock Power Down. Active High. 0x0 Yes RW

16 PCI_Clk_PD PCI IF Generated Clock Power Down. Active High. 0x0 Yes RW


10 MDMA_AhbClk_PD MDMA AHB Clock Power Down. Active High. 0x0 Yes RW

9 I2C_SPI_AhbClk_PD I2C and SPI AHB Clock Power Down. Active High. 0x0 Yes RW

8 UART_AhbClk_PD UART AHB Clock Power Down. Active High. 0x0 Yes RW

7 IPSEC_AhbClk_PD IPSEC AHB Clock Power Down. Active High. 0x0 Yes RW

6 TDM_AhbClk_PD TDM AHB Clock Power Down. Active High. 0x0 Yes RW

5 USB1_AhbClk_PD USB1 AHB Clock Power Down. Active High. 0x0 Yes RW

4 USB0_AhbClk_PD USB0 AHB Clock Power Down. Active High. 0x0 Yes RW

3 GEMAC1_AhbClk_PD GEMAC1 AHB Clock Power Down. Active High. 0x0 Yes RW

2 GEMAC0_AhbClk_PD GEMAC0 AHB Clock Power Down. Active High. 0x0 Yes RW

1 PUI_AhbClk_PD PUI AHB Clock Power Down. Active High. 0x0 Yes RW

0 HIF_AhbClk_PD PCI AHB Clock Power Down. Active High. 0x0 Yes RW

M821xx Data Sheet


6.2.7 Random Number Control (RNG_CNTRL)Default Value: 0x0

Table 6-8 Fields of Rndm Nbr Control (RNG_CNTRL)


Dyn Acc


7 LFSR_Lock Enables LFSR to shift independent of RNG State machine. Active High. 0 Yes RW

6 LFSR_Bypass Opens LFSR Feedback to observe Noise Source. Active High. 0 Yes RW

5 Insert_Error Test Feature puts the RNG in the Error State. Active High. 0 Yes RW

4 Flush_Error Flushes LFSR error from system by reset and clear. Active High. 0 Yes RW

3 Clear_Error Clear LFSR error from system by generating a new Number. Active High. 0 Yes RW

2 Read_Req System Request for New Random Number. Need to be Reseted manualy after acknowledgeb by RNG

• 0 — No System Requests for New Random Number

• 1 — System Request for a New Random Number

0 Yes RW

1 RSVD This bit must be written as zero unlike other reserved bit. 0 N/A N/A

0 Noise_En Internal Ring Oscillator Enable/Disable.• 0 — Internal Ring Oscillator is Disabled• 1 — Internal Ring Oscillator is Enbaled

0 Yes RW

M821xx Data Sheet


6.2.8 ARM Clk Control 2 (ARM_CLK_CNTRL2)Default Value: 0x1414

6.2.9 PLL Status (PLL_STATUS)Default Value: 0x0

Table 6-9 Fields of ARM Clk Control 2 (ARM_CNTRL2)


Dyn Acc


12 ARM1_DIV_BYP ARM1 divider bypass Enable. Selects between ARM1_clk/Divider_val to ARM1_clk.

• 0 — Bypass Mode Disabled• 1 — Bypass Mode Enabled

1 Yes RW

11:8 ARM1_DIV_VAL ARM 1 divider value. 4 Yes RW


4 ARM0_DIV_BYP ARM0 divider bypass Enable. Selects between ARM0_clk/Divider_val to ARM0_clk

• 0 — Bypass Mode Disabled• 1 — Bypass Mode Enabled

1 Yes RW

3:0 ARM0_DIV_VAL ARM 0 divider value. 4 Yes RW

Table 6-10 Fields of PLL Status (PLL_STATUS)


Dyn Acc


1 AHBCLK_PLL_Lock AHBCLK PLL Lock Status. 0 N/A R

0 FCLK_PLL_Lock FCLK PLL Lock Status. 0 N/A R

M821xx Data Sheet


6.2.10 Random Number Status (RNG_STATUS)Default Value: 0x0

Table 6-11 Fields of Rndm Nbr Status (RNG_STATUS)


Dyn Acc


17 Noise_Error A pair-wise consistency or lock-up error exists 0 Yes R

16 RNG_Busy RNG Request Status• 0 — RNG is ready for a new Request• 1 — RNG cannot process a new Request

0 Yes R

15:0 Rndm_Number 16-bit Random Number Output 0 Yes R

M821xx Data Sheet


6.3 Reset RegistersReset Registers are detailed:

6.3.1 Register: Block Reset (BLK_RESET)Default Value: 0x0


Register Address DescriptionBLK_RESET 0x100 Block Reeset

AHB_CLK_CNTRL 0x104 CSP Reset

Table 6-13 Fields of Block Reset (BLK_RESET)


Dyn Acc


12 RNG_Reset_N • 0 — Keep RNG block in Reset• 1 — De-activate Reset

0x0 Yes R/W

11 IPSEC_Reset_N • 0 — Keep IPSEC block in Reset• 1 — De-activate Reset

0x0 Yes R/W

10 DDR_Reset_N • 0 — Keep DDR block in Reset• 1 — De-activate Reset

0x0 Yes R/W

9 RSVD 0x0 N/A N/A

8 RSVD 0x0 N/A N/A

7 USB1_Reset_N • 0 — Keep USB1 IF in Reset• 1 — De-activate Reset

0x0 Yes R/W


0x0 Yes R/W

5 GEMAC1_Reset_N • 0 — Keep GEMAC1 IF in Reset• 1 — De-activate Reset

0x0 Yes R/W


0x0 Yes R/W

3 TDM_Reset_N • 0 — Keep TDM IF in Reset• 1 — De-activate Reset

0x0 Yes R/W

2 PUI_Reset_ • 0 — Keep PUI IF in Reset• 1— De-activate Reset

0x0 Yes R/W

1 HIF_Reset_N • 0 — Keep Host IF except PCI IF and all PCI Clock circuitry in Reset

• 1 — De-activate Reset

0x0 Yes R/W

0 PCI_IF_Reset_N • 0 — Keep PCI IF and all PCI Clock circuitry in Reset


0x0 Yes R/W

M821xx Data Sheet


6.3.2 CSP Reset (CSP_RESET)Default Value: 0x1

Table 6-14 Fields of CSP Reset (CSP_RESET)


Dyn Acc


0 CSP_Reset_N 0 — Keep CSP in Reset

1 — De-activate Reset

0x1 Yes R/W

.


7.0 Expansion Bus Interface

7.1 Features• Support for up to 5 peripheral devices. NAND flash and 4 general-purpose device interfaces, i.e.

NOR flash devices. NAND flash chip-select is controlled by software and driven on a GPIO pin. When NAND flash is not used, a 5th generic device can be supported.

• Support for 8, 16 and, on M8219x devices, 32-bit data bus interfaces; configurable per chip select.

• AHB transaction size that is larger than the external bus width will be split into separate transactions by the Expansion Bus Interface block, meanwhile halting the AHB interface.

• Programmable chip select level, configurable per chip select.

• Each chip-select supports up to 4M of memory address space.

• Chip-select 0 is dedicated to external boot flash when used, enabled by default. Otherwise, it can be configured to support any generic peripheral device.

• 2 input pins are used to set the default bus size of chip-select 0 device, 8/16-bit data bus can be selected. This bus size may be overwritten by software to support an 8-, 16-, or 32-bit Expansion Bus Interface.

• Provides support for multiplexed address-data mode with address latch enable.

• Programmable timings per chip select; counts in terms of expansion clock cycles.

• Support for byte-enable writes, up to 4 bytes on the Expansion Interface.

• Provides support for Ready/Busy# acknowledge signal for terminating transactions. Detecting the de-assertion of Read/Busy# signal will override the Chip-Select and Write Enable/ Read Enable to be de-asserted for the current transaction. Detection of Ready signal on rising/falling edge is configurable.

• Synchronous interface. The AHB clock can be a divide down by 5, 6 or 7. The divide integer is configurable by software, default is set to 7. Sync clock max frequency will be 33 MHz (AHB Clock 165 MHz divide by 5).

• External expansion clock is provided and maybe suppressed by software, when not used by any of the peripherals. All programmable timing parameters are synchronized to this expansion clock.

• Two separate sets of read/write controls are provided; one set is dedicated for NAND flash: WE_NAND#/RE_NAND#, and the other set is for the generic devices: EXP_RE/ EXP_WE.

• Extended support for External flash devices are provided through GPIO pins when enabled.

M821xx Data Sheet


7.2 Expansion Bus Functional DescriptionFor a view of the Expansion Bus block within the top-level block diagram, see Figure 2-1.

The Expansion Interface controls data flow to / from up to 4 generic memories and 1 dedicated NAND Flash device. When NAND Flash is not used, a fifth generic memory device may be used. Initially CS0, which is part of the generic interface, can be configured to be used for the external boot flash, occupying address space zero of the expansion memory map; two pins will determine the external boot flash bus size.

When the Expansion Bus Interface block is accessed by the system, the Expansion controller will fetch/store data from/to these memory flash like devices until de-selected. Depending on the memory device type being accessed, the required timing parameters are configured to comply with the device timing-requirements, before initiating any transactions. RDY pulse sampling, when supported, will be synchronized to AHB clock (HClk) before causing the de-assertion of the CS and the RE or WE control signals. The read data will be latched upon de-assertion of the CS or RE signal, whichever comes first. A configuration bit per chip-select is provided to enable/disable detection of the RDY signal and should be disabled for devices don’t provide the RDY signals. If RDY signal, when enabled, is not detected, will cause an error response on the AHB interface.

Figure 7-1 Expansion Bus Block Diagram

GenericPeripheral

Device#4or

NANDFlash

GenericPeripheral

Device#1- 3

Expansion BusController

Block

GenericPeripheral

Device#0or

Boot Flash

CS# 0

CS# 1 - 3

Data & Strobes

Addr & Control

APB Bus

AH

B B

us

AHB I/F

APB

I/F

Dali Chip

CS# 4

GPIONAND Strobes

NAND CS#

M821xx Data Sheet


7.2.1 NAND Flash AccessAs for the NAND Flash, when accessed (an AHB access to its space), the software will control the CLE and ALE signals as well as the device Chip-select through GPIO dedicated pins. The Expansion Bus Controller will provide the flash address/data/command and drive the NAND_WE # \NAND_RE# signals. Each NAND flash access phase will be considered a full expansion bus access cycle.

7.2.2 AHB Address DecodingAccesses to the Expansion Interface block are decoded internally to assert the appropriate chip-select of the targeted device. 64-bit AHB input data will be latched in case of write operations. Depending on the peripheral bus size used, the latched data will be transferred over decoded number of expansion cycles. The maximum number of expansion cycles to write 64-bit data over an 8-bit bus peripheral will be 8 cycles, meanwhile the AHB bus is halted until all data bytes are transferred. In case of read operations, the input data from the peripheral device is latched and formatted over a 64-bit AHB bus according to the peripheral bus size selected. The read data is duplicated over the 64-bit AHB data bus, i.e. if MEM_SIZE is set to 16, the read byte will be latched over all half-words of AHB data bus.

Figure 7-2 Expansion Bus Chip Select Region

CS0#

CS1#

CS2#

CS3#

CS4#

Default

Default

Default

Default

Default

Default

0x2000_0000

0x2040_0000

0x2400_0000

0x2440_0000

0x2800_0000

0x2840_0000

0x2C00_0000

0x2C40_0000

0x3000_0000

0x3040_0000

0x3FFF_FFFF

M821xx Data Sheet


Depending on the memory size and the access size, the expansion address bus is decoded from the internal AHB address bus. The lowest bit of the AHB bus is dropped when a half word access is performed, and the lowest two bits are dropped when a word access is performed. Hence, word accesses are always aligned to word boundaries in memory. Depending on the memory size, the interface will complete the Expansion bus address with the Expansion cycle count bits, and decode the DM signals.

7.3 Signal DescriptionThe control signals unique to NAND FLASH interfacing are controlled by software through GPIO pins.

NOTE: AHB accesses outside the expansion chip-selects allocated memory segments will cause an AHB Error response.

Table 7-1 Expansion Bus Interface Signals

Signal Name Dir Size Signal Description

EXP_CLK O 1 Expansion Bus Clock — to the peripheral devices. This clock is generated in the Expansion Block by dividing down the AHB clock by any of the following integers: 5, 6 or 7. Ranges from 23.6 to 33 MHz. This clock is gated-off when accessing asynchronous devices by setting EXP_CLK_EN to 0.

EXP_CS#[3:0] O 4 Expansion Bus Chip Select — Chip Selects with programmable active level, enable and disable selection of the targeted peripheral devices. EXP_CS0 will be dedicated to select external boot flash when used.

EXP_WE# / EXP_RW#

O 1 Write Enable / Read-Write Normal Mode: Write Enable, when asserted, indicates a write operation to peripheral.Strobe Mode: Read/Write Enable signal. Assertion level of this signal is configurable.

EXP_RE# /EXP_STRB#

O 1 Read Enable / StrobeNormal Mode: Read Enable, when asserted, indicates a read operation from peripheral.Strobe Mode: Command Strobe signal.Assertion level of this signal is configurable.

EXP_NAND_RE# O 1 Read Enable dedicated for NAND Flash — when asserted low, indicates a read operation from flash device. Assertion level of this signal is configurable.NAND flash chip-select is driven by software through GPIO pin.

EXP_NAND_WE#/EXP_CS#[4]

I 1 Write Enable dedicated for NAND Flash — when asserted low, indicates a write operation to the flash device. When NAND flash is not used, this pin can be used as a chip-select and can be configured to support generic peripheral device. Assertion level of this signal is configurable.Note: NAND flash chip-select is driven by software through a GPIO pin.

EXP_DM[3:0] O 4 Data Byte Mask — Input data byte to the peripheral device is masked when DM is sampled high during a write access. One DM pin per data byte.

EXP_RDY_BSY# I 1 Peripheral Device Ready / Busy Status — When set low indicates that the current transaction is in progress. Set high when the device is ready for a new transaction. Detection edge of this signal is configurable (high->low) or (low->high). When detected will cause de-assertion of the CS and RE/WE for the current transaction.

M821xx Data Sheet


EXP_A_L_[14:0]EXP_A_U_[21:15]

O 22 Expansion Address Bus — Specifies one Memory location along with the DM[3:0] when supported. Will address 4M of memory address space, per chip-select.Internally 24 bits are supported, but only 22 of the 24 bits are output from the device.

Muxing of lower Expansion Bus to bootstraps active on reset:EXP_A_L_0/ TM_MII0_MODE1EXP_A_L_1 / TM_MII0_MODE0EXP_A_L_2 / TM_MII1_MODE0EXP_A_L_3 / TM_BOOT_OP1EXP_A_L_4 / TM_BOOT_OP0EXP_A_L_5 / TM_GPBT_OP3EXP_A_L_6 / PCIMODE / HBMODE#EXP_A_L_7 / PCIHOST# / HBBURSTEN#EXP_A_L_8 / TD_TDM_CLKSRC_ENEXP_A_L_9 / HBBUSSIZE0EXP_A_L_10 / HBBUSSIZE1EXP_A_L_11 / TM_GPBT_OP0EXP_A_L_12 / TM_GPBT_OP1EXP_A_L_13 / TM_GPBT_OP2EXP_A_L_14 / TM_MII1_MODE1

Muxing of upper Expansion Bus to GPIOs:EXP_A_U_15 / GPIO08EXP_A_U_16 / GPIO09EXP_A_U_17 / GPIO10EXP_A_U_18 / GPIO11EXP_A_U_19 / GPIO12EXP_A_U_20 / GPIO13EXP_A_U_21 / GPIO14

EXP_ALE O 1 Address Latch Enable — The ALE, active high output, controls address latching to the peripheral device when multiplexed address / data bus mode is used.

EXP_DQ[31:0] B 32 Data Bus — Will be configured to support 8, 16 or 32 active bits. For 8-bit, EXP_DATA[7:0] and for 16-bit EXP_DATA[15:0] are active. Least significant bits are always active.NOTE: 32-bit data bus only supported in M219x devices.

Table 7-1 Expansion Bus Interface Signals (Continued)


M821xx Data Sheet


7.4 Modes of OperationThis block is highly configurable per chip select to accommodate for most common types of memory/flash in the industry. Four modes of operation can be configured to support the targeted peripheral timings. Note that EXP_CS4 is muxed with the EXP_NAND_WE_N. Chip-select 4 address space will be used by the NAND chip-select (GPIO pin) when NAND_MODE is enabled (default). Setting NAND_MODE to 0 and CS4_EN to 1 will disable NAND support, and CS4 pin will be used to access generic peripheral.

These modes support both, Synchronous and asynchronous devices. By default, synchronous support is set and the output expansion clock is provided by setting EXP_CLK_EN global bit to 1 (high). When a asynchronous device is accessed, EXP_CLK_EN global bit should be set to 0 (low) which will suppress expansion clock output.

7.4.1 Normal ModeThis mode is supported by all chip selects, and is set by programming the following configuration bits:

• ALE_MODE = 0

• STRB_MODE = 0

• NAND_MODE = 0 (CS4 will be used as the 5th chip-delect)

Normal Mode is the default mode for all chip selects except for 5th chip-select which requires NAND_MODE to be set to 0. Table 7-2, Normal Mode Signal List and Figures 7-3 and 7-4 depict the list of external pins that are valid when the Normal mode is set.

M821xx Data Sheet


The following timing diagram shows the Normal Mode relative signals and their programmable fields. CS and the RE or WE command will be asserted, depending on the access type, after a programmed number of expansion clock cycles from the active address. Note that, the expansion clock is a divide down frequency from the AHB clock; it is generated from dividing down hclk by one of the configured divide integers (5, 6, or 7).

In the read cycle, the data bus is tri-stated and data is expected to be ready sometime after the assertion of the RE command. The expansion controller will latch the data upon de-assertion of either the RE command or the CS signal, whichever comes first. The CS is terminated after the expiration of the CS

Table 7-2 Normal Mode Signal List



EXP_CS#[3:0] O 4 Expansion Bus Chip Select — Chip Selects with programmable active level, enable and disable selection of the targeted peripheral devices. Active level will be configuralble by software.

EXP_CS#4/EXP_NAND_WE#

O 1 Write Enable dedicated for NAND Flash — when asserted low, indicates a write operation to the flash device. When NAND flash is not used, this pin can be used as a chip-select and can be configured to support generic peripheral device. Assertion level of this signal is configurable.Note: NAND flash chip-select is driven by software through a GPIO pin.

EXP_RE# O 1 Read Enable — Read Enable. When asserted indicates a read operation from peripheral. Active level is configurable by software.

EXP_WE# O 1 Write Enable — When asserted, indicates a write operation to peripheral. Active level is configurable by software.

EXP_DM[3:0] O 4 Data Byte Mask — Input data byte to the peripheral device is masked when EXP_DM is sampled high during a write access. One EXP_DM pin per data byte. The timing of these signals is configurable by writing to DM_MODE field:0: DM timing will mimic the EXP_CS.1: DM timing will mimic the EXP_WE command.

EXP_RDY / BSY# I 1 Peripheral device ready/busy status — When set low indicates that the current transaction is in progress. Set high when the device is ready for a new transaction. Detection edge of this signal is configurable (high->low) or (low->high). When Detected will cause de-assertion of the CS and RE/WE for the current transaction.

EXP_A[21:0] O 22 Expansion Address Bus — Specifies one Memory location along with the DM[3:0] when supported. Will address 4M of memory address space, per chip-select.

EXP_DQ[31:0] B 32 Data bus — MEM_BUS_SIZE field of the Chip Select Configuration register is used to configure the peripheral interface width:00: Peripheral has an 8 bits data bus interface.01: Peripheral has a 16 bits data bus interface.10: Peripheral has a 32 bits data bus interface.11: Reserved.NOTE: 32-bit data bus only supported in M219x devices.

M821xx Data Sheet


width count or upon detection of the de-assertion of the RDY signal provided by the device (when enabled by setting EXP_RDY_EN to 1).

During the Write cycle, CS and WE command are asserted some programmable cycles after the valid address. The external device is expected to latch the data by the de-assertion of the WE command. The data will be held valid for some programmable cycles after the de-assertion of the CS.

Next Read/Write transaction can only be started after the expiration of the Data-hold time count.

When EXP_RDY_EN bit is set high, detected RDY pulse will be synchronized to AHB clock (HClk) before causing the de-assertion of the CS and the RE or WE control signals, as was mentioned above, that the read data will be latched upon de-assertion of the CS or RE signal, whichever comes first. A configuration bit per chip-select is provided to enable/disable detection of the RDY signal and should be disabled for devices that don’t provide the RDY signals. If case of RDY is enabled and was not detected by the expansion controller before the de-assertion of the CS, an error response will be indicated on the AHB interface for this transaction.

In Figure 7-4 in regards of the read and write commands, when a read access is being performed, only RE signal will toggle. Also, when a write command is being performed, only WE command will toggle, not both.

Figure 7-3 Normal Mode Timing Diagram (RDY_EN = 0)

NOTE: AHB accesses outside the expansion chip-selects allocated memory segments will cause an AHB Error response.

M821xx Data Sheet


.

7.4.2 ALE ModeThis mode is supported by all chip selects, and is set by programming the following configuration bits:

• ALE_MODE = 1

• STRB_MODE = 0

• NAND_MODE = 0 (CS4 will be used)

ALE Mode can be supported by chip selects 0-3 by setting ALE_MODE bit to 1. Also chip select 4 shall support this mode when ALE_MODE is set to 1 and NAND_MODE is set to 0. In this mode, the data bus will be used to transfer both the valid address and valid data, Active high EXP_ALE will be used by the peripheral device to latch the valid address. The valid address should be stable for the configured address hold time before placing valid data on the bus in case of writes. Read data will be latched by the Expansion controller upon de-assertion of the EXP_RE signal or EXP_CS, whichever comes first. Valid address will also be driven on the address bus, to provide support for devices that may require it.

Table 7-3, ALE Mode Signal List and Figure 7-5 depict the list of signals that are valid when the ALE mode is set:

Figure 7-4 Normal Mode Timing Diagram (RDY_EN = 1)

M821xx Data Sheet


Table 7-3 ALE Mode Signal List

Signal Names Dir Size Signal Description


EXP_CS#[3:0] O 4 Expansion Bus Chip Select — Chip Selects with programmable active level, enable and disable selection of the targeted peripheral devices. Active level will be configuralble by software.

EXP_CS#4 / EXP_NAND_WE#

O 1 Chip Select #4 — EXP_CS4 configuration bit must be set high in order to support the 5th peripheral. By default this pin is used as NAND flash write enable pin (EXP_NAND_WE#) when CS4_EN is set low. Active level is configurable by software.

EXP_RE# O 1 Read Enable — When asserted indicates a read operation from peripheral. Active level is configurable by software.

EXP_WE# O 1 Write Enable —When asserted, indicates a write operation to peripheral. Active level is configurable by software.

EXP_DM[3:0] O 4 Data Byte Mask —Input data byte to the peripheral device is masked when EXP_DM is sampled high during a write access. One EXP_DM pin per data byte. The timing of these signal is configurable by writing to DM_MODE field:00: Disabled. DM signals will be masked.01: DM timing will mimic the EXP_CS.10: DM timing will mimic the EXP_WE command.

EXP_RDY / BSY# I 1 Peripheral Device Ready/Busy Status — When set low indicates that the current transaction is in progress. Set high when the device is ready for a new transaction. Detection edge of this signal is configurable (high->low) or (low->high). When Detected will cause de-assertion of the CS and RE/WE for the current transaction.

EXP_DQ[31:0] B 32 Expansion Multiplexed Address/Data Bus — During the address phase, EXP_ALE pulse is used by the peripheral to latch the address. After address hold-time the data will be valid on the bus.MEM_BUS_SIZE field of the Chip Select Configuration register is used to configure the peripheral interface width:00: Peripheral has an 8 bits data bus interface.01: Peripheral has a 16 bits data bus interface.10: Peripheral has a 32 bits data bus interface.11: Reserved.NOTE: 32-bit data bus only supported in M219x devices.

EXP_ALE O 1 Address Latch Enable pulse, used by the peripheral device to latch the valid address.

EXP_ADDR(21:0) O 22 Expansion Address Bus

M821xx Data Sheet


.

7.4.3 Strobe ModeThis mode is supported by all chip selects, and is set by programming the following configuration bits:

• ALE_MODE = 0• STRB_MODE = 1• NAND_MODE = 0 (will use CS4)

This mode can be supported by chip selects 0-3 by setting STRB_MODE bit to 1. Also chip select 4 shall support this mode when STRB_MODE is set to 1 and NAND_MODE is set to 0. In this mode, EXP_WE# pin will be used by the peripheral device as EXP_RW# command signal. Also, EXP_RE# pin will be used by the peripheral as the EXP_STRB command strobe signal. The active level of these 2 signals is configurable, depending on the polarity supported by the peripheral device.

Table 7-4, Command Strobe Mode Signal List and Figure 7-6 depict the list of signals that are valid when the Command Strobe mode is set.

Figure 7-5 ALE Mode Timing Diagram

M821xx Data Sheet


Table 7-4 Command Strobe Mode Signal List


EXP_CLK O 1 Expansion Clock to the Peripheral Devices — This clock is generated in the Expansion block by dividing down the AHB clock by any of the following integers: 5, 6 or 7.This clock is suppressed when EXP_CLK_EN is set to 0.

EXP_CS[3:0] O 4 Chip Selects #0-3 — are supported by default. enables and disables selection of the targeted peripheral devices. Active level is configurable by software.

EXP_CS#4 / EXP_NAND_WE#

O 1 Chip Select #4 — CS4_EN configuration bit must be set high and NAND_MODE must be low, in order to support the 5th peripheral. By default this pin is used as NAND flash write enable pin (Exp_NAND_WE#)) when NAND_MODE is set high. Active level is configurable by software.

EXP_RE# / EXP_STRB

O 1 Command Strobe — By default, when set low, This signal is used by the peripheral for command strobing. Active level is configurable by software.

EXP_WE# / EXP_RW#

O 1 Read/Write Enable — By default, when set high, indicates a read operation from peripheral. When asserted low, indicates a write transaction to the peripheral. Active level is configurable by software.

EXP_DM[3:0] O 4 Data Byte Mask — Input data byte to the peripheral device is masked when EXP_DM is sampled high during a write access. One EXP_DM pin per data byte. The timing of these signal is configurable by writing to DM_MODE configuration bit:0: DM timing will mimic the EXP_CS timing. (Default)1: DM timing will mimic the EXP_WE command timing.

EXP_RDY / BSY# I 1 Peripheral Device Ready/Busy Status — When set low indicates that the current transaction is in progress. Set high when the device is ready for a new transaction. Detection edge of this signal is configurable (high->low) or (low->high). When Detected will cause de-assertion of the CS and RE/WE for the current transaction.

EXP_ADDR [21:0] O 22 Expansion Address Bus — Specifies one Memory location along with the DM[3:0] when supported. Will address 16Mbyte of memory space, per chip-select.

EXP_DQ[31:0] B 32 Data Bus — The MEM_BUS_SIZE field of the Chip Select Configuration Register is used to configure the peripheral interface width:00: Peripheral has an 8 bits data bus interface.01: Peripheral has a 16 bits data bus interface.10: Peripheral has a 32 bits data bus interface (supported only on 821x devices)11: Reserved.NOTE: 32-bit data bus only supported in M219x devices.

M821xx Data Sheet


.

7.4.4 NAND ModeThis mode is relevant for CS4 only, chip select #4 will be used as the NAND write enable signal (Exp_nand_we_n). Not supported by the chip selects #0-3. This mode is set by programming the following configuration bits (set by default):

• ALE_MODE = 0

• STRB_MODE = 0

• NAND_MODE = 1 (disables CS4)

The chip select and latch controls for this mode are provided by a dedicated GPIO pin. NAND_RE/NAND_WE commands, address and data are initiated by the expansion block as an expansion cycle. Each NAND transaction should be broken up into several expansion (Normal Mode type) transactions. The software has the ultimate control over NAND transactions. NAND ECC support is also provided by software only.

The following Table 7-5, NAND Mode Signal List and Figures 7-7, 7-8, and 7-9 depict the list of signals that are valid when the NAND mode is set:

Figure 7-6 Strobe Mode Timing Diagram

NOTE: In this mode, both EXP_RW# and EXP_STRB# signals shall be switching within read and write transactions. The read data will be sampled by the Expansion Bus Interface block upon de-assertion of the EXP_CS or EXP_STRB, whichever comes first.

M821xx Data Sheet


.

Table 7-5 NAND Mode Signal List


NAND_CS# (GPIO29)

O 1 Chip Selects — Enables and disables selection of the targeted NAND peripheral device. Driven by software.

NAND_RE# O 1 Read Enable dedicated for NAND Flash — when asserted low, indicates a read operation from flash device. Assertion level of this signal is configurable. Not assigned a dedicated GPIO pin.

NAND_WE# O 1 Write Enable dedicated for NAND Flash — when asserted low, indicates a write operation to the flash device. When NAND is not used, this pin can be configured as a peripheral chip-select. Assertion level of this signal is configurable.Not assigned a dedicated GPIO pin.

NAND_RDY/BSY# (GPIO06)

I 1 NAND operating condition Ready/Busy# — When high indicates that the device is ready for access. When set low indicates no access will be granted.

NAND_ALE (GPIO30)

O 1 NAND Address Latch Enable — The NAND_ALE output controls writing to the address register. When ALE is high, the address is loaded on the rising edge of WE#. NAND_ALE must remain high during the entire address sequence.

NAND_CLE (GPIO31)

O 1 NAND Command Latch Enable — The CLE output controls writing to the command register. When CLE is high, the command is loaded on the rising edge of WE#.

EXP_DATA[31:0] B 32 Expansion multiplexed Address/Data Bus — During the address phase, NAND_ALE pulse is used by the peripheral to latch the address. After address hold-time the data will be valid on the bus.MEM_BUS_SIZE field of the Chip Select Configuration Register is used to configure the peripheral interface width:00: Peripheral has an 8 bits data bus interface.01: Peripheral has a 16 bits data bus interface.10: Peripheral has a 32 bits data bus interface.11: Reserved.NOTE: 32-bit data bus only supported in M219x devices.

Figure 7-7 NAND Command Latch Timing Diagram

1

Command

NAND_CLE (GPIO)

NAND_CS (GPIO)

NAND_WE

NAND_ALE (GPIO)

EXP_Data

M821xx Data Sheet


.

.

Each toggle of WE or RE to access the NAND flash will be executed over a full expansion cycle, from the point view of the expansion bus, it is an expansion cycle in normal mode. The software initiates a transaction in the NAND allocated address space, which will cause an expansion cycle to be started. During the NAND Address cycle or the NAND Command cycle, the software will initiate the write transaction to the NAND address space placing the NAND address or command type value on the data bus. The expansion controller will issue a write access to the NAND flash, as if accessing a generic device. The software at the meantime will drive the NAND chip-select and the controls (CLE/ALE) through dedicated GPIO pins.

Note that NAND_RE and NAND_WE will not be toggled when there is an access to CS#[3:0].

Figure 7-8 NAND Addrss Latch Timing Diagram

Figure 7-9 NAND Data Latch Timing Diagram

1

Addr1 Addr2 Addr3

NAND_CLE (GPIO)

NAND_CS (GPIO)

NAND_WE

NAND_ALE (GPIO)

EXP_Data

1

Data1 Data2 DataN

NAND_CLE (GPIO)

NAND_CS (GPIO)

NAND_ALE (GPIO)

NAND_WE

EXP_Data

M821xx Data Sheet


7.5 Examples for Boot Flash ConfigurationsChip-select 0 is dedicated for external boot when used. By default, EXP_CS0 is enabled and configured to operate in the Normal Mode. The External flash bus width is determined by the 2 input pins to the expansion block. Mode fields are configured as the following:

• ALE_MODE = 0• STRB_MODE = 0

7.6 ClocksOne clock is input to the expansion block running at AHB clock rate (165MHz). The expansion block has a built in ExpClk Generator, which is responsible of generating a divided synchronous clock to the external peripherals with a maximum of 33 MHz. A clock switch selects, glitch-free, between AHB clock and the divider output, and shall default to AHB Clock upon reset and will switch to the divided AHB clock right after reset ends.

Power down logic shall be default to activate the clock. When reset is asserted, output clock might have glitches when switching to reference clock.

This clock generator circuitry can be configured to divide the AHB clock with the following divide values: 5,6 and 7.

7.7 ResetAsynchronous reset will be used to reset the block’s internal logic. This reset may be a combination of the HW and SW resets provided by the chip and is synchronized externally to the AHB clock. A self-clear soft reset can be generated by the block’s internal configuration logic when asserted by software. This self-clear reset will reset the entire block’s logic synchronously. Configuration register are not affected by the block’s soft-reset.

7.8 Control RegistersFor expansion bus information, refer to Section 8.0 Expansion Bus Interface Registers on page 137.

M821xx Data Sheet


7.9 Expansion Interface AC Timing

Table 7-6 AC Timing Parameters

Figure 7-10 Expansion Bus AC Timing

NOTE: These timing parameters are with respect to the M821xx. Timing requirements for peripheral devices may vary.

Symbol Parameter Min. Max. Units Notes

EXP_CLK (Frequency) 23.6 33 MHz

EXP_CLK Duty cycle 40 60 %

Tod Expansion Outputs relative the rising edge of the EXP_CLK(Output Delay Time)

0 11 ns (1)

Tis Expansion Inputs Setup Time for read data with respect to the rising edge (When Trdy is not used)

1 Cycle (2)

Tih Expansion Inputs Hold Time for read data with respect to the rising edge (When Trdy is not used)

0 ns (3)

Trdy Ready Input required pulse width 9 ns (4)

Tvd Expected valid data after the rising/falling edge of the RDY Pulse. Since the active low RDY edge detection is configurable.

0 ns (5)

NOTES:1) Test Load 50pF.2) Tis (min) value should be configured to be at least 1 EXP_CLK cycle.3) Tih timing is relevant to the cycle in which CS and/or RE is de-asserted.4) RDY is sampled and synchronized by HCLK (165MHz).5) Due to RDY synchronization logic before valid input data latching.

M821xx Data Sheet


7.10 Notes Regarding Asynchronous InterfaceFor an example of asynchronous timing, see Figure 7-4, Normal Mode Timing Diagram (RDY_EN = 1).

1. When Expansion output signals are changing on the same clock edge, the delay between these signals is considered to be between 0 -11 (ns).

2. When Expansion output signals are changing on different clock cycles, the maximum delay between these signals is considered to be: Nx(Period of EXP_CLK)-11 (ns) to Nx(Period of EXP_CLK)+11 (ns) where N depends on the configured parameters.

3. The read data (if exp_rdy is not used) relative to rising edge of CS or RE (whichever de-asserted first) should be at least (EXP_CLK Period)+11 (ns).

4. Upon EXP_RDY de-assertion state, expansion transaction may be completed within 2 EXP_CLK cycles when relative configuration parameters are set to minimum values.

5. The cycle in the figure in which the read data is sampled upon de-assertion of RE and/or CS whichever comes first.

6. While in Asynchronous mode (when RDY is used), the design does not guarantee the relationship between the CS and RE/WE signals. Since the detection of RDY pulse will cause the de-assertion of the CS and RE/WE signals simultaneously.

DSH Mindspeed Technologies™8-155Mindspeed Proprietary and Confidential

8.0 Expansion Bus Interface Registers

For details on accessing these registers, see Register Access Modes.

8.1 Register Map

NOTE: The memory addressing of the Expansion Bus is offset from the base address:0x 101A 0000.

Table 8-1 Register Map for Expansion Bus Registers

Register Address Description

EX_SWRST_ R 0x0 Expansion Soft-Reset Register

EX_CSEN_ R 0x4 Expansion Chip Select Enable Register

EX_CS0_SEG_ R 0x8 EXP_CS0 Segment Size Configuration Register

EX_CS1_SEG _ R 0xC EXP_CS1 Segment Size Configuration Register

EX_CS2_SEG _ R 0x10 EXP_CS2 Segment Size Configuration Register



EX_CS0_CFG_ R 0x1C Expansion Chip Select 0 Configuration Register

EX_CS1_CFG_ R 0x20 Expansion Chip Select 1 Configuration Register



EX_CS4_CFG_ R 0x2C Expansion Chip Select 4 Configuration Register

EX_CS0_TMG1_ R 0x30 EXP_CS0 Timing parameter 1 Configuration Register



EX_CS3_TMG1_ R 0x3C EXP_CS3 Timing parameter 1 Configuration Register




M821xx Data Sheet


8.2 Control Registers

8.2.1 Expansion Soft-Reset (EX_SW_RST_R)Default Value: 0x0









EX_CLOCK_DIV_R 0x6C Expansion Clock Divider Configuration

RSVD 0x70 - 0xFFFF Reserved

NOTE: “No” in the Dyn field of the register description table means that: this field shall be configured before the associated Chip-Select Enable configuration bit is set.

Table 8-2 Fields of Expansion Soft-Reset (EX_SW_RST_R)

Bits Field Name Description Reset Value Dyn Acc

31:1 RSVD Reserved N/A N/A N/A

0 SW_RST 2-cycle self-clear soft-reset pulse used to reset the entire expansion block internal logic synchronously. Configuration registers are not affected.

0 Yes RWSC

Table 8-1 Register Map for Expansion Bus Registers (Continued)


M821xx Data Sheet


8.2.2 Expansion Chip-Select Enable (EX_CS_EN_R)Default Value: 0x3

8.2.3 Expansion Memory Segment Size (EX_CSx_SEG_R); Where x = 0 – 4These registers configure the upper end of the memory region associated with each chip select. See Figure 7-2.

Default Value: 0x3FF

Table 8-3 Fields of Chip Select Enable (EX_CS_EN_R)



5 CS4_EN Chip-select 4 Enable/Disable; to disable should be done at the end of the current transaction.0: Disabled1: Enabled

0 Yes RW


0 Yes RW


0 Yes RW


0 Yes RW


1 Yes RW

0 EXP_CLK_EN Enable/disable expansion clock output:1: Enable expansion output clock to the external interface.0: Disable (gate-off) expansion output clock.

1 No RW

Table 8-4 Fields of Memory Segment Size Control (EX_CSx_SEG_R)



9:0 SEG_SIZE This field specifies the upper limit address of Expansion EXP_ CSx in address space increments of 4 K. In other words, these 10 bits specify the ending EXP_A[21 – 12] of the address for EXP_CSx.

0x3FF No RW

M821xx Data Sheet


8.2.4 Chip Select x Configuration (EX_CSx_CFG_R); Where x = 0 – 4Each expansion chip-select has an associated configuration register that is configured to the access and timing requirement of the external peripheral device supported. Chip Select 0 is dedicated for NOR boot ROM when external boot is selected.

Default Value: 0x200

Table 8-5 Fields of Chip Select Control (EX_CSx_CFG_R)



11 EXP_RDY_EDG RDY pulse edge detection: (RDY is an active low signal).1: Rising edge detection of the RDY signal.0: Falling edge detection of the RDY signal.

0 No RW

10 EXP_RDY_EN Enable/disable expansion detection of RDY signal provided by the peripheral device:1: Enable expansion detection of the RDY signal.0: Disable expansion detection of the RDY signal.

0 No RW

9 NAND_MODE Enable/disable support for NAND flash (CS4 only):1: Enable NAND flash support.0: Disable NAND flash support, CS4 will be used as a generic Chip-select.Note: Only CS[4] can support NAND mode. This bit will return 0, for CS[3:0].

1 No RW

8 DM_MODE Used to decode Data Mask mode:0: DM timing will mimic the CS.1: DM timing will mimic the WE command.

0 No RW

7 STRB_MODE Strobe mode enable:0: Disabled: Both RE and WE command signals are used.1: Strobe Mode Enabled: Multiplexed RW command and data strobe are used. The WE signal is used to indicate the command type (RW), and the RE signal is used as the output strobe.

0 No RW

6 ALE_MODE Used to enable “Address Latch” mode.When set (enabled), address and data are assumed to be driven on the same bus (data bus). The ALE generated signal will be used by the peripheral to latch the address before the data is being placed on the bus.

0 No RW

5 RE_CMD_LVL Used to select RE commands level.0: Active low commands.1: Active high commands.

0 No RW

4 WE_CMD_LVL Used to select WE commands level.0: Active low commands.1: Active high commands.

0 0 RW

3 CS_LEVEL Used to select chip-select level.0: Active low chip-select.1: Active high chip-select.

0 0 RW

M821xx Data Sheet


8.2.5 Chip Select x Timing Configuration (EX_CSx_TMG1_R); Where x = 0 - 4Each Expansion Chip Select has an associated timing configuration register that specifies the timing configurations depending on its timing requirements.

Default Value: 0x1A1A401F

2:1 MEM_BUS_SIZE Used to select external peripheral interface size:00: Peripheral has an 8 bits data bus interface.01: Peripheral has a 16 bits data bus interface.10: Peripheral has a 32 bits data bus interface.11: Reserved.Note: for CS0, default size is defined by 2 input pins. The value of this field will overwrite the default value when block is out of reset.

0 0 RW

0 Reserved 1 0 RW

Table 8-6 Fields of Chip Select Control (EX_CSx_TMG1_R


31:24 WE_WIDTH Used to configure the Write commands (EXP_WE#, NAND_WE# and EXP_WR#) assertion pulse width in terms of Expansion slow clock cycles. Minimum width is 2 clock cycles. Maximum pulse width = 28-1

0x1A No RW

23:16 RE_WIDTH Used to configure the Read commands (EXP_RE#, NAND_RE# and EXP_STRB) assertion pulse width in terms of Expansion slow clock cycles. Minimum width is 2 clock cycles. Maximum pulse width = 28-1

0x1A No RW

15:12 ALE_WIDTH Used to configure the ALE assertion pulse width in terms of Expansion slow clock cycles. Minimum width is 1 clock cycle. Maximum ALE pulse width = 24-1

4 No RW

11:0 CS_WIDTH Used to configure the chip-select assertion pulse width in terms of Expansion slow clock cycles. Minimum width is 2 clock cycles. Maximum chip-select pulse width = 212-1

0x01F No RW

Table 8-5 Fields of Chip Select Control (EX_CSx_CFG_R) (Continued)


M821xx Data Sheet


8.2.6 Chip Select x Timing Configuration (EX_CSx_TMG2_R); Where x = 0 - 4Each Expansion Chip Select has an associated timing configuration register that specifies the timing configurations depending on its timing requirements.

Default Value: 0x6060A04

8.2.7 Chip Select x Timing Configuration (EX_CSx_TMG3_R); Where x = 0 - 4Each Expansion Chip Select has an associated timing configuration register that specifies the timing requirements of the address hold. This register is effective when ALE_EN bit is set.

Default Value: 0x2

Table 8-7 Fields of Chip Select Control (EX_CSx_TMG2_R)


31:24 SU_WE Used to configure EXP_WE, NAND_WE and EXP_RW commands setup in terms of Expansion slow clock cycles.This parameter determines the timing relation between the valid address and the assertion of the command.

6 No RW

23:16 SU_RE Used to configure EXP_RE, NAND_RE and EXP_STRB command setup in terms of Expansion slow clock cycles.This parameter determines the timing relation between the valid address and the assertion of the command.

6 No RW

15:8 H_DATA Used to configure Data hold time, in terms of Expansion slow clock cycles.This parameter determines the timing for the data to remain stable after de-assertion of the chip-select.

0A No RW

7:0 SU_DATA Used to configure Data setup in terms of Expansion slow clock cycles.This parameter determines the timing relation between the valid address and the assertion of the chip-select.

4 No RW

Table 8-8 Fields of Segment Size Control (EX_CSx_TMG3_R)



7:0 H_ADDR This configuration parameter is effective when ALE_EN bit is set. Used to configure Address hold time, in terms of Expansion slow clock cycles.This parameter determines the timing for the address to be stable on the data bus before valid data is to be driven.

2 No RW

M821xx Data Sheet


8.2.8 Clock Divider Configuration (EX_CLOCK_DIV_R)The Generated Expansion clock frequency is configurable in terms of AHB clock. The field is used to configure the divide count from the AHB clock frequency.

Default Value: 0x7

8.3 Register Access Modes

Table 8-9 Fields of Chip Select Control (EX_CLOCK_DIV_R



2:0 DIV_VAL Used to configure the frequency division integer of the AHB Clock to generate the Expansion slow clock to the external interface and for the internal logic use.Clock divide values are from 5to 7. Minimum configuration value is 5 (33MHz).

7 No RW

Table 8-10 Register Access Modes

ModeLetters Description

R Read Only. This register field may be read at any time. Writing to this register field is not permitted.

W Write Only. The result of reading from this register field is undefined.

RW Read-Write. The register field may be read at any time. Writing to the register field is permitted.

RC Read-Only, autonomous Clear. The register field resets to zero autonomously (usually when read).

RL Read-Only, Latched value. The value is the value of the register field that was latched when a specific event occurred (usually an external signal asserted such as One-Sec for counters).

RL_RC This register field can behave as either RC or RL, depending on a separate configuration field.

RWC Read-Write autonomous Clear. This register behaves like RW but may clear to zero autonomously (usually when read).

RWSC Read-Write Self-Clear. Same as RWC.

N No access. This field may not be read or written. Used only for Reserved addresses.

T Test access. R/W behavior is defined in description, or in non-test mode attributes.

Notes: “No” in the Dyn field of the register description table means that: This field shall be configured before the associated Chip-Select Enable configuration bit is set.

.


9.0 DDR2 SDRAM Interface

This section provides details on the Comcerto device’s DDR2 SDRAM controller.

For a view of the SDRAM interface within the top-level block diagram, see Figure 2-1.

For details on configuration, see Section 10.0 DDR2 SDRAM Registers on page 162.

9.1 DDR2 SDRAM Interface Features• Differential clock (CK and CK#) commands provided on each clock edge. Data is fetched/stored

on both edges of CK.

• Support of clock frequencies from 125 to 165 MHz.

• 16-bit or 32-bit data bus interfacing to x8 of x16 memories (x4 not supported). 16-bit interface intended for low-cost applications using a single x16 memory.

• Maximum bandwidth (theoretical) for 32-bit data bus: 10.5 Gbps (same as internal host bus). Maximum bandwidth (theoretical) for 16-bit data bus: 5.25 Gbps (half the internal host bus rate).

• Address bus supports up to 1 GByte of memory with two CS# signals.

• Four or eight internal banks for concurrent operation.

• Data mask (DM) for masking write data.

• Supports burst lengths of 4 cycles.

• Supports programmable auto-refresh.

• Configurable terminations: no termination, 75 Ω, 150 Ω.

• Drive strength:13.4mA.

• 1.8 V I/O (SSTL_18 compatible).

• Full initialization of memory on memory controller reset.

• A programmable register interface to control memory device parameters and protocols.

• Built-in adjustable Delay Compensation Circuitry (DCC) for reliable data send and capture timing.

• Support for DDR2 power-down.

NOTE: Mindspeed provides a DDR2 SDRAM design.

For details, refer to M821xx Hardware Requirements App Note (821xx-APP-002).

M821xx Data Sheet


9.2 Signal Description

9.3 DDR2 SDRAM Interface Bus Timing

Table 9-1 DDR2 Signals


DDR_CLKDDR_CLK#

O 2 Differential Clock Outputs — Differential DDR clock outputs.

DDR_CKE O 1 Clock Enable Active High — Active high clock enable signal.

DDR_CS# O 2 Chip Select — Active low chip select signal.

DDR_RAS# O 1 Memory Row Address Strobe — Active-low row address strobe signal.

DDR_CAS# O 1 Memory Column Address Strobe — Active-low column address strobe signal.

DDR_WE# O 1 Memory Write Enable — Active-low write enable strobe signal.

DDR_DM O 4 Data Byte Mask — Active-high data mask signal. In the 16 bit data bus mode only the 2 least significant bits are used.

DDR_BA O 3 Bank Select Address

DDR_A O 14 Adress Bus

DDR_DQ B 32 Data Bus — Bidirectional data line to the memory devices. In 16bit data bus mode only 16LSbits are used.

DDR_DQS B 4 Data Strobe — Bidirectional data strobes (one DQS per byte). In 16bit data bus mode only 2 least significant bits are used.

DDR_ODT O 2 On-Die Termination Signals.

Figure 9-1 DDR2 Write Cycle Timing

TSA THA

TSDW THDW

TDQSSmin TDQSSmax

CLOCK

ADDR/CMD

DQS

WRITE DATA

TCL TCH

M821xx Data Sheet


Table 9-2 DDR2 Timing Parameters

9.4 DDR2 SDRAM Configuration RegistersSection 10.0 DDR2 SDRAM Registers on page 162.

Figure 9-2 DDR2 Read Cycle Timing


TCH Clock high level width 46 54 %

TCL Clock low level width 46 54 %

TSA Setup time for address and command signals to rising edge of clock

2 ns

THA Hold time for address and command signals to rising edge of clock

2 ns

TSDW Setup time for data signals to DQS in write 0.75 ns 3

THDW Hold time for data signals from DQS in write 0.75 ns 3

TDQSS First DQS latching transition to associated clock edge

-1.2 0.5 ns 3

TDQSDQSK DQS-DQ skew for DQS and associated DQ signals

-0.85 0.85 ns 1

TRTRIP Round trip from chip to memory (CLK) and back (DQS)

3.5 5 ns 2

NOTES:1) The Input DQS-DQ skew is based on 50% Duty-Cycle of the DQS signal. In case the DC is not 50% the Min and Max

number need to be adjusted according to the following formula (where tck is the clock period):TDQSDQSK = 0.85 - ((0.5-DC) * tck /2)

2) The round trip calculation does not include the 0.5 ns maximal skew inside the memory from clock to DQS.3) The timing is for each DQS and its corresponding 8 bits of data.

TDQSDQSKmin

DQS

READ DATA

TDQSDQSKmax

.


10.0 DDR2 SDRAM Registers

10.1 Alternative ConfigurationsThese alternative configurations are based on experience using five different DDR2 SDRAM devices on different PCBs. Table 10-1 presents details on these configurations. The configuration letter “A” – “E” in the left-hand column is used to identify these configurations in this setion (for example in Table 10-2).

1

When only one “CFG” is shown in the register descriptions in the following subsections, it is because only one register setting worked with all the memories listed above.

Table 10-1 Alternative Memory Configurations

Configuration # Description Memory Device Number of Devices Total Memory

A ASIC check-out PCB Micron MT47H64M8CB-5E:B 512Mb (16 Meg x 8 x4 banks)

4 256 MB

B ASIC check-out PCB Micron MT47H128M8-5E 1Gb (16 Meg x 8 x 8 banks)

8 1 GB

C ASIC check-out PCB Samsung: K4T1G084QA-CC 1Gb (16 Meg x 8 x 8 banks)

8 1 GB

D Packet IAD PCB Micron MT47H32M16CC-5E 512Mb (8 Meg x 16 x 4 banks)

2 128 MB

E Router PCB Micron MT47H16M16BG-5E 256Mb (4 Meg x 16 x 4 banks)

2 64 MB

NOTE:The following sections group DDR2 SDRAM configuration settings based on whether they depend on the device or the system.

Typically device-dependent settings will remain the same even if you put the associated device in a different PCB layout.

If the PCB layout closely resembles one of the three PCBs identified above, there is a good chance the system-dependent settings associated with it will work.Importantly, the best configuration values may be ones other than shown here.

M821xx Data Sheet


10.2 Changing DDR2 SDRAM Interface RegistersThe bit fields listed in this document are typically not modified after DDR2 SDRAM initialization is complete.

For board bring up, debugging tools may be used to set and test memory configuration.

Eventually, software parameters in the boot code must be changed to properly initialize new designs. For information on UBOOT, see M821xx Linux BSP Technical Description (821xx-SWG-002).

Note that the registers on the AHB bus are 64-bits in width. As shown below, all the bit fields are aligned on 8-bit boundaries. Bit fields vary in length.

Figure 1-1: Example Bit Fields with 64-Bit Register

To modify, bit field settings, software can use 8-, 16-, 32-, or 64- bit addresses and transactions. When writing to fields other than those to be modified, care must be taken to avoid changing the configuration.

When writing to “Reserved” fields, always clear to ‘0’. In “Read-Modify-Write’”transactions, “Reserved” fields will always read as ‘0’s.

10.3 System-Dependent Bit FieldsThis section presents register bit fields depending on the configuration of the overall memory subsystem. These may be affected by DDR2 SDRAM implementation details like total size of memory, number of devices and PCB layout. Typically, these values are not affected by changes in the specific DDR2 SDRAM device.

NOTE: The memory addressing of the SDRAM configuration registers is offset from the base address: 0x 0D00 0000.

NOTE: This document presents register settings that worked with PCBs built by Mindspeed. These are not the only valid settings. Other settings may work with very similar designs using the same DDR2 SDRAM devices.

Please contact your Mindspeed FAE with any questions.

0816243240485664

081624

RESERVED RESERVED RESERVED

[1:0] BIT FIELD[10:8] BIT FIELD[16] BIT FIELD[25:24] BIT FIELD

M821xx Data Sheet


10.3.1 Memory Size Configuration

The AHB should be configured based on the max DDR2 address space:

10.3.2 DRIVE_DQ_DQSDDR2_CTL_01 (AHB address 0x0D000008)CFG# A, D, E: 0 x 0100000100000001CFG# B, C: 0 x 0100010100000001

Bit 32 selects if the DQ output enables and DQS output enables will be driven active when the memory controller is in an idle state.

• ’b0 = Leave the output enables de-asserted when idle.

• ’b1 = Drive the output enables active when idle.

10.3.3 POWER_DOWN, SREFRESHDDR2_CTL_02 (AHB address 0x0D000010)

CFG#1, 2, 3, 4, 5: 0 x 0100010000010100

During DDR2 SDRAM use, these fields remain the same:

• POWER_DOWN (bit 0) cleared to ‘0’

• SREFRESH (bit 24) cleared to ‘0’

Field details: Bit 0 (POWER_DOWN): When this parameter is written with a “1”, the memory controller will complete processing of the current burst for the current transaction (if any), issue a pre-charge all command and then disable the clock

Table 10-2 Memory Size Configuration

Configuration # DDR2 SizeValue of AHB’s

Max Memory Address Register(AHB Address: 0x1006 0010)

A 256 MB 0x8FFFFFFF

B 1 GB 0xBFFFFFFF

C 1 GB 0xBFFFFFFF

D 128 MB 0x87FFFFFF

E 64 MB 0x83FFFFFF

NOTE: This register field setting stays at ‘1’ in implementations tested by Mindspeed. Configuration alternatives are related to 8-bank mode.

M821xx Data Sheet


enable signal to the DDR2 SDRAM devices. Any subsequent commands in the command queue will be suspended until this parameter is written with a “0”.

• ’b0 = Enable full power state.

• ’b1 = Disable the clock enable and power down the memory controller.

Bit: 24 (SREFRESH): When this parameter is written with a ’b1, the DDR2 SDRAM device(s) will be placed in self-refresh mode. For this, the current burst for the current transaction (if any) will complete, all banks will be closed, the self-refresh command will be issued to the SDRAM, and the clock enable signal will be de-asserted. The system will remain in self-refresh mode until this parameter is written with a ’b0. The DRAM devices will return to normal operating mode after the self-refresh exit time (txsr) of the device and any DLL initialization time for the DRAM is reached. The memory controller will resume processing of the commands from the interruption point.

• ’b0 = Disable self-refresh mode.

• ’b1 = Initiate self-refresh of the DRAM devices.

10.3.4 CS_MAP, ODT_WR_MAP_CS0, ODT_WR_MAP_CS1DDR2_CTL_04 (AHB address 0x0D000020)CFG# A, D, E: 0 x 0000010100000001CFG# B, C: 0 x 0000010200000003

In Mindspeed implementations, CS_MAP has been successfully set to 0x1 and 0x3. Likewise, ODT_WR_MAP_CS0 has been set to 0x1 and 0x2. The other fields have remained the same across all memory implementations:

Bits 1:0 (CS_MAP) determine the number of active Chip Selects in the interface: Bit 0 activates DDR_CS#_0, and bit 1 activates DDR_CS#_1. Set to ‘b01 if DDR_CS#_0 is used alone, and set to ‘b11 in both DDR_CS#_0 and DDR_CS#_1. Note that ‘b10 is an invalid setting.

Bits 33:32: (ODT_WR_MAP_CS0) ODT Chip Select 0 map for writes. Determines which chip(s) will have termination when a write occurs on chip 0.

Bits 41:40:(ODT_WR_MAP_CS1) ODT Chip Select 1 map for writes. Determines which chip(s) will have termination when a write occurs on chip 1.

NOTE: Put the interface in Power-Down Mode only when the AHB Master will not read or write to the DDR2 SDRAM.

NOTE: Do not put the DDR2 SDRAM into self-refresh mode unless there will be no AHB Master accesses to the DDR2 SDRAM.

NOTE: When only one row of memory devices is used (all DDR2 SDRAMs are selected with DDR_CS#_0) then. ODT_WR_MAP_CS0 is set to ‘1’ and ODT_WR_MAP_CS1 can be either ‘1’ or ‘0’.

When both chip selects are used, both ODT_WR_MAP_CS0 and ODT_WR_MAP_CS1 are set to ‘1’.

M821xx Data Sheet


10.3.5 RTT, RTT_PAD_TERMINATIONDDR2_CTL_05 (AHB address 0x0D000028)Alternative CFG# A, B, C: 0 x 0203010300000101Alternative CFG# D: 0 x 0203010300010101Alternative CFG# E: 0 x 0203020300010101

Note that the three settings that have worked for Mindspeed are due to changes in the two DDR configuration fields at this location: ADDR_PINS, and COLUMN_SIZE.

The system-dependent fields at this location have remained the same across tested implementations:

• RTT is set to ‘1’

• RTT_PAD_TERMINATION is set to ‘1’

Bits 01:00: (RTT) Defines the On-Die termination resistance for all DRAM devices.

• b00 = Termination Disabled

• b01 = 75 Ohm

• b10 = 150 Ohm

• b11 = Reserved

Bits 9:8: (RTT_PAD_TERMINATION) Sets the termination resistance in the memory controller pads. The memory controller decodes this information and sets the pads to enable termination on reads. If this parameter is set to ’b00, termination will be disabled.

• b00 = Termination Disabled

• b01 = 75 Ohm

• b10 = 150 Ohm

• b11 = Reserved.

10.3.6 CASLAT_LINDDR2_CTL_06 (AHB address 0x0D000030)CFG# A, B, C, D, E: 0 x 060a020200020202Note the fields in the register have remained the same across all Mindspeed implementations.

Configuration based on setting in CASLAT for the specific DDR2 SDRAM (see Section 10.3.14 ADDR_PINS, CASLAT, COLUMN_SIZE, TCKE, TEMRS).

Bits 59:56: (CASLAT_LIN):

• •’b00000 - ’b00010 = Reserved

• •’b00011 = Reserved

• •’b00100 = 2 cycles


• •’b00110 = 3 cycles


M821xx Data Sheet


• •’b01000 = 4 cycles


• •’b01010 = 5 cycles

• •All other settings Reserved

10.3.7 CASLAT_LIN_GATE, INT_ACKDDR2_CTL_07 (AHB address 0x0D000038)CFG# A, B, C, D, E: 0 x 0000000300000206Note the fields in the register have remained the same across all Mindspeed implementations.

Configuration based on setting in CASLAT for the specific DDR2 SDRAM (see Section 10.3.14 ADDR_PINS, CASLAT, COLUMN_SIZE, TCKE, TEMRS).

Bits 03:00: (CASLAT_LIN_GATE):

• ‘b00000 – ’b00010 = Reserved

• ’b00011 = Reserved

• ’b00100 = 2 cycles


• ’b00110 = 3 cycles


• ’b01000 = 4 cycles


• ’b01010 = 5 cycles

• All other settings. = Reserved

Bits 44:40: INT_ACK: Controls the clearing of the int_status parameter. If any of the int_ack bits are set to a “1,” the corresponding bit in the int_status parameter will be set to “0.” Any int_ack bits written with a “0” will not alter the corresponding bit in the int_status parameter. This parameter will always read back as “0”.

10.3.8 INT_MASK, INT_STATUSDDR2_CTL_08 (AHB address 0x0D000040)CFG# A, D, E: 0 x 6400003f3f0a0200CFG# B, C: 0 x 6400003f3f0a0207

Note that the alternative configurations reflect differences in the settings for the device-dependent field: TFAW.

For Mindspeed tested DDR2 implementations, these bit fields have remained the same:

• INT_MASK is set 0x00

• INT_STATUS is set 0x00

M821xx Data Sheet


Bits 45:40: (INT_MASK) Active-high mask bits that control the value of the memory controller_int signal on the ASIC interface. This mask is inverted and then logically AND’ed with the outputs of the int_status parameter.

Bits 53:48 (INT_STATUS) shows the status of all possible interrupts generated by the memory controller. The MSB is the result of a logical OR of all the lower bits. This parameter is read-only. Note: Backwards compatibility is available for register parameters across configurations. However, even with this compatibility, the individual bits, their meaning and the size of the int_status parameter may change. The int_status bits correspond to these interrupts

• 0 = A single access outside the defined PHYSICAL memory space detected.

• 1 = Multiple accesses outside the defined PHYSICAL memory space detected.

• 2 = DRAM initialization complete.

• 3 = Address cross page boundary detected.

• 4 = DLL unlock condition detected.

• 5 = Logical OR of all lower bits.

10.3.9 REDUCDDR2_CTL_18 (AHB address 0x0D000090)CFG# A, B, C, D, E: 0 x 0303000000000001

Both settings described here worked in all Mindspeed implementations.

Bit 24: Cleared to ‘0’ in Mindspeed implementations. Controls the width of the memory data path. When enabled, the upper half of the memory buses (DQ, DQS and DM) are unused and relevant data only exists in the lower half of the buses. This parameter expands the DDR2 memory controller for use with memory devices of the configured width or half of the configured width.

• ’b0 = Standard operation using full memory bus.

• ’b1 = Memory data path width is half of the maximum size.

NOTE: In half datapath mode, throughput is much lower.

M821xx Data Sheet


10.3.10 Device-Dependent Bit Fields

The device-dependent bit fields shown in this section change in Mindspeed testing for different DDR2 SDRAM devices. For list, see section 1.3 on page 5.

10.3.11 Auto_Refresh_ModeDDR2_CTL_00 (AHB address 0x0D000000)CFG# A, B, C, D, E: 0 x 0100000101010101

Bit 48 sets the mode for when the automatic refresh will occur. If auto_refresh_mode is set and a refresh is required to memory, the memory controller will delay this refresh until the end of the current transaction (if the transaction is fully contained inside a single page), or until the current transaction hits the end of the current page.

• ’b0 = Issue refresh on the next DRAM burst boundary, even if the current command is not complete.

• ’b1 = Issue refresh on the next command boundary.

10.3.12 Eight_Bank_Mode, NO_CMD_INTDDR2_CTL_01 (AHB address 0x0D000008)CFG# A, D, E: 0 x 0100000100000001CFG# B, C: 0 x 0100010100000001

Bit 40 (Eight_Bank_Mode) indicates that the memory devices have eight banks.

• •’b0 = Memory devices have 4 banks.

• •’b1 = Memory devices have 8 banks.

Note that alternative configurations for this register only reflect the Eight_Bank_Mode bit change shown above.

NO_CMD_INIT has been cleared to ‘0’ in Mindspeed test implementations.

Bit 48 (NO_CMD_INT) disables DRAM commands until DLL initialization is complete and tdll has expired.

• ’b0 = Issue only REF and PRE commands during DLL initialization of the DRAM devices.

• ’b1 = Do not issue any type of command during DLL initialization of the DRAM devices.

NOTE: This document presents register settings that worked with PCBs built by Mindspeed. These are not the only valid settings. Other settings may work with very similar designs using the same DDR2 SDRAM devices.

Please contact your Mindspeed FAE with any questions.

M821xx Data Sheet


10.3.13 WRITEINTERPDDR2_CTL_02 (AHB address 0x0D000010)CFG# A, B, C, D, E: 0 x 0100010000010100

Bit 40 defines whether the memory controller can interrupt a write burst with a read command. Some memory devices do not allow this functionality

• ’b0 = The device does not support read commands interrupting write commands

• ’b1 = The device does support read commands interrupting write commands.

10.3.14 ADDR_PINS, CASLAT, COLUMN_SIZE, TCKE, TEMRSDDR2_CTL_05 (AHB address 0x0D000028)CFG# A, B, C: 0 x 0203010300000101CFG# D: 0 x 0203010300010101CFG# E: 0 x 0203020300010101In the DDR2 implementations tested OK by Mindspeed, the ADDR_PINS fields and COLUMN_SIZE bit fields vary:

• ADDR_PINS is ‘0’ or ‘1’.

• COLUMN_SIZE is ‘1’ or 2 (b’010)

The CSLAT, TCKE, and TEMRS bit field have remained the same:

• ADDR_PINS is ‘0’ or ‘1’.



Bits: 18:16 (ADDR_PINS) define the difference between the maximum number of address pins configured (14) and the actual number of pins being used. The user address is automatically shifted so that the user address space is mapped contiguously into the memory map based on the value of this parameter.

Bits 34:32 (CASLAT) is the programmed CAS latency of the memory devices set during initialization.

Bits: 42:40 (COLUMN_SIZE) Shows the difference between the maximum column width available (11) and the actual number of column pins being used. The user address is automatically shifted so that the user address space is mapped contiguously into the memory map based on the value of this parameter.

Bits 50:48 (TCKE) defines the minimum CKE pulse width in cycles.

Bits 58:56 (TEMRS) defines the DDR2 SDRAM extended mode parameter set time, in cycles.

M821xx Data Sheet


10.3.15 TPDEX, TRRD, TRTP, TWTR, WRLAT. APREBITDDR2_CTL_06 (AHB address 0x0D000030)CFG# A, B, C, D, E: 0 x 060a020200020202

These bit fields have been set the same in all Mindspeed implementations:

• TPDEX is set to 0x2

• TRRD is set to 0x2

• TRTP is set to 0x2

• TWTR is set to 0x2

• WRLAT is set to 0x2

• APREBIT is set to 0xA

Bits 2:0 (TPDEX) set the DRAM power-down exit command period in cycles.

Bits 10:08 (TRRD) define the DRAM activate to activate delay for different banks, in cycles.

Bits 18:16 (TRTP) define the DRAM tRTP (read to pre-charge time) parameter, in cycles.

Bits 34:32 (TWTR) sets the number of cycles needed to switch from a write to a read operation, as dictated by the DDR2 SDRAM specification.

Bits 42:40 (WRLAT) define the write latency from when the write command is issued to the time the write data is presented to the DDR2 SDRAM devices, in cycles.

Bits 51:48 (APREBIT) define the location of the auto pre-charge bit in the DDR2 DRAM address in decimal encoding.

10.3.16 TFAW, TMRD, TRCDDR2_CTL_08 (AHB address 0x0D000040)CFG# A, D, E: 0 x6400003f3f0a0200CFG# B, C: 0 x 6400003f3f0a02

Note that only the TFAW value changed for memories tested by Mindspeed

• TFAW is cleared to ‘0’s or is set to 0x7

• TRMD is set to 0x2

• TRC is set to 0xA

Bits 04:00 (TFAW) set DRAM tFAW parameter (4-bank activate period) in cycles.

Bits 12:08 (TMRD) defines the DRAM mode register set command time, in cycles.

Bits 20:16 (TRC) defines the DRAM period between active commands for the same bank, in cycles.

M821xx Data Sheet


10.3.17 TRFC, TCPDDDR2_CTL_11 (AHB address 0x0D000058)CFG# A, D: 0 x 433a34124a650a00CFG# B, C: 0 x 433a34164a650a00CFG# E: 0 x 433a340d4a650a00

Note that only the TRFC field changes in the memory configurations tested by Mindspeed:

• .TRFC varies from 0xd to 0x12 to 0x16

• .TCPD is set to 0x43

Bits 39:32 (TRFC) varies to configure TRFC (DRAM refresh command time) parameter in cycles.

Bits 63:56 (TCPD) define the clock enable to pre-charge delay time for the DRAM devices, in cycles.

10.3.18 TRAS_MINDDR2_CTL_12 (AHB address 0x0D000060)CFG# A, B, C, D, E: 0 x 0000000000000700

TRAS_MIN is set to 0x7 all Mindspeed implementations.

Bits 15:08 (TRAS_MIN) define the DDR2 SDRAM minimum row activate time, in cycles.

10.3.19 TREFDDR2_CTL_15 (AHB address 0x0D000078)CFG# A, B, C, D, E: 0 x 050e000000000000

In Mindspeed implementations testing OK, the TREF field was always set to 0x50e

Bits 61:48 (TREF) define the DDR2 SDRAM cycles between refresh commands

10.3.20 TRAS_MAXDDR2_CTL_16 (AHB address 0x0D000080)CFG# A, B, C, D, E: 0 x 000000002d890000

In Mindspeed implementations, TRAS_MAX is always set to 0x2D89.

Bits 31:16 (TRAS_MAX) defines the SDRAM maximum row active time, in cycles.

10.3.21 TWR_INTDDR2_CTL_18 (AHB address 0x0D000090)CFG# A, B, C, D, E: 0 x 0302000000000000Bits 58:56 (TWR_INT) Defines the DRAM write recovery time, in cycles. Mindspeed test implementations worked with TWR_INT set to 0x3.

M821xx Data Sheet


10.3.22 TRCD_INT, TDLL, TXSNRDDR2_CTL_19 (AHB address 0x0D000098)CFG# A, D: 0 x 00001400c8030600CFG# B, C: 0 x 00001700c8030600CFG# E: 0 x 00000f00c8030600In Mindspeed implementations testing OK, TRCD_INT, and TDLL remained constant while TXSNR varied:

• TRCD_INT is set to 0x3

• TDLL is set to 0xC8

• TXSNR is 0xf, 0x14, or 0x17

Bits 23:16 (TRCD_INT) Defines the DRAM RAS to CAS delay, in cycles

Bits 39:24 (TDLL) Defines the DRAM DLL lock time, in cycles.

Bits 55:40 (TXSNR) Defines the DRAM tXSNR parameter, in cycles.

10.3.23 TXSR, TINITDDR2_CTL_20 (AHB address 0x0D0000A0)CFG# A, B, C, D, E: 0 x 00000000823600c8

In Mindspeed implementations testing OK, these parameters remain constant:

• TXSR is set to 0xc8

• TINT is set to 0x8236

Bits 15:00 (TXSR) Defines the DRAM self-refresh exit time, in cycles.

Bits 39:16 (TINIT) Defines the DRAM initialization time, in cycles.

.


11.0 Ethernet Interface

11.1 Introduction

The Mindspeed Comcerto M821xx devices support one or two Ethernet Media Access Controllers (MACs). For a view of the Ethernet blocks within the top-level block diagram, see Figure 2-1. Possible configurations by part number are summarized in the following table.

Table 11-1 Features by Part Number

11.2 FeaturesEthernet MAC Features include:

• Compatible with IEEE 802.3 standards for 10/100/1000 Mbps Ethernet

• Supports half- or full-duplex operation in all three speeds

• Interrupt generation on signal receive and transmit completion, or errors

• Automatic pad and cyclic redundancy check (CRC) generation on transmitted frames

• Frame extension and frame bursting at 1000 Mbps in half duplex mode

• Automatic discard of frames received with errors

• Receive IP, TCP, and UDP checksum off-load

• Address checking logic for four specific 48 bit addresses, four type Ids, promiscuous mode, hash matching of unicast and mulitcast destination addresses

• Support for jumbo frames up to 10,240 bytes

• Full-duplex flow control with recognition of incoming pause frames and hardware generation of transmitted pause frames using software decision

• Compatible with RMII standard 1.2 and RGMII standard 1.3

NOTE: For details on setting Ethernet interface configuration registers inside the M821xx, see Section 12.0 Ethenet Interface Registers on page 177.

Ethernet MAC M82104 M82108 M82152 M82154 M82170 M82172 M82174 M82190 M82192 M82194

Ethernet 0 WAN: GMII / RGMII/ MII/ RMII

MII / RMII

Ethernet 1 LAN: RGMII / MII / RMII n/a n/a

MII / RMII

M821xx Data Sheet


11.3 Signal DescriptionsSee Section 11.4 for Ethernet mode selection details.

11.3.1 MII Mode Signal DescriptionsFor AC timing specification, see Section 11.6.

11.3.2 RMII Mode Signal DescriptionsFor AC timing specification, see Section 11.7.

Table 11-2 MII Signals


MII_TX_CLK I 1 MII Transmit Clock. 25 MHz in 100-Base mode, and 2.5 MHz in 10-Base mode, with ±100 ppm accuracy.

MII_TXD[3:0] O 4 MII Transmit Data. Nibble-wide transmit data stream. Synchronous with MII_TX_CLK.

MII_TX_EN O 1 MII Transmit Enable. Indicates data on MII_TXD is valid.

MII_TX_ER O 1 MII Transmit Error. Request out for a transmit error condition.

MII_RX_CLK I 1 MII Receive Clock. 25 MHz in 100-Base mode, and 2.5 MHz in 10-Base mode.

MII_RXD[3:0] I 4 MII Receive Data– Nibble-wide receive data stream. Synchronous with MII_RX_CLK.

MII_RX_DV I 1 MII Receive Data Valid – Indicates receive frame in progress, and data on MII_RXD pins is valid.

MII_RX_ER I 1 MII Receive Error Detected – Indicates an error is occurring during a receive frame.

MII_CRS I 1 MII Carrier Sense – Indicates traffic on link. Asynchronous signal.

MII_COL I 1 MII Collision Detect – Indicates a collision has occurred. Asynchronous signal.

MII_MDC O 1 Serial Management Interface Clock

MII_MDIO B 1 Serial Management Interface Data – Transfers data in and out of the device synchronously with MII_MDC.

Table 11-3 RMII Signals


RMII_REFCLK I 1 RMII Reference Clock. Continuous 50 MHz reference clock, with ± 50 ppm accuracy.

RMII_TX_EN O 1 RMII Transmit Enable. When high, indicates that MAC is presenting di-bits. Asserted synchronously with first nibble of the preamble and remains asserted while all di-bits to be transmitted are present. Synchronous with RMII_REFCLK.

RMII_TXD[1:0] O 2 RMII Transmit Data. RMII_TXD1 is the most significant. Synchronous to RMII_REFCLK.

RMII_CRS_DV I 1 RMII Carrier Sense / Receive Data Valid. Asserted by the PHY when the medium is non-idle. Data on RMII_RXD[1:0] is considered valid when RMII_CRS_DV is asserted. During a false carrier event, RMII_CRS_DV shall remain asserted for the duration of the carrier activity. Not synchronous with RMII_REFCLK.

M821xx Data Sheet


11.3.3 GMII Mode Signal DescriptionsFor AC timing specification, see Section 11.8.

RMII_RX_ER I 1 RMII Receive Error Detected – High for one or more REFCLK cycles to indicate that an error was detected somewhere in the Frame presently being transferred. Synchronous to REFCLK.NOTE: In the WAN port (Eth0) this pin is not used, and must be driven to a constant low when in RMII mode.

RMII_RXD[1:0] I 2 RMII Receive Data – RMII_RXD1 is the most significant. Synchronous with RMII_REFCLK.

RMII_PHY_LINK I 1 RMII PHY Link – Receives PHY activity indication.

RMII_PHY_DPX I 1 RMII PHY Duplex – Duplex/half-duplex indication from PHY. Typically, Low indicates duplex and high indicates half-duplex.

RMII_PHY_SPEED I 1 RMII PHY Speed – Speed indication from PHY. Typically, Low indicates 100-Base mode and high indicates 10-Base mode.

RMII_MDC O 1 Serial Management Interface Clock

RMII_MDIO B 1 Serial Management Interface Data – Transfers data in and out of the device synchronously with RMII_MDC.

NOTE: To time the transmission of data, the device receives GMII_GTX_REFCLK and transmits GMII_TX_CLK. A clock input on the MII transmit clock input, MII_TX_CLK enables the M821xx device to shift into this GMII transmit clock mode. In designs witout MII mode support, use any clock may to drive MII_TX_CLK. If the design supports both MII and GMII, then maintain the correct MII_TX_CLK input (see Table 11-2) while the device supports GMII..

Table 11-4 GMII Signals


GMII_TX_CLK O 1 Gigabit Transmit Clock – 125 MHz in 1000-Base mode.

GMII_GTX_REFCLK I 1 Gigabit Transmit Reference Clock – 125 MHz, with ±100 ppm accuracy.

GMII_TXD[7:0] O 8 GMII Transmit Data. Byte-wide transmit data stream. Synchronous with GMII_GTX_CLK.

GMII_TX_EN O 1 GMII Transmit Enable. Indicates data on GMII_TXD is valid.

GMII_TX_ER O 1 GMII Transmit Error. Request out for a transmit error condition.

GMII_RX_CLK I 1 GMII Receive Clock– 125 MHz in 1000-Base mode.

GMII_RXD[7:0] I 8 GMII Receive Data – Byte-wide receive data stream. Synchronous with GMII_RX_CLK.

GMII_RX_DV I 1 GMII Receive Data Valid– Indicates receive frame in progress, and data on GMII_RXD pins is valid.

Table 11-3 RMII Signals (Continued)


M821xx Data Sheet


11.3.4 RGMII Mode Signal DescriptionsFor AC timing specification, see Section 11.9.

GMII_RX_ER I 1 GMII Received Error Detected – Indicates an error is occurring during a receive frame.

GMII_CRS I 1 GMII Carrier Sense – Indicates traffic on link. Asynchronous signal.

GMII_COL I 1 GMII Collision Detect – Indicates a collision has occurred. Asynchronous signal.

GMII_MDC O 1 Serial Management Interface Clock

GMII_MDIO B 1 Serial Management Interface Data – Transfers data in and out of the device synchronously with GMII_MDC.

Table 11-5 RGMII Signals


RGMII_REFCLK I 1 125 MHz reference clock with ±50 ppm accuracy.

RGMII_TXC O 1 RGMII Transmit Clock. Depending on speed, this is a 125 MHz, 25 MHz, or a 2.5 MHz clock.

RGMII_TXD[3:0] O 4 RGMII Transmit Data. Interface is run at double data rate, with bits [3:0] presented on the rising edge of RGMII_TXC, and bits [7:4] presented at the falling edge of RGMII_TXC.

RGMII_RXC I 1 RGMII Receive Clock. Depending on speed, this is a 125 MHz, 25 MHz, or 2.5 MHz clock with a ±50 ppm accuracy.

RGMII_RX_CTL I 1 RGMII Receive Control. RGMII_RX_DV is presented on rising edge of RGMII_RXC. A logical derivative of RGMII_RX_DV and RGMII_RX_ER is presented on the falling edge of RGMII_RXC.

RGMII_RXD[3:0] I 4 RGMII Receive Data. Interface is run at double data rate, with bits [3:0] presented on the rising edge of RGMII_RXC, and bits [7:4] presented at the falling edge of RGMII_RXC.

RGMII_TX_CTL O 1 RGMII Transmit Control – RGMII_TX_EN is presented on the rising edge of RGMII_ TXC. A logical derivative of RGMII_TX_EN and RGMII_TX_ER is presented on the falling edge of TXC.

RGMII_MDC O 1 Serial Management Interface Clock

RGMII_MDIO B 1 Serial Management Interface Data – Transfers data in and out of the device synchronously to RGMII_MDC.

Table 11-4 GMII Signals (Continued)


M821xx Data Sheet


11.4 Ethernet Signal MultiplexingLogic levels latched at reset on TM_MII0_MODE[1:0] for Ethernet0 determine the MAC configuration as shown in the following tables.

Table 11-6 Ethernet0 (WAN) ConfigurationTM_MII0_MODE[0] [=] 1TM_MII0_MODE[1] [=] 1

GMII

TM_MII0_MODE[0] [=] 0TM_MII0_MODE[1] [=] 0

RMII


RGMII


MII

GMII0_MDC RMII0_MDC RGMII0_MDC MII0_MDC

GMII0_MDIO RMII0_MDIO RGMII0_MDIO MII0_MDIO

GMII0_RXD0 RMII0_RXD0 RGMII0_RXD0 MII0_RXD0

GMII0_RXD1 RMII0_RXD1 RGMII0_RXD1 MII0_RXD1

GMII0_RXD2 RMII0_PHY_DPX RGMII0_RXD2 MII0_RXD2

GMII0_RXD3 RMII0_PHY_SPEED RGMII0_RXD3 MII0_RXD3

GMII0_TXD0 RMII0_TXD0 RGMII0_TXD0 MII0_TXD0

GMII0_TXD1 RMII0_TXD1 RGMII0_TXD1 MII0_TXD1

GMII0_TXD2 RGMII0_TXD2 MII0_TXD2

GMII0_TXD3 RGMII0_TXD3 MII0_TXD3

GMII0_RX_CLK RMII0_REFCLK RGMII0_RXC MII0_RX_CLK

GMII0_RX_DV RMII0_CRS_DV RGMII0_RX_CTL MII0_RX_DV

GMII0_TX_EN RMII0_TX_EN RGMII0_TXC MII0_TX_EN

GMII0_TX_CLK RGMII0_REFCLK MII_TX_CLK

GMII_COL MII_COL

GMII0_CRS RMII0_PHY_LINK MII0_CRS

GMII0_RX_ER RMII0_RX_ER MII0_RX_ER

GMII0_TX_ER RGMII0_TX_CTL MII0_TX_ER

M821xx Data Sheet


Logic levels latched at reset on TM_MII1_MODE[1:0] for Ethernet1determine the MAC configuration as shown in the following tables.

Table 11-7 Ethernet1 (LAN) ConfigurationTM_MII1_MODE[0] [=] 0TM_MII1_MODE[1] [=] 1

MII


RMII


RGMII

MII1_MDC RMII1_MDC RGMII1_MDC

MII1_MDIO RMII1_MDIO RGMII1_MDIO

MII1_RXD0 RMII1_RXD0 RGMII1_RXD0

MII1_RXD1 RMII1_RXD1 RGMII1_RXD1

MII1_RXD2 RMII1_PHY_DPX RGMII1_RXD2

MII1_RXD3 RMII1_PHY_SPEED RGMII1_RXD3

MII1_TXD0 RMII1_TXD0 RGMII1_TXD0

MII1_TXD1 RMII1_TXD1 RGMII1_TXD1

MII1_TXD2 RGMII1_TXD2

MII1_TXD3 RGMII1_TXD3

MII1_RX_CLK RMII1_REFCLK RGMII1_RXC

MII1_RX_DV RMII1_CRS_DV RGMII1_RX_CTL

MII1_TX_EN RMII1_TX_EN RGMII1_TXC

MII1_TX_CLK RGMII1_REFCLK

MII1_TX_ER RGMII1_TX_CTL

MII1_CRS RMII1_PHY_LINK

MII1_RX_ER RMII1_RX_ER

M821xx Data Sheet


11.5 MDIO Interface TimingFigure 11-1 MDIO Interface Timing

Table 11-8 MDIO Interface Timing Parameters

Symbol Parameter Min. Typ. Max. Units Notes

Clock edge rate (All Clocks) 0.25 2 V/ns 1

MDC Frequency 2.5 MHz

MDC Duty Cycle 40 60 %

Tis MDIO Input Setup Time 20 ns

Tih MDIO Input Hold Time 0 ns

Tod MDIO Output Delay Time -10 10 ns

NOTES:1. The rise and fall times are determined by the edge rate in V/ns. A “Max” edge rate is the fastest rate at which a clock transitions.

M821xx Data Sheet


11.6 MII Interface Timing

*MII_COL and MII_CRS are specified as asynchronous.

Figure 11-2 MII Interface Timing Diagram

Table 11-9 MII Interface Timing Parameters


Clock edge rate (All Clocks) 0.25 2 V/ns

MII_CLK Frequency, 100 Mbps 25 MHz

MII_CLK Frequency, 10 Mbps 2.5 MHz

MII_CLK Accuracy -100 100 ppm

MII_CLK Duty Cycle 35 65 %

Tis Input Setup Time 10 ns 1

Tih Input Hold Time 10 ns 2

Tod Output Delay Time 1 15 ns 2

NOTES:1. Referenced to clock level of 0.8V.2. Referenced to clock level of 2.0V.

*

M821xx Data Sheet


11.7 RMII Interface TimingFigure 11-3 RMII Interface Timing Diagram

Table 11-10 RMII Interface Timing Parameters


Rise and fall times (signals and clock)

1 5 ns 1

RMII_REFCLK Frequency 50 MHz

RMII_REFCLK Accuracy -50 50 ppm

RMII_REFCLK Duty Cycle 35 65 %

Tis Input Setup Time 4 ns 2

Tih Input Hold Time 2 ns 2

Tod Output Delay Time 2 14 ns 2,3

NOTES:1. Measured between the points on the waveform which cross 0.8V and 2.0V.2. Reference to clock level of 1.4V.3. Output drivers shall be capable of meeting the output requirements while driving a 25pF or greater load.

M821xx Data Sheet


11.8 GMII Interface Timing

* GMII_COL and GMII_CRS are specified as asynchronous.

Figure 11-4 GMII Interface Timing Diagram

Table 11-11 GMII Interface Timing Parameters


Clock rise / fall time (all clocks) 1 ns 1, 5

Clock rate slew (all clocks) 0.6 V/ns 1, 2, 5

GTX_CLK and GTX_REFCLK frequency

125 MHz

GTX_CLK and GTX_REFCLK accuracy

-100 100 ppm

GTX_CLK period 7.5 8.5 ns

GTX_REFCLK period 8

RX_CLK period 7.5 ns

RX_CLK and GTX_CLK high/low time

2.5 ns

GTX_REFCLK high/low time 3.2

Tis Input setup time 2 ns 3

Tih Input hold time 0 ns 4

Tod Output delay time 0.5 4.5 ns 4, 6

*

M821xx Data Sheet


NOTES:1. Reference levels of 0.7V and 1.9V.2. Clock Skew rate is the instantaneous rate of change of the clock potential with respect to time (dV/dt), not an average value over the entire rise or fall time interval. Conformance with this specification guarantees that the clock signals will rise and fall monotonically through the switching region. 3. Referenced to clock level of 0.7V.4. Referenced to clock level of 1.9 V.5. Must be measured using a test circuit defined in Figure 35-20 in the standard.6. Must be measured using a test circuit defined in Figure 35-21 in the standard.

Table 11-11 GMII Interface Timing Parameters (Continued)


M821xx Data Sheet


11.9 RGMII Interface TimingFigure 11-5 RGMII Interface Timing Diagram

Table 11-12 RGMII Interface Timing Parameters


TskewT Data to Clock output Skew (at Transmitter)

-500 0 500 ps 1

TskewR Data to Clock output Skew (at Receiver)

1 2.6 ns 2

Tcyc Clock Cycle Duration (1000 Mbps) 7.2 8 8.8 ns 3

Tcyc Clock Cycle Duration (100 Mbps) 36 40 44 ns 3

Tcyc Clock Cycle Duration (10 Mbps) 360 400 440 ns 3

Clock Accuracy -50 50 ppm

Duty_G Duty Cycle for Gigabit 45 50 55 % 4, 5

Duty_T Duty Cycle for 10/100T 40 50 60 % 4, 5

Tr/Tf Rise / Fall Time (20-80%) 0.75 ns

M821xx Data Sheet


NOTES:1. The skew at the transmitter is specified for 15pF clock and data loads. If the load is significantly different on the board, it is the

responsibility of the board designer to characterize the output skew and to account for it. Parallel and serial terminations are required. Cicuit simulation / signal integrity analysis is essential.

2. To overcome the difference between TskewT and TskewR, use PHYs and switches which add internal delays to RGMII clocks in both TX and RX.directions. For additional information on RGMII interface design, see subsection 3.9 of the M821xx Hardware Requirements App Note (821xx-APP-002).

3. For 10Mbps and 100Mbps, Tcyc will scale to 400ns ±40ns and 40ns ±4ns respectively.4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet’s clock domain as long as the

minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.5. Cycle values are defined in percentages of the nominal clock period so to make this table speed independent.

Table 11-12 RGMII Interface Timing Parameters (Continued)


DSH Mindspeed Technologies™12-190Mindspeed Proprietary and Confidential

12.0 Ethenet Interface Registers

12.1 GMAC OverviewThe M821xx multi-MAC block (GMAC, GEM, or GEMAC) implements a 10/100/1000 Mbps Ethernet MAC compatible with the IEEE 802.3 standard. The GMAC can operate in either half or full duplex at all three speeds. See Table 12-1 below.

Network control and configuration registers (see Section 12.3 GigE MAC Configuration, Control, and Status Registers) are used to set the speed, duplex mode, and interface type.

Ethernet register addressing is in offsets with respect to:

• Ethernet 0 (WAN) registers start at 0x 100D 0000

• Ethernet 1 (LAN) registers start at 0x 1019 0000

12.1.1 GEMAC to PHY interface and clock frequencyTable 12-1 Supported Ethernet Modes

* Available only on WAN port, Ethernet 0.

NOTE: The terms “Rx” and “Tx” are with reference to specific logic blocks. To clarify data direction with respect to the M821xx, the terms“In-bound” and “out-bound” are often used. In general:

• TX refers to packet flow from the M821xx’s DDR2 SDRAM towards the external PHY.

• RX describes packet flow from the external PHY towards the M821xx DDR2 interface.

Refer to Figure 12-1.

MODE Ethernet 10 Fast Ethernet 100 Gigabit Ethernet 1000

MII 2.5 MHz 25 MHz —

RMII 50 MHz 50 MHz —

GMII* — — 125 MHz

RGMII 2.5 MHz 25 MHz 125 MHz

M821xx Data Sheet


Figure 12-1 shows the logic blocks within each of the two Ethernet ports.

NOTE: Only the WAN port support GMII.

Register offsets are with respect to:

• WAN (Ethernet 0) 0x 100D 0000

• LAN (Ethernet 1) 0x 1019 0000

The register offsets in this section present the least significant two bytes of the APB address.

Figure 12-1 GMAC Block Diagram

GEM IFRegister Offset 0xF000

GEM MUX

IDMA

HICORERegister Offsets

0xD000, 0xD024, 0xD028

APB

GEM_COL_FIFOGEM_DMAIF_TX

Register Offsets0xF004, 0xF008

RGMII

RMII

SMII

CLKGEN

GMII

GEM(MII / GMII)Cadence IP

Register Offsets 0xE000 – 0xE400

GEM_DMAIF_RXGEM_STS_FIFO

Register Offsets0xF010 – 0xF01C

Packet FIFO(OUT-BOUND FIFO)

(RX FIFO)

Packet FIFO(IN-BOUND FIFO)

(TX FIFO)

Rx

Tx

(TX FIFO)

(RX FIFO)

M821xx Data Sheet


12.2 HICORE Packet FIFO RegistersTable 12-2 summarizes the HICORE Packet FIFO registers detailed in the following subsections.

Table 12-2 HICORE Packet FIFO Register Summary

In the field descriptons below “RX” refers to In-bound traffic towards M821xx internal DMA while “TX” refers to Out-bound traffic towards the GEMAC interface. Refer to Figure 12-1.

12.2.1 GEM FIFO Control Register [0xD000] (read/write) default 0x1BTable 12-3 FIFO Control Register

12.2.2 TXFHTH [0xD024] (read/write) default 0xC0Table 12-4 RXFHTH Register

HICORE Packet FIFO Offset Register (Read) Register (Write)

0xD000 GEM FIFO Control GEM FIFO Control

0xD024 GEM TX FIFO High Threshold GEM TX FIFO High Threshold

NOTE: Register offsets are with respect to:

• WAN (Ethernet 0) 0x 100D 0000

• LAN (Ethernet 1) 0x 1019 0000

These registers cannot be read from or written to during data transfers, either Rx or Tx.

Field Name Description

0 RXFF_EN Enables RX FIFO operation. The FIFO is enabled on reset.

1 HBRXRQ_EN Enables operation of HBREQW, which indicates to the GEMIP it can start writing. Enabled on reset.

2 Reserved Reserved

3 TXFF_EN Enables the TX FIFO operation. The FIFO is enabled on reset.

4 HBTXRQ_EN Enables operation of HBREQR, which indicates to the GEM IP that it can start reading. Enabled on reset.

5:10 Reserved Reserved

11 TXCMPLTIE Internal transmit DMA Buffer Empty Interrupt Enable. Also, this condition can trigger the HBREQR signal without reaching the threshold, if it is enabled.



0-15 GEM TX FIFO High Threshold

The high threshold value of the TX FIFO. Once the FIFO depth reaches the TX FIFO high threshold value, the GMAC will start reading data from the FIFO. Threshold value must be lower than “HCSM TX FIFO high threshold’ register (0x0028) value. Reading returns the last value written.

M821xx Data Sheet


12.3 GigE MAC Configuration, Control, and Status RegistersGigE MAC Register Address Range: 0x100DE000 — 0x100DE400 (WAN) and 0x1019E000 — 0x1019E400 (LAN)

Table 12-5 GEMAC Conifg, Control and Status Register Map

Registers Offset Register (Read) Register (Write)

0x0000 Network Control Register Network Control Register

0x0004 Network Configuration Register Network Configuration Register

0x0008 — Network Status Register

0x0014 Transmit Status Register Transmit Status Register

0x0020 Receive Status Register Receive Status Register

0x0024 Interrupt Status Register Interrupt Status Register

0x0028 — Interrupt Enable Register

0x002C — Interrupt Disable Register

0x0030 Interrupt Mask Register —

0x0034 PHY Maintenance Register PHY Maintenance Register

0x0038 Received Pause Quantum Register —

0x003C Transmit Pause Quantum Register Transmit Pause Quantum Register

0x0080 Hash Bottom [31:0] Register Hash Bottom [31:0] Register

0x0084 Hash Top [63:32] Register Hash Top [63:32] Register

0x0088 Specific Address 1 Bottom [31:0] Register Specific Address 1 Bottom [31:0] Register

0x008C Specific Address 1 Top [47:32] Register Specific Address 1 Top [47:32] Register

0x0090 Specific Address 2 Bottom [31:0] Register Specific Address 2 Bottom [31:0] Register

0x0094 Specific Address 2 Top [47:32] Register Specific Address 2 Top [47:32] Register

0x0098 Specific Address 3 Bottom [31:0] Register Specific Address 3 Top [47:32] Register

0x009C Specific Address 3 Top [47:32] Register Specific Address 3 Top [47:32] Register

0x00A0 Specific Address 4 Bottom [31:0] Register Specific Address 4 Bottom [31:0] Register

0x00A4 Specific Address 4 Top [47:32] Register Specific Address 4 Top [47:32] Register

0x00A8 Type ID Match 1 Register Type ID Match 1 Register

0x00AC Type ID Match 2 Register Type ID Match 2 Register

0x00B0 Type ID Match 3 Register Type ID Match 3 Register

0x00B4 Type ID Match 3 Register Type ID Match 3 Register

0x00BC IPG Stretch Register IPG Stretch Register

0x00FC Module ID Register Module ID Register

M821xx Data Sheet


12.3.1 Network Control Register[0x0000] (read/write) default 0x0000_0000

The network control register contains general MAC control functions for both receiver and transmitter.

Table 12-6 Network Control Register


31:15 Reserved Reserved, read as zero, ignored on write.

14 Read snapshot Read snapshot - writing a one means that the snapshot value of the statistics register will be read back, otherwise the raw statistic register will be read.

13 Take snapshot Take snapshot - writing a one will record the current value of all statistics registers in the snapshot registers and clear the statistics registers.

12 Transmit zero quantum pause frame

Transmit zero quantum pause frame - writing one to this bit causes a pause frame with zero quantum to be transmitted.

11 Transmit pause frame Transmit pause frame - writing one to this bit causes a pause frame to be transmitted.

10 Transmit halt Transmit halt - writing one to this bit halts transmission as soon as any ongoing frame transmission ends. This bit is write only.

9 Start transmission Start transmission - writing one to this bit starts transmission. This bit is write only.

8 Reserved Reserved

7 Write enable for statistics registers

Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes.

6 Incremental statistics registers

Incremental statistics registers -this bit is write only. Writing a one increments all the statistics registers by one for test purposes.

5 Clear statistics registers Clear statistics registers - this bit is write only. Writing a one clears the statistics registers.

4 Management port enable Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low.

3 Transmit enable Transmit enable - when set, it enables the GMAC transmitter to send data. When reset transmission will stop immediately.

2 Receive enable Receive enable - when set, it enables the GMAC to receive data. When reset frame reception will stop immediately.

1 Loop back local Loop back local - asserts the loopback_local signal to the system clock generator. Also connects txd to rxd, tx_en to rx_dv and forces full duplex mode. rx_clk and tx_clk may malfunction as the GMAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back.

0 Reserved Set to ‘0’.

M821xx Data Sheet


12.3.2 Network Configuration Register [0x0004] (read/write) default 0x0010_0000

The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC.

Table 12-7 Network Configuration Register


31:30 Reserved Reserved, read as zero, ignored on write

29 Receive bad preamble Receive bad preamble. When set frames with non-standard preamble are not rejected.NOTE: For proper operation, this bit must be set to ‘1’.

28 IPG stretch enable IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register.


26 Ignore RX FCS Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected and no FCS error statistics will be collected. For normal operation this bit must be set to zero.

25 Enable Rx half-duplex mode Enable frames to be received in half-duplex mode while transmitting.

24 Receive checksum offload enable

Receive checksum offload enable - when set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded.

23 Disable copy of pause frames Disable copy of pause frames - set to one to prevent valid pause frames being copied to memory. When set, pause frames are not copied to memory regardless of the state of the copy all frames bit; whether a hash match is found; whether a type ID match is identified or if a destination address match is found. Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required.

22:21 Reserved Set to ‘00’.

20:18 MDC clock division MDC clock division - set according to AHB clk speed. These three bits determine the number AHB frequency will be divided by to generate MDC. The default value for AHB is 165 MHz. For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations).

• 000: divide AHB by 8 (AHB up to 20 MHz) • 001: divide AHB by 16 (AHB up to 40 MHz) • 010: divide AHB by 32 (AHB up to 80 MHz) • 011: divide AHB by 48 (AHB up to 120MHz) • 100: divide AHB by 64 (AHB up to 160 MHz) • 101: divide AHB by 96 (AHB up to 240 MHz) • 110: divide AHB by 128 (AHB up to 320 MHz) • 111: divide AHB by 224 (AHB up to 540 MHz)

17 FCS remove FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode.

16 Length field error frame discard

Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600.

15:14 Reserved Reserved.

13 Pause enable Pause enable - when set, transmission will pause if a non zero pause quantum frame is received.

12 Retry test Retry test -must be set to zero for normal operation — this bit can be used to support testing. If set to one the backoff between collisions will always been one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter’s decrement time from 512 bit times, to every rx_clk cycle.

M821xx Data Sheet


12.3.3 Network Status Register [0x0008] (read only) default 0x0000_0004

The network status register returns status information with respect to the PHY management interface.


10 Reserved

9 Reserved

8 Receive 1536 byte frames Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes.

7 Unicast hash enable Unicast hash enable - when set, unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register.

6 Multicast hash enable Multicast hash enable - when set, multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register.

5 No broadcast No broadcast - when set to logic one, frames addressed to the broadcast address of all ones will not be accepted.

4 Copy all frames Copy all frames - when set to logic one, all valid frames will be accepted.

3 Jumbo frames Jumbo frames - set to one to enable jumbo frames up to 10,240 bytes to be accepted.

2 Discard non-VLAN frames Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic.

1 Reserved Reserved.

0 Reserved Reserved

Table 12-8 Network Status Register



5:3 Reserved Reserved. Clear to ‘0’.

2 PHY management logic is idle The PHY management logic is idle (i.e. has completed).

1 status of the mdio_in pin Returns status of the mdio_in pin.

0 Reserved Reserved. Clear to ‘0’.

Table 12-7 Network Configuration Register (Continued)

M821xx Data Sheet


12.3.4 Transmit Status Register [0x0014] (read/write) default 0x0000_0000

This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.

12.3.5 Receive Status Register [0x0020] (read/write) default 0x0000_0000

This register, when read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.

Table 12-10 Receive Status Register

Table 12-9 Transmit Status Register



8 Reserved

7 Late collision occurred Late collision occurred - only set if the condition occurs in gigabit mode, as retry is not attempted. Cleared by writing a one to this bit.

6 Transmit under run Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable.Cleared by writing a 1 to this bit.

5 Transmit complete Transmit complete - set when a frame has been transmitted. Cleared by writing a one to this bit.


3 Transmit go Transmit go -if high transmit is active. This bit represents bit 3 of the network control register.

2 Retry limit exceeded Retry limit exceeded - cleared by writing a one to this bit.

1 Collision occurred Collision occurred - set by the assertion of collision. Cleared by writing a one to this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. In gigabit mode, this status is not set for a late collision.

0 Reserved Clear to ‘0’.


31:4 Reserved Reserved, read as 0, ignored on write.

3 Reserved

2 Receive overrun Receive overrun - this bit is set if the block was unable to store the receive frame due to a FIFO overflow. This bit is cleared by writing a one to it.

1 Frame received Frame received - one or more frames have been received and placed in memory. Cleared by writing a one to this bit.

0 Reserved Clear to ‘0’.

M821xx Data Sheet


12.3.6 Interrupt Status Register [0x0024] (read/write) default 0x0000_0000

The GMAC generates a single interrupt. This register indicates the source of this interrupt. The corresponding bit in the mask register must be cleared for a bit to be set. All bits are reset to zero on read. If any bit is set in this register the interrupt signal towards the INTC block will be asserted.

Table 12-11 Interrupt Status Register




14 Pause frame transmitted Pause frame transmitted - indicates a pause frame has been successfully transmitted after being initiated from the network control register. Cleared on read.

13 Pause Time Zero Pause time zero - set when either the pause time register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field. Cleared on read.

12 Pause frame with non-zero pause quantum received

Pause frame with non-zero pause quantum received -indicates a valid pause has been received that has a non-zero pause quantum field. Cleared on read.

11 Reserved

10 Receive overrun Receive overrun - set when the receive overrun status bit gets set. Cleared on read.

9 Reserved

8 Reserved Reserved

7 Transmit complete Transmit complete - set when a frame has been transmitted. Cleared on read.

6 Reserved

5 Retry limit exceeded or late collision

Retry limit exceeded or late collision - transmit error. Late collision will only cause this status bit to be set in gigabit mode (as a retry is not attempted). Cleared on read.

4 Transmit under run Transmit under run - this interrupt is set if the transmitter was forced to terminate a frame that it has already began transmitting due to further data being unavailable. If an under run occurs, the transmitter will force bad crc and tx_er high. Cleared on read.

3:2 Reserved

1 Receive complete Receive complete - a frame has been stored in memory. Cleared on read.

0 Management frame sent Management frame sent -the PHY maintenance register has completed its operation. Cleared on read.

M821xx Data Sheet


12.3.7 Interrupt Enable Register [0x0028] (write only) default 0x0000_0000

At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.

Table 12-12 Interrupt Enable Register



14 Enable pause frame transmitted interrupt

Enable pause frame transmitted interrupt

13 Enable pause time zero interrupt

Enable pause time zero interrupt

12 Enable pause frame with non-zero pause quantum interrupt

Enable pause frame with non-zero pause quantum interrupt

11 Reserved

10 Enable receive overrun interrupt

Enable receive overrun interrupt

9 Reserved Reserved

8 Not used Not used

7 Enable transmit complete interrupt

Enable transmit complete interrupt

6 Reserved Reserved

5 Enable retry limit exceeded or late collision interrupt

Enable retry limit exceeded or late collision interrupt

4 Enable transmit buffer under run interrupt

Enable transmit buffer under run interrupt

3: 2 Reserved

1 Enable receive complete interrupt

Enable receive complete interrupt

0 Enable management done interrupt

Enable management done interrupt

M821xx Data Sheet


12.3.8 Interrupt Disable Register [0x002C] (write only) default 0x0000_0000

Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.

Table 12-13 Interrupt Disable Register



14 Disable pause frame transmitted interrupt

Disable pause frame transmitted interrupt

13 Disable pause time zero interrupt

Disable pause time zero interrupt

12 Disable pause frame with non-zero pause quantum interrupt

Disable pause frame with non-zero pause quantum interrupt

11 Reserved Reserved

10 Disable receive overrun interrupt

Disable receive overrun interrupt

9 :8 Reserved Reserved

7 Disable transmit complete interrupt

Disable transmit complete interrupt

6 Reserved Reserved

5 Disable retry limit exceeded or late collision interrupt

Disable retry limit exceeded or late collision interrupt

4 Disable transmit buffer under run interrupt

Disable transmit buffer under run interrupt


1 Disable receive complete interrupt

Disable receive complete interrupt

0 Disable management done interrupt

Disable management done interrupt

M821xx Data Sheet


12.3.9 Interrupt Mask Register [0x0030] (read only) default 0x0000_0000

The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register.

Table 12-14 Interrupt Mask Register



14 Pause frame transmitted interrupt masked

Pause frame transmitted interrupt masked

13 Pause time zero interrupt masked

Pause time zero interrupt masked

12 Pause frame with non-zero pause quantum interrupt masked

Pause frame with non-zero pause quantum interrupt masked


10 Receive overrun interrupt masked

Receive overrun interrupt masked


7 Transmit complete interrupt masked

Transmit complete interrupt masked

6 Reserved Reserved

5 Retry limit exceeded or late collision (gigabit mode only) interrupt masked

Retry limit exceeded or late collision (gigabit mode only) interrupt masked

4 Transmit buffer under run interrupt masked

Transmit buffer under run interrupt masked


1 Receive complete interrupt masked

Receive complete interrupt masked

0 Management done interrupt masked

Management done interrupt masked

M821xx Data Sheet


12.3.10 PHY Maintenance Register [0x0034] (read/write) default 0x0000_0000

The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 2000 AHB clock cycles to complete, when MDC is set for AHB clock divide by 32 in the network configuration register. An interrupt is generated upon completion.

During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard.

Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.

The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1.

For a description of MDC generation, see Network Configuration Register.

Table 12-15 PHY Maintenance Register


31 Rserved.. Must be written with ‘0’.

30 Clause 22 operation. Must be written to ‘1’ for Clause 22 operation. ‘0’ for Clause 45.

29:28 Operation. Operation. ‘10’ is read. ‘01’ is write.

27:23 PHY address. PHY address.

22:18 Register address. Register address - specifies the register in the PHY to access.

17:16 Reserved. Must be written to ‘10’.

15:0 Write Operation write data, Read Operation read data.

For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY.

M821xx Data Sheet


12.3.11 Received Pause Quantum Register [0x0038] (read only) default 0x0000_0000

12.3.12 Transmit Pause Quantum Register [0x003C] (read/write) default 0x0000_FFFF

12.3.13 Hash Bottom [31:0] Register [0x0080] (read/write) default 0x0000_0000

12.3.14 Hash Top [63:32] Register [0x0084] (read/write) default 0x0000_0000

Table 12-16 Received Pause Quantum Register



15:0 Received pause quantum Received pause quantum - stores the current value of the received pause quantum register which is decremented every 512 bit times.

Table 12-17 Transmit Pause Quantum Register



15:0 Transmit pause quantum Transmit pause quantum - written with the pause quantum value for pause frame transmission.

Table 12-18 Hash Bottom Register


31:0 first 32 bits of the hash address register

The first 32 bits of the hash address register. See Hash Addressing

Table 12-19 Hash Top Register


31:0 remaining 32 bits of the hash address register

The remaining 32 bits of the hash address register. See Hash Addressing

M821xx Data Sheet


12.3.15 Specific Address 1 Bottom [31:0] Register [0x0088] (read/write) default 0x0000_0000

12.3.16 Specific Address 1 Top [47:32] Register [0x008C] (read/write) default 0x0000_0000


12.3.18 Specific Address 2 Top [47:32] Register [0x0094] (read/write) default 0x0000_0000

Table 12-20 Specific Address 1 Bottom Register


31:0 Least significant 32 bits of the destination address

Least significant 32 bits of the destination address, that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.

Table 12-21 Specific Address 1 Top Register



15:0 most significant bits of the destination address

Specific address 1. The most significant bits of the destination address, that is bits 47:32.





Table 12-23 Specific Addres 2 Top





M821xx Data Sheet



12.3.20 Specific Address 3 Top [47:32] Register [0x009C] (read/write) default 0x0000_0000

12.3.21 Specific Address 4 Bottom [31:0] Register [0x00A0] (read/write) default 0x0000_0000

12.3.22 Specific Address 4 Top [47:32] Register [0x00A4] (read/write) default 0x0000_0000



















M821xx Data Sheet


12.3.23 Type ID Match 1 Register [0x00A8] (read/write) default 0x0000_0000

12.3.24 Type ID Match 2 Register [0x00AC] (read/write) default 0x0000_0000

12.3.25 Type ID Match 3 Register [0x00B0] (read/write) default 0x0000_0000

Table 12-28 Type ID Match 1 Register


31 Enable copying of type ID matched frames.

Enable copying of type ID matched frames.


15:0 Type ID match Type ID match 1. For use in comparisons with received frames type ID/length field.













M821xx Data Sheet


12.3.26 Type ID Match 4 Register [0x00B4] (read/write) default 0x0000_0000

12.3.27 IPG Stretch Register [0x00BC] (read/write) default 0x0000_0000

12.3.28 Module ID Register [0x00FC] (read only) default 0x0000_0000

This register indicates a module identification number and module revision.

12.3.29 Specfic Address Top and Bottom Registers

Table 12-31 Type ID Match 4 Registeer






Table 12-32 IPG Stretch Register



15:0 inter-packet-gap Bits 7:0 are multiplied with the previously transmitted frame length (including preamble) bits 15:8 +1 divide the frame length. If the resulting number is greater than 96 and bit 28 is set in the network configuration register then the resulting number is used for the transmit inter-packet-gap. 1 is added to bits 15:8 to prevent a divide by zero.

Table 12-33 Module ID Register


31:16 Module identification number Module identification number -for the GEM, this value is fixed at 0x0002.

15:0 Module revision Module revision -fixed byte value specific to the revision of the design.

Table 12-34 Specific Address Top and Bottom Registers

Registers Offset Bottom Register Register Offset Top Register

0x0300 Address 5 Bottom 0x0304 Address 5 Top

0x0308 Address 6 Bottom 0x030C Address 6 Top




M821xx Data Sheet





0x0340 Address13 Bottom 0x0344 Address 13 Top












0x03A0 Address 25 Bottom 0x03A4 Address 25 Top

0x03A8 Address 26 Bottom 0x03AC Address 26 Top

0x03B0 Address 27 Bottom 0x03B4 Address 27 Top

0x03B8 Address 28 Bottom 0x03BC Address 28 Top

0x03C0 Address 29 Bottom 0x03C4 Address 29 Top

0x03C8 Address 30 Bottom 0x03CC Address 30 Top

0x03D0 Address 31 Bottom 0x03D4 Address 31 Top


Table 12-34 Specific Address Top and Bottom Registers

M821xx Data Sheet


12.3.29.1 Specific Address (5 — 32) Bottom [31:0] Registers

[0x0300 - 0x03D8] (read/write) default 0x0000_0000

12.3.29.2 Specific Address (5—32) Top [47:32] Register

[0x0304 - 0x3DC] (read/write) default 0x0000_0000

12.3.30 Statistics RegistersThese registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data.

The receive statistics registers are only incremented when the receive enable bit is set in the network control register.

The statistics registers optionally have a snapshot capability which, when exercised, will simultaneously store and clear the current values of all the statistics registers into a snapshot register set in order to allow a consistent set of statistics to be read by the processor. The snapshot is controlled using bit 13 of the network control register. The read snapshot control indicated by bit 14 of the network control register determines whether the processor reads the snapshot registers (logic 1) or the incrementing registers (logic 0).

All the statistics registers are read only.

Once a statistics register has been read, it is automatically cleared. When reading the bytes transmitted and bytes received registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. The statistics register block contains the following registers.

Table 12-35 Specific Address Bottom Registers




Table 12-36 Specific Address Top Registers





M821xx Data Sheet


Table 12-37 Statistics Registers


0x0100 BytesTransmitted [31:0] Register —

0x0104 Bytes Transmitted [47:32] Register —

0x0108 Frames Transmitted Register —

0x010C Broadcast Frames Transmitted Register —

0x0110 Multicast Frames Transmitted Register —

0x0114 Pause Frames Transmitted Register —

0x0118 64 Byte Frames Transmitted Register —

0x011C 65 to 127 Byte Frames Transmitted Register —

0x0120 128 to 255 Byte Frames Transmitted Register —



0x012C 1024 to 1518 Byte Frames Transmitted Register —

0x0130 Greater than 1518 Byte Frames Transmitted Register —

0x0134 Transmit Under Runs Frames Register —

0x0138 Single Collision Frames Register —

0x013C Multiple Collision Frames Register —

0x0140 Excessive Collisions Register —

0x0144 Late Collisions Register —

0x0148 Deferred Tansmission Frames Register —

0x014C Carrier Sense Errors Register —

0x0150 Bytes Received [31:0] Register —

0x0154 Bytes Received [47:32] Register —

0x0158 Frames Received Register —

0x015C Broadcast Frames Received Register —

0x0160 Multicast Frames Received Register —

0x0164 Pause Frames Received Register —

0x0168 64 Byte Frames Received Register —

0x016C 65 to 127 Byte Frames Received Register —

0x0170 128 to 255 Byte Frames Received Register —



0x017C 1024 to 1518 Byte Frames Received Register —

0x0180 1519 to Maximum Byte Frames Received Register —

0x0184 Undersize Frames Received Register —

M821xx Data Sheet


12.3.31 BytesTransmitted [31:0] Register [0x0100] (read only) default 0x0000_0000

12.3.32 Bytes Transmitted [47:32] Register [0x0104] (read only) default 0x0000_0000

0x0188 Oversize Frames Received Register —

0x018C Jabbers Received Register —

0x0190 Frame Check Sequence Errors Register —

0x0194 Length Field Frame Errors Register —

0x0198 Receive Symbol Errors Register —

0x019C Alignment Errors Register —

0x01A4 Receive Overruns RegisterIP Header Checksum Errors Register

—

0x01A8 IP Header Checksum Errors Register —

0x01AC TCP Checksum Errors Register —

0x01B0 UDP Checksum Errors Register —

Table 12-38 Bytes Transmitted Register


31:0 Transmitted bytes in frame without errors

Transmitted bytes in frame without errors [31:0]. The number of bytes transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include bytes from automatically generated pause frames.

Table 12-39 Bytes Tramsmitted Register


31:0 Transmitted bytes in frame without errors

Transmitted bytes in frame without errors [47:32]. The number of bytes transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include bytes from automatically generated pause frames.

Table 12-37 Statistics Registers (Continued)

M821xx Data Sheet


12.3.33 Frames Transmitted Register [0x0108] (read only) default 0x0000_0000

12.3.34 Broadcast Frames Transmitted Register [0x010C] (read only) default 0x0000_0000

12.3.35 Multicast Frames Transmitted Register [0x0110] (read only) default 0x0000_0000

12.3.36 Pause Frames Transmitted Register [0x0114] (read only) default 0x0000_0000

Table 12-40 Frmaes Tramsmitted Register


31:0 Frames transmitted without error

Frames transmitted without error. A 32 bit register counting the number of frames successfully transmitted, i.e. no under run and not too many retries. Excludes pause frames.

Table 12-41 Broadcast Frames Transmitted Register


31:0 Broadcast frames transmitted without error

Broadcast frames transmitted without error. A 32 bit register counting the number of broadcast frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames.

Table 12-42 Multicast Frames Transmitted Register


31:0 Multicast frames transmitted without error

Multicast frames transmitted without error. A 32 bit register counting the number of multicast frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames.

Table 12-43 Pause Frames Transmitted Register



15:0 Transmitted pause frame Transmitted pause frames - a 16 bit register counting the number of pause frames transmitted. Only pause frames triggered by the register interface are counted as pause frames. Pause frames received from the memory are counted along with other frames in the frames transmitted counter.

M821xx Data Sheet


12.3.37 64 Byte Frames Transmitted Register [0x0118] (read only) default 0x0000_0000

12.3.38 65 to 127 Byte Frames Transmitted Register [0x011C] (read only) default 0x0000_0000

12.3.39 128 to 255 Byte Frames Transmitted Register [0x0120] (read only) default 0x0000_0000


Table 12-44 64 Byte Frames Transmitted Register


31:0 64 byte frames transmitted without error

64 byte frames transmitted without error. A 32 bit register counting the number of 64 byte frames successfully transmitted without error, i.e. no under run and not too many retries. Excludes pause frames.

Table 12-45 65 to 127 Byte Frames Tramsmitted Register


31:0 65 to127 byte frames transmitted without error

65 to127 byte frames transmitted without error. A 32 bit register counting the number of 65 to127 byte frames successfully transmitted without error, i.e. no under run and not too many retries.

Table 12-46 128 to 255 Byte Frames Transmitted Register


31:0 128 to 255 byte frames transmitted without error

128 to 255 byte frames transmitted without error. A 32 bit register counting the number of 128 to 255 byte frames successfully transmitted without error, i.e. no under run and not too many retries.





M821xx Data Sheet



12.3.42 1024 to 1518 Byte Frames Transmitted Register [0x012C] (read only) default 0x0000_0000

12.3.43 Greater than 1518 Byte Frames Transmitted Register [0x0130] (read only) default 0x0000_0000

12.3.44 Transmit Under Runs Frames Register [0x0134] (read only) default 0x0000_0000

Table 12-48 512 to 1023 Byte Frames Tranmitted Register








Table 12-50 Greater than 1518 Byte Frames Transmitted Register


31:0 Greater than 1518 byte frames transmitted without error

Greater than 1518 byte frames transmitted without error. A 32 bit register counting the number of 1518 or above byte frames successfully transmitted without error, i.e. no under run and not too many retries.

Table 12-51 Transmit Under Runs Frames Register



9:0 Transmit under runs Transmit under runs - a 10 bit register counting the number of frames not transmitted due to a transmit under run. If this register is incremented then no other statistics register is incremented.

M821xx Data Sheet


12.3.45 Single Collision Frames Register [0x0138] (read only) default 0x0000_0000

12.3.46 Multiple Collision Frames Register [0x013C] (read only) default 0x0000_0000

12.3.47 Excessive Collisions Register [0x0140] (read only) default 0x0000_0000

12.3.48 Late Collisions Register [0x0144] (read only) default 0x0000_0000

Table 12-52 Singe Collision Frames Register



17:0 Single collision frames Single collision frames - an 18 bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no under run.

Table 12-53 Multipe Collision Frames Register



17:0 Multiple collision frames Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no under run and not too many retries.

Table 12-54 Excessive Collisions Register



9:0 Excessive collisions Excessive collisions - a 10 bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions.

Table 12-55 Late Collisions Register



9:0 Late collisions Late collisions - a 10 bit register counting the number of late collision occurring after the slot time (512 bits) has expired. In 10/100 mode, late collisions are counted twice i.e. both as a collision and a late collision. In gigabit mode, a late collision causes the transmission to be aborted, thus the single and multi collision registers are not updated.

M821xx Data Sheet


12.3.49 Deferred Tansmission Frames Register[0x0148] (read only) default 0x0000_0000

12.3.50 Carrier Sense Errors Register [0x014C] (read only) default 0x0000_0000

12.3.51 Bytes Received [31:0] Register [0x0150] (read only) default 0x0000_0000

Table 12-56 Deferred Transmission Frames Register



17:0 Deferred transmission frames Deferred transmission frames - an 18 bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit under run.

NOTE: The count in this register is not valid when the interface is configured in RGMII mode.

Table 12-57 Carrier Sense Errors Register



9:0 Carrier sense errors Carrier sense errors - a 10 bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was de-asserted after being asserted in a transmit frame without collision (no under run). Only incremented in half duplex mode. The only effect of a carrier sense error is to increment this register. The behavior of the other statistics registers is unaffected by the detection of a carrier sense error.


Table 12-58 Bytes Received Register


31:0 Received bytes in frame without errors [31:0]

Received bytes in frame without errors [31:0]. The number of bytes received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include bytes from pause frames.

M821xx Data Sheet


12.3.52 Bytes Received [47:32] Register [0x0154] (read only) default 0x0000_0000

12.3.53 Frames Received Register [0x0158] (read only) default 0x0000_0000

12.3.54 Broadcast Frames Received Register [0x015C] (read only) default 0x0000_0000

12.3.55 Multicast Frames Received Register [0x0160] (read only) default 0x0000_0000

Table 12-59 Bytes Received Register



15:0 Received bytes in frame without errors [47:32]

Received bytes in frame without errors [47:32]. The number of bytes received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include bytes from pause frames.

Table 12-60 Frames Received Register


31:0 Frames received without error Frames received without error. A 32 bit register counting the number of frames successfully received. Excludes pause frames.

Table 12-61 Broadcast Frames Received Register


31:0 Broadcast Frames received without error

Broadcast frames received without error. A 32 bit register counting the number of broadcast frames successfully received without error. Excludes pause frames.

Table 12-62 Multicast Frames Received Register


31:0 Multicast Frames received without error

Multicast frames received without error. A 32 bit register counting the number of multicast frames successfully received without error. Excludes pause frames.

M821xx Data Sheet


12.3.56 Pause Frames Received Register [0x0164] (read only) default 0x0000_0000

12.3.57 64 Byte Frames Received Register [0x0168] (read only) default 0x0000_0000

12.3.58 65 to 127 Byte Frames Received Register [0x016C] (read only) default 0x0000_0000

12.3.59 128 to 255 Byte Frames Received Register [0x0170] (read only) default 0x0000_0000

Table 12-63 Pause Frames Received Register



15:0 Received pause frames Received pause frames - a 16 bit register counting the number of pause frames received without error.

Table 12-64 64 Byte Frames Received Register


31:0 64 byte frames received without error

64 byte frames received without error. A 32 bit register counting the number of 64 byte frames successfully received without error. Excludes pause frames.

Table 12-65 65 to 127 Byte Frames Received Register


31:0 65 to 127 byte frames received without error

65 to 127 byte frames received without error. A 32 bit register counting the number of 65 to 127 byte frames successfully received without error. Excludes pause frames.

Table 12-66 128 to 255 Bytes Frames Received Register




M821xx Data Sheet




12.3.62 1024 to 1518 Byte Frames Received Register [0x017C] (read only) default 0x0000_0000

12.3.63 1519 to Maximum Byte Frames Received Register [0x0180] (read only) default 0x0000_0000




256 to 511 byte frames received without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error. Excludes pause frames.









Table 12-70 1519 to Maximum Byte Frames Received Register



1519 to maximum byte frames received without error. A 32 bit register counting the number of 1519 byte or above frames successfully received without error. Maximum frame size is determined by the network configuration register bit 8 (1536 maximum frame size) or bit 3 (jumbo frame size). Excludes pause frames.

M821xx Data Sheet


12.3.64 Undersize Frames Received Register [0x0184] (read only) default 0x0000_0000

12.3.65 Oversize Frames Received Register [0x0188] (read only) default 0x0000_0000

12.3.66 Jabbers Received Register [0x018C] (read only) default 0x0000_0000

Table 12-71 Undersixe Frames Received Register



9:0 Undersize frames received Undersize frames received - a 10 bit register counting the number of frames received less than 64 bytes in length (10/100 mode or gigabit mode, full duplex) that do not have either a CRC error or an alignment error. In gigabit mode, half duplex, this register counts either frames not conforming to the minimum slot time of 512 bytes or frames not conforming to the minimum frame size once bursting is active.

Table 12-72 Oversize Frames Received Register



9:0 Oversize frames received Oversize frames received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 bytes if bit 8 is set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register) in length but do not have either a CRC error, an alignment error, nor a receive symbol error.

Table 12-73 Jabber Received Register



9:0 Jabbers received Jabbers received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error.

M821xx Data Sheet


12.3.67 Frame Check Sequence Errors Register [0x0190] (read only) default 0x0000_0000

12.3.68 Length Field Frame Errors Register [0x0194] (read only) default 0x0000_0000

12.3.69 Receive Symbol Errors Register [0x0198] (read only) default 0x0000_0000

Table 12-74 Frame Check Sequence Errors Register



9:0 Frame check sequence errors Frame check sequence errors - a 10 bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes.

Table 12-75 Length Field Frame Errors Register



9:0 Length field frame errors Length field frame errors -this 10-bit register counts the number of frames received that have a measured length shorter than that extracted from the length field (bytes 13 and 14). This condition is only counted if the value of the length field is less than 0x0600, the frame is not of excessive length and checking is enabled through bit 16 of the network configuration register.

Table 12-76 Receive Symbol Errors Register



9:0 Receive symbol errors Receive symbol errors - a 10-bit register counting the number of frames that had rx_er asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks. For gigabit mode the frame must satisfy slot time requirements in order to count a symbol error. Additionally, in gigabit half duplex mode, carrier extension errors are also recorded. Receive symbol errors will also be counted as an FCS or alignment error if the frame is between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register, 10240 bytes if bit 3 is set in the network configuration register). If the frame is larger it will be recorded as a jabber error.

M821xx Data Sheet


12.3.70 Alignment Errors Register [0x019C] (read only) default 0x0000_0000

12.3.71 Receive Overruns Register [0x01A4] (read only) default 0x0000_0000

12.3.72 IP Header Checksum Errors Register [0x01A8] (read only) default 0x0000_0000

Table 12-77 Alignment Errors Register



9:0 Alignment errors Alignment errors - a 10 bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register, 10,240 bytes if bit 3 is set in the network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes.

Table 12-78 Receive Overruns Register



9:0 Receive overrun Receive overruns - a 10 bit register counting the number of frames that were not copied to memory due to a receive overrun.

Table 12-79 IP Header Checksum Errors Register



7:0 IP header checksum errors IP header checksum errors - an 8-bit register counting the number of frames flagged as having an incorrect IP header checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error.

M821xx Data Sheet


12.3.73 TCP Checksum Errors Register [0x01AC] (read only) default 0x0000_0000

12.3.74 UDP Checksum Errors Register [0x01B0] (read only) default 0x0000_0000

12.4 GEM IF, Tx, Rx, Col and STS FIFO RegistersGEM Control, Configuration, and Status Register Address Range: 0xF000 - 0xF01C

Table 12-82 GEM IF, Tx, Rx, Col and STS FIFO Registers

Table 12-80 TCP Checksum Errors Register



7:0 TCP checksum errors TCP checksum errors - an 8-bit register counting the number of frames flagged as having to an incorrect TCP checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error.

Table 12-81 UDP Checksum Errors Register



7:0 UDP checksum errors UDP checksum errors - an 8-bit register counting the number of frames flagged as having an incorrect UDP checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3 is in the network configuration register) and do not have a CRC error, an alignment error, nor a symbol error.


0xF000 GEM Configuration Register GEM Configuration Register

0xF004 TX Control TX Control

0xF008 TX Collision FIFO Depth —

0xF010 RX Control RX Control

0xF014 RX Status Pack Size RX Status Pack Size

0xF018 RX Status FIFO Depth —

0xF01C RX Status FIFO Data —

M821xx Data Sheet


12.4.1 GEM Configuration Register[0xF000] (read/write)

Default value depends on bootstrap configuration.

Table 12-83 GEM Configuration Register


0 MODE SEL Mode mux select0: PIN mode1: GEM mode

3-1 GEM MODE Interface Mode Setup000 - MII001 - GMII010 - RMII011 - RGMII100 - N/A101 - N/A110 - N/A111 - N/A

6-4 PIN STRAP MODE Interface mode setup from pin gmii_mode strapping (read only). 000 - MII001 - GMII010 - RMII011 - RGMII100 - N/A101 - N/A110 - N/A111 - N/A

7 Reserved

8 Duplex SEL Duplex mux select0: PHY Duplex control1: GEM Duplex control

9 GEM Duplex GEM Duplex control0: Half duplex1: Full Duplex

10 PHY Duplex PHY Duplex from PHY’s side-band or in-band signal (NOT for MII/GMII, read only)0: Half duplex1: Full Duplex

11 Speed SEL Speed mux select0: PHY Speed control1: GEM Speed control

13-12 GEM Speed GEM Speed control00: 10 Mbps (MII,RMII,RGMII)01: 100 Mbps (MII,RMII,RGMII)10: 1000 Mbps (GMII, RGMII)11: reserved

M821xx Data Sheet


12.4.2 TX Control [0xF004] (read/write) default 0x07

12.4.3 TX Collision FIFO Depth [0xF008] (read only)

15-14 PHY Speed PHY Speed control (NOT for MII, read only)00: 10 Mbps01: 100 Mbps10: 1000 Mbps11: reserved

16 PHY Link Status PHY Link from PHY’s side-band or in-band signal (NOT for MII/GMII, read only)0: Link down1: Link up

17 GEM loopback GEMCORE internal interface level loopback. Require interface clock. (test only)0: disable1: enable

24-18 Reserved Reserved


Table 12-84 TX Control Register


0 GEM Transmit DMAIF Control

Transmit DMAIF enable1: enable; 0: disable

1 CRC Control Transmit CRC append1: enable; 0: disable

2 Re-Transmit Control

Re-Transmit on FIFO underrun, late-collision, or too many retries1: enable; 0: disable

15-3 Reserved

19-16 GEM Transmit State Transmit DMAIF debug state (read only)

31-20 Reserved

Table 12-85 TX Collission FIFO Depth Register


4-0 GEM Collision FIFO Depth Transmit DMAIF Collision FIFO Depth. (Depth number: 0 to 19).

31-5 Reserved

Table 12-83 GEM Configuration Register

M821xx Data Sheet


12.4.4 RX Control [0xF010] (read/write) default 0x01

12.4.5 RX Status Pack Size [0xF014] (read/write) default 0x100

12.4.6 RX Status FIFO Depth [0xF018] (read only)

12.4.7 RX Status FIFO Data [0xF01C] (read only)

Table 12-86 RX Control Register


0 GEM Receive DMAIF Control

Receive DMAIF enable1: enable; 0: disable

15-1 Reserved

17-16 GEM Receive State Receive DMAIF debug state (read only)

31-18 Reserved

Table 12-87 RX Status Pack Size


9-0 GEM RX Status Pack Size Receive DMAIF Status Pack Size. (Pack Size: 0 to 512). Every time the RX FIFO receives the configure amount of bytes, it writes another status line to the status FIFO. This will cause a request to the DMA to start reading data.

31-10 Reserved

Table 12-88 RX Status FIFO Depth


4-0 GEM RX Status FIFO Depth Receive DMAIF Status FIFO Depth. (Depth number: 0 to 16).

31-5 Reserved

Table 12-89 RX Staus FIFO Data


31-0 GEM RX Status FIFO Data Receive DMAIF Status FIFO Data.

M821xx Data Sheet


12.5 GEM External FIFO Interface Registers (IDMA-Side Control Registers)GEM External FIFO Interface Registers Address Range: 0x0000 - 0xCFFF

12.5.1 HCSM FIFO Control Register[0x0000] (read/write) default 0x08

Table 12-90 GEM External FIFO Interface Registers

HCSM Address Register (Read) Register (Write)

0x0000 HCSM FIFO Control Registerl HCSM FIFO Control Register

0x0004 HCSM FIFO Interrupt Status Register HCSM FIFO Interrupt Acknowledge Register

0x0014 HCSM RX FIFO Size Reserved

0x0024 HCSM TX FIFO Size Reserved

0x0028 HCSM TX FIFO High Threshold HCSM TX FIFO High Threshold

0x002C HCSM TX FIFO Low Threshold HCSM TX FIFO Low Threshold

Table 12-91 HCSM FIFO Control Register


0-1 Reserved

2 TXDREQWE TX FIFO Write Request Enable

3 RXDREQRE RX FIFO Read Request Enable


12 RXFF_RES Setting this bit to a “1” will reset the RX_FIFO “read” and “write”.

13 TXFF_RES Setting this bit to a “1” will reset the TX_FIFO “read” and “write” pointers.


15 TXCP_INH Inhibits hardware TX Completed after DMA buffer empty condition.


M821xx Data Sheet


12.5.2 HCSM FIFO Interrupt Status Register [0x0004] (read only)

12.5.3 HCSM FIFO Interrupt Acknowledge Register [0x0004] (write only)

12.5.4 RXFF DEPTH [0x0014] (read only)

Table 12-92 HCSM FIFO Interrupt Status Register


0 RXF The RX FIFO is full.

1 RXTH The RX FIFO depth is greater than the threshold value.

2 TXE The TX FIFO is empty.

3 TXTH The TX FIFO depth is less than the threshold value.


Table 12-93 HCSM FIFO Interrupt Acknowledge Register


0:6 Reserved

7 FLUSH_TX Writing a “1” will trigger the HBREQR signal without reaching the threshold.

8 Reserved

9 Reserved

10-31 Reserved

Table 12-94 RXFF Depth Register


0-15 HCSM RX FIFO Size The current depth of the receiving FIFO.


M821xx Data Sheet


12.5.5 TXFF DEPTH [0x0024] (read only)

12.5.6 TXFF HTH [0x0028] (read/write) default 0x1CE

12.5.7 TXFF LTH [0x002C] (read/write) default 0x40

Table 12-95 TXFF DEPTH


0-15 HCSM TX FIFO Size The current depth of the transmit FIFO.


Table 12-96 TXFF HTH


0-15 HCSM TX FIFO High Threshold The high threshold value of the Tx FIFO. Once the FIFO depth is more than the high threshold the DMA request signal is de-asserted and the DMA will stop writing data. The DMA request signal will not be reasserted until the GEM IP has removed enough data so that the depth of the FIFO is less than the low threshold. Value must be higher than “GEM TX FIFO high threshold” register (0xD024) value. Reading returns the last written value.


NOTE: For 10 Mbps mode this register is typically set to 0x1C0. For 100 and 1000 Mbps modes, it is typically set to 0x1D0.

Table 12-97 TXFF LTH


0-15 HCSM TX FIFO Low Threshold The low threshold value of the TX FIFO. Once the FIFO depth is less than the low threshold the DMA request signal is asserted and the DMA starts to write. Reading returns the last value written.


M821xx Data Sheet


12.6 FIFO Threshold ManagementIt is very important to setup the FIFO thresholds correctly to prevent data overflow, underrun, or lockup the FIFOs. The following table gives the constraints to program the FIFO thresholds.

Table 12-98 Transmit External TX FIFO

EDMA / HCSM Side Threshold (Decimal)

GEM-IP Side Threshold(Decimal)

Max High Min Low Max High Min Low

> HCSM low Threshold &

< 472

X < HCSM High Threshold

X

Table 12-99 Receive External RX FIFO

EDMA / HCSM Side Threshold (Decimal)

GEM-IP Side Threshold(Decimal)

Max High Min Low Max High Min Low

X X X X

.


13.0 UTOPIA/Packet over Sonet (PoS) Interface

M821xx devices support full-duplex communication over PoS Level 2 (Packet over SONET) and UTOPIA Level 2 (Universal Test and Operations PHY Interface for ATM).

These UTOPIA and PoS interfaces are multiplexed. Software configuration and the level applied to the PoS/Utopia Master/Slave Mode Input (PU_MSTMODE#) determine the interface type.

13.1 Features• Supports both master (ATM/Link Layer) and slave (PHY) modes.

• Supports both UTOPIA Level 2 and PoS Level 2.

• Supports 8- and 16-bit data bus widths for both UTOPIA and PoS.

• Supports both cell and packet modes. Multiple cell sizes are supported, based on UTOPIA bus width.

• Supports clock rates up to 50 MHz.

• Slave mode support for one port only.

• Master Mode can support up to 8 devices.

13.2 UTOPIA / PoS OverviewThe UTOPIA and PoS standards define a “receive” and “transmit” direction with a system of devices. Hence a device interface on which data is outbound may be in the receive path. In the receive direction, data flows from the PHY to the ATM/Link layer. In the transmit direction, data flows from the ATM/Link Layer to the PHY. Although the Comcerto M8219x device is not PHY it may be termed as such when it interfaces with an ATM/link layer device.

The PUI (PoS/UTOPIA) interface subset provides full-duplex mapping of packets into PoS L2 and ATM cells into UTOPIA. PUI supports flow control, polling, arbitration, and error detection. The PUI configuration defines its operation as either master (ATM/Data Link) or slave (PHY) mode; as well as for either PoS or UTOPIA interface.

PoS is basically a superset of UTOPIA. At level two both standards support data rates in the hundreds of megabits per second.

The following tables summarize support for PoS / UTOPIA standards.

M821xx Data Sheet


13.3 Multiple-PHY Mode Functional Operation

13.3.1 TX Master ArbitrationBased on the low data throughput on TX master/ATM/Link, all TXPHY will be available when TXM selects any of them. There is no arbitration done in TXM by itself. That means the M8219x assumes TXM can transfer any frames anytime without hitting busy selected TXPHY.

13.3.2 RX Master ArbitrationPolling:

The RX master/ATM/Link polls PHYID with 5-bit of address bus. The polling sequence and PHY ID are provided by the polling calendar list. Each PHY can only be assigned to one DAY of the polling calendar. The status of ready to service on polled slave/PHY causes the flags raised in ready service port status register and used by RXM internal arbiter.

Table 13-1 UTOPIA Level 2 Modes Support

Single-PHY Multi-PHY

Direct Direct 1 Multiplexed

Octet Cell Octet Cell Group Addr 2

(Cell)Full Addr 3

(Cell)

YES YES NO NO NO YES

Notes:

1. Direct Status Indication is not supported. Refer to the ATM Forum UTOPIA Level2, v1.0, section 4.3

2. Group Address for Multiplexed Status Polling is not supported. Refer to the ATM Forum UTOPIA Level2, v1.0, section 4.4

3. One Tx Cell available (TxClav) and one Rx Cell available (RxClav) is supported. Refer to the ATM Forum UTOPIA Level2, v1.0, section 4.2

Table 13-2 PoS Level 2 Modes Support

Single-PHY Multi-PHY

Direct Direct Multiplexed

Byte Packet BYTE Packet Group Addr (Packet)

Full Addr (Packet)

YES NO NO NO NO YES

M821xx Data Sheet


Selection:

RXM arbiter has a priority counter which maintains a sequence of a priority list of PHYID and changes the priority to the next PHY in order when the current PHY is selected. If no PHY is ready, the priority arbiter stays the same PHY until either the current PHY available or any other lower priority PHY available.

13.3.3 Processor ArbitrationPolling:

The PUI masters poll PHYID with 5-bit of address bus. The polling sequence and PHY ID are provided by the polling calendar list. The status of ready to service on polled slave (PHY) causes the flags raised in ready service port status register. If ready-to-service interrupt control is enabled, the processor may read the status of which ports are ready and disable those ports from triggering interrupts again until those ports are serviced completely.

Selection:

The processor selects one of ready-to-service ports at a time by setting select port register. The selected slave (PHY) transmits or receives the cell or packets from the master. When the selected PHY’s transfer is complete or aborted by errors, the TX/RX master enables its ready service port interrupt control bit if the AUTO INT bit is enabled. This keeps the ready service port status updated to trigger interrupts to the processor.

The polling calendar registers should only be changed before enabling master mode.

13.3.4 Error Handling Parity Error

Parity check control has to be enabled first. When a cell/packet with any data parity errors received, the FIFO controller sets parity error flag or sends an interrupt to the processor.

Figure 13-1 Polling & Selection Timing Diagram

3 1F 8 1F 23 1F 3 1F 8 1F 23 1F 3 1F 8 1F 23 1F

P46 P47 P48 H1 H2 H3 H4 UD P47 P48

PHY3 auto enable intPHY3 selectedPHY3 service int & status

0ns 100ns 200ns 300ns

CLK

Addr

Clav

Enb

Data

SOCP

M821xx Data Sheet


Abort Packet Error (PoS mode only)

When a packet is ended with ERR abort signal asserted, the FIFO controller sets the abort packet flag or sends an interrupt to the processor.

Frame Error

When SOC/SOP is received prior to the end of a cell or end of a packet (EOP) or the size of receiving frame is greater than maximum allowed size, the FIFO controller sets cell/packet frame error flag or sends an interrupt to processor.

Transmit Window Error (TX PHY only)

When a cell/packet has data lost out of transmit window (i.e. data cannot be written into FIFO) after threshold or FIFO full condition but master still keeps transmitting data, the FIFO gets overflow condition and the controller sets transmit window error flag in the Frame Status Register or sends an interrupt to the processor.

Timeout (RX ATM/Link only)

When the master initiates a transfer to RX PHY and the start of cell/packet of a frame cannot be detected within two cycles, the FIFO controller sets timeout flag or triggers an interrupt.

13.4 Signal DescriptionsThe M8219x serves as either Master (ATM/Link layer) or a Slave (PHY) and uses the signal name prefixes PUO (POS/UTOPIA Out-bound) and PUI (POS/UTOPIA In-bound) as shown in the following table:

Note that as a POS/UTOPIA Master, the M8219x device receives data from the PHY on its in-bound interface (PUI) and transmits it out on the out-bound interface (PUO). However, when the M8291x device is configure as a Slave, it operates like a PHY between the network and a master, so PUO transmits in-bound or receive traffic while PUI receives out-bound or transmit traffic.

UTOPIA/POS Interface configuration requires the PU_MSTMODE# pin along with the internal register configuration.

• Tables 13-4 and 13-5 show mapping of M8291x pins in support of UTOPIA.

• Tables 13-6 and 13-7 show mapping of M8291x pins in support of PoS.

For detailed signal descriptions, refer to:

• Section 13.4.1 Utopia Interface to PHY Device

• Section 13.4.2 Utopia Interface to Link Layer Device.

• Section 13.4.3 PoS Interface to PHY Device.

• Section 13.4.4 PoS Interface to Link Layer Device.

Table 13-3 M8219x UTOPIA/POS Signal Prefixes

Configuration Interface Function

Receive Prefix

Transmit Prefix

Master ATM/Link layer device

PUI PUO

Slave PHY device PUO PUI

M821xx Data Sheet


13.4.1 Utopia Interface to PHY Device

NOTE: Strap PU_MSTMODE# to set the PoS / UTOPI inteface in either slave mode (logic high) or master mode (logic low).

Table 13-4 UTOPIA TX ATM Signals


PUO_CLK I 1 Transmit Clock – Used to synchronize data transfers between the link layer and the PHY layer. It can operate at rates of 25/33/50 MHz.

PUO_ADR[4:0] O 5 Transmit Address – 5 bit wide data bus used to poll and select the device polled on Transmit Cell Available.

PUO_DAT[15:0] O 16 Transmit Data bus for transfer of data from link layer device to PHY.

PUO_PRTY O 1 Transmit Parity – Indicate parity on Transmit Data bus. Register settings determine odd or even parity.

PUO_SOCP O 1 Transmit Start of Cell – Asserted high on first word of a cell.

PUO_CTRL1 O 1 Transmit Enable – Active low signal asserted to indicate Transmit Data and Transmit Start of Cell will be sampled at the end of next cycle.

PUO_CTRL3 I 1 Transmit Full / Cell Available – In direct byte level access, the PHY device asserts Transmit Full to indicate a FIFO over-run condition. In polled cell level access, the PHY device asserts Transmit Cell Available. Transmit Cell Available goes high to indicated space for the transfer of a complete cell, and is de-asserted four cycles before the transfer of the final octet/word.

Table 13-5 UTOPIA RX ATM Signals


PUI_CLK I 1 Receive Clock – Used to synchronize data transfers between the link layer and the PHY layer. It can operate in 25/33/50 MHz.

PUI_ADR[4:0] O 5 Receive Address – 5 bit wide data bus used to poll and select the device responding on Receive Cell Available.

PUI_DAT[15:0] I 16 Receive Data – Valid only when Receive Enable is asserted and Receive Address is valid.

PUI_PRTY I 1 Receive Parity – Indicates the parity of the data being driven onto Receive Data bus. Parity mode is programmed for odd or even parity. It is tri-stated by Receive Enable or mismatched Receive Address bus contents.

PUI_SOCP I 1 Receive Start of Cell – Asserted high on first word of cell. Tri-stated by Receive Enable.

PUI_CTRL1 I 1 Receive Empty/ Cell Available – For polled cell level access, Cell Available is asserted when there is data available in the polled device’s FIFO. For direct byte level access, Empty indicates no data is available in the transmitting device’s FIFO.

PUI_CTRL2 O 1 Receive Enable – Active low signal asserted to indicate that Receive Data and Receive Start of Cell will be sampled at the end of the next cycle.

M821xx Data Sheet


13.4.2 Utopia Interface to Link Layer DeviceTable 13-6 UTOPIA RX PHY Signals



PUO_ADR[4:0] I 5 Receive Address – 5 bit wide data bus used to poll and select the M8219x responding on Receive Cell Available.

PUO_DAT[15:0] O 16 Transmit Data bus for transfer of data from M8219x to link layer device.


PUO_SOCP O 1 Receive Start of Cell – Asserted high on first word of cell. Tri-stated by Receive Enable.

PUO_CTRL1 O 1 Receive Empty/ Cell Available – For polled cell level access, Cell Available is asserted when there is data available in the M8219x’s FIFO. For direct byte level access, Empty indicates no data is available in the M8219x’s FIFO.

PUO_CTRL2 I 1 Receive Enable – Active low signal asserted to indicate that Receive Data and Receive Start of Cell will be sampled at the end of the next cycle.

Table 13-7 UTOPIA TX PHY Signals



PUI_ADR[4:0] I 5 Transmit Address – 5 bit wide data bus used to poll and select the device polled on Transmit Cell Available.



PUI_SOCP I 1 Transmit Start of Cell – Asserted high on first word of a cell.

PUI_CTRL1 I 1 Transmit Enable – Active low signal asserted to indicate Transmit Data and Transmit Start of Cell will be sampled at the end of next cycle.

PUI_CTRL3 O 1 Transmit Full / Cell Available – In direct byte level access, the M8219x asserts Transmit Full to indicate FIFO over-run condition. In polled cell level access, the M8219x asserts Transmit Cell Available to indicate space to receive a cell.

M821xx Data Sheet


13.4.3 PoS Interface to PHY DeviceTable 13-8 PoS TX Link Signals



PUO_ADR[4:0] O 5 Transmit Address – 5 bit wide data bus used to poll and select the device responding on Transmit Packet Available.

PUO_DAT[15:0] O 16 Transmit Data bus for transfer of data from link layer device to PHY.


PUO_SOCP O 1 Transmit Start of Packet – Asserted high on first word of a cell.

PUO_EOP O 1 Transmit End of Packet – Marks the end of the packet.

PUO_MOD O 1 Transmit Modulo – Used to indicate the modulo of the last word of a packet. Transmit Modulo high indicates the last word of a transfer contains one byte.

PUO_ERR O 1 Transmit Error – Used to indicate the current packet is aborted and should be discarded.

PUO_CTRL1 O 1 Transmit Multi-PHY Write Enable – This signal goes active low to initiate writes to tranmit FIFOs.

PUO_CTRL2 I 1 Polled-PHY Transmit Packet Available – Transitions high when a minimum number of bytes is reached in the polled transmit FIFO. Once high, this signal indicates that the FIFO is not full.

PUO_CTRL3 I 1 Direct Transmit Packet Available – Transitions high when a minum number of bytes is reached in the transmit FIFO for a specific port. Once high, this signal indicates that the FIFO is not full.

Table 13-9 PoS RX Link Signals



PUI_ADR[4:0] O 5 Receive Address – 5 bit wide data bus used to poll and select the device responding on Receive Polled Packet Available.



PUI_SOCP I 1 Receive Start of Packet– Asserted high on first word of packet. Tri-stated by Receive Enable.

PUI_EOP I 1 Receive End of Packet – Marks the end of a packet. Tri-stated when Receive Enable is high or address does not match PHY.

PUI_MOD I 1 Receive Modulo – Used to indicate the modulo of the last word of a packet. Receive Modulo high indicates the last word of a transfer contains one byte.

M821xx Data Sheet


13.4.4 PoS Interface to Link Layer Device

PUI_ERR I 1 Receive Error – Used to indicate the current packet is aborted and should be discarded.

PUI_CTRL1 I 1 Receive Polled Multi-PHY Packet Available / Receive Packet Available Direct Status Indication – Whether the device is setup for polled packet level mode or direct byte level mode, this signal will indicate data available in the polled recieve FIFO, or it will provide a direct status indication for the corresponding port. When high, this signal indicates that the receive FIFO has at least one end of packet or a pre-defined number of bytes to be read.

PUI_CTRL2 O 1 Receive Multi-PHY Read Enable – This signal goes active low to initiate reads from receive FIFOs.

PUI_CTRL3 I 1 Receive Valid – Indicates validity of Receive Data, Receive Start of Packet, Receive End of Packet, Receive Modulo, Receive Parity and Receive Error. Tri-stated by Receive Enable or mismatch of PHY’s address.

Table 13-10 PoS RX PHY Signals



PUO_ADR[4:0] I 5 Receive Address – 5 bit wide data bus used to poll and select the device responding on Receive Cell Available.

PUO_DAT[15:0] O 16 Transmit Data – Data bus for transfer of data from the M8219x to the link layer device.


PUO_SOCP O 1 Receive Start of Packet – Asserted high on first word of packet. Tri-stated by Receive Enable.

PUO_EOP O 1 Receive End of Packet – Marks the end of a packet. Tri-stated when Receive Enable is high or address does not match M8219x.

PUO_MOD O 1 Receive Modulo – Used to indicate the modulo of the last word of a packet. Receive Modulo high indicates the last word of a transfer contains one byte.

PU_ERR O 1 Receive Error – Used to indicate that the current packet is aborted and should be discarded.

PUO_CTRL1 O 1 Receive Packet Available Direct Status Indication / Receive Polled Multi-PHY Packet Available – Depening on whether the device is setup for polled packet level mode or direct byte level mode, this signal will indicate data available in the polled recieve FIFO, or it will provide a direct status indication for the corresponding port. When high, this signal indicates that the receive FIFO has at least one end of packet or a pre-defined number of bytes to be read.

PUO_CTRL2 I 1 Receive Multi-PHY Read Enable – This signal goes active low to initiate reads from receive FIFOs.

PUO_CTRL3 O 1 Receive Valid – Indicates validity of Receive Data, Receive Start of Packet, Receive End of Packet, Receive Modulo, Receive Parity and Receive Error. Tri-stated by Receive Enable or mismatch of M8129x’s address.

Table 13-9 PoS RX Link Signals (Continued)


M821xx Data Sheet


Table 13-11 PoS TX PHY Signals



PUI_ADR[4:0] I 5 Transmit Address – 5 bit wide data bus used to poll and select the device on Transmit Packet Available.



PUI_SOCP I 1 Transmit Start of Cell – Asserted high on first word of cell. Tri-stated by Receive Enable.

PUI_EOP I 1 Transmit End of Packet – Marks the end of a packet. Tri-stated when Receive Enable is high or address does not match link level device.

PUI_MOD I 1 Transmit Modulo – Used to indicate the modulo of the last word of a packet. Receive Modulo high indicates the last word of a transfer contains one byte.

PUI_ERR I 1 Transmit Error – Used to indicate the current packet is aborted and should be discarded.

PUI_CTRL1 I 1 Transmit Multi-PHY Write Enable – This signal goes active low to initiate writes to tranmit FIFOs.

PUI_CTRL2 O 1 Transmit Packet Available – For polled access, asserted high when receiving FIFO can accept data

PUI_CTRL3 O 1 Direct Transmit Packet Available / Polled PHY Transmit Packet Available – As Direct Transmit Packet Availble, this signal transitions high when a pre-defined minimum number of bytes are available in the transmit FIFO. As Polled PHY Transmit Packet Available, the signal transitons high when a pre-defined minimum number of bytes are available in the polled transmit FIFO. Both signals, when high indicate that the FIFO is not full, and when low, indicate the FIFO is full or nearly full.

M821xx Data Sheet


13.5 UTOPIA ATM-PHY Interface TimingSee the following figures for information on UTOPIA ATM-PHY interface timing.

Figure 13-2 End and Restart of Cell Transmission at Transmit Interface

Figure 13-3 Transmission to PHY paused for Three Cycles

M821xx Data Sheet


Figure 13-4 Polling Phase and Selection Phase at Receive Interface

Figure 13-5 End and Restart of Cell Transmission at Receive Interface

M821xx Data Sheet


Figure 13-6 Unexpected Receipt of Two Back-to-Back Cells from the Same PHY

Figure 13-7 Two Subsequent Cells from the Same PHY

M821xx Data Sheet


13.6 PoS-PHY Interface TimingSee the following figures for information on POS-PHY interface timing.

Figure 13-8 Single-PHY and Byte Level-Multi-PHY Transmit Logical Timing

M821xx Data Sheet


Figure 13-9 Packet-Level Multi-PHY Addressing Transmit Logical Timing

M821xx Data Sheet


Figure 13-10 Single PHY Receive Logical Timing

M821xx Data Sheet


Figure 13-11 Packet Level Multi-PHY Logical Timing

M821xx Data Sheet


13.7 UTOPIA / PoS Timing

13.7.1 PUI Timing (PoS and UTOPIA)Figure 13-12 UTOPIA Interface Timing Waveforms

Table 13-12 PUI Setup and Hold Timing


Clock frequency 25 50 MHz

Clock duty cycle 40 60 %

CLK peak to peak jitter 5 %

CLK edge rise/fall time 2 ns

Tsu Input setup time 4 ns

Th Input hold time 0 ns

Tval Outputs valid time. 1 12 ns

Ton Outputs low impedance 1 12 ns

Toff Outputs high impedance 1 10 ns

NOTES:

1. Maximum output propagating delays are measured with a 30pF load on the outputs.

2. Input and output timing reference level is typically 1.4 V.

M821xx Data Sheet


13.7.2 UTOPIA TimingFigure 13-13 UTOPIA Interface Timing Waveforms

M821xx Data Sheet


Table 13-13 UTOPIA Timing

Signal Name Direction Item Description Min. Max. Units Notes

RxClKTxClk A ==> P

f1 Clk Frequency (nominal) 25 50 MHz

fT2 Clk Duty Cycle 40 60 %

fT3 Clk peak-to-peak jitter 5 %

fT4 Clk rise/fall time 2 ns

RxEnbRxAddr[4:0]TxData[15:0]TxPrtyTxSOCTxEnbTxAddr[4:0]

A==> PfT5 Input setup to associated Clk 4 ns

tT6 Input hold from associated Clk 1 ns

RxData[15:0]RxPrtyRxSOCRxClavTxClav

A <== P

tT7 Input setup to associated Clk 4 ns

tT8 Input hold from associated Clk 1 ns

tT9 Signal going low impedance to associated Clk

4 ns

tT10 Signal going high impedance to associated Clk

0 ns 1

tT11 Signal going low impedance from associated Clk

1 ns

tT12 Signal going high impedance from associated Clk

1 ns

NOTES:

1. This gives the clock period time for the driver to switch in the high impedance state (signal going high impedance 0ns in front of the next associated CLK).

2. Maximum output propagation delays are measured with a 30pF load on the outputs (defined typically as 10pF by the standard).

3. Input and output timing reference level is typically 1.4V (from the standard).

4. From the UTOPIA standard:

The A.C. characteristics are based on the timing specifications for the receiver side of a signal. Taking the actual used clock frequency into account (e.g. up to the max. frequency), the corresponding (min. and max.) transmit side “clock to output” propagation delay specifications can be derived.

The transmit side propagation delays are not given here, but this interface is muxed with the POS level 2 interface, and they are defined for that standard.

5. RxClk and TxClk peak-to-peak jitter, (for one cycle) measured from one rising edge to the next rising edge (from the standard).

M821xx Data Sheet


13.7.3 PoS TimingThe following timings are from the standard and reflect system rather than device requirements.

Figure 13-14 PoS Interface Timing Waveforms

Table 13-14 PUI Setup and Hold Timing


TFCLK Frequency 25 50 MHz

TFCLK Duty Cycle 40 60 %

tSTXXX TXXXX Set-up time to TFCLK(TXXX = TENB, TDAT, TPRTY, TSOP, TEOP, TMOD, TERR, TADR)

4 ns

tHTXXX TXXXX Hold time to TFCLK(TXXX = TENB, TDAT, TPRTY, TSOP, TEOP, TMOD, TERR, TADR)

0 ns

M821xx Data Sheet


tPXTPA TFCLK High to XTPA Valid(XTPA = STPA, PTPA, DTPA)

1 12 ns

tZXTPA TFCLK High to XTPA Tri-state(XTPA = STPA, PTPA)

1 10 ns

tZBXTPA TFCLK High to XTPA Driver(XTPA = STPA, PTPA)

0 ns

NOTES:

1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.

2. When a hold time is specified between an input and clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.

3. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output.

4. Maximum output propagation delays are measured with a 30 pF load on the outputs.

Table 13-14 PUI Setup and Hold Timing (Continued)


.


14.0 PoS / UTOPIA Interface Registers

14.1 IntroductionThis section presents PoS / UTOPIA registers.

14.2 PoS / UTOPIA Interface-Side Registers

14.2.1 TX and RX TerminologyThe M8219x serves as either Master (ATM/Link layer) or a Slave (PHY) and uses the signal name prefixes PUO (PoS/UTOPIA Out-bound) and PUI (PoS/UTOPIA In-bound) as shown in the following table:

Note that as a PoS/UTOPIA Master, the M8219x device receives data from the PHY on its in-bound interface (PUI) and transmits it out on the out-bound interface (PUO). However, when the M8291x device is configure as a Slave, it operates like a PHY between the network and a master, so PUO transmits in-bound or receive traffic while PUI receives out-bound or transmit traffic.

14.2.2 Address Offset

NOTE: The APB registers in offset 0xD0XX must not be written or read while the PoS/UTOPIA block is transferring data. Reading or writing to these registers while in data transfer can cause unexpected value in the registers (in writing) or from the registers (in reading) and corruption of transmitted data.

Table 14-1 M8219x UTOPIA/PoS Signal Prefixes

Configuration Interface Function

Receive Prefix

Transmit Prefix

Master ATM/Link layer device

PUI PUO

Slave PHY device PUO PUI

NOTE: Register offsets are with respect to 0x100C 0000 in the APB bus.

M821xx Data Sheet


14.2.3 PoS-UTOPIA Interface Side Registers MapTable 14-2 Register Map for Interface-Side Registers

APB AddressOffset

Register Description( READ )

Register Description( WRITE )

0xD000 PUI FIFO Control PUI FIFO Control

0xD014 PUI TX FIFO High Threshold PUI TX FIFO High Threshold

0xD018 PUI TX FIFO Low Threshold PUI TX FIFO Low Threshold

0xF000 PUI Mode Control PUI Mode Control

0xF004 PUI RX FIFO High Threshold PUI RX FIFO High Threshold

0xF008 PUI RX FIFO Low Threshold PUI RX FIFO Low Threshold

0xF010 TX Master Control TX Master Control

0xF014 TX Master Polling Calendar0 TX Master Polling Calendar0

0xF018 TX Master Polling Calendar1 TX Master Polling Calendar1

0xF01C TX Master Polling Calendar Length TX Master Polling Calendar Length

0xF020 TX Master Ready Service Port Control TX Master Ready Service Port Control

0xF024 TX Master Select Port TX Master Select Port

0xF030 RX Slave Control RX Slave Control

0xF040 RX Master Control RX Master Control

0xF044 RX Master Polling Calendar0 RX Master Polling Calendar0

0xF048 RX Master Polling Calendar1 RX Master Polling Calendar1

0xF04C RX Master Polling Calendar Length RX Master Polling Calendar Length

0xF050 RX Master Ready Service Port Control RX Master Ready Service Port Control

0xF054 RX Master Select Port RX Master Select Port

0xF060 TX Slave Control TX Slave Control

0xF070 ATM Cell Size ATM Cell Size

0xF074 ATM Cell Overshoot ATM Cell Overshoot

0xF078 UDMA Pack Size UDMA Pack Size

0xF07C Frame Max Size Frame Max Size

0xF080 PUI Status Threshold IBEXFIFO Threshold

0xF084 PUI Status Depth

0xF088 PUI Status Data

0xF08C PUI INT Control PUI INT Control

0xF090 PUI INT Status PUI INT Acknowledge

M821xx Data Sheet


14.3 Interface-Side Registers

14.3.1 PUI FIFO Control Register0xD000 (read/write) default 0x1B

14.3.2 PUI TX FIFO High Threshold (TXFHTH ) 0xD014 (read/write) default 0xF3

Table 14-3 PUI FIFO Control Register


0 TXFF_EN Enables TX FIFO operation. The FIFO is enabled on reset.

1 HBTXRQ_EN Enables operation of HBREQW. Enabled on reset.

2 Reserved

3 RXFF_EN Enables the RX FIFO operation. The FIFO is enabled on reset.

4 HBRXRQ_EN Enables operation of HBREQR. Enabled on reset.

5 TXCP_INH Inhibits hardware TX Completed after DMA buffer empty condition.

6-7 Reserved

8 TXEIE TX FIFO Empty Interrupt Enable.

9 TXTHIE TX FIFO Threshold Interrupt Enable.

10 TXM3IE TX MAIL3 Interrupt Enable.

11 RXCMPLTIE Internal RX DMA Buffer Empty Interrupt Enable. Also, this condition can trigger the HBREQR signal without reaching the threshold, if it is enabled.

12 RXFIE RX FIFO Full Interrupt Enable.

13 RXTHIE RX FIFO Threshold Interrupt Enable.

14 RXM3IE RX MAIL3 Interrupt Enable.

31-15 Reserved

Table 14-4 PUI TX FIFO High Theshold Register


0-15 PUI TX FIFO High Threshold

The high threshold value of the TX FIFO. This value can also be used to control the external DMA request line. The PUI DMA can be used to fill the FIFO. Once the FIFO depth reaches the PUI TX FIFO High Threshold the DMA request signal is de-asserted. If the DMA threshold feature is active, the DMA request signal will not be reasserted until the HCSM has removed enough data so that the depth of the FIFO is less than the low threshold. Once the (host) DMA request is asserted, the DMA will start filling the FIFO. Once the TX FIFO depth reaches the high threshold the DMA request line will again be de-asserted. Reading returns the last value written.

31-16 Reserved

M821xx Data Sheet


14.3.3 PUI TX FIFO Low Threshold (TXFLTH )0xD018 (read/write) default 0x40

14.3.4 PUI Mode Control0xF000 (read/write) default 0x00D9

Table 14-5 PUI TX FIFO Low Threshold Register


0-15 PUI TX FIFO Low Threshold

The low threshold value of the TX FIFO. A TX FIFO depth less than this value will cause an interrupt to the host if enabled. This value can also be used to control the external DMA request line. The PUI DMA can be used to fill the FIFO. Once the FIFO depth reaches the PUI TX FIFO High Threshold the DMA request signal is de-asserted. If the DMA threshold feature is active, the DMA request signal will not be reasserted until the HCSM has removed enough data so that the depth of the FIFO is less than the low threshold. Once the (host) DMA request is asserted, the DMA will start filling the FIFO. Once the TX FIFO depth reaches the high threshold the DMA request line will again be de-asserted. Reading returns the last value written.

31-16 Reserved

Table 14-6 PUI Mode Control Register


0 PoS MODE Interface mode setup.• 0: UTOPIA mode• 1: PoS mode

1~2 PHY MODE ATM or PHY (Master/Slave) operation mode setup (only when bit 8 is set to 1):

00: PHY RX and PHY TX (all Slave)

• 11: ATM/LINK TX and ATM/LINK RX (all Master)• 10: ATM/LINK TX and PHY TX • 01: PHY RX and ATM/LINK RX

3 DATA WIDTH Data bus width setup:• 0: 8 Bit (UTP or PoS)• 1: 16 Bit (UTP or PoS)

4 MULTI PHY Static input which determines if the core operates in Single PHY or Multiple PHY mode. • 0: Single (No port polling, No tristate)• 1: Multiple (Polling, Tristate, No Octet level handshake)

5 HANDSHK In Single PHY mode, determines whether the interface supports Octet or Cell laveel handshaking. In MPHY mode, this bit must set to 0.

• 0: Cell/Packet• 1: Octet/Byte

6 ODD PARITY Odd or even Parity • 0: Even• 1: Odd

7 PARITY EN Parity enable• 0: Disable• 1: Enable (TXM/RXP: parity generation or RXM/TXP: parity check)

M821xx Data Sheet


14.3.5 PUI RX FIFO High Threshold (RXFHTH) 0xF004 (read/write) default 0x0036

14.3.6 PUI RX FIFO Low Threshold (RXFLTH) 0xF008 (read/write) default 0x08

14.3.7 TX Master Control0xF010 (read/write) default 0x10

8 MUX CTRL Mux Control• 0: Hardware Strapping control• 1: Software control

9 LPBK CTRL Internal Loopback Control• 0: Loopback disable• 1: Loopback enable

10-31 Reserved

Table 14-7 PUI RX FIFO High Threshold


0-15 PUI RX FIFO High Threshold

The high threshold value of the RX FIFO. Once the FIFO depth reaches the PUI RX FIFO High Threshold, the PUI request signal is asserted.

16-31 Reserved

Table 14-8 PUI RX FIFO Low Threshold


0-15 PUI RX FIFO Low Threshold

The low threshold value of the RX FIFO. A RX FIFO depth less than this value will cause the PUI request line will again be de-asserted.

16-31 Reserved

Table 14-9 TX Master Control Register


0 TXM EN Enable the TX master /ATM/Link block circuitry. After enable set, not allow change any control registers.

• 0: Disable (Reset state)• 1: Enable

1 AUTO INT EN Automatically enables the control bit for interrupt when the transfer of selected port is completed or error abort.

• 0: Disable• 1: Enable

Table 14-6 PUI Mode Control Register

M821xx Data Sheet


14.3.8 TX Master Polling Calendar00xF014 (read/write) default 0x00

2~5 OVERSHOOT Number of overshoot cycle to stop transfer after PHY de-asserts TxFull/DTPA/STPA. This does not apply to UTP cell handshake mode.

• Overshoot counts from 1:• UTP octet mode: 4 (default)• PoS mode: 0 (Predefined by management level)

6~31 Reserved

Table 14-10 TX Master Polling Calendat0


0~4 DAY0 PHYID in Calendar Day 0

5~7 Reserved


13~15 Reserved


21~23 Reserved


29~31 Reserved

Table 14-9 TX Master Control Register

M821xx Data Sheet


14.3.9 TX Master Polling Calendar10xF018 (read/write) default 0x00

14.3.10 TX Master Polling Calendar Length0xF01C (read/write) default 0x00

14.3.11 TX Master Ready Service Port Control 0xF020 (read/write) default 0x00

Table 14-11 TX Master Polling Calendar1



5~7 Reserved


13~15 Reserved


21~23 Reserved


29~31 Reserved

Table 14-12 TX Master Polling Cakendar Length


0~2 CAL SIZE The number of using calendar day fields (number –1)

3~31 Reserved

Table 14-13 TX Master Ready Service Port Control


0~7 RSP INT CTRL Each bit controls one calendar day field interrupt enable.• 0: Disable• 1: Enable

If TXM auto interrupt is enabled, the transfer complete will set the selected port interrupt enable.

8~31 Reserved

M821xx Data Sheet


14.3.12 TX Master Select Port0xF024 (read/write) default 0x00

14.3.13 RX Slave Control 0xF030 (read/write) default 0x00

14.3.14 RX Master Control0xF040 (read/write) default 0x04

Table 14-14 TX Master Select Port


0~2 SEL PORT Select calendar day number to choose PHY ID.

3~31 Reserved

Table 14-15 RX Slave Control


0 RXP EN Enable the RX slave/PHY block circuitry. After enable set, not allow change any control registers.


1~5 PHY ID The ID (address) of the PHY device. The PHY ID cannot be 0x1F (reserved to null).

6~31 Reserved

Table 14-16 RX Master Control


0 RXM EN Enable the RX master/ATM/Link block circuitry. After enable set, not allow change any control registers.


1 AUTO INT EN Automatically enables the control bit for interrupt when the transfer of selected port is completed or error abort.

• 0: Disable• 1: Enable

2 ARB EN RX Master arbiter enable (only used in Multi-PHY mode).• 0: Disable• 1: Enable

3 TIMEOUT EN RX Master start of frame timeout check enable • 0: Disable• 1: Enable (only can be used in Multi-PHY mode)

4~31 Reserved

M821xx Data Sheet


14.3.15 RX Master Polling Calendar00xF044 (read/write) default 0x00

14.3.16 RX Master Polling Calendar10xF048 (read/write) default 0x00

14.3.17 RX Master Polling Calendar Size0xF04C (read/write) default 0x00

Table 14-17 RX Master Polling Calendar0



5~7 Reserved


13~15 Reserved


21~23 Reserved


29~31 Reserved

Table 14-18 RX Master Polling Calendar1



5~7 Reserved


13~15 Reserved


21~23 Reserved


29~31 Reserved

Table 14-19 RX Master Polling Calendar Size


0~2 CAL SIZE The number of using calendar day fields (number –1)

3~31 Reserved

M821xx Data Sheet


14.3.18 RX Master Ready Service Port Control0xF050 (read/write) default 0x00

14.3.19 RX Master Select Port0xF054 (read/write) default 0x00

14.3.20 TX Slave Control0xF060 (read/write) default 0x00

14.3.21 PUI ATM Cell Size0xF070 (Read/Write) default 0x36

Table 14-20 RX Master Ready Service Port Control


0~7 RSP INT CTRL Each bit controls one calendar day field interrupt enable.• 0: Disable• 1: Enable

If RXM auto interrupt is enabled, the transfer complete will set the selected port interrupt enable.

8~31 Reserved

Table 14-21 RX Master Select Port


0~2 SEL PORT Select calendar day number to choose PHY ID.

3~31 Reserved

Table 14-22 TX Slave Control


0 TXP EN Enable the TX slave/PHY block circuitry. After enable set, not allow change any control registers.


1~5 PHY ID The ID (address) of the PHY device. The PHY ID cannot be 0x1F (reserved to null).

6~31 Reserved

Table 14-23 PUI ATM Cell Size


0~9 CELL SIZE ATM cell size:• 52 octets without HEC • 53 octets with HEC in 8-bit data width• 54 octets with HEC in 16-bit data width (default)

10~31 Reserved

M821xx Data Sheet


14.3.22 PUI ATM Cell Overshoot0xF074 (Read/Write) default 0x6

14.3.23 PUI UDMA Pack Size0xF078 (Read/Write) default 0x00080040

14.3.24 PUI Frame Max Size0xF07C (Read/Write) default 0x03

Table 14-24 PUI ATM Cell Overshoot


0~3 CELL OVERSHOOT

ATM cell overshoot only used by TX PHY UTOPIA cell handshake mode.Overshoot 6 as default. ([2 beats delay + 4 beats]*Data Width)Data width:

• 8-Bit mode: 6 (default)• 16-Bit mode: 12

4~31 Reserved

Table 14-25 PUI UDMA Pack Size


0~9 IB PACK SIZE In-Bond UDMA packing size for each transfer. Only use even number when data width 16-bit mode is selected. The pack size has to be less than TXFIFO PUI side low threshold value to avoid lock-up situation.

16~25 OB PACK SIZE Out-Bond UDMA packing size for each transfer. Only use even number when data width 16-bit mode is selected. The pack size has to be less than RXFIFO UDMA side low threshold value to avoid lock-up situation. The larger pack size can reduce the 50% gap between cells.

25~31 Reserved

Table 14-26 PUI Frame Max Size


0~2 FRAME MAX SIZE • 000: no limit control• 001: frame < 512B• 010: frame < 1 KB• 011: frame < 2 KB• 100: frame < 4 KB• 101: frame < 8 KB• 110: frame < 16 KB• 111: frame < 32 KB

3~31 Reserved

M821xx Data Sheet


14.3.25 PUI STATUS FIFO Threshold0xF080 (Read/Write) default 0x09

14.3.26 PUI STATUS FIFO Depth0xF084 (Read only)

14.3.27 PUI STATUS FIFO Data0xF088 (Read only)

Table 14-27 PUI Status FIFO Threshold


0~4 STATUS FIFO THRES

Status FIFO depth thresholdRange: 1 ~ 16 FIFO depth has to keep less than threshold to maintain operation on RXM or TXP.

5~31 Reserved

Table 14-28 PUI Status FIFO Depth


0~4 STATUS FIFO DEPTH

Status FIFO depth Range: 0~16

5~31 Reserved

Table 14-29 PUI Status FIFO Data


0~16 STATUS FIFO DATA

RXM or TXP Status wordNOTE: For test use only. Not accessed during normal operation.

17~31 Reserved

M821xx Data Sheet


14.3.28 PUI INT Control0xF08C (read/write) default 0x00Table 14-30 PUI INT Control


0~15 Reserved

16 TXM DONE INT EN TX master/ATM/Link transfer complete interrupt enable.• 0: Disable• 1: Enable

17 RXM DONE INT EN RX master/ATM/Link transfer complete interrupt enable.• 0: Disable• 1: Enable

18 STATUS REQ INT EN Status FIFO request interrupt enable. (Status FIFO depth > 0)• 0: Disable• 1: Enable

19 PERR INT EN Parity error interrupt enable• 0: Disable• 1: Enable

20 ABORT INT EN Packet abort interrupt enable• 0: Disable• 1: Enable

21 FERR INT EN Frame error interrupt enable. (SOP-SOP error or frame max size error)• 0: Disable• 1: Enable

22 TXPWINERR INT EN TX slave/PHY Window Error interrupt enable. (TX FIFO overflow)• 0: Disable• 1: Enable

23 RXM TIMEOUT INT EN

RX master/ATM/Link timeout interrupt enable. (No soc/sop detected)• 0: Disable• 1: Enable

24~31 Reserved

M821xx Data Sheet


14.3.29 PUI INT Status0xF090 (read only) default 0x00

14.3.30 PUI INT Acknowledge0xF090 (Write only)

Table 14-31 PUI INT Status


0~7 TXM RSP STATUS TX master/ATM/Link ready service port status flag. The status flag is set when the port is polled as ready for service. Each bit represents a field in the polling calendar.

8~15 RXM RSP STATUS RX master/ATM/Link ready service port status flag. The status flag is set when the port is polled as ready for service. Each bit represents a field in the polling calendar.

16 TXM DONE STATUS TX master/ATM/Link transfer complete status.

17 RXM DONE STATUS RX master/ATM/Link transfer complete status.

18 STATUS REQ STATUS

Status FIFO request status.

19 PERR STATUS Parity error status

20 ABORT STATUS Abort status

21 FERR STATUS Frame error status. (SOP-SOP error or frame max size error)

22 TXPWINERR STATUS

TX slave/PHY Window Error status. (TX FIFO overflow)

23 RXM TIMEOUT STATUS

RX master/ATM/Link timeout status. (No soc/sop detected)

24~30 Reserved

31 HICORE STATUS Indicate HICORE FIFO interrupt status

Table 14-32 PUI INT Acknowledge


0~15 Reserved

16 TXM DONE INT ACK Write 1 to clear TX master done INT.

17 RXM DONE INT ACK Write 1 to clear RX master done INT.

18 STATUS REQ INT ACK

Write 1 to clear IBEXFIFO request INT.

19 PERR INT ACK Write 1 to clear TX Parity error INT.

20 ABORT INT ACK Write 1 to clear TX Abort error INT.

21 FERR INT ACK Write 1 to clear TX Frame error INT.

22 TXPWINERR INT ACK

Write 1 to clear TX Window error INT.

23 RXM TIMEOUT INT ACK

Write 1 to clear RX master time out INT.

24~31 Reserved

M821xx Data Sheet


14.4 PoS / UTOPIA IDMA-Side Register MapNOTE: Register offsets are with respect to 0x100C 0000 in the APB bus.

Table 14-33 Register Map for Processor-Side Registers

APB AddressOffset

Register Description( READ )

Register Description( WRITE )

0x0000 HCSM FIFO Control HCSM FIFO Control

0x0004 HCSM FIFO Interrupt Status HCSM FIFO Interrupt Acknowledge

0x0014 HCSM TX FIFO Size Reserved

0x0018 HCSM TX FIFO High Threshold HCSM TX FIFO High Threshold

0x001C HCSM TX FIFO Low Threshold HCSM TX FIFO Low Threshold

0x0024 HCSM RX FIFO Size Reserved

0x0028 HCSM RX FIFO High Threshold HCSM RX FIFO High Threshold

0x002C HCSM RX FIFO Low Threshold HCSM RX FIFO Low Threshold

M821xx Data Sheet


14.5 IDMA-Side Registers

14.5.1 HCSM FIFO Control Register 0x0000 (read/write) default 0x0

14.5.2 HCSM FIFO Interrupt Status Register 0x0004 (read only)

Table 14-34 HCSM FIFO Control Register


0-1 Reserved

2 RXDREQWE RX FIFO Write Request Enable

3 TXDREQRE TX FIFO Read Request Enable

4 Reserved

5 TXCMPLTIE TX Complete Interrupt Enable

6 TXFIE TX FIFO Full Interrupt Enable.


8 RXEEI The RX FIFO Empty Interrupt Enable.

9 RXTHIE The RX FIFO Threshold Interrupt Enable.




13 RXFF_RES Setting this bit to a “1” will reset the TX_FIFO “read” and “write” pointers.

14 Reserved

15 RXCP_INH Inhibits hardware RX Completed after DMA buffer empty condition.

16-31 Reserved

Table 14-35 HCSM FIFO Interrupt Status Register


0 TXF The TX FIFO is full.

1 TXTH The TX FIFO depth is greater than the threshold value.

2 RXE The RX FIFO is empty.

3 RXTH The RX FIFO depth is less than the threshold value.

4 RXM3I The Host has acknowledged an RXM3 FULL interrupt from the RX MAIL3 Register.

5 TXM3I The Host has written data to the TX MAIL3 Register.

6 TXCMPLT TX COMPLETED bit set by Host in target mode.

7-31 Reserved

M821xx Data Sheet


14.5.3 HCSM FIFO Interrupt Acknowledge Register0x0004 (write only)

14.5.4 HCSM TX FIFO SIZE (TXFFDEPTH)0x0014 (read only)

14.5.5 HCSM TX FIFO High Threshold (TXHTH)0x0018 (read/write) default 0xC0

Table 14-36 USCM FIFO Inerrupt Acknowledge Register


0 TXFIAK Writing a “1” Clears the corresponding interrupt status bit.

1 TXTHIAK Writing a “1” Clears the corresponding interrupt status bit.

2 TXM3IAK Writing a “1” Clears the corresponding interrupt status bit.

3 Reserved

4 RXEIAK Writing a “1” Clears the corresponding interrupt status bit.

5 RXTHIAK Writing a “1” Clears the corresponding interrupt status bit.

6 RXM3IAK Writing a “1” Clears the corresponding interrupt status bit.

7 FLUSH_RX Writing a “1” will trigger the HBREQR signal without reaching the threshold.

8 SRESET Soft Reset. Writing a “1” resets the entire device. The action is equivalent to resetting the device via the power-on reset pin.

9 TXCMPLTIAK Writing a “1” Clears the corresponding interrupt status bit.

10-31 Reserved

Table 14-37 HCSM TX FIFO Size (TXFFDEPTH)


0-15 HCSM TX FIFO Size

The current depth of the transmitting FIFO.

16-31 Reserved

Table 14-38 HCSM TX FIFO HIgh Threshold (TXHTH)


0-15 HCSM TX FIFO Threshold

The high threshold value of the TX FIFO. A TX FIFO depth greater than this value will cause an interrupt to the HCSM if enabled. This value can also be used to control the internal DMA request line. The internal DMA can be used to empty the FIFO. Once the FIFO depth is below the low threshold the DMA request line is de-asserted. If the DMA threshold feature is active, then the DMA request signal will not be asserted until the HOST has written enough data so that the depth of the TX FIFO is greater than the high threshold. This value can’t be greater than 0xFE

16-31 Reserved

M821xx Data Sheet


14.5.6 HCSM TX FIFO Low Threshold (TXLTH)0x001C (read/write) default 0xD

14.5.7 HCSM RX FIFO Size (RXFF Depth)0x0024 (read only)

14.5.8 HCSM RX FIFO High Threshold (RXHTH) 0x0028 (read/write) default 0xF3

14.5.9 HCSM RX FIFO Low Threshold (RXLTH) 0x002C (read/write) default 0x40

Table 14-39 HCSM TX FIFO Low Threshold (TXLTH)


0-15 HCSM TX FIFO Low Threshold

The low threshold value of the TX FIFO. A TX FIFO depth below this value will cause an interrupt to occur to the HCSM if enabled. This value can also be used to control the internal DMA request line. The IDMA(UDMA) can be used to flush the RX FIFO. Once the FIFO depth is below the low threshold the DMA request signal is de-asserted. If the DMA threshold feature is active, then the DMA request signal will not be reasserted until the Host has filled enough data so that the depth of the FIFO is more than the high threshold. Reading returns the last value written.

16-31 Reserved

Table 14-40 HCSM RX FIFO Size (RXFF Depth)


0-15 HCSM RX FIFO Size Current depth of the receiving FIFO

Table 14-41 HCSM RX FIFO High Threshold (RXHTH)


0-15 HCSM RX FIFO High Threshold

Once the FIFO depth is more than the high threshold the DMA request signal is de-asserted. Reading returns the last written value

16-31 Reserved

Table 14-42 HSXM RX FIFO Low Threshold (RXLTH)


0-15 HCSM RX FIFO Low Threshold

The low threshold value of the RX FIFO. ARX FIFO depth below this value will cause an interrupt to occur to the HCSM if enabled. This value can also be used to control the internal DMA request line. The IDMA(UDMA) can be used to fill the RX FIFO. Once the FIFO depth is more than the high threshold the DMA request signal is de-asserted. If the DMA threshold feature is active, then the DMA request signal will not be reasserted until the Host has removed enough data so that the depth of the FIFO is less than the low threshold. Reading returns the last value written.

16-31 Reserved

.


15.0 PCI/µP Interface

This chapter discusses the functions of the PCI/µP interface and includes the following topics:

• PCI/µP Interface Overview (Section 15.2)

• PCI/µP Signal Description (Section 15.3)

• PCI Interface Timing (Section 15.4)

• PCI DMA Operation (Section 15.5)‘

• PCI – SDRAM Windowing Operation (Section 15.6)

• PCI – AHB (ARM Host Bus) Direct Access (Section 15.7)

• PCI Host Mode Operations (Section 15.8)

– PCI Host Configuration Programming (Section 15.8.1)

– PCI Configuration Registers (Section 15.8.2)

– PCI Host Mode Arbiter Operations (Section 15.8.3)

• µP (microProcessor) Bus Interface (Section 15.9)

For a view of the PCI/µP (HIF/PCI) block within the top-level block diagram, see Figure 2-1.

15.1 PCI/µP Interface Features• In PCI (Peripheral Component Interconnect) mode, three types of operations are supported: (1) DMA

operations (with associated mailboxes), (2) windowing operations (where a portion of the M821xx’s SDRAM is directly mapped onto PCI), and (3) direct mapping operations (where the external PCI bus is mapped directly onto the internal ARM Host Bus). In the generic µP mode, only DMA operations are supported.

• The M821xx PCI interface supports only +3.3 V signaling.

• FIFO size is 512 bytes (in each direction) for DMA operations, and 256 bytes (in each direction) for windowing operations. FIFOs are not used in ARM Host Bus (AHB) to PCI direct mapping operations.

• PCI interface, when configured as host, can configure the entire PCI bus and serve as the PCI arbiter supporting an internal master as well as 2 external masters.

• The Microprocessor (µP) Bus Interface is a general purpose microprocessor bus interface that allows data transfer at up to 66 MHz, and it always looks like a slave peripheral to the microprocessor.

• µP Bus Interface supports different bus-sized host processors: 8, 16, and 32 bits.

• µP Bus Interface can be configured to run in burst mode, non-burst synchronous mode, or asynchronous mode.

M821xx Data Sheet


15.2 PCI/µP Interface OverviewA functional block diagram of the PCI/µP Interface is shown in Figure 15-1. The IDMA functional block acts as the central DMA engine in the M821xx device and provides DMA services for all I/O blocks in the device.

The M821xx PCI/µP Bus I/O pins support either PCI or a generic µP interface:

• PCI interface — When configured in PCI mode, the M821xx can be used as either a PCI host or non-host. When the PCI interface is a host, it is used as a master and can also be used as a slave. When, not the host, the interface can be used as either a master or a slave according to the configuration.

As a PCI host, the M821xx configures other devices on the bus and handles arbitration for the bus among masters. Up to 2 external bus master are supported. A PCI bus master is the device which initiates bus cycles. The M821xx PCI interface supports three operational modes:

– DMA operations via the FIFO — In this mode, DMA blocks are moved between the IDMA controller and the external PCI bus through the Tx/Rx FIFOs, the Mux blocks, and the PCI Controller Block. External PCI devices and the M821xx use the Mailbox Registers to coordinate block transfers.

– Windowing of SDRAM — When operating as a slave, the PCI interface allows external PCI devices to directly access the M821xx’s external DDR2 SDRAM with DMA transfers. In Figure 15-1, this path consists of the PCI I/O Pin Mux through the PCI Controller and the PCI Bridge to the IDMA (Internal DMA) Controller.

Figure 15-1 PCI/µP Interface Functional Block Diagram

I/O PinMUX

PCI/µPBus

PCI _REQn#

PCI _GNTn#

PCI BusMasterArbiter

PCICntlrand

ConfigurationSpace (HostMaster/Slave)

µP BusController(Slave only)

PCI Bridgewith FIFO

(PCI slaves)

MUX

Tx/Rx

Mailbox

FIFOs(Master/Slave)

High SpeedBus (AHB)

IDMACntlr

Registers(Slave only)

PCI

DirectAccessARM/PCIBus

Bridge

MUX

M821xx Data Sheet


– Direct mapping of PCI bus to AHB bus — In this mode transfers between the AHB and the PCI bus are supported via the Direct Access ARM/PCI Bus Bridge shown in Figure 15-1.

• µP interface— A generic interface which is compatible with commonly used external microprocessors. In this mode, the interface is a µP slave interface only. In this context “host” refers to the external microprocessor. In this mode, transfers between the external µP and the M821xx flow from the I/O Pin Mux to the IDMA controller thorugh the µP bus controller the muxes, and the Tx/Rx FIFOs as shown in Figure 15-1.

15.3 Signal DescriptionsTable 15-1 PCI/µProcessor Bus Signals


PCIMODE/HBMODE#

I 1 PCI Bus Mode / µP Bus Mode Select — It selects either the PCI bus or µP bus. This pin is latched at reset as a bootstrap:

1 = PCI bus selected.0 = µP bus selected.

PCI_HOST#/HBURSTEN#

I 1 PCI Host Mode Select — When the interface is in PCI mode, this configures PCI Peripheral Mode or PCI Host Mode.

µP Bus Burst Enable — When the interface is in µP mode, this signal enables burst access; so multiple data can be transferred on single pule of HBCS# = 0. When HBBURSTEN# = 1, burst access is not enabled and each HBCS# = L pulse has only one data transfer, either 8 bit, 16 bit, or 32 bit. When HBBURSTEN# = 0, the interface is said to be in Burst Mode, and when HBURSTEN# = 1, in Non-Burst mode. This pin is latched at reset as a bootstrap. For asynchronous mode, HBBURSTEN# must be set high.

Reserved/HBBUSSIZE[1:0]

I 2 Reserved.

µP Bus Size — Specifies the width of the external µP data bus. When the bus width is less than 32 bits, the upper, un-connected µP signals will be driven low all the time. This pin is latched at reset as a bootstrap.

11 or 10 = 32 bit data bus.01 = 16 bit data bus.00 = 8 bit data bus.

PCIREQ2/Reserved

I 1 Request2— REQ# is used to indicate to the arbiter that an external PCI device requires use of the bus. Connect to PCI Bus REQ#.

Reserved.

PCIGNT2# /Reserved

O 1 Grant2 — GNT# is used to indicate to the external PCI device requiring access the bus has been granted. Used only in PCI Host Mode. Connect to PCI Bus: GNT#.

Reserved.

PCI_PERR/HBWAIT#

B 1 Parity Error — PERR# is used for the reporting of data parity errors. Connect to PCI Bus: PERR#.

I µP Bus Wait — µP Host Bus adds one wait clock, HBWAIT# = 0 adds one HBCLK to the address setup and the data access during the Burst Mode; each data is transferred in 2 HBCLK instead of every HBCLK. This pin is not latched at reset, but must be kept static. For asynchronous mode, HBWAIT# must be set low.

M821xx Data Sheet


PCI_CLK/HBCLK

I 1 PCI Bus Clock — Input provides timing for all transactions on PCI. Connect to PCI Bus: CLK.

µP Bus Clock — This input clock supports timing for the µP in synchronous mode.

PCI_STOP#/HBFIFO

B 1 PCI Bus Stop — STOP# is asserted to indicate the Bus Interface is requesting the master to stop the current transaction. Connect to PCI Bus: STOP#.

I µP Bus FIFO Select — FIFO or registers select, it indicates the current bus access is to the FIFO or registers. It should be tied to the appropriate address bit of the external microprocessor.

1 = access FIFO0 = access registers

PCI_IRDY#/HBA6

B 1 Initiator Ready — IRDY# is used to indicate the initiating agent’s (bus master’s) ability to complete the current data phase of the transaction.IRDY# is used in conjunction with TRDY#.Connect to PCI Bus: IRDY#.

I µP Bus Address Bits — Address to select register, these bits select the register to be accessed. When HBFIFO = 1 these address signals are ignored. Note that HBA[1] is never used in the µP Bus, because all the registers have 8 bit or 16 bits and are aligned to the 32-bit word boundary.

PCI_IDSEL /HBA5

I 1 Initialization Device — IDSEL input is used as a chip select during configuration read and write transactions. Connect to PCI Bus: IDSEL.

µP Bus Address Bit 5

PCI_FRAME#/HBA4

B 1 Cycle Frame — FRAME# is driven by the current master to indicate the beginning and duration of an access. Connect to PCI Bus: FRAME#.

I µP Bus Address Bit 4

PCI_DEVSEL#/HBA3

B 1 Device Select — When actively driven, DEVSEL# indicates the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. Connect to PCI Bus: DEVSEL#


PCI_PAR/HBA2

B 1 Parity — Parity is even parity across AD[31:00] and CBE[3:0]#. The master drives PAR for address and write data phases; the Bus Interface drives PAR for address and write data phases. Connect to PCI Bus: PAR.


PCI_AD[31:0]/HBD[31:0]

B 32 PCI Address and Data Bus [31:0]

µP Bus Data Bits [31:0] — HBD[31] is the most significant bit of the data bus, and HBD[0] is the least significant bit of the data bus.

Table 15-1 PCI/µProcessor Bus Signals (Continued)


M821xx Data Sheet


PCI_CBE#[3:0]/HBBE#[3:0]

B 4 PCI Bus Command and Byte Enable — Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, CBE#[3:0] defines the bus command. During the data phase, CBE#[3:0] are used as Byte Enables.Connect to PCI Bus: CBE#[3:0].

I µP Bus Byte Enable or Address Bit 0 — Connect to µP Bus Byte Enable [3:0] (low active) or Address Bit 0.HBBE3 indicates if HBD[31:24] is active.HBBE2 indicates if HBD[23:16] is active HBBE1 indicates if HBD[15:8] is active HBBE0 indicates if HBD[7:0] is active, or is used as HBA address LSbit.

PCI_TRDY#/HBCS#

B 1 Target Ready — TRDY# is used to indicate the Bus Interface’s ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. Connect to PCI Bus: TRDY#.

I µP Bus Chip Select — Low active. Connect to Microprocessor Bus Chip Select.

PCI_SERR#/HBW#

B 1 System Error — SERR# is an open drain output asserted to report address parity errors, data parity errors on the Special Cycle Command, or any other system error where the result will be catastrophic. Connect to PCI Bus: SERR#.

I µP Bus Write — Low active. Connect to µP Bus Write. HBW# = 0 for a write cycle, and HBW# = 1 for a read cycle.

PCIGNT1#/HBLAST#

B 1 Grant — GNT# is used to indicate to the agent that access to the bus has been granted. It is used as output when the device is the PCI arbiter, and as an input it is not. Connect to PCI Bus: GNT#.

I µP Bus Burst Last Indicator — For synchronous burst mode, indicates that the current data is the last of the burst transfer. HBLAST# = 1 indicates the continuation of a burst. For synchronous non-burst mode, this signal is ignored and it should stay high. For asynchronous mode, controls data output enable.

PCI_INTA# /HBINT#

O 1 Interrupt A — INTA# is an open drain output asserted to request an interrupt. Used only in when the PCI interface is in Host Mode. Connect to PCI Bus: INTA#.

µP Bus Interrupt — HBINT# is an active low open drain output asserted to request an interrupt. Connect to µP Bus INT#.

PCI_INTB#/Reserved

O 1 Interrupt B (Optional) — INTB# is an open drain output asserted to request an interrupt. Used only in Host Mode. Connect to PCI Bus INTB#.

Reserved.

PCIREQ1#/Reserved

B 1 Request — REQ# is used to indicate to the arbiter that a PCI device requires use of the bus. It is used as input when the M821xx is the PCI arbiter, and as an output when the M821xx is not. Connect to PCI Bus: REQ#.

Reserved.

Table 15-1 PCI/µProcessor Bus Signals (Continued)


M821xx Data Sheet


15.4 PCI Interface Timing The PCI Bus Interface is fully compatible with the 32-bit, 33 MHz PCI Local Bus Specification, Production Version, Revision 2.1, June 1, 1995. Please refer to this document when clarification is needed. Features not supported are PME and LOCK. The PCI Bus interface description and registers are described in this section.

15.4.1 PCI Bus Interface TimingThe PCI output data timing is shown in Figure 15-2. The PCI input data timing is shown in Figure 15-3. The PCI Bus data timing is specified in PCI Bus Input and Output Data Interface Timing.

Figure 15-2 PCI Bus Output Data Timing

Figure 15-3 PCI Bus Input Data Timing

Delay -All PCI Outputs

Tri-state -All PCI Outputs

Ton

Toff

PCI_CLKV_th

V_tl

Tval

All PCI Inputs

Tsu

PCI_CLKV_th

V_tl

Th

M821xx Data Sheet


Table 15-2 PCI Bus Input and Output Data Interface Timing


Slew Rate 1 4 V/ns 1

PCI_CLK frequency 33 MHz

PC_CLK duty cycle 36 64 %

Tval PCI_CLK to Signal Valid Delay - bused signals 2 11 ns 5, 6

Tval (ptp) PCI_CLK to Signal Valid Delay - point to point 2 12 ns 5, 6

Ton Float to Active Delay 2 ns 3, 5

Toff Active to Float Delay 28 ns 3, 5

Tsu Input Setup Time to PCI_CLK - bused signals 7 ns 4, 5

Tsu (ptp) Input Setup Time to PCI_CLK - point to point 10, 12 ns 2, 5

Th Input Hold Time from PCI_CLK 0 ns 5

Notes:1) Condition: 0.2 Vcc - 0.6Vcc load.2) PCI_REQ# and PCI_GNT# are point-to-point signals and have different output valid delay and input setup times than do bused signals.

PCI_GNT# has a setup of 10 ns; PCI_REQ# has a setup of 12 ns. All other signals are bused.3 )For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total current delivered through the

component pin is less than or equal to the leakage current specification.4) Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. Refer to PCI

Local Bus Specification for additional details.5) Based on standard PCI timing specification conventions.

M821xx Data Sheet


15.5 PCI DMA OperationFigure 15-4 highlights the hardware supporting PCI DMA operations. Note that the M821xx may be configured as PCI bus host or non-host and may be acting as master or slave during these operatiions.

In this operational mode, transfers between the M821xx and the external PCI bus are via transfers of Tx/Rx FIFO contents. These FIFOs support DMA transaction on the AHB bus by the the IDMA Controller.

15.5.1 Mailbox and FIFO Registers The PCI DMA interface (see Figure 15-5) is served by two FIFOs, one for transmitted data (inbound) from the M821xx and one for received data (outbound) to the M821xx. In addition to the FIFOs, there are four transmit and four receive “mailbox” registers that serve for out-of-band control data between the external PCI device and the M821xx. Status and interrupt control registers are also provided.

Each FIFO is 512 bytes deep. The interface is 64 bits wide. Each FIFO can be accessed at the long word (64 bits wide), double-word (32 bits wide), word (16 bits wide), or byte (8 bits wide) level. The design of the FIFOs and associated registers allows simultaneous access by both the external PCI device and the M821xx without the loss or modification of any data being exchanged.

Figure 15-4 PCI-DMA Operations Block Diagram

NOTE: All Mailbox, Control, and Status Registers are 16-bit words. For 8-bit access, the external mP or PCI device must read or write Register bits [7:0] first, then read or write bits [15:7]. Also for 8-bit FIFO access, the external mP or PCI device must read or write FIFO bits [7:0] first, then read or write FIFO bits [15:7].

I/O PinMUX

PCI/µPBus

PCI _REQn#

PCI _GNTn#


PCICntlrand



PCI Bridgewith FIFO

(PCI slaves)

MUX

Tx/Rx

Mailbox

FIFOs(Master/Slave)

High SpeedBus (AHB)

IDMACntlr


PCI


Bridge

MUX

M821xx Data Sheet


15.5.2 Mailbox Register DescriptionsThe mailbox interface consists of 18 registers, all of which can be read or written by either the external PCI device or the M821xx.

For a detailed description of these registers, contact your Mindspeed representative.

Figure 15-5 FIFO / Mailbox Register Interface Block Diagram

RX_FIFO TX_FIFO

Host Interface Control

ARM MCU Interface Control

Internal System Bus

PCI B

us

MAILBOXInterface

M821xx Data Sheet


15.6 PCI – SDRAM Windowing OperationsFigure 15-4 highlights the hardware supporting PCI-SDRAM windowing operations.

In PCI-SDRAM Windowing access operations, the M821xx is always the slave. The external PCI bus master can use this mode to access the M821xx’s DDR2 SDRAM.

The PCI Memory Bridge (also referred to as PCI Host Memory Bridge) supports windowing of the SDRAM on to the PCI bus, thus allowing external PCI bus masters to access M821xx SDRAM via 256 byte FIFOs.

The PCI Host Memory Bridge provides data transfer between peripheral devices on the PCI Bus and the SDRAM attached to the M821xx device. The PCI Host Memory Bridge supports single and burst reads and writes.

Figure 15-6 PCI-SDRAM Windowing Operations Block Diagram

NOTE: ‘Host’ in this context refers to any external PCI master which also may be the PCI bus host on the PCI bus. However, this operational mode is also supported when the M821xx is the PCI bus host.

I/O PinMUX

PCI/µPBus

PCI _REQn#

PCI _GNTn#


PCICntlrand



PCI Bridgewith FIFO

(PCI slaves)

MUX

Tx/Rx

Mailbox

FIFOs(Master/Slave)

High SpeedBus (AHB)

IDMACntlr


PCI


Bridge

MUX

M821xx Data Sheet


15.6.1 PCI Host Memory Bridge (HMB) FunctionsThe following is a list of functions:

• PCI Transfers are Queued in an internal FIFO• PCI Retry (Time-out) Timer Capability• PCI Memory Read

• PCI read burst data every clock• Prefetch read data size (4, 8, 16, 32) 32-bit words• Preserve read data for PCI retry transfer

• PCI Memory Write• PCI write burst data every clock• Non-contiguous byte-enabled writes are NOT allowed• System Error interrupt.

15.6.1.1 HMB Block Overview

The HMB provides bridging PCI interface to IDMA module for system memory access. This interface supports data flow control through the FIFO system and translates PCI memory-mapped address space into internal AHB system address space. The HMB provides two address mapping windows. The HMB is integrated in the current HIF module and adds one more IDMA channels for data transfers.

NOTE: Configuring the HMB interface for retry mode may lower PCI throughput. For best performance, leave the interface set up for the default non-retry mode.

Figure 15-7 HMB Block Diagram

PCI

HICORE

HMB CTRL

IDMA

HIFCORE

HICORE

HMBCORE

TX FIFO

RX FIFO

AX FIFO

M821xx Data Sheet


15.6.1.2 HMB Function

The HMB behaves as a PCI memory slave (not a memory-mapped I/O or I/O) in the PCI bus system. It is required to have a host to configure the HMB after the system startup. There are three configuration base registers in the PCI module which has one base address register for the HICORE register and FIFO system, and the other two base address registers are assigned to HMB for PCI system memory allocation. The size of these two memory windows in HMB has to be defined before the PCI host configures the memory base address registers.

The HMB is responsible for the PCI memory target access such as memory read and memory write. It also supports both PCI single and burst access if the bit 3 of BME interface control register is enabled in the HICORE module.

The HMB bridges the PCI bus to the internal memory space of the AHB bus system through the HMDMA (HMB DMA is part of IDMA module). Due to the nature of AHB bus system, the HMDMA requires a certain of time latency to complete the task from HMB or PCI. This time latency depends on the traffic and arbitration inside of HMDMA, memory, and AHB bus system. In the case of extensive long latency from the HMDMA or the AHB bus, the HMB may timeout by issuing a retry or disconnect on the PCI side.

The first time of PCI memory read access requires some latency to have the HMB to send a command to HMDMA. If the HMDMA can not get all read data in the time limit programmed in the HMB wait cycle of the mode control register, the HMB will give a retry back to the PCI initiator and in the meantime preserve those lately coming data from HMDMA in the HMB FIFO. If the same read access retries right after the first time read and the read data is already available in the HMB, the read access will be completed, otherwise it could be timeout by retry again. If the second time access does not match with the previous access terminated by the retry, the HMB will flush the previous data and start the new access (read or write). This event is also applied to the write access but the HMB does not care about the same access or not.

The HMB does not support PCI write access with non-contiguous byte-enable on both the single and burst transfers. Any byte-enable violation will cause a system error asserted when the system error is enabled in the PCI configuration registers. In the meantime, it may also generate an interrupt to the ARM with the system error flag set in the HMB status register.

15.6.1.3 HMB Interface Registers (Including HICORE Host Side Register)

See Section 16.4 HMB Interface Registers (Including HICORE Host Side Register).

M821xx Data Sheet


15.7 PCI – AHB Direct AccessIn PCI – AHB direct access operations, the M821xx transfers data between the external PCI bus and the AHB. In these transfers, one AHB bus cyle of 64-bit long words corresponds to two PCI bus cycles with two 32-bit dwords. Transfers can involve 2 cycle PCI bust bursts with a corresponding bus cyle on the AHB bus. However, the M821xx also supports transfers of 8-, 16- and 32-bit words between the AHB and the PCI.

15.7.1 Functional DescriptionThe Direct Access ARM / PCI Bus Bridge (APBB) controls the data path from the ARMs to the PCI Bus. This allows the ARMs to perform a single transaction on the AHB which is translated into a maximum of two burst transactions on the PCI bus.

This enables the ARMs to do a master transaction on the PCI bus. However, the addresses accessed by the ARM are the same addresses to be driven onto the PCI bus. Therefore, PCI slaves responding to this access must be in the appropriate range — 0x4000 0000 to 0x4FFF FFFF.

To enable the Direct Acces ARM / PCI Bus Bridge, an internal ARM configures the registers detailed in Section 15.7.2 APBB Registers during intialization.

Once the APBB starts a transaction it will not relinquish the PCI interface until the transaction is over. The master on the AHB will not receive a ready indication until the transaction on the PCI is completed, even in a write transaction. The execution of the transaction on the PCI bus can be delayed for an undefined number of cycles due to disconnects and/or retries on the PCI bus.

Figure 15-8 PCI-SDRAM Windowing Operations Block Diagram

I/O PinMUX

PCI/µPBus

PCI _REQn#

PCI _GNTn#


PCICntlrand



PCI Bridgewith FIFO

(PCI slaves)

MUX

Tx/Rx

Mailbox

FIFOs(Master/Slave)

High SpeedBus (AHB)

IDMACntlr


PCI


Bridge

MUX

M821xx Data Sheet


15.7.2 APBB RegistersSee Section 16.5 APB Accessible Registers.

15.8 PCI Host Mode OperationsThe 32-bit, 33 MHz PCI Host Mode provides configuration and control for peripheral devices (both Master and Slave) on the PCI Bus. The PCI Host Mode provides the following features:

• PCI Host Memory Bridge (HMB) for data transfers between peripherals and SDRAM.

• PCI Host Mode Bus Arbiter for two Bus Masters.

15.8.1 PCI Host Configuration Programming NoteEach PCI device has a set of PCI configuration registers. Before a PCI bus starts any operations, the PCI Host must configure all PCI devices on the PCI bus, including the PCI Host device.

The M821xx PCI Host mode supports PCI configuration access. The M821xx PCI Host can issue a configuration transaction to a PCI device on the PCI bus. In a Type 0 configuration access, the upper 16 address lines, PCI AD[31:16], are routed to the IDSEL pins. The system board designer uses these signal lines as IDSEL signals to the various physical devices (up to 16 of them). Device0 is always the source Host/bridge of the bus and its IDSEL is routed to AD[16] (i.e. The device0 configuration base address is mapped to 0x00010000).

NOTE: The M821xx device can perform HMB data transfers without being configured as host.

NOTE: The Host must configure its own PCI Configuration Space, which requires connecting an Address line to IDSEL.

M821xx Data Sheet


The M821xx Host Interface (HIF) module is used to initiate a configuration transaction on the PCI Bus. The following programming example shows how to use the M821xx Host Interface (HIF) module to generate a configuration transaction.

15.8.1.1 Example 1: Configuration Write

Program write 0x02900046 to Host Configuration Command Register (offset 0x4)

1. Write the PCI configuration command register address (0x00010004) to the PCI TX/RX DMA Starting Address register (APB address: 0x10010060).

2. Write the burst size 4 to the HI BME Transfer Burst Size register (0x10010064).3. Write the transfer length 4 to the HI BME DMA Transfer Length register (0x10010068).4. Write the configuration word value 0x02900046 to the HI RX FIFO register (0x1001C000).5. Write 0x80 to HI FIFO Interrupt Acknowledge Register (0x10010004) to flush.6. Write 0x0004003B to the HI BME Interface Control register (0x10010050) to start the host configuration write

transaction.7. Poll the bit 1 of the HI BME Interface Control register clear to 0 to wait for configuration write transaction done.

(1: busy; 0: done).

15.8.1.2 Example 2: Configuration Read

Program read from Host Configuration Device ID Register (offset 0x0)

1. Write the PCI configuration device ID register address (0x00010000) to the HI BME DMA Starting Address register (APB address: 0x10010060).

2. Write the burst size 4 to the HI BME Transfer Burst Size register (0x10010064).3. Write the transfer length 4 to the HI BME DMA Transfer Length register (0x10010068).4. Write 0x0004003F to the HI BME Interface Control register (0x10010050) to start the host configuration read

transaction.5. Poll the bit 1 of the HI BME Interface Control register clear to 0 to wait for configuration read transaction done.

(1: busy; 0: done).

Figure 15-9 PCI Host Configuration

PCI AD[16]

PCI AD Bus

PCI AD[17] PCI AD[18]

PCI HOST

Device Host

IDSEL PCI AD[19] PCI AD[20]

IDSEL IDSEL

IDSEL IDSELPCI Master or

SlaveDevice 4

PCI Master or Slave

Device 3

PCI Master or Slave

Device 1

PCI Master or Slave

Device 2

M821xx Data Sheet


6. Read the configuration value from the HI TX FIFO register (0x1001C000). The word value should be 0x015018DC.

15.8.2 PCI Bus Configuration Registers and Allocation Maps See Section 16.3 PCI Bus Configuration Registers and Allocation Maps.

15.8.3 PCI Host Mode Bus ArbiterThe M821xx supports arbitration for two external masters. Figure 15-10 presents an example in which an external PCI device can use request and interrupt signals to gain bus mastery and access to M821xx via PCI – SDRAM windowing.

15.8.3.1 PCI Arbiter Requirements

The PCI Arbiter Requirements extracted from the 33 MHz PCI Specification 2.1 (mostly from Section 3.4.1) are summarized below:

• The arbiter may de assert an agent's GNT_N on any clock.

• A master is allowed to start a transaction when its GNT_N is asserted and the bus is in an Idle state independent of the state of its REQ_N.

• Once asserted, GNT_N may be de asserted according to the following rules:

Figure 15-10 PCI Host Mode Block Diagram

PCI Host ModeController

SDRAMInterface

PCI Host ModeBridge

PCI Host ModeBus Arbiter

InterruptController(optional)

PCI Bus to Peripherals

REQ_1

GNT_1

REQ_5

GNT_5

INT_1

INT_n

PCI Host Mode in Comcerto DeviceGPIO [7:0]

REQ_2

GNT_2

M821xx Data Sheet


– If GNT_N is deasserted and FRAME_N is asserted on the same clock, the bus transaction is valid and will continue.

– One GNT_N can be deasserted coincident with another GNT_N being asserted if the bus is not in the Idle state. Otherwise, a one clock delay is required between the deassertion of a GNT_N and the assertion of the next GNT_N.

– While FRAME_N is deasserted, GNT_N may be deasserted at any time in order to service a higher priority master, or in response to the associated REQ_N being de-asserted.

15.8.3.2 PCI Host Mode Arbiter Operation

The Mindspeed Comcerto device PCI Host Mode Arbiter meets the requirements of the 33MHz PCI Specification 2.1. During the PCI Idle cycles, the arbiter inserts a no-grant cycle to add delay between the de assertion of a gnt_n and the assertion of the next gnt_n, and no delay is added when the PCI is not idle. When frame_n is de asserted, the arbiter may de assert the gnt_n at any time, but when frame_n is asserted and req_n is also asserted, gnt_n will be asserted for a minimum of 3 bus clock cycles before the arbiter responds to other higher priority requests.

The arbiter supports two arbitration schemes: Priority or Round_Robin. When the Priority scheme is selected, the req_n(0) is the highest priority input and req_n(2) is the lowest priority input. When the Round_Robin scheme is selected, the priority of the req_n signal that was last granted is changed to the lowest priority at the start of frame_n assertion, and the priority of req_n signals that had lower priority than the last granted req_n signal are all moved up one level higher in priority. Both priority schemes have aging counters associated with each req_n signal. When the aging count of a req_n expires, the priority of the associated req_n is changed to highest level, so it will win the arbitration as soon as possible. The aging counter is active when the associated req_n is asserted, and the aging counter is reset when the request is granted. The maximum aging count is the same for every req_n signal.

When a (malfunctioning) PCI master asserts req_n without ever asserting frame_n, the arbiter will wait up to 16 bus clock cycles while checking frame_n assertion, before deciding that the req_n is broken and change that request to the lowest priority, disable its aging counter, and deny the arbitration for that req_n input for 120 clock cycles out of every 128 clock cycles. In other words, when a req_n is asserted forever (and its master never asserts frame_n after receiving gnt_n), the priority of that req_n will become the lowest, its aging counter disabled, and it is only allowed to participate in arbitration during a window of 8 clock cycles out of every 128 clock cycles. The req_n will be marked as broken until its master starts asserting frame_n after receiving gnt_n.

NOTE: The specification requires that the master must de-assert REQ_N when the Latency Timer expires and GNT_N is de asserted. Also, when complete bus lock (PCI Specification 2.1, Section 3.6.6.) is implemented, LOCK_N is de asserted when FRAME_N is asserted for the lock owner access, so the arbiter must not grant the bus to other masters during a locked cycle with FRAME_N asserted.

NOTE: GNT_N may be de asserted as soon as FRAME_N is asserted, or two clock cycles after FRAME_N is asserted. The Mindspeed Comcerto Device arbiter provides a programmable counter for the number of bus clock cycles to delay GNT_N assertion after FRAME_N and REQ_N are asserted.

M821xx Data Sheet


15.9 Microprocessor (µP) Bus InterfaceThe purpose of the uP Interface is to allow efficient data transfer between the memory within the M821xx and an external microprocessor (uP). The M821xx uP is capable of interfacing to either the PCI bus or the General Purpose Microprocessor Bus (Microprocessor Bus). If the input pin HBMODE# is high, the PCI bus will be selected; if HBMODE# is low, the µP Host Bus will be selected. The logic value of the HBMODE# input pin must be static and never change after system reset. The PCI Bus Interface is described in previous sections.

The Microprocessor Bus Interface is a general purpose microprocessor bus interface supporting various microprocessor types at up to 66 MHz, and always appears as a slave peripheral to the external microprocessor.

The M821xx data flow convention is such that the transmit (TX) direction shall be from the external uP to the M821xx and the receive (RX) direction shall be from the M821xx to the external uP.

For more information, refer to the following Application Note - Connecting a PowerQuicc MPC8260 to the M826xx Microprocessor Interface Application Note (82620-APP-001).

15.9.1 8-bit, 16-bit, and 32-bit µP BusThe uP Bus interface supports different host processor bus sizes, and the HBSIZESEL input pins select the bus size to be used by uP Bus Interface. Refer to Table 15-3 for a recommended hardware connection with different host processors.

Table 15-3 Microprocessor Bus Connection to Host Processor Bus

Microprocessor Bus Signals 8-bit Bus Host Processor 16-bit Bus Host Processor 32-bit Bus Host Processor

HBSIZESEL[1, 0] [Low, Low] [Low, High] [High, High]

HBA[6: 2] Address[6: 2] Address[6: 2] address[6: 2]

HBBE3#, High High byte enable for data[31: 24], active low

HBBE2# High High byte enable for data[23: 16], active low

HBBE1# High byte enable for data[15: 8], active low

byte enable for data[15: 8], active low

HBBE0# / HBA[0] Address[0] byte enable for data[7: 0], active low

byte enable for data[7: 0], active low

HBD[31: 24] Do not connect (driven low) Do not connect (driven low) data[31: 24]

HBD[23: 16] Do not connect (driven low) Do not connect (driven low) data[23: 16]

HBD[15: 8] Do not connect (driven low) data[15: 8] data[15: 8]

HBD[7: 0] data[7: 0] data[7: 0] data[7: 0]

M821xx Data Sheet


15.9.2 µP Bus General DescriptionThe µP Bus can be configured to run in Burst Mode or Non-Burst Mode. When HBBURSTEN#= low, the Burst Mode is enabled and multiple data can be transferred on a single HBCS# = low pulse (FIFO Burst Read With No Wait State and FIFO Burst Write With No Wait State). When HBBURSTEN#= high, the Non-Burst Mode is enabled, and only single data is transferred per each HBCS# pulse (Non-Burst Read From FIFO or Register and Non-Burst Write To FIFO or Register).

For more information on the FIFO / Mailbox Register subsystem, refer to Section 15.5.1 Mailbox and FIFO Registers.

Burst Mode In Burst Mode, depending on the frequency of the HBCLK, it may be required to add a wait state to the burst transfers. HBWAIT# can be used to add one more clock on the address setup and on each data transfer. When HBWAIT# = high, the first address setup time is one HBCLK clock and the data is transferred on every HBCLK clock. When HBWAIT# = low, the first address setup time is two HBCLK clocks and the data is transferred on every two HBCLK clock cycles (FIFO Burst Read With Wait State and FIFO Burst Write With Wait State).

Burst reads or writes to HREGS will affect only the first register, even if the address on the µP Bus is incrementing. The address of the burst is latched and not incremented during the burst, and the last data value of a burst write will be the final value of the register. Burst reads will have the value of the first addressed register driving the bus throughout the burst cycle; no other registers will be addressed.

Non-Burst ModeIn non-burst mode, a single data is transferred at the rising edge of HBCS# pulse. Regardless, if the HBCS# pulse is one HBCLK clock long or a hundred clocks long, the data is written to HICORE only once. On the read cycle, the data is driven on the bus as long as HBCS# is asserted.

In non-burst mode, the cycle time (high and low) of a HBCS# pulse must have at least three HBCLK clocks duration. The HBCS# pulse must have at least two-clocks-high-one-clock-low or one-clock-high-two-clock-low in the back-to-back accesses.

Asynchronous ModeIn asynchronous mode, transfers are made with reference to HBCS# rather than HBCLK. For timing, refer to Table 15-5 on page 298.

Asynchronus mode is effected by holding the BURSTEN# input high and shifting the HBWAIT# input low.

NOTE: In asynchronous mode only one slave can be connected without external logic.

M821xx Data Sheet


15.9.3 µP Interface FIFO / Register MapSee Section 16.2 Mailbox and FIFO Registers.

15.9.4 Microprocessor Bus WaveformsFigure 15-11 FIFO Burst Read With No Wait State

1 2 3 4 5 6 7 8 9 10

D1

D0 D1 D2

D2 D3

READ IDLE

D3 D4 D5 D6 D7

D4 D5 D6 D7 D8D0

X X

X

uP Host Bus FIFO Burst Read With No Wait State

IDLE

50ns 100ns 150ns 200ns 250ns

hbclk

hbbursten#

hbbussize

hbwait#

..

hbcs#

hba

hbfifo

hbw#

hbbe#

hbblast#

hbd

.

HBSTATE(internal)

cs (internal)

fifo_out (internal)

M821xx Data Sheet


Figure 15-12 FIFO Burst Read With Wait State

1 2 3 4 5 6 7 8 9 10 11

Read IDL

X X

X

D0 D1 D2 D3 D4

D0 D1 D2 D3

AWait DWait DWait Read_ST DWait Read DWait Read

uP Host Bus FIFO Burst Read With Wait State

IDLE

50ns 100ns 150ns 200ns 250ns

hbclk

hbbursten#

hbbussize

hbwait#

..

hbcs#

hba

hbfifo

hbw#

hbbe#

hbblast#

hbd

.

HBSTATE (internal)

cs (internal)

fifo_out (internal)

M821xx Data Sheet


Figure 15-13 FIFO Burst Write With No Wait State

1 2 3 4 5 6 7 8 9

D0 D1 D2

WRITE IDL

D3 D4 D5 D6 D7

X X

X

D0 D1 D2 D3 D4 D5 D6 D7

uP Host Bus FIFO Burst Write With No Wait State

IDLE

50ns 100ns 150ns 200ns 250ns

hbclk

hbbursten#

hbbussize

hbwait#

..

hbcs#

hba

hbfifo

hbw#

hbbe#

hbblast#

hbd

.

HBSTATE (internal)

cs (internal)

fi fo_in (internal)

M821xx Data Sheet


Figure 15-14 FIFO Burst Write With Wait State

1 2 3 4 5 6 7 8 9

D0 D1

IDLE

X X

X

D0 D1 D2 D3

D2 D3

AWait Write DWait Write DWait Write DWait Write

uP Host Bus FIFO Burst Write With Wait State

50ns 100ns 150ns 200ns 250ns

hbclk

hbbursten#

hbbussize

hbwait#

..

hbcs#

hba

hbfifo

hbw#

hbbe#

hbblast#

hbd

.

HBSTATE (internal)

cs (internal)

fi fo_in (internal)

M821xx Data Sheet


Figure 15-15 Non-Burst Read From FIFO or Register

1 2 3 4 5 6 7 8 9 10

A1

D1

A2

D2

CS NNOCSNOCS CS

50ns 100ns 150ns 200ns

hbclk

hbbursten#

hbbussize

hbw ait#

..

hbcs#

hbw #

hba

hbbe#

hbfifo

hbd

.

HBSTATE (internal)

cs (internal)

M821xx Data Sheet


Figure 15-16 Non-Burst Write To FIFO or Register

1 2 3 4 5 6 7 8 9 10

A1

D1

A2

D2

CS NNOCSNOCS CS

uP Host Bus Non-burst Write to FIFO or Registers

D1 D2

50ns 100ns 150ns 200ns

hbclk

hbbursten#

hbbussize

hbwait#

..

hbcs#

hbw#

hba

hbbe#

hbfifo

hbd

.

HBSTATE(internal)

Wdata (internal)

cs (internal)

M821xx Data Sheet


Figure 15-17 Burst Read With HBBLAST# Not Used

1 2 3 4 5 6 7 8 9 10

D1

D0 D1 D2

D2 D3

READ IDLE

D3 D4 D5 D6 D7

D4 D5 D6 D7 D8D0

X X

X

uP Host Bus FIFO Burst Read With No Wait State andhbblast# not used (tied high)

IDLE

50ns 100ns 150ns 200ns 250ns

hbclk

hbbursten#

hbbussize

hbwait#

..

hbcs#

hba

hbf ifo

hbw#

hbbe#

hbblast#

hbd

.

HBSTATE(internal)

cs (internal)

f if o_out (internal)

M821xx Data Sheet


15.9.5 µP Bus AC Timing ParametersRegardless of the modes of operation, HBCS# must meet the setup and hold times specified below for the M821xx to work properly.

For the Burst Mode, all input signals and data output signals are referenced to the rising edge of HBCLK. The output is enabled asynchronously whenever HBCS# is asserted in a read cycle (HBW# = high), and the µP data output stays enabled until the last data transfer completes and HBCS# is de-asserted.

For the Non-Burst Mode, all input signals must meet the setup and hold times on the last rising edge of the HBCLK when HBCLK# is low. The µP data is accessed asynchronously when HBCS# is asserted with a valid HBA / HBFIFO and HBBE[3:0]# input in a read cycle. The µP data output is enabled as long as HBCS# is asserted and HBW# is high.

HBCLK maximum frequency is 66 MHz.

Synchronous Mode

Figure 15-18 Microprocessor Bus Synchronous AC Timing Waveforms

M821xx Data Sheet


Table 15-4 Microprocessor Bus Synchronous AC Timing Parameters

Parameter Description Minimum Maximum Units Notes

Bus clock frequency 66 MHz

Clock duty cycle 40 % 60% %

Slew rate 1 4 V/ns

HBCS# cycle time (rising edge to falling edge) in Non-Burst Mode back-to-back accesses

18 ns 1

Tadr HBCS#/HBW#/HBA / HBFIFO and HBBE[3:0]# valid to HBD valid in the Non-Burst Mode read.

15 ns

Tckdr HBCLK rising edge to HBD valid on the Burst Mode read. 11 ns

Tdoen HBCS# = L and HBW# = H to HBD start driving the bus. 3.5

Tdz_a HBCS# = H or HBW# = L to HBD tri-stated. For Burst Mode and Non-burst Mode.

12.5 ns 2, 3

Tdz_b Rising edge of HBCLK after the last data read in the Burst Mode to HBD tri-stated.

13 ns 2, 3

Tsetup Host bus signals to HBCLK active edge set up time. 7 ns

Thold Host bus signals to HBCLK active edge hold time. 1 ns

Notes:1) The numbers are calculated based on an AHB clock period of 6 ns (165 MHz).2) For Burst Mode, Tdz is the maximum of Tdz_a and Tdz_b.3) For Non-burst Mode, Tdz is equal to Tdz_a.

M821xx Data Sheet


Asynchronous Mode

Figure 15-19 Microprocessor Bus Asynchronous AC Timing Waveforms

Table 15-5 Microprocessor Bus Asynchronous AC Timing Parameters


Tccss HBA/HBFIFO/HBBE# valid to HBCS# = L 0 ns

Tcslprw HBCS# = L to HBW# = H 12 ns 1

Tcslpow HBW#=H to HBCS# = H 6 ns 1

Tcsh HBCS#=H to HBCS# = L 12 ns 1

Tccsh HBCS# = H to HBA/HBFIFO/HBBE# not valid. 0 ns

Twrl HBW# = L to HBW# =H. 12 ns 1

Tds Host bus data valid to HBW# = H (write operation). 12 ns

Tdh HBW# = H to Host bus data not valid (write operation) 6 ns

HBCS#

HBA/HBBE#/HBFIFO

HBW#

HBD(WR)

HBD(RD)

OEN(HBBLAST#)

tccss tcslprw tcslpowtcsh

tccsh

twrl

tds tdh

tdztval

tcoen

HBCS#(Read Operation)

tcslr tcshdval

M821xx Data Sheet


Tval HBLAST# = L to Host bus data valid (read operation) 3 12 ns

Tdz HBLAST# = H to Host bus data tri-stated (read operation) 3 12 ns

Tcslr HBCS# = L to HBCS#=H (read operation) 12 ns 1

Tcshdval HBCS#=H to Host bus data not valid (read operation) 18 24 ns 1

Tcoen HBCS# = L and HBA/HBFIFO/HBBE# VALID TO HBLAST = L#

6 ns 1

Notes:1) The numbers are calculated based on an AHB clock period of 6 ns (165 MHz).

Table 15-5 Microprocessor Bus Asynchronous AC Timing Parameters


.


16.0 PCI/µP Interface Registers

16.1 IntroductionThis chapter presents details on PCI/µP registers:

• “Mailbox and FIFO Registers” on page 300

• “PCI Bus Configuration Registers and Allocation Maps” on page 309

• “HMB Interface Registers (Including HICORE Host Side Register)” on page 316

• “APB Accessible Registers” on page 323

16.2 Mailbox and FIFO Registers The PCI DMA interface (see Figure 16-1) is served by two FIFOs, one for transmitted data (inbound) from the M821xx and one for received data (outbound) to the M821xx. In addition to the FIFOs, there are four transmit and four receive “mailbox” registers that serve for out-of-band control data between the external PCI device and the M821xx. Status and interrupt control registers are also provided.

Each FIFO is 512 bytes deep. The interface is 64 bits wide. Each FIFO can be accessed at the long word (64 bits wide), double-word (32 bits wide), word (16 bits wide), or byte (8 bits wide) level. The design of the FIFOs and associated registers allows simultaneous access by both the external PCI device and the M821xx without the loss or modification of any data being exchanged.

NOTE: All Mailbox, Control, and Status Registers are 16-bit words. For 8-bit access, the external uP or PCI device must read or write Register bits [7:0] first, then read or write bits [15:7]. Also for 8-bit FIFO access, the external mP or PCI device must read or write FIFO bits [7:0] first, then read or write FIFO bits [15:7].

M821xx Data Sheet


The mailbox interface consists of 18 registers, all of which can be read or written by either the external PCI device or the M821xx.

The first four are TXMAIL0-TXMAIL3 and the second four are RXMAIL0-RXMAIL3. Normally, the TXMAIL registers are written by the external PCI device (and read by the M821xx, and the RXMAIL registers are written by the M821xx and read by the external PCI device. TXMAIL3 has a special feature such that a mailbox write interrupt request is triggered to the M821xx when the external PCI device writes to TXMAIL3. A mailbox acknowledge interrupt is asserted to the external PCI device when the M821xx acknowledges the TXMAIL3 interrupt; similarly, the M821xx writing to RXMAIL3 will interrupt the external device, and the external device acknowledge of that interrupt will trigger an interrupt to the M821xx.

Note that the external device may be a PCI component or an exernal µP acting as bus master. For more on µP interface operations, refer to Section 9 of the M821xx Data Sheet (821xx-DSH-002).

Figure 16-1 FIFO / Mailbox Register Interface Block Diagram

RX_FIFO TX_FIFO

Host Interface Control

ARM MCU Interface Control

Internal System Bus

PCI B

us

MAILBOXInterface

M821xx Data Sheet


Table 16-1 Mailbox and FIFO Registers

External Bus Address Offset

Register (READ) Register (WRITE)

0x00 FIFO Control FIFO Control

0x04 FIFO Status FIFO Interrupt Acknowledge

0x10 FIFO TX Size Reserved

0x14 TX FIFO High Threshold TX FIFO High Threshold

0x18 TX FIFO Low Threshold TX FIFO Low Threshold

0x20 RX FIFO FIFO Size Reserved

0x24 RX FIFO High Threshold RX FIFO High Threshold

0x28 RX FIFO Low Threshold RX FIFO Low Threshold

0x30 Txmail0 [15:0] Txmail0 [15:0]

0x34 Txmail1 [15:0] Txmail1 [15:0]

0x38 Txmail2 [15:0] Txmail2 [15:0]

0x3C Txmail3 [15:0] Txmail3 [15:0]A external µP or PCI device write to this register will cause an interrupt to the M821xx. Acknowledging this interrupt will cause a corresponding interrupt to the external µP or PCI device.

0x40 Rxmail0 [15:0] Reserved



0x4C Rxmail3 [15:0]A M821xx write to this register will cause an interrupt to the external µP or PCI device. The external µP or PCI device acknowledge of this interrupt will cause a corresponding interrupt to the M821xx.

Reserved

0x70 HBCFG HBCFG

0x100 —0x7FF

RX_FIFO data TX_FIFO data

NOTE: For the Microprocessor (mP) Bus, the FIFO Read/Write Register is selected by the HBFIFO signal which can be connected to any external mP or PCI device Address Line above HBA6.The FIFO Read/Write Register supports a 2KByte Address Range for DMA Controllers that need to increment or decrement the address for each data transfer..

M821xx Data Sheet


16.2.1 FIFO Control Register (Address 0x00, R/W)The FIFO control register contains control (enable) bits for the external µP or PCI device transmit and receive FIFO and the mailbox interface.

Table 16-2 FIFO Control Register [15:8]

15 14 13 12 11 10 9 8

TGTABORTIE RXM3IE RXTHIE RXFIE RXCMPLTIE TXM3IE TXTHIE TXEIE

Table 16-3 FIFO Control Register [7:0]

7 6 5 4 3 2 1 0

Reserved Reserved TXCP_INH RXRQ_EN RXFF_EN Reserved TXRQ_EN TXFF_EN

Table 16-4 FIFO Control Register Bit Descriptions

Bit Parameter Description

15 TGTABORTIE Target Abort Interrupt Enable.0 = Disable interrupt when Target Transfer Aborted status bit is set.1 = Enable interrupt when Target Transfer Aborted status bit is set.

14 RXM3IE RXMAIL3 Interrupt Enable.0 = Disable interrupt when RXMAIL3 Register Written status bit is set.1 = Enable interrupt when RXMAIL3 Register Written status bit is set.

13 RXTHIE RX_FIFO Threshold Interrupt Enable.0 = Disable interrupt when RX_FIFO Exceeded Threshold status bit is set.1 = Enable interrupt when RX_FIFO Exceeded Threshold status bit is set.

12 RXFIE RX_FIFO Full Interrupt Enable.0 = Disable interrupt when RX_FIFO Full status bit is set.1 = Enable interrupt when RX_FIFO Full status bit is set.

11 RXCMPLTIE Internal RX DMA Transfer Complete Interrupt Enable.0 = Disable interrupt when Internal RX DMA Transfer Complete status bit is set.1 = Enable interrupt when Internal RX DMA Transfer Complete status bit is set.

10 TXM3IE TXMAIL3 Interrupt Enable.0 = Disable interrupt when TXMAIL3 Full status bit is set.1 = Enable interrupt when TXMAIL3 Full status bit is set.

9 TXTHIE TX_FIFO Threshold Interrupt Enable.0 = Disable interrupt when TX_FIFO Less than Threshold status bit is set.1 = Enable interrupt when TX_FIFO Less than Threshold status bit is set.

8 TXEIE TX_FIFO Empty Interrupt Enable.0 = Disable interrupt when TX_FIFO Empty status bit is set.1 = Enable interrupt when TX_FIFO Empty status bit is set.


5 TXCP_INH TX Complete Interrupt Inhibit. 0 = Enable hardware TX Completed Interrupt after DMA buffer empty condition.1 = Inhibit hardware TX Completed Interrupt after DMA buffer empty condition.

M821xx Data Sheet


4 RXRQ_EN RX DMA Request Enable. Note: RXRQ_EN must be set, to enable PCI Bus Master Mode.0 = Disable operation of HB_REQR (Default).1 = Enable operation of HB_REQR for PCI Bus Master Mode.

3 RXFF_EN RX_FIFO Operation Enable. Note: The RX_FIFO and the TX_FIFO are enabled on reset.0 = Disable RX_FIFO operation. 1 = Enable RX_FIFO operation (Default).

2 Reserved Reserved

1 TXRQ_EN TX DMA Request Enable. Note: TXRQ_EN must be set, to enable PCI Bus Master Mode.0 = Disable operation of HB_REQW (Default).1 = Enable operation of HB_REQW for PCI Bus Master Mode.

0 TXFF_EN TX_FIFO Operation Enable. Note: The RX_FIFO and the TX_FIFO are enabled on reset.0 =Disable TX_FIFO operation. 1 = Enable TX_FIFO operation (Default).

Table 16-4 FIFO Control Register Bit Descriptions (Continued)


M821xx Data Sheet


16.2.2 FIFO Status Register (Address 0x04, R)This register contains FIFO status indicator bits.

Table 16-5 FIFO Status Register [15:8]

15 14 13 12 11 10 9 8

TRGABORT RXM3I RXTH RXF RXCMPLT TXM3I TXTH TXE

Table 16-6 FIFO Status Register [7:0]

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Table 16-7 FIFO Status Register Bit Descriptions


15 TRGABORT Target Transfer Aborted Status.0 = The PCI has not aborted a target transfer.1 = The PCI has aborted a target transfer.

14 RXM3I RXMAIL3 Register Written Interrupt Status. 0 = The M821xx has not written data to the RXMAIL3 Register.1 = The M821xx has written data to the RXMAIL3 Register.

13 RXTH RX_FIFO Exceeded Threshold Status.0 = The RX_FIFO depth is equal to or less than the threshold value.1 = The RX_FIFO depth is greater than the threshold value.

12 RXF RX_FIFO Full Status.0 = The RX FIFO is not full.1 = The RX FIFO is full.

11 RXCMPLT Internal RX DMA Transfer Complete. 0 = The internal RX DMA Buffer is not empty.1 = The internal RX DMA Buffer is empty.

10 TXM3I TXMAIL3 Full Interrupt Status.0 = The M821xx has not acknowledged the TXMAIL3 Full Interrupt.1 = The M821xx has acknowledged the TXMAIL3 Full Interrupt.

9 TXTH TX_FIFO Less than Threshold Status. 0 = The TXFIFO depth is equal to or greater than the threshold value.1 = The TXFIFO depth is less than the threshold value.

8 TXE TX FIFO Empty Status. 0 = TX FIFO is not empty.1 = TX FIFO is empty.

7:0 Reserved Reserved.

M821xx Data Sheet


16.2.3 FIFO Interrupt Acknowledge Register (Address 0x04, W)This register contains FIFO interrupt acknowledge bits corresponding to status bits in the FIFO Status Register.

The FIFO interrupt acknowledge bits, 0-2, 4-6, and 9, are used to clear the corresponding interrupt status bit in FIFO Status Register. Any or all interrupt bits may be acknowledged simultaneously. Writing a 1 to the corresponding interrupt acknowledge bit causes the status bit to be cleared and the corresponding interrupt de-asserted if currently active. Writing a 0 to bits 0-2, 4-6, and 9 has no effect.

The external µP or PCI device must write a zero to all reserved bits.

Table 16-8 FIFO Interrupt Acknowledge Register [15:8]

15 14 13 12 11 10 9 8

Reserved Reserved Reserved Reserved Reserved Reserved TRGABORTIAK HSRESET

Table 16-9 FIFO Interrupt Acknowledge Register [7:0]

7 6 5 4 3 2 1 0

TXCMPLT RXM3IAK RXTHAK RXFAK RXCMPLTAK TXM3IAK TXTHIAK TXEIAK

Table 16-10 FIFO Interrupt Acknowledge Register Bit Descriptions


15:10 Reserved

9 TRGABORTIAK Target Aborted Interrupt Status Clear.Writing a 1 clears the Target Aborted Interrupt Status bit.

8 HSRESET Soft Reset. Writing a “1” resets the entire device. The action is equivalent to resetting the device via the RESET# pin, except the PCI configuration is not reset.

7 TXCMPLT TX DMA Transfer Complete.Writing a 1 sets the M821xx internal TXCMPLT Interrupt status bit after the current internal TX DMA operation is completed. This allows the external µP or PCI device to indicate “end-of-data-block” to the M821xx.

6 RXM3IAK RXMAIL3 Register Written Status Clear. Writing a 1 clears the RXMAIL3 Register Written Status bit (RXM3I).

5 RXTHAK RX_FIFO Exceeded Threshold Status Clear.Writing a 1 clears the RX_FIFO Exceeded Threshold Status bit (RXTH).

4 RXFAK RX_FIFO Full Status Clear.Writing a 1 clears the RX_FIFO Full Status bit (RXF).

3 RXCMPLTAK RX DMA Transfer Complete Status Clear.Writing a 1 clears the RX DMA Buffer Empty Interrupt Status bit (RXCMPLT).

2 TXM3IAK TXM3 Full Interrupt Status Clear.Writing a 1 clears the TXM3 Full Interrupt Status bit (TXM3I).

1 TXTHIAK TX_FIFO Less than Threshold Status Clear. Writing a 1 clears the TX_FIFO Less than Threshold Status bit (TXTH).

0 TXEIAK TX FIFO Empty Status. Writing a 1 clears the TX FIFO Empty Status bit (TXE).

M821xx Data Sheet


16.2.4 TX_FIFO Size[15:0] (Address 0x10, R)Current depth of the TX_FIFO in bytes:

16.2.5 TX_FIFO High Threshold[15:0] (Address 0x14, R/W)The high threshold value of the TX_FIFO. A TX_FIFO depth greater than this value will not cause an interrupt to occur to the external µP or PCI device.

16.2.6 TX_FIFO Low Threshold[15:0] (Address 0x18, R/W)The low threshold value of the TX_FIFO. A TX_FIFO depth less than this value will cause an interrupt to occur to the external µP or PCI device if enabled.

16.2.7 RX_FIFO Size[15:0] (Address 0x20, R)The current depth of the RX_FIFO. An RX_FIFO depth greater than this value will not cause an interrupt to occur to the external µP or PCI device.

16.2.8 RX_FIFO High Threshold[15:0] (Address 0x24, R/W)The high threshold value of the RX_FIFO. Exceeding this value will cause an interrupt to occur to the external µP or PCI device if enabled. The interrupt cannot be cleared until sufficient data has been removed from the FIFO by the external µP or PCI device to cause the size to be less than the threshold.

16.2.9 RX_FIFO Low Threshold[15:0] (Address 0x28, R/W)The low threshold value of the RX_FIFO. Exceeding this value will cause an interrupt to occur to the external µP or PCI device if enabled. The interrupt cannot be cleared until sufficient data has been removed from the FIFO by the external µP or PCI device to cause the size to be less than the threshold.

NOTE: For PCI DMA operations FIFO size is 512 bytes. For PCI – SDRAM Windowing Operations FIFO size is 256 bytes

M821xx Data Sheet


16.2.10 Bus Configuration [7:0] (Address 0x070, R/W)This register contains external µP or PCI device Bus Swap Enable settings for both 2 and 4 byte transfers.

16.2.11 RX_FIFO Data[15:0] (Address 0x100-0x7FF, R)Used to read data from the RX_FIFO. Read only. Writing to this register writes TX_FIFO Data.

16.2.12 TX_FIFO Data[15:0] (Address 0x100-0x7FF, W)Used to write data into the TX_FIFO. Write only. Reading this register returns RX_FIFO Data.

Table 16-11 Bus Configuration [7:0] Bit Descriptions


15:4 Reserved

3 Reserved

2 Bus Byte Swap Enable Bit 2 = 0, byte swapping is disabled. (default)Bit 2 = 1, byte swapping is enabled, as follows: For 2 bytes transfer:

bus high byte ↔ FIFO low byte bus low byte ↔ FIFO high byte

For 4 byte transfer:bus byte 0 ↔ FIFO byte 3bus byte 1 ↔ FIFO byte 2bus byte 2 ↔ FIFO byte 1bus byte 3 ↔ FIFO byte 0

1:0 Reserved

NOTE: For the Microprocessor (mP) Bus, the FIFO Read/Write Register is selected by the HBFIFO signal which can be connected to any external mP or PCI device Address Line above PCI_STOP#.The FIFO Read/Write Register supports a 2 KByte Address Range for DMA Controllers that need to increment or decrement the address for each data transfer.

NOTE: For the Microprocessor (mP) Bus, the FIFO Read/Write Register is selected by the HBFIFO signal which can be connected to any Address Line above PCI_STOP#.The FIFO Read/Write Register supports a 2KByte Address Range for DMA Controllers that need to increment or decrement the address for each data transfer.

M821xx Data Sheet


16.3 PCI Bus Configuration Registers and Allocation Maps Registers marked with (xxxx) have the power-on defaults listed. Registers marked with (xxxx-E) have power-on defaults which can be modified through the Configuration Pre-Load Interface. For un-implemented or reserved registers (shaded), the values in parenthesis are hard-wired, read only values.

Table 16-12 PCI Configuration Registers

31 24 23 16 15 8 7 0

00 Device ID (0150-E)(Refer to Table: PCI Device ID per Product.)

Vendor ID (18DC -E)(Refer to Table: PCI Device ID per Product.)

04 Status (0290) Command (0000 / 0004) See note below.

08 Class Code (078000) Revision ID (00)(Refer to Table: PCI Device ID

per Product.)

0C BIST (Not Implemented 00) Header Type (00-E) Latency Timer (00) Cache Line Size(Not Implemented 00)

10 Base Address Register 0 (BAR0) (00000000)



1C Base Address Register 3 (BAR3) (Not Implemented 00000000)

20 Base Address Register 4 (BAR4) (Not Implemented 00000000)

24 Base Address Register 5 (BAR5) (Not Implemented 00000000)

28 CardBus CIS Pointer (Not Implemented 00000000)

2C Subsystem ID (0150-E)(Refer to Table: PCI Device ID per Product.)

Subsystem Vendor ID (18DC -E)(Refer to Table: PCI Device ID per Product.)

30 Expansion ROM Base Address (Not Implemented 000000)

34 Reserved (000000) Cap_Ptr (40)

38 Reserved (00000000)

3C Max Latency (00-E) Min Grant (00-E) Interrupt Pin (01-E) Interrupt Line (FF)

40 Power Management Capabilities (0001-E) Next Capability Pointer (00) Capability ID (01)

44 Data (00-E) PMCSR_BSE(Not Implemented 00)

Power Management CSR (0000)

48 Pre-Load Control

4C Reserved

50 Reserved

NOTE: Bit 4 of the command register device’s ability to act as a master on the PCI bus. A value of 0 disables the device from generating PCI accesses. A value of 1 allows the device to behave as a bus master. As the device boots, this bit reflects the voltage level at the PCI_HOST# input, with the bit set with PCI_HOST# is low and cleared when PCI_HOST# is high. During runtime operations, when the M821xx is not the host, software may enable or disable this bit to achieve Master functionality.

PME Polarity Bit

M821xx Data Sheet


16.3.1 PCI Device IDsTable 16-13 PCI Device ID

16.3.2 Vendor ID RegisterVendor ID is a 16-bit field identifying the device manufacturer. The field is read only. The power-on default can be overwritten through the use of the Configuration Pre-Load Interface.

16.3.3 Device ID RegisterDevice ID is a 16-bit field that identifies the particular device. This identifier is allocated by the vendor. This field is read only. The power-on default can be overwritten through the use of the Configuration Pre-Load Interface.

16.3.4 Command RegisterThe command register controls a device’s basic PCI capabilities.

Product Device ID Vendor ID Revision ID Subsystem ID

Subsystem Vendor ID

M82104M82108M82152M82154M82170M82172M82174M82176M82190M82192M82194

0x0150 0x18DC 0x00 0x150 0x18DC

Table 16-14 Command Register [15:8]

15 14 13 12 11 10 9 8

Reserved Fast Back-to-Back Enable

System Error Enable

Table 16-15 Command Register [7:0]

7 6 5 4 3 2 1 0

Wait Cycle Enable

Parity Error Response.

VGA Palette Snoop Enable

Memory Write and Invalidate Enable

Special Cycle Recognition

Master Enable Memory Access Enable

I/O Access Enable

M821xx Data Sheet


16.3.5 Status RegisterThe status register monitors the progress of PCI events within the device. Status bits can be read and some can be cleared, but they cannot be set. Status bits are cleared by writing a 1 to that bit position. Writing a 0 to any status bit has no affect.

Table 16-16 Command register Bit Descriptions

Bit r/w/c Default Description

15:10 n/a n/a Reserved.

9 r 0 Fast Back-to-Back Enable.

8 r/w 0 System Error Enable. This bit is an enable bit for the SERR# driver. A value of 0 disables the SERR# driver. A value of 1 enables the SERR# driver.

7 r 0 Wait Cycle Enable. Not Supported.

6 r/w 0 Parity Error Response. This bit controls the device’s response to parity errors. When the bit is set, the device must take its normal action when a parity error is detected. When the bit is 0, the device must ignore any parity errors that it detects and continue normal operation.

5 r 0 VGA Palette Snoop Enable. Not Supported.

4 r 0 Memory Write and Invalidate Enable. Not Supported.

3 r 0 Special Cycle Recognition. Not Supported.

2 r/w 0 Master Enable. Controls a device’s ability to act as a master on the PCI bus. A value of 0 disables the device from generating PCI accesses. A value of 1 allows the device to behave as a bus master. As the device boots, this bit reflects the voltage level at the PCI_HOST# input, with the bit set with PCI_HOST# is low and cleared when PCI_HOST# is high. During runtime operations, when the M821xx is not the host, software may enable or disable this bit to achieve Master functionality.

1 r/w 0 Memory Access Enable. Controls a device’s response to Memory Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to Memory Space accesses.

0 r/w 0 I/O Access Enable. Controls a device’s response to I/O Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to I/O Space accesses.

Table 16-17 Status Register [15:8]

15 14 13 12 11 10 9 8

Detected Parity Error

Signaled System Error

Received Master Abort

Received Target Abort

Signaled Target Abort

Device Select Timing Data Parity Reporting

Table 16-18 Status Register [7:0]

7 6 5 4 3 2 1 0

Fast Back-To-Back Capable

UDF Supported

66 MHz Capable

Capabilities List

Reserved

M821xx Data Sheet


16.3.6 Revision ID RegisterRevision ID is an 8-bit field that specifies a device specific revision identifier. This value is chosen by the vendor (zero is acceptable). This field should be viewed as a vendor defined extension to the Device ID.

16.3.7 Class Code RegisterClass Code is a 24-bit field with three 8-bit sub-fields. The upper byte is a base class code. The middle byte is a sub-class code. The lower byte specifies any register-level programming interface that may exist.

The hard-wired default value: 0x078000

• Base Class Code: 07 = simple communications controller• Sub Class Code: 80 = “other”• Prog I/F: 00 = none

Table 16-19 Status Register Bit Descriptions

Bit r/w/c Default Description

15 r/c 0 Detected Parity Error. This bit must be set by the device whenever it detects a parity error, even if parity error handling is disabled (as controlled by bit 6 in the Command register).

14 r/c 0 Signaled System Error. This bit must be set whenever the device asserts SERR#. Devices who will never assert SERR# do not need to implement this bit.

13 r/c 0 Received Master Abort. This bit must be set by a master device whenever its transaction (except for Special Cycle) is terminated with Master-Abort. All master devices must implement this bit.

12 r/c 0 Received Target Abort. This bit must be set by a master device whenever its transaction is terminated with Target-Abort. All master devices must implement this bit.

11 r 0 Signaled Target Abort. Not supported.

10-9 r 01 Device Select Timing. These bits encode the timing of DEVSEL#. These are encoded as 00 for fast, 01 for medium, and 10 for slow (11 is reserved.) These bits are read only and must indicate the slowest time that a device asserts DEVSEL# for any bus command except Configuration Read and Configuration Write.

8 r/c 0 Data Parity Reporting. This bit is only implemented by bus masters. It is set when three conditions are met: 1) the bus agent asserted PERR# itself or observed PERR# asserted; 2) the agent setting the bit acted as the bus master for the operation in which the error occurred; and 3) the Parity Error Response bit (Command Register) is set.

7 r 1 Fast Back-To-Back Capable.

6 r 0 UDF Supported. Not supported.

5 r 0 66 MHz Capable. Not supported.

4 r 1 Capabilities List. Indicates that an extended capabilities list exists and is pointed to by the cap_ptr field at configuration offset 0x34. All 3 functions include a power management capabilities list. Read only.

3-0 r 0 Reserved.

M821xx Data Sheet


16.3.8 Latency Timer RegisterThe Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. This register has 5 read/write bits (MSBs) plus 3 bits of hard-wired zero (LSBs). The Latency Timer Register is loaded into the PCI Latency counter each time FRAME# is asserted to determine how long the master is allowed to retain control of the PCI bus. This register is loaded by system software. The default value for Latency Timer is 00.

16.3.9 Header Type RegisterHeader type is an 8-bit field that identifies the layout of the configuration space. Bit 7 of this field is used to identify a multifunction device (when set to 1). The Header type values default to 00 at power up, which represents a single-function system. They can then be loaded through the Configuration Pre-Load Interface.

16.3.10 Base Address RegistersSystem software can determine how much address space the device requires by writing a value of all 1’s to the register and then reading the value back. The device will return 0’s in all don’t care address bits, effectively specifying the address space required. Unimplemented base address registers are hard-wired to read all 0’s, indicating that no memory allocation is required.

Function 0 implements a single base address register (BAR0). Bits 10:0 are always tied to zero indicating that 2048 bytes of memory-mapped address space are required. The power-up default for this register is 0x00000000000.

Function 1 implements a single base address register (BAR1). Bits 15:0 are tied to zero by default indicating that 64 KB of memory-mapped address space are required. The HMB size mask register 1 can be programmed to change the memory mapping size. The power-up default for this register is 0x00000000000.

Function 2 implements a single base address register (BAR2). Bits 15:0 are tied to zero by default indicating that 64 KB of memory-mapped address space are required. The HMB size mask register 2 can be programmed to change the memory mapping size. The power-up default for this register is 0x00000000000.

16.3.11 Subsystem Vendor ID RegisterHolds the Subsystem Vendor ID, which is obtained from PCI SIG. This register loads defaults at reset and can then be loaded through the Configuration Pre-Load Interface.

16.3.12 Subsystem ID RegisterHolds the Subsystem ID as defined by the Subsystem Vendor. This register loads defaults at reset and can then be loaded through the Configuration Pre-Load Interface.

16.3.13 Cap_Ptr RegisterContains the byte offset from the beginning of the configuration header to the first Capability ID defined in the configuration header. This register defaults to 0x40 at reset.

M821xx Data Sheet


16.3.14 Interrupt Line RegisterIndicates which of the available system interrupts (1 of 8) the respective function has been routed. This register defaults to 0xFF, which indicates that the function’s interrupt has not been routed to the system. Configuration software will write the appropriate value to this register.

16.3.15 Interrupt Pin RegisterIndicates which of the physical interrupt pins (A through D) this function will use. This is a read only register. For function 0, this register defaults to 0x01 (INITA). It can be modified through the Configuration Pre-Load Interface.

16.3.16 Min Grant RegisterThis read only register indicates how long a master device would like to retain PCI ownership whenever it is the initiator of a transaction. It specifies increments of 250ns. This register defaults to 0x00. It can then be loaded through the Configuration Pre-Load Interface.

16.3.17 Max Latency RegisterThis read only register indicates how often the device needs access to the PCI bus, in 250nS units. This register defaults to 0x00 for all functions. It can then be loaded through the Configuration Pre-Load Interface.

16.3.18 Capability ID RegisterThis register identifies the type of capability described by the Capabilities List Data Structure pointed to by the Cap_Ptr register. This register is hard wired to 0x01 to indicate PCI Power Management.

16.3.19 Next Capability Pointer RegisterThis register points to the next Capabilities List Data Structure. It is set to 0x00 to indicate that no further structures exist in the configuration space.

16.3.20 Data RegisterThe read only Data register is used to report state dependent operating data such as power consumed or heat dissipation. When the host writes a selection to the Data_Select bits of the CSR, the function responds by placing appropriate information into the Data_Scale CSR bits and into the Data register.

M821xx Data Sheet


16.3.21 PME Polarity Control RegisterBit 0 controls the PME# output drive state.

Table 16-20 PME Polarity Control Register [15:8]

7 6 5 4 3 2 1 0

Reserved PME Polarity

Table 16-21 PME Polarity Control Register [7:0]

Bits r/w/c/s Default Description

7:1 0 Reserved.

0 r/w 0 PME Polarity.0 = Open-drain, active low.1= Always driven, active high. This bit is writable only when in the Configuration Space Pre-Load mode.

r = readable, w = writable, c = clearable by writing a 1, s =’sticky’

M821xx Data Sheet


16.4 HMB Interface Registers (Including HICORE Host Side Register)

This block enables an external PCI master to access M821xx memory directly. The HMB block interfaces the IDMA on one side and the PCI block on the other side.

The HMB interface has 2 FIFOs of 256 Bytes in it, one for each direction, which holds the data until it’s written to the memory or to the external master.

This block supports two configured base address and address ranges and the base address are mapped to the Base Address Registers (BAR1 and 2) in the PCI configuration space, therefore any address on the PCI can be mapped to any address in the memory with suitable configuration (unlike in the APBB block).

In this mode, the M821xx operate as slave only.

The HMB interface block supports burst and non-burst transactions.


Table 16-22 HMB Interface Registers (Including HICORE Host Side Register)

APB Addr. Base 0x10010000

Offset Register(Read) Register(Write)

0xD000 FIFO Control FIFO Control

0xD008 HCSM BIST Control Register HCSM BIST Status Register

0xE000 HMB TX FIFO Data Byte Mode HMB RX FIFO Data, Byte Mode

0xE100 HMB TX FIFO Data 16 bit Mode HMB RX FIFO Data, 16 Bit Mode

0xE200 HMB TX FIFO Data 32 bit Mode HMB RX FIFO Data, 32 Bit Mode

0xF000 Reserved Reserved

0xF004 HMB Mode Control HMB Mode Control

0xF008 HMB Status HMB Interrupt Ack

0xF00C HMB Interrupt Control HMB Interrupt Control

0xF010 PCI Base Address1

0xF014 System Base Address1 System Base Address1

0xF018 Size Mask1 Size Mask1

0xF020 PCI Base Address2

0xF024 System Base Address2 System Base Address2

0xF028 Size Mask2 Size Mask2

0xF030 Reserved (read only)



M821xx Data Sheet


0xF03C N/A Reserved (write-only)

0xF040 PCI Arbiter Control PCI Arbiter Control

Table 16-22 HMB Interface Registers (Including HICORE Host Side Register) (Continued)

APB Addr. Base 0x10010000

M821xx Data Sheet


16.4.1 HMB FIFO Interface Registers (ARM Processor Side Control)

16.4.1.1 HMB Control Register (read/write)Table 16-23 HMB Controll


0xD000 default 0x0

0-1 Reserved



4 Reserved









13 RXFF_RES Setting this bit to a “1” will reset the TX_FIFO “read” and “write” pointers.

14 REQIOEN_N When ‘1’ enable RX and TX requests observed through general purpose I/O6&7


M821xx Data Sheet


16.4.1.2 Memory BIST Register (Read/Write)Table 16-24 Memory BIST

16.4.1.3 HMB TX FIFO Data Byte Mode – Read onlyTable 16-25 HMB TX FIFO Data Byte Mode - Read


0xD008

0 RXBIST_RESET Active Low. Reset BIST controller.

1 RXBIST_TEST Starts BIST controller

2 RXBIST_DEBUG 1: Debug mode 0: Normal mode

3 RXBIST_RESUME_RETN Resume BIST after required retention time has elapsed.Write operation: During write, this signal should produce a single clock cycle ‘high’ pulseRead operation: During read, the value should always be a ‘low’

4 RXBIST_DONE Read-only. BIST completed

5 RXBIST_FAIL Read-only. Pass/fail during normal mode; During debug mode – this indicates when there is a fail and failure data is shifted out through Bist_debug_out signal.

6 RXBIST_START_RETN Read-only. Indicates start of retention time

7 Reserved

8 TXBIST_RESET Active Low. Reset BIST controller.

9 TXBIST_TEST Starts BIST controller

10 TXBIST_DEBUG 1: Debug mode 0: Normal mode

11 TXBIST_RESUME_RETN Resume BIST after required retention time has elapsed.Write operation: During write, this signal should produce a single clock cycle ‘high’ pulseRead operation: During read, the value should always be a ‘low’

12 TXBIST_DONE Read-only. BIST completed

13 TXBIST_FAIL Read-only. Pass/fail during normal mode; During debug mode – this indicates when there is a fail and failure data is shifted out through Bist_debug_out signal.

14 TXBIST_START_RETN Read-only. Indicates start of retention time

15 Reserved


0xE000 – 0xE0FF

0-7 HMB TX FIFO Data Transmitting FIFO data from host to device. Support burst read

M821xx Data Sheet


16.4.1.4 HMB RX FIFO DATA Byte Mode – Write onlyTable 16-26 HMB RX FIFO Data Byte Mode - Write

16.4.1.5 HMB TX FIFO Data 16 Bit Mode – Read onlyTable 16-27 HMB TX FIFO Data 16 Bit Mode - Read Only

16.4.1.6 HMB RX FIFO DATA 16 Bit Mode – Write onlyTable 16-28 HMB RX FIFO Data 16 Bit Mode

16.4.1.7 HMB TX FIFO Data 32 Bit Mode – Read onlyTable 16-29 HMB TX FIFO Data 32 Bit Mode - Read only

16.4.1.8 HMB RX FIFO DATA 32 Bit Mode – Write onlyTable 16-30 HMB RX FIFO Data 32 Bit Mode - Write Only


0xE000 – 0xE0FF

0-7 HMB RX FIFO Data Receiving FIFO data from device back to host. Support burst read


0xE100 – 0xE1FF



0xE100 – 0xE1FF



0xE200 – 0xE2FF



0xE200 – 0xE2FF


M821xx Data Sheet


16.4.2 HBM Mode Control

16.4.3 HMB Status

16.4.4 HMB Interrupt Control

Table 16-31 HMB Mode Control


0xF004 HMB Mode Control (read/write) default 0x50

1~0 READ PREFETCH SIZE Allow HDMA burst read prefetch max length.00: 4 words01: 8 words10: 16 words11: 32 words

2 PROGRAMIO 0: HMDMA1: Reserved for testing

3 TIMEOUT IMPORTANT!: Defaults to 0 on reset but must always be set to 1 on initialization.

7~4 Reserved

31~8 Reserved

Table 16-32 HMB Status


0xF008 HMB Status (read/write) default 0x00000000

0 Retry/Disconnect PCI retry or disconnect activities, Writing 1 will clear status

1 System Error PCI write with non contiguous byte enable, Writing 1 will clear status

14~2 Reserved

15 Retry/Disconnect Counter reset Writing 1 will clear counter

31~16 Retry/Disconnect Counter Monitor PCI retry or disconnect activitiesFree running counter

Table 16-33 HMB Interrupt Control


0xF00C HMB Interrupt Control (read/write) default 0x00

0 Retry/Disconnect PCI retry or disconnect interrupt enable

1 System Error PCI system error interrupt enable

31~2 Reserved

M821xx Data Sheet


16.4.5 PCI Base Address1/PCI Base Address2

16.4.6 System Base Address 1/ System Base Address2

16.4.7 Size Mask 1 / Size Mask 2

16.4.8 PCI Arbiter Control

Table 16-34 PCI Base Address1/PCI Base Address2


0xF010/0xF020 PCI Base Address 1 and 2 (read only) default 0x00

0~11 Reserved

12~31 PCI Base Address PCI memory base address for window mapping

Table 16-35 System Base Address1/System Base Address2


0xF014/0xF024 System Base Address 1 and 2 (read/write) default 0x00

0~11 Reserved

12~31 System Base Address System memory base address for window mapping. System base memory address must be aligned on 4KB boundary.

Table 16-36 Size Mask1/Size Mask2


0xF018/0xF028 Size Mask 1 and 2 (read/write) default 0xFFFF0000

0~11 Reserved

12~31 Size Mask Define the number of bits that the PCI Bridge allows to be writable during PCI configuration. After Setup Size Mask Register, PCI host needs to do PCI configuration. Min size is 4KB.

Table 16-37 PCI Arbiter Control


0xF040 PCI Arbiter Control (read/write) default 0xFF00

0 Priority Scheme 0: Round Robin; 1: Priority. Port 0 has highest priority. Port 5 has lowest priority.

5~1 Request Enable Request enable for port 5 ~ port 1. Default: 00. Port 0 is always enabled.

7~6 Reserved

15~8 Aging Aging Period for all requests. Default: FF

31~16 Reserved

M821xx Data Sheet


16.5 APB Accessible RegistersThese regisers control the data path from the ARMs to the PCI Bus. This interfaces the AHB bus from one side and muxed with HICORE interface to the PCI block on the other side. Configuration and registers read/writes are done through the APB bus.

Setting up these registers allows the ARMs to perform a single transaction on the AHB, which will translate into a maximum of 2 burst transaction on the PCI Bus.

The ARMs can do from a Dword transaction to a byte transaction, which will be translated into 2 word transaction to a byte transaction on the PCI Bus. Only when the read or the write transaction is done, the ARM can issue the next transaction.

These registers actually enable the ARMs to do a master transaction on the PCI. However the address the ARM issues is the address, which will be driven on the PCI Bus, therefore since the address space to access this block is 0x40000000 to 0x4FFFFFFF, the PCI slave being accessed must be configured to responsd to this range of address.

NOTE: Register AB address sub-range 0x0000 – 0x0068 is repeating within the range 0x0000 – 0x3FFF

Table 16-38 APB Accessible Registers

APB Address Register(Read) Register(Write)

0x04000-4FFF APB TX FIFO Data Byte Mode APB RX FIFO Data, Byte Mode

0x08000-8FFF APB TX FIFO Data 16 bit Mode APB RX FIFO Data, 16 Bit Mode

0x0C000-CFFF APB TX FIFO Data 32 bit Mode APB RX FIFO Data, 32 Bit Mode

0x0000 APB FIFO Control APB FIFO Control

0x0004 APB FIFO Interrupt Status APB FIFO Interrupt Acknowledge

0x0008 APB BIST Control Register APB BIST Status Register

0x0014 APB TX FIFO Size Reserved

0x0018 APB TX FIFO High Threshold APB TX FIFO High Threshold

0x001C APB TX FIFO Low Threshold APB TX FIFO Low Threshold

0x0024 APB RX FIFO Size Reserved

0x0028 APB RX FIFO High Threshold APB RX FIFO High Threshold

0x002C APB RX FIFO Low Threshold APB RX FIFO Low Threshold

0x0030 TX Mail0 Reserved



0x003C TX Mail3 Reserved

0x0040 RX Mail0 RX Mail0


M821xx Data Sheet


16.5.1 APB TX FIFO Data Byte Mode – Read onlyTable 16-39 APB TX FIFO Data Byte Mode

16.5.2 APB RX FIFO DATA Byte Mode – Write onlyTable 16-40 APB RX FIFO Data Byte Mode

16.5.3 APB TX FIFO Data 16 Bit Mode – Read onlyTable 16-41 APB TX FIFI Data 16 Bit Mode


0x004C RX Mail3 RX Mail3

0x0050 PCI DMA Engine Interface Control PCI DMA Engine Interface Control

0x0054 PCI DMA Engine Interface Status Reserved

0x0060 PCI TX/RX DMA Starting Address PCI TX/RX DMA Starting Address

0x0064 PCI TX/RX DMA Transfer Burst Size PCI TX/RX DMA Transfer Burst Size

0x0068 PCI TX/RX DMA Transfer Length PCI TX/RX DMA Transfer Length

0x0100 APBB Interrupt Enable APBB Interrupt Enable

0x0104 APBB Interrupt Status APBB Interrupt Status

0x0108 APBB Control APBB Control


0x04000 - 4FFF

0-7 APB TX FIFO Data Transmitting FIFO data from host to device. Support burst read


0x04000 - 4FFF

0-7 APB RX FIFO Data Receiving FIFO data from device back to host. Support burst read


0x08000 - 8FFF


Table 16-38 APB Accessible Registers (Continued)

M821xx Data Sheet


16.5.4 APB RX FIFO DATA 16 Bit Mode – Write onlyTable 16-42 APB RX FIFO DATA 16 Bit ode

16.5.5 APB TX FIFO Data 32 Bit Mode – Read onlyTable 16-43 APB TX FIFO DATA 32 Bit Mode

16.5.6 APB RX FIFO DATA 32 Bit Mode – Write onlyTable 16-44 APB RX FIFO DATA 32 Bit Mode

16.5.7 APB FIFO Control Register – Read / WriteNote: The Interrupt Enables described in this register only control interrupt event to the ARM processors. They have no effect on status register offset 0x4.


0x08000 - 8FFF



0x0C000 - CFFF



0x0C000 - CFFF


M821xx Data Sheet


Table 16-45 APB FIFO Control Register


0x00 Default 0x8

0-1 Reserved



4 Reserved








12 TXFF_RES Setting this bit to a “1” will generate one-clock duration reset pulse to TX_FIFO “read” and “write” pointers. Should allow about 10 ARM or HOST clock cycles, whichever slower , before any attempt writing to the FIFO.

13 RXFF_RES Setting this bit to a “1” will generate one-clock duration reset pulse to RX_FIFO “read” and “write” pointers. Should allow about 10 ARM or HOST clock cycles, whichever slower , before any attempt writing to the FIFO.

14 REQIOEN_N When ‘1’ enable RX and TX requests observed through general purpose I/O6&7


16 TFOVURIE TX FIFO Overflow or Under-run Interrupt Enable.

17 RFOVURIE RX FIFO Overflow or Under-run Interrupt Enable.

M821xx Data Sheet


16.5.8 APB FIFO Interrupt Status Register – Read onlyTable 16-46 APB FIFO Interrupt Status Regiter.

16.5.9 APB FIFO Interrupt Acknowledge Register – Write onlyTable 16-47 APB FIFO Interrupt Acknowledge Register


0x04 Default 0xC

0 TXF The TX FIFO is full.

1 TXTH The TX FIFO depth is greater than the threshold value.

2 RXE The RX FIFO is empty.

3 RXTH The RX FIFO depth is less than the threshold value.

4 RXM3I The Host has acknowledged an RXM3 FULL interrupt from the RX MAIL3 Register.

5 TXM3I The Host has written data to the TX MAIL3 Register.

6 TXCMPLT TX COMPLETED bit set by Host side s/w or h/w (in target mode).

9-15 Reserved

16 TFOVURI TX FIFO is overflow or under-run interrupt.

17 RFOVURI RX FIFO is overflow or under-run interrupt.


0x04

0 TXFIAK Writing a “1” Clears the corresponding interrupt status bit.

1 TXTHIAK Writing a “1” Clears the corresponding interrupt status bit.

2 TXM3IAK Writing a “1” Clears the corresponding interrupt status bit.

3 Reserved

4 RXEIAK Writing a “1” Clears the corresponding interrupt status bit.

5 RXTHIAK Writing a “1” Clears the corresponding interrupt status bit.

6 RXM3IAK Writing a “1” Clears the corresponding interrupt status bit.

7 FLUSH_RX Writing a “1” will trigger the HBREQR signal without reaching the threshold.

8 SRESET Soft Reset. Writing a “1” resets the entire device. The action is equivalent to resetting the device via the power-on reset pin.

9 TXCMPLTIAK Writing a “1” Clears the corresponding interrupt status bit.

16 TFOVIAK Writing a “1” Clears the corresponding interrupt status bit.

17 RFURIAK Writing a “1” Clears the corresponding interrupt status bit

12-15 Reserved

M821xx Data Sheet


16.5.10 BIST Status Register – Read / WriteTable 16-48 BIST Status Register

16.5.11 APB TX FIFO Size – Read onlyTable 16-49 APB TX FIFO Size


0x08 Default 0x0

0 RXBIST_RESET Active Low. Reset BIST controller.

1 RXBIST_TEST Starts BIST controller

2 RXBIST_DEBUG 1: Debug mode 0: Normal mode

3 RXBIST_RESUME_RETN Resume BIST after required retention time has elapsed.Write operation: During write, this signal should produce a single clock cycle ‘high’ pulseRead operation: During read, the value should always be a ‘low’

4 RXBIST_DONE Read-only. BIST completed

5 RXBIST_FAIL Read-only. Pass/fail during normal mode; During debug mode – this indicates when there is a fail and failure data is shifted out through Bist_debug_out signal.

6 RXBIST_START_RETN Read-only. Indicates start of retention time

7 reserved

8 TXBIST_RESET Active Low. Reset BIST controller.

9 TXBIST_TEST Starts BIST controller

10 TXBIST_DEBUG 1: Debug mode 0: Normal mode

11 TXBIST_RESUME_RETN Resume BIST after required retention time has elapsed.Write operation: During write, this signal should produce a single clock cycle ‘high’ pulseRead operation: During read, the value should always be a ‘low’

12 TXBIST_DONE Read-only. BIST completed

13 TXBIST_FAIL Read-only. Pass/fail during normal mode; During debug mode – this indicates when there is a fail and failure data is shifted out through Bist_debug_out signal.

14 TXBIST_START_RETN Read-only. Indicates start of retention time

15 reserved


0x14

0-15 APB TX FIFO Size The current depth of the transmitting FIFO.

M821xx Data Sheet


16.5.12 APB TX FIFO High Threshold – Read / WriteTable 16-50 APB TX FIFO High Threshold

16.5.13 APB TX FIFO Low Threshold – Read / WriteTable 16-51 APB TX FIF Low Threshold

16.5.14 APB RX FIFO Size – Read onlyTable 16-52 APB RX FIFO Size


0x18 Default 0x180

0-15 APB TX FIFO High Threshold The programmed value can’t be greater 0x1FE. The high threshold value of the TX FIFO. A TX FIFO depth greater than this value will cause an interrupt to the ARM if enabled. This value can also be used to control the internal DMA request line. The internal DMA can be used to empty the FIFO. Once the FIFO depth is below the low threshold the DMA request line is de-asserted. If the DMA threshold feature is active, then the DMA request signal will not be asserted until the HOST has written enough data so that the depth of the TX FIFO is greater than the high threshold. This value can’t be greater than 0x1FE


0x1C Default 0x40

0-15 APB TX FIFO Low Threshold Programmed value can’t be less than 0x18. The low threshold value of the TX FIFO. A TX FIFO depth below this value will cause an interrupt to occur to the ARM if enabled. This value can also be used to control the internal DMA request line. The ARM DMA can be used to flush the RX FIFO. Once the FIFO depth is below the low threshold the DMA request signal is de-asserted. If the DMA threshold feature is active, then the DMA request signal will not be reasserted until the Host has filled enough data so that the depth of the FIFO is more than the high threshold. Reading returns the last value written.


0x24 Default 0x0

0-15 APB RX FIFO Size The current depth of the receiving FIFO.

M821xx Data Sheet


16.5.15 APB RX FIFO High Threshold – Read / WriteTable 16-53 APB RX FIFO High Threshold

16.5.16 APB RX FIFO Low Threshold – Read / WriteTable 16-54 APB RX FIFO Low Threshold


0x28 Default 0x1CE

0-15 APB RX FIFO High Threshold Programmed value can’t be greater than 0x1F8. Once the FIFO depth is more than the high threshold the DMA request signal is de-asserted. Reading returns the last written value


0x2C Default 0x40

0-15 APB RX FIFO Low Threshold Programmed value can’t be less than 0x8. The low threshold value of the RX FIFO. ARX FIFO depth below this value will cause an interrupt to occur to the ARM if enabled. This value can also be used to control the internal DMA request line. The ARM DMA can be used to fill the RX FIFO. Once the FIFO depth is more than the high threshold the DMA request signal is de-asserted. If the DMA threshold feature is active, then the DMA request signal will not be reasserted until the Host has removed enough data so that the depth of the FIFO is less than the low threshold. Reading returns the last value written.

M821xx Data Sheet


16.5.17 PCI DMA Engine Interface Control Register – Read / WriteNote: The Interrupt Enables described in this register only control interrupt event to the ARM processors. They have no effect on status register offset 0x54.

Table 16-55 PCI DMA Engine Interface Control Register


0x50 Default 0x00038

0 MMEMIO Master Mode Memory Transfer Mode 1 = memory, 0 = I/O

1 DMATXRXEN Bus Master Engine Mode DMA Enable. Auto-cleared after transfer completion

2 DMATXRX_N DMA Transfer Direction, 1: transmit 0: receive

3 TBURSTEN In target mode, must be high to enable burst mode. If set to 0 transfer will be terminated after first data phase. Must be set high for proper operation of PCI bridge.

4 LATTMR Disable latency timer; continue to assert request.

5 M_REQLAST Enable master to request PCI bus till last data cycle of a burst.

6 T_STOP_EN Enable Target Stop mode operation. Revision 1 addition

7 Reserved

8 IOACCENIE I/O Access Enable Interrupt Enable

9 MEMACCENIE Memory Access Enable Interrupt Enable

10 MSTRENIE Master Enable Interrupt Enable

11 RXTRGABRTIE RX Target Abort Interrupt Enable

12 RXMSTRABRTIE RX Master Abort Interrupt Enable

13 SYSERRORIE Signaled System Error Interrupt Enable

14 PARERRORIE Detected Parity Error Interrupt Enable

15 XFERDNIE Transfer Completed Interrupt Enable (in master mode)

16 RETRYIE In master mode if trans. end w/ Retry or Disconnect Interrupt Enable

17 XFERREADYIE After transfer completion or cancellation master mode is ready IRQ Enable

18 XFERCYCEN In Host mode allows Monet to send PCI configuration cycles to PCI bus.

19 XFERCYCTYPE If bit 18 is enable:0: Type 0, configure devices on PCI bus connected to Monet.1: Type 1, configure devices in other PCI bus behind the bridge(s).(Please refer to PCI spec 2.1 page 87 for further details.)

20-31 Reserved

M821xx Data Sheet


16.5.18 PCI DMA Engine Interrupt Status & Bus Status Register - Read onlyTable 16-56 PCI DMAEngine Interrupt Status & Bus Status Register


0x54

0 IOACCEN I/O Access Enable Detected

1 MEMACCEN Memory Access Enable Detected

2 MSTREN Master Enable Detected

3 RXTRGABRT RX Target Abort Detected

4 RXMSTRABRT RX Master Abort Detected

5 SYSERROR Signaled System Error Detected

6 PARERROR Detected Parity Error Detected

7 XFERDN DMA Transfer Done Detected

8 RETRY Retry Status Detected

9 XFERREADY Transfer Ready Detected

10-15 Reserved

16 IOACCEN I/O Access Enable Status for polling

17 MEMACCEN Memory Access Enable Status for polling

18 MSTREN Master Enable Status for polling

19 RXTRGABRT RX Target Abort Status for polling

20 RXMSTRABRT RX Master Abort Status for polling

21 SYSERROR Signaled System Error Status for polling

22 PARERROR Detected Parity Error Status for polling

23 RETRY Retry Status for polling

24 XFERREADY Transfer Ready Status for polling

25-31 Reserved

M821xx Data Sheet


16.5.19 PCI DMA Engine Interface Interrupt Acknowledge Register - Write onlyTable 16-57 PCI DMA Engine Interface Interrupt Acknowledge Register

16.5.20 PCI TX/RX DMA Starting Address – Read / WriteTable 16-58 PCI TX/RX DMA Starting Address

16.5.21 PCI TX/RX Transfer Burst Size – Read / WriteTable 16-59 PCI TX/RX Transfer Burst Size


0x54

0 IOACCENIAK Clearing I/O Access Enable Interrupt Status bit

1 MEMACCENIAK Clearing Memory Access Enable Interrupt Status bit

2 MSTRENIAK Clearing Master Enable Interrupt Status bit

3 RXTRGABRTIAK Clearing RX Target Abort Interrupt Status bit

4 RXMSTRABRTIAK Clearing RX Master Abort Interrupt Status bit

5 SYSERRORIAK Clearing Signaled System Error Interrupt Status bit

6 PARERRORIAK Clearing Detected Parity Error Interrupt Status bit

7 XFERDONEIAK Clearing Transfer Done Interrupt Status bit

8 RETRYIAK Clearing Retry Status Interrupt Status bit

9 XFERREADYIAK Clearing Transfer Ready Interrupt Status bit

8-31 Reserved


0x60 Default 0x0

0-31 DMASTRTADDR Master mode PCI memory starting address.


0x64 Default 0x0

0-9 DMAXFERBSZ Master mode PCI burst size in increment of PCI data cycles.

M821xx Data Sheet


16.5.22 PCI TX/RX DMA Transfer Length – Read / WriteTable 16-60 PCI TX/RX DMA Transfer Length

16.5.23 APBB Interrupt Enable – Read / WriteTable 16-61 APBB Interrupt Enable

16.5.24 APBB Interrupt Status – Read OnlyIn order to clear the status bit, a ‘1’ need to be written to it.

These interrupts mark events that happened only when the APBB was working.

Table 16-62 APBB Interrupt Status


0x68 Default 0x0

0-15 DMAXFERLEN Master mode DMA transfer length in byte.


0x100 Default 0x0

5-31 Reserved Not Used.

4 RETRYINT_EN Retry interrupt enable.

3 PRTYINT_EN Parity error interrupt enable.

2 RSVD Rreserved

1 MASTRABTINT_EN Master abort interrupt enable.

0 TRGABTINT_EN Target abort interrupt enable.


0x104 Default 0x0


4 RETRYINT_STAT Retry interrupt status.

3 PRTYINT_STAT Parity error interrupt status.

2 RSVD Reserved

1 MASTRABTINT_STAT Master abort interrupt status.

0 TRGABTINT_STAT Target abort interrupt status.

M821xx Data Sheet


16.5.25 APBB Control – Read / WriteTable 16-63 APBB Control


0x108 Default 0xE


3 MEMIO When set, memory address. When reset, I/O address.

2 LATTMR Disable latency timer for PCI transactions.

1 REQLAST Assert request signal until end of transaction.

0 APBB_EN APBB block enable.

.


17.0 IPSec Engine

The IPSec Engine provides cryptograhic functionality. It accelerates IPSec protocol processing by combining hash and ciphering engines, a special purpose DMA engine, Encapulating Security Payload (ESP) / Authentication Header (AH) packet processing logic, and interrupt mitigation. The M821xx hardware architecture provides direct access to the IPSec Engine’s slave interface, thus supporting software control of the raw cryptograhic mode.

For a view of the IPSec Engine within the top-level block diagram, see Figure 2-1.

17.1 Features• AES-CBC mode cipher. 128, 192, 256 bit key sizes

• DES-CBC mode cipher. 56 and 168 bit (3DES) key sizes

• HMAC-MD5 mode hash

• HMAC-SHA1 mode hash

• HMAC-SHA256 mode hash

• Raw hashing modes: MD5, SHA-1, SHA-256

• AH mode processing

• ESP mode processing

• Transport mode processing

• Tunnel mode processing

• IPv4 processing

• Extended Sequence Numbers

• DDT based packet memory architecture

• SA bundles and nested tunnels are not handled explicitly by the hardware. They may be constructed by sequencing the same packet through the EAOE multiple times via software

• Provides 64 entries long (per IN/OUT direction) control FIFOs holding multiple configurations to be written to IPSEC configurations registers

• Provides 64 entries long (per IN/OUT direction) status FIFOs holding multiple status reads from IPSEC status registers

• ARM interrupt mitigation

• Allows access to slave interface, in order to support software-controlled raw cryptographic mode

M821xx Data Sheet


17.2 Functional DescriptionAs shown in Figure 17-1, the IPsec Engine consists of an Offload Interface and an Encapsulating Security Payload / Authentication Header core (ESP/AH).

The IPsec Engine bridges the gap between raw cryptographic offload and complete IPsec offload. By combining hash and ciphering engines, a special purpose DMA engine, and ESP/AH packet processing logic, the IPsec engine allows of the all mathematically intensive IPsec operations to be offloaded from the host ARM processor. With the Offload Interface, host processor responsibilities are minimized.

Figure 17-1 IPsec Engine Operations Overview

IPsec Engine

ARMHost Processor

AHB Master Port

AHB Master Slot

DDR2SDRAM Interface

AHB Slave Port

AHB Slave Slot

AHB Bus

External System Memory

SADs

DDTs

Incoming/OutgoingPackets

AHB Master Slot

AHB Slave Slot

AHB Slave Port

Registersand

FIFOs

IPsec Engine

Offload Interface ESP/AH

Security Resource Manager and

Security Module

AHB Slave Port

AHB Master Port

LoopProcess

M821xx Data Sheet


The IPsec Engine works to en-crypt and de-crypt, as well as peform authentication processing for streams of packets moving both in and out of the M821xx device simultaneously. In all, 17 standard algorithms are supported. These include:

• AH-SHA-1

• AH MD5

• ESP DES/NULL

• ESP DES/SHA-1

• ESP 3DES/MD5

• ESP 3DES/NULL

• ESP 3DES/SHA-1

• ESP 3DES/MD5

• ESP AES128/NULL

• ESP AES128/SHA-1

• ESP 3DES/NULL

• ESP 3DES/SHA-1

• ESP 3DES/MD5

• ESP AES128/NULL

• ESP AES128/SHA-1

• ESP AES256/MD5

The system memory external to the M821xx holds both the Security Association Database (SAD) defining the algorithm and the packets prior to and subsequent to being processed by the IPsec core. The host is responsible for setting up the SAD with the proper parameters. Entries in the SAD will be updated on a per packet basis as packets are processed by the inbound and outbound processing engines. The host dispatches packets to the inbound or outbound engines by writing to IPsec Engine registers which point to the packets in memory and the corresponding SAD pointer. The IPsec Engine will then respond with status codes indicating successful operation or various error conditions.

Raw cryptographic operations are supported through direct host access to the cryptographic engines. A resource manager handles the allocation of cryptographic resources. The host must request and release cryptographic resources exclusively through this manager. Use of cryptographic resources directly by the host will, of course, impact any concurrent packet processing throughput.

The offload interface allows the ARM processeor to setup up to 64 packets for processing (per IN/OUT direction), and then frees the processor, as it programs the ESP/AH core for each packet’s configurations, polls the core for processing completion, reads back the completion status, and stores the status in a FIFO, to be read back by the ARM processor at its own time.

M821xx Data Sheet


17.3 Programming ModelThe following subsections outline how software sets up and drives the IPsec Engine.

17.3.1 Packet Formating and TransformationsOn the outbound path, IP header addition must be performed prior to passing a packet to the ESP/AH engine. AH processing requires the IP header to be in place to authenticate the header. Tunnel mode packets will have two IP headers, an inner header to be tunneled, and the outer tunnel header. The ESP or AH header will be inserted between the two headers by the core (The IPsec Engine does not explicitly handle Security Association bundles and nested tunnels. Software can construct these by sequencing the same packet through the IPsec Engine multiple times.).

On the receive path, the complete IP packet must be re-assembled in the system memory external to the M821xx prior to passing pointers to it to the ESP/AH engine. The outer IP header is left in place. The ESP/AH core will process and remove the security header and decrypt the packet. The AH process does not validate the fragment offset field or the MF flag in the IP header. It is assumed that these fields are always clear after completion of the re-assembly process.

Packets are stored in the system memory in a specialized list of links, denoted as a DDT structure (see section 5.3 for a detailed description). When the ARM host initiates processing by the IPsec Enginge, it writes a pointer to the start of the DDT to the x_SRC_PTR registers (where x = IN or OUT). If the IP header is not at the start of the structure, an offset may be provided into the x_OFFSET register. A pointer to a pre-formatted destination memory structure in system memory must be provided in the x_DST_PTR register. This receiving memory structure must have sufficient length to hold the packet after compltetion of the cipher transform.

17.3.1.1 Transforms for Tunnel and Transport Modes

Figures 17-2 and 17-3 show the packet formats for inbound and outbound directions for transport and tunnel modes.

The IPsec Engine does not explicitly handle Security Association bundles and nested tunnels. Software can construct these by sequencing the same packet through the IPsec Engine multiple times.

The IPsec Engine makes no distinction in how it processes transport and tunnel modes — it simply inserts the IPsec header immeadiately after the leading IP header.

In Figures 17-2 and 17-3, the ESP or Encasulating Security Payload is shown as the header, but it could be the AH or Authentication Header.

Figure 17-2 IPv4 Tranform for Transport Mode

IP Payload

IP ESPHeader Encrypted Payload ESP

Trailer

InboundTransfer

OutboundTransfer

M821xx Data Sheet


In both tunnel and transport modes, transform operations result in updating of fields in the IP header:

• Total length – will be updated for the new total length of the packet

• Protocol field – will be updated for the correct next protocol

• Header checksum – an incremental update of this field will be performed for the changes in the total length and protocol fields. The update is performed in an incremental fashion so as not to mask any errors which exist in the checksum prior to security processing

17.3.2 IPSec Packet ProcessingThe ARM host processor must intitialize system memory external to the M821xx with both packet data in DDT stuctures (described in Section 17.3.5.4 Data Descriptor Table (DDT) Format) and the Security Association Database (described in Section 17.3.5.1 Security Association Database (SAD)). Once this external memory is setup, the ARM host processor writes pointers to these data structures to the IPsec Engine to start processing.

The ARM host can write directly to ESP/AH registers, or it can use the Offload Interface to mitigate interrupts and reduce overall requirements for host processor intervention (see Section 17.3.3 Offload Interface Programming).

To submit an IP packet for IPsec processing the packet must be available in a DDT memory structure. A pointer to the memory structure is written to the x_SRC_PTR register. A second memory structure must be allocated and the pointer to this structure is written to the x_DST_PTR register. The destination memory structure must be large enough to handle the resulting packet. The destination pointer may be the same as the source pointer, assuming the source memory structure has enough space allocated to absorb any increase in packet size.

If the IP header is not located at the start of the memory buffer, an offset in number of bytes may be written to the x_OFFSET register. Otherwise a value of zero must be placed in this register. Separate offsets may be configured for source and destination memory structures. If a single memory structure is used to hold both the source and destination packet, the destination offset must be less than or equal to the source offset.

To start the ESP/AH core in processing a particular packet, a pointer to the start of the appropriate SAD structure is written to the x_SAI register. Note that the pointer must meet the 128 byte boundary requirement for SADs. The x_STAT.RET_CODE field will transition to BUSY until the operation completes, where it will contain a return code. For details on return, or status codes, see Section 17.3.4 Status Codes.

Figure 17-3 IPv4 Transform for Tunnel Mode

IP Payload

IP ESPHeader Encrypted Payload ESP

Trailer

InboundTransfer

OutboundTransfer

TunnelIP

Local

M821xx Data Sheet


17.3.3 Offload Interface Programming

17.3.3.1 Functional OverviewThe Offload Interface allows the ARM host processor to setup IPsec processing for multiple packets atone time and mitigates interrupts by the IPsec to the ARM.

Without the Offload Interface, the ESP/AH requires intervention every packet: requiring that severalconfiguration registers be programmed, the IPSEC operation needs to be polled for completion, and thena status must be read back. The process is then repeated. If there is “dead” time between packets, itdirectly affects the IPSEC performance capabilities.

Having the ARM host processor perform this intervention every packet would require servicing manyinterrupts. The Offload Interface allows the ARM host core to program several (up to 64, per direction)packets’ configurations, ahead of time, and will only notify (via interrupt) the ARM when severaloperations are completed. The ARM may then read the return statuses for the completed packets, andconfigure the next set of packets for IPsec processing. The Offload Interface includes two mechanisms:one for the IN direction, and the other for the OUT direction.

If the ARM host processor requires a low-latency packet stram to be prioritized, it can do so by disablingthe corresponding direction’s process loop within the Offload Interface, and taking over full control of theIPSEC IP’s configurations and status reads (direct interaction with the ESP/AH as decribed in Section17.3.2 IPSec Packet Processing). The Offload Interface indicates to the ARM when it has finished anongoing process loop cycle, and has yielded to the disable request.

The Offload Interface monitors the fill level of the configuration FIFOs and of the status FIFOs. When thefill level of one of the configuration FIFOs is equal to or below a configured threshold or when the fill levelof one of the status FIFOs is equal to or above a configured threshold, an interrupt is generated to theARM host processor , indicating availability to program more packets’ configurations or to read morestatus indications. Separate threshold configuration registers are provided for the configuration FIFOsand for the status FIFOs.

The configuration FIFOs cannot underrun, since the Offload Interface does not program any additionalpackets to the IPSEC if it has no more configurations. The configuration FIFOs should not overflow. Theonly reason for them to do so is due to misbehavior of the ARM code, which may have attempted toprogram more packets than there was room for.

The status FIFOs should not underrun. The only reason for them to do so is due to misbehavior of theARM code, which attempted to read more statuses than were available. The status FIFOs cannotoverflow, since the Offload Interface does not program any additional packets to the ESP/AH if it has noroom for the resulting status.

An overflow/underrun of the FIFOs is monitored for, and interrupted on if occurring. Such an interrupt isan error requiring the ARM’s attention, but does not cause the hardware’s internal read/write pointers tooverlap. The ESP/AH will continue functioning correctly even if an overflow/underrun condition wasdetected (as it will internally prevent it from happening), but software may lose input/output packetsynchronization.

ESP/AH interrupts are output through a separate interrupt indication.

M821xx Data Sheet


17.3.4 Status Codes After an operation is complete, the x_STAT.RET_CODE field will transition to BUSY until the operation completes, where it will contain a return code. See Table 17-1.

Table 17-1 Status Codes

Code Name CodeValue

Width(Bytes)

Descriptions

OK 0 Both Processing has completed successfully.

BUSY 1 Both Processing is in progress. The input registers must not be modified during operation.

SOFT_TTL 2 Both During processing, the soft TTL limit was hit. This is not considered an error, but is and indication to the IKE process to begin negotiation of a new SA. The packet was fully processed. This event may be asked by other fatal errors, so TTL values should be checked by SW on receipt of a fatal error to see if key renegotiation should be performed.

HARD_TTL 3 Both The hard TTL limit was hit. The SA has been deactivated. The packet was not processed.

SA_INACTIVE 4 Both The SA is not active. The packet was not processed.

REPLAY5 In The packet was determined to be a replay. The packet must be

dropped.

ICV_FAIL 6 In The ICV check failed. The packet must be dropped.

SEQ_ROLL 7 Out The Sequence Number rolled over to zero. This is considered an error if the SEQ_ROLL flag in the SA is clear and the packet must be dropped. The SA is disabled in this case. If the SEQ_ROL flag is set, the packet was processed and this return code is simply a notification.

MEM_ERROR 8 Both The destination (or source) memory structure was not of sufficient length to handle the result (or initial) IP packet. Yhe packet wasnot fully processed.

VERS_ERROR 9 Both The IP version (v4 or v6) was incorrect for the SA. The packet was not processed.

PROT_ERROR 10 In The packet IPsec protocol (ESP or AH) does not match the SA. The packet was not processed.

PYLD_ERROR 11 In The payload length for ESP does not align to a multiple of the block size. or in AH mode, the Payload Length field in the AH header was incorrect for the cipher suite defined in SA.

PAD_ERROR 12 In The ESP padding contained within the received packet has incorrect values.

M821xx Data Sheet


17.3.5 External Memory InitializationThe ARM host can operate the ESP/AH core directly or, more efficiently, through the Offload Interface. In either case it must set up the packets to be processed along with the parameters controling the process in main memory external to the M821xx:

• Packets to be processed — Data Descriptor Tables (DDTs)

• Security parameters — Security Association Database (SADs)

Importantly, the system memory can hold a large number of DDTs each associated with unique SAD among a large number of SADs. The ARM host makes this association by writing to IPsec Engine registers.

17.3.5.1 Security Association Database (SAD)

The SAD is defined in Table 17-2. Byte-ordering within the SAD is big-endian. All reserved fields must be set to 0x0.

SADs must be aligned on 128-byte boundaries for cipher suites not using SHA-256. This means the pointer to the SA must have the least significant 7 bits clear. Cipher suites using SHA-256 have their SAs aligned on 256 byte boundaries: that is, the least significant 8 bits of the pointer to the SA must be clear.

NOTE: If the Authentication Header mode is selected for any particular SA entry, then the corresponding confidentially algorithm must be set to null. It is invalid to specify AH mode (which requires a hashing algorithm) and a non-NULL encryption/decryption algorithm.

Table 17-2 Security Association Database

Name AddressOffset

Width(Bytes)

Outbound Description Inbound Description

Sequence Number

0x00 8 Sequence number of the previously sent packet. This field must be initialized to zero on creation of the SA.

Sequence number of the left edge of the anti-replay window. This field must be initialized to zero on creation of the SA.

The first word (at address 0x00) is the upper 32 bits. The second word (at address 0x04) is the lower 32 bits. Only the lower 32 bits is used if ESN mode.

Anti-Replay Mask

0x08 8 RESERVED Bit mask indicating packets received within the anti-replay window. This must be initialized to zero on creation of the SA.

Authentication Key

0x10 20 Key for authentication algorithm. First 20 bytes only. Hashing algorithms (SHA-256) requiring more key material have the remainder of the key stored inthe Extended Authentication Key field.

Cipher Key 0x24 32 Key for cipher algoritms.

M821xx Data Sheet


InitalizationVector

0x44 16 Initialization vector for cipher algorithm CBC mode. On creation of the SA this field must be initialized to a cryptographically secure random number. It is automatically updated with the last block of cipher text upon completion of each packet encryption. ESP mode SAs only.

Not used on inbound path. Initialization vector is obtained directly from the ESP header.

Remote SPI 0x54 4 SPI of receiver corresponding to this SA. This value is initialized by the key exchange process and is placed in the

This field is not used on inbound.

RESERVED 0x58 8 RESERVED

RESERVED 0x60 4 RESERVED

Cipher Token

0x64 2 Context token last allocated by the resource manager for the cipher algorithm. This field is used to optimize subsequently processed packets on the same SA. This field must be initialized to NULL on SA creation.

AuthenticationToken

0x66 2 Context token last allocated by the resource manager for the authentication algorithm. This field is used to optimize subsequently processed packets on the same SA. This field must be initialized to NULL on SA creation.

Reserved 0x58 8 RESERVED

Reserved 0x60 4 RESERVED

Hard TTL LO 0x70 4 Lower 32 bits of hard lifetime of the SA in bytes. This field is initialized on creation of the SA and decremented as packet processing proceeds when in byte based SA expiry mode. Upon expiration (decrement past zero), the SA is disabled automatically.

Soft TTL HI 0x74 4 Upper 32 bits of soft lifetime in bytes. This field is not used for time based SA expiration.

Soft TTL LO 0x78 4 Lower 32 bits of soft lifetime of the SA in bytes. This field is initialized on creation of the SA and decremented as packet processing proceeds when in byte based SA expiry mode. Upon expiration (decrement past zero), a notification is sent to the control processor.

Table 17-2 Security Association Database (Continued)

Name AddressOffset

Width(Bytes)


M821xx Data Sheet


Algorithms 0x7C 1 Lower nibble indicates which authentication algorithm to apply. Supported values are as follows:

0 NULL 1 HMAC-MD5-96 2 HMAC-SHA1-96 3 HMAC-SHA256-128

Upper nibble indicates which confidentiality algorithm to apply. Supported values are as follows:

0 NULL 1 DES 2 3DES 3 AES-128 4 AES-192 5 AES-256

The authentication selection gives the length of the ICV, and the confidentiality gives the length of the key.

RESERVED 0x7D 1 RESERVED

Flags 0x7E 2 Flags controlling this SA defined in a 16-bit field as follows:

0) ACTIVE. Indicates the SA is active. If an attempt is made to process a packet on an inactive SA, the packet is not processed and an error is returned.

1) SEQ_ROLL. If this bit is set, the sequence number will be allowed to roll over. If this bit is clear, the ACTIVE flag will automatically clear if the sequence number rolls over and the current packet will be dropped. Regardless of whether or not this bit is set, a notification is sent to the control processor on any sequence number roll over event. This bit only has meaning for outbound processing.

2) TTL_EN. Enables the TTL expiry decrement. If this bit is clear, the SA will never expire based on TTL.

3) TTL_CTRL. 0=byte count, 1=time count (note: Time count is not performed by the hardware).

4) HDR_TYPE. 0=ESP, 1=AH

5) RESERVED. Set to 0x0.

6) RESERVED . Set to 0x0.

7) AR_EN. Enable anti-replay check. This flag only affects inbound. Anti-replay protection is always generated by the outbound.




Name AddressOffset

Width(Bytes)


M821xx Data Sheet


17.3.5.2 Time Based TTL (Time to Live)If the TTL_CFG flag is set to time count mode, the ESP/AH Offload Engine does not do any TTL checks. It is the responsibiity of the host processor to maintain this real-time function by periodically walking the entire SAD, to check the TTL values. Any SAD which has hit the HARD_TTL expiration limit must be cleared by clearing the ACTIVE flag.

17.3.5.3 Extended Sequence Numbers

If Extended Sequence Numbers are enabled, receipt of any packet to the left of the anti-replay window will compute the ICV using the upper 32 bits of the sequence number incremented by one. Upon successful ICV validation the incremented upper 32 bits of the sequence sequence number will be stored back to the SAD.

Hardware does not support the resynchronization due to significant packet loss algorithm. It is assumed that loss of more than four billion packets is not acceptable to real world transport and/or application protocols. If this feature is required, it may be done in software, using the cryptographic resources to accelerate the process.

17.3.5.4 Data Descriptor Table (DDT) Format

The Data Descriptor Table (DDT) format is a descriptor designed to handle fragmented blocks by providing a NULL terminated list of pointer-length pairs. The length of each fragment is in bytes. The pointer within each pointer-length pair is not required to point at a word-aligned segment. However, the DDT structure itself must be 8-byte aligned. This requirement arises out of the fact that each of the pointer and length elements in the pointer-length pair are 32-bits wide.

Each DDT fragment has a maximum size of 64KB. DDT fragments must not straddle 64KB memory boundaries. The DDT structure itself must also not straddle a 64KB boundary. Flat (linear) blocks may be accommodated by providing a single (pointer, length) pair followed by a NULL termination pair.





14) ESN_EN. Set to enable extended sequence number processing. Anti-replay checking (AR_EN) must be enabled if ESN_EN==1.

15) RESERVED.

ExtendedAuthenticationKey

0x80 12 Remainder of authentication key bytes. This field is not used for implementation that do not use SHA-256.

RESERVED 0x8C 116 RESERVED


Name AddressOffset

Width(Bytes)


M821xx Data Sheet


All descriptor addresses must be physical addresses. Hence, to handle virtual pointers, the software must extract the physical addresses of the various fragments (if any) and construct the appropriate DDT structure. A NULL pointer is indicated by a value of 0x0 in the pointer value.

17.4 IPSec Engine RegistersFor details on registers, see Section 18.0 IPSec Engine Registers on page 348.

Figure 17-4 IDDT Function

.


18.0 IPSec Engine Registers

18.1 Register Access TypesR–Read only

W–Write only

RW–Read/write

RW1–Read/write; write ‘1’ to clear

RC–Read and clear (value reset when read)

Dyn–(applies only to Offload Interface registers) Dynamic access yes/no (a no-dynamic access is allowed only when the block is in a static state, i.e. when all four FIFOs are empty; a dynamic access is allowed at any time)

18.2 ESP/AH Registers

NOTE: The memory addressing of the IPSec registers is offset from the base address: 0x 0E00 0000.

Table 18-1 ESP/AH Register Map


INT_EN 0x0_0000 Interrupt Enable

INT_STAT 0x0_0004 Interrupt Status.

SEC_REQ 0x0_0008 Security Bus Arbiter Request

SEC_GNT 0x0_000C Security Bus Arbiter Grant

SRM_GO 0x0_0010 Security Resource Manager Initiate Request

SRM_RDY 0x0_0014 Security Resource Manager Status

ENDIAN_CTRL 0x0_0018 Endian Swap Control

OUT_SRC_PTR 0X0_0020 Outgoing Packet Source Location Pointer

OUT_DST_PTR 0X0_0024 Outgoing Packet Destination Location Pointer

OUT_OFFSET 0X0_0028 Outgoing Packet Offsets

OUT_SAI 0x0_002C Outgoing SA Structure Location Pointer

OUT_STAT 0x0_0030 Outgoing Status

IN_SRC_PTR 0x0_0040 Incoming Packet Source Location Pointer

IN_DST_PRT 0x0_0044 Incoming Packet Destination Location Pointer

IN_OFFSET 0x0_0048 Incoming Packet Offsets

M821xx Data Sheet


18.3 ESP/AH Control and Status Registers

18.3.1 Interrupt Enable (INT_EN)Default Value: 0x0000

IN_SAI 0x0_004C Incoming SA Structure Location Pointer

IN_STAT 0x0_0050 Incoming Status

SRM_CMD_0 0x0_0060 Security Resource Manager Command 0



SRM_RET_0 0x0_0070 Security Resource Manager Return 0

SRM_RET_1 0x0_0074 Security Resource Manager Return 1

SecurityBlock

0x2_0000-0x3_FFFF

Security Block Access Area



Acc

31 GLBL_EN Global enable of all other interrupts. 0 R/W

30:20 RSVD Reserved. N/A N/A

19 AES_EN Enable of interrupts from AES block. 0 R/W

18 RSVD Reserved. N/A N/A

17 DES_EN Enable of interrupts from DES block. 0 R/W

16 HASH_EN Enable of interrupts from hash block. 0 R/W


8 SRM_EN Enable for interrupts from security resource manager block.

0 R/W


1 INBND_EN Enable for interrupts from inbound packet logic. 0 R/W

0 OUTBND_EN Enable for interrupts from outbound packet logic. 0 R/W

Table 18-1 ESP/AH Register Map

M821xx Data Sheet


18.3.2 Interrupt Status (INT_STAT)Default Value: 0x0000

18.3.3 Security Bus Arbiter Request (SEC_REQ)Default Value: 0x0000

18.3.4 Security Bus Arbiter Grant (SEC_GNT)Default Value: 0x0000



Acc


19 AES_EN Interrupts from AES block. Write ‘1’ to clear. 0 R/W1

18 RSVD Reserved. N/A N/A

17 DES_EN Interrupts from DES block. Write ‘1’ to clear. 0 R/W1

16 HASH_EN Interrupts from hash block. Write ‘1’ to clear. 0 R/W1


8 SRM_EN Interrupts from security resource manager block. Write ‘1’ to clear.

0 R/W1


1 INBND_EN Interrupts from inbound packet logic. Write ‘1’ to clear.

0 R/W1

0 OUTBND_EN Interrupts from outbound packet logic. Write ‘1’ to clear.

0 R/W1

Table 18-4 Security Bus Arbiter Request Register


Acc


0 REQ Set this bus to request the security bus arbiter. 0 R/W

Table 18-5 Security Bus Arbiter Grant Register


Acc


0 GNT Set this bus to set the security bus arbiter. 0 RO

M821xx Data Sheet


18.3.5 Security Resource Manager Start (SRM_GO)Default Value: 0x0000

18.3.6 Security Resource Manager (SRM_RDY)Default Value: 0x0000

18.3.7 Endian Control (ENDIAN_CTRL)Default Value: 0x0000

18.3.8 Outgoing Packet Source Pointer (OUT_SRC_PTR)Default Value: 0x0000

Table 18-6 Security Resource Manager Start Register


Acc


0 GO Kicks of a request for security resources. 0 WO

Table 18-7 Security Resource Manager Register


Acc


0 RDY Indicates status of SRM service request by SRM_GO.

0 RO

Table 18-8 Endisn Control Register


Acc


0 SWAP Swaps endianess of data security bus for host access. If the host operates in little-endian mode, this bit must be set when transferring data. Control data must still be transferred in big-endian format.

0 R/W

Table 18-9 Outgoing Packet Source Pointer Register


Acc

31:3 PTR Pointer to source packet location in DDR2 memory. Must be 8-byte aligned.

0 RW


M821xx Data Sheet


18.3.9 Outgoing Packet Destination Pointer (OUT_DST_PTR)Default Value: 0x0000

18.3.10 Outgoing Offset (OUT_OFFSET)Default Value: 0x0000

18.3.11 Outgoing Security Database Pointer (OUT_SAI)Default Value: 0x0000

18.3.12 Outgoing Status (OUT_STAT)Default Value: 0x0000

Table 18-10 Outgoing Packet Destination Pointer Register


Acc

31:3 PTR Pointer to destination packet location in DDR2 memory for post-processed packet. Must be 8-byte aligned.

0 RW


Table 18-11 Outgoing Offset Register


Acc


29:16 SRC_OFFSET Offsets in packet memory structure at start of packet. 0 RW


13:0 DST_OFFSET Offsets in packet memory structure at start of packet. 0 RW

Table 18-12 Outgoing Security Database Pointer


Acc

31:7 SAI Pointer to SA structure in SAD. Writing to this register causes the command to be placed in the outgoing command FIFO. The OUT_STAT.CMD_FIFO_FULL flag must be clear when writing this register.

0 RW


Table 18-13 Outgoing Status Register


Acc

31 BUSY Indicates that the process is busy. Clears when complete. Other fields in this register are not valid until this field is clear.

0 RO


27:24 RET_CODE Return code from the last operation. 0 RO


15:0 LENGTH Post ciphered length. 0 RO

M821xx Data Sheet


18.3.13 Incoming Packet Source Pointer (IN_SRC_PTR)Default Value: 0x0000

18.3.14 Incoming Packet Destination Pointer (IN_DST_PTR)Default Value: 0x0000

18.3.15 Incoming Offset (IN_OFFSET)Default Value: 0x0000

18.3.16 Incoming Security Database Pointer (IN_SAI)Default Value: 0x0000

Table 18-14 Incoming Packet Source Pointer Register


Acc

31:3 PTR Pointer source packet location in DDR2 memory. Must be 8-byte aligned.

0 RW


Table 18-15 Incoming Packet Destination Pointer Register


Acc

31:3 PTR Pointer packet destination location in DDR2 memory for post-processed packet. Must be 8-byte aligned.

0 RW


Table 18-16 Incoming Offset Register


Acc


29:16 SRC_OFFSET Offsets in packet memory structure at start of packet. 0 RW


13:0 DST_OFFSET Offsets in packet memory structure at start of packet. 0 RW

Table 18-17 Incoming Security Database Pointer Register


Acc

31:7 SAI Pointer to SA structure in SAD. Writing to this register causes the command to be placed in the inbound command FIFO. The IN_STAT.CMD_FIFO_FULL flag must be clear when writing this register.

0 RW


M821xx Data Sheet


18.3.17 Incoming Status (IN_STAT)Default Value: 0x0000

18.4 ESP/AH Access FIFOs

18.4.1 Security Resource Manager Command Registers (SRM_CMD[2:0])The command structure to the Security Resource Manager is formatted in these registers.

18.4.2 Security Resource Manager Return Registers (SRM_CMD[1:0])The return structure from the Security Resource Manager is formatted across these registers.

Table 18-18 Incoming Status Register


Acc

31 BUSY Indicates that the process is busy. Clears when complete. Other fields in this register are not valid until this field is clear.

0 RO


27:24 RET_CODE Return code from the last operation. 0 RO


15:0 LENGTH Post ciphered length. 0 RO

Table 18-19 Security Resource Manager Command Register Map

Register Address Bit Field Type Description

SRM_CMD_0 0x0_0060 31:0 RW SRM Command [31:0]



Table 18-20 Security Resource Manager Return Register Map


SRM_CMD_0 0x0_0070 31:0 RO SRM Return [31:0]

SRM_CMD_1 0x0_0074 31:0 RO SRM Return [63:32]

M821xx Data Sheet


18.4.3 Security BlockThis area is reserved for security block access including DES, AES, HMAC. Appropriate tokens must be acquired from the resource manager prior to accessing this block. The internal memory map is accessed by using the acquired tokens.

18.5 Offload Interface Registers

Table 18-21 Security Block


Security Block 0x2_000 –0x3_FFF

— RW See paragraph above.



0x00000 – 0x3FFFF ESP/AH memory space

INT_EN_R 0x40000 Interrupt enable

EV_STAT_R 0x40004 Event status

THRSH_CFG_R 0x40008 Threshold configuration

FILL_LVL_STAT_R 0x4000C Fill level status

PL_DISABLE_CFG_R 0x40010 Process loop disable configuration

PL_DISABLE_STAT_R 0x40014 Process loop disable status

OUT_SRC_PTR_FIFO 0x40020 FIFO holding OUT_SRC_PTR entries

OUT_DST_PTR_FIFO 0x40024 FIFO holding OUT_DST_PTR entries

RSVD 0x40028 Reserved

OUT_SAI_FIFO 0x4002C FIFO holding OUT_SAI entries

OUT_STAT_FIFO 0x40030 FIFO holding OUT_STAT entries

IN_SRC_PTR_FIFO 0x40040 FIFO holding IN_SRC_PTR entries

IN_DST_PTR_FIFO 0x40044 FIFO holding IN_DST_PTR entries

RSVD 0x40048 Reserved

IN_SAI_FIFO 0x4004C FIFO holding IN_SAI entries

IN_STAT_FIFO 0x40050 FIFO holding IN_STAT entries

RSVD 0x40054 – 0x400FF Reserved

M821xx Data Sheet


18.6 Offload Interface Control Registers

18.6.1 Interrupt Enable (INT_EN_R)Default Value = 0x0000

18.6.2 Threshold Configuration (THRSH_CFG_R)Default Value: 0x0000



Dyn Acc


7 OUT_STAT_FIFO_UND_IE OUT status FIFO’s underrun interrupt enable. When set, interrupt is enabled.

0 Yes RW

6 OUT_STAT_FIFO_THR_IE OUT status FIFO’s threshold interrupt enable. When set, interrupt is enabled.

0 Yes RW

5 OUT_CFG_FIFO_OVF_IE OUT configuration FIFO’s overflow interrupt enable. When set, interrupt is enabled.

0 Yes RW

4 OUT_CFG_FIFO_THR_IE OUT configuration FIFO’s threshold interrupt enable. When set, interrupt is enabled.

0 Yes RW

3 IN_STAT_FIFO_UND_IE IN status FIFO’s underrun interrupt enable. When set, interrupt is enabled.

0 Yes RW

2 IN_STAT_FIFO_THR_IE IN status FIFO’s threshold interrupt enable. When set, interrupt is enabled.

0 Yes RW

1 IN_CFG_FIFO_OVF_IE IN configuration FIFO’s overflow interrupt enable. When set, interrupt is enabled.

0 Yes RW

0 IN_CFG_FIFO_THR _IE IN configuration FIFO’s threshold interrupt enable. When set, interrupt is enabled.

0 Yes RW

Table 18-24 Threshold Configutration Register


Dyn Acc


13:8 STAT_FIFO_THR_CFG Status FIFOs’ threshold configuration.When the IN/OUT status FIFOs’ fill level is equal to or greater than this level, the associated status/interrupt is high.

0 No RW


5:0 CFG_FIFO_THR_CFG Configuration FIFOs’ threshold configuration.When the IN/OUT configuration FIFOs’ fill level is equal to or lesser than this level, the associated status/interrupt is high.

0 No RW

M821xx Data Sheet


18.6.3 Process loop disable configuration (PL_DISABLE_CFG_R)Default Value: 0x0000Table 18-25 Process Loop Disable Configuration Register


Dyn Acc


1 OUT_PL_DISABLE_CFG OUT process loop disable configuration. When set, the OUT process loop will disable itself upon finishing the currently ongoing loop. The corresponding status bit must be polled after disable configuration.

0 Yes RW

0 IN_PL_DISABLE_CFG IN process loop disable configuration. When set, the IN process loop will disable itself upon finishing the currently ongoing loop. The corresponding status bit must be polled after disable configuration.

0 Yes RW

M821xx Data Sheet


18.7 Offload Interface Status Registers18.7.1 Event status (EV_STAT_R)Default Value: 0x0055

Table 18-26 Event Status Register


Dyn Acc


7 OUT_STAT_FIFO_UND_IS OUT status FIFO’s underrun interrupt status. This bit is set when the FIFO underruns. This bit is cleared when written to with a ‘1’ value. If this bit is set and the corresponding interrupt enable is also set, the Offload Interface’s interrupt output is asserted.

0 N/A RWC

6 OUT_STAT_FIFO_THR_IS OUT status FIFO’s threshold interrupt status. This bit is high when the FIFO’s fill level is greater than or equal to the configurable threshold level. Note that this bit cannot be explicitly cleared; it is cleared indirectly when enough statuses are read to bring the fill level below the threshold configuration. If this bit is set and the corresponding interrupt enable is also set, the Offload Interface’s interrupt output is asserted.

1 N/A R

5 OUT_CFG_FIFO_OVF_IS OUT configuration FIFO’s overflow interrupt status. This bit is cleared when written to with a ‘1’ value. If this bit is set and the corresponding interrupt enable is also set, the Offload Interface’s interrupt output is asserted.

0 N/A RWC

4 OUT_CFG_FIFO_THR_IS OUT configuration FIFO’s threshold interrupt status. This bit is high when the FIFO’s fill level is lesser than or equal to the configurable threshold level. Note that this bit cannot be explicitly cleared; it is cleared indirectly when enough configurations are written to bring the fill level above the threshold configuration. If this bit is set and the corresponding interrupt enable is also set, the Offload Interface’s interrupt output is asserted.

1 N/A R

3 IN_STAT_FIFO_UND_IS IN status FIFO’s underrun interrupt status. This bit is set when the FIFO underruns. This bit is cleared when written to with a ‘1’ value. If this bit is set and the corresponding interrupt enable is also set, the Offload Interface’s interrupt output is asserted.

0 N/A RWC

2 IN_STAT_FIFO_THR_IS IN status FIFO’s threshold interrupt status. This bit is high when the FIFO’s fill level is greater than or equal to the configurable threshold level. Note that this bit cannot be explicitly cleared; it is cleared indirectly when enough statuses are read to bring the fill level below the threshold configuration. If this bit is set and the corresponding interrupt enable is also set, the Offload Interface’s interrupt output is asserted.

1 N/A R

1 IN_CFG_FIFO_OVF_IS IN configuration FIFO’s overflow interrupt status. This bit is set when the FIFO overflows. This bit is cleared when written to with a ‘1’ value. If this bit is set and the corresponding interrupt enable is also set, the Offload Interface’s interrupt output is asserted.

0 N/A RWC

0 IN_CFG_FIFO_THR_IS IN configuration FIFO’s threshold interrupt status. This bit is high when the FIFO’s fill level is lesser than or equal to the configurable threshold level. Note that this bit cannot be explicitly cleared; it is cleared indirectly when enough configurations are written to bring the fill level above the threshold configuration. If this bit is set and the corresponding interrupt enable is also set, the Offload Interface’s interrupt output is asserted.

1 N/A R

M821xx Data Sheet


18.7.2 Fill level status (FILL_LVL_STAT_R)Default Value: 0x0000

18.7.3 Process loop disable status (PL_DISABLE_STAT_R)Default Value: 0x0003

Table 18-27 Fill Level Status Register


Dyn Acc

31 RSVD Reserved N/A N/A N/A

30:24 OUT_STAT_FILL_LVL OUT status FIFO’s fill level. This value depicts the number of statuses currently in the FIFO.

0 N/A R


22:16 OUT_CFG_FILL_LVL OUT configuration FIFO’s fill level. This value depicts the number of configurations currently in the FIFO. The number of entries that may be configured without causing the OUT configuration FIFO to overflow may deduced from this number, and from the FIFO’s 64-entry size.

0 N/A R


14:8 IN_STAT_FILL_LVL IN status FIFO’s fill level. This value depicts the number of statuses currently in the FIFO.

0 N/A R


6:0 IN_CFG_FILL_LVL IN configuration FIFO’s fill level. This value depicts the number of configurations currently in the FIFO. The number of entries that may be configured without causing the IN configuration FIFO to overflow may deduced from this number, and from the FIFO’s 64-entry size.

0 N/A R

Table 18-28 Process Loop Disable Status Register


Dyn Acc


1 OUT_PL_DISABLE_STAT OUT process loop disable status. When set, the OUT process loop is disabled.

1 Yes R

0 IN_PL_DISABLE_STAT IN process loop disable configuration. When set, the IN process loop is disabled.

1 Yes R

M821xx Data Sheet


18.8 Offload Interface FIFO Registers

18.8.1 FIFO holding OUT_SRC_PTR entries (OUT_SRC_PTR_FIFO)

Default Value: Undef

18.8.2 FIFO holding OUT_DST_PTR entries (OUT_DST_PTR_FIFO)


18.8.3 FIFO holding OUT_SAI entries (OUT_SAI_FIFO)

Default Value: N/A

Table 18-29 FIFO holding OUT_SRC_PTR entries Register

Bits Name Description Reset ValueUndef

Dyn Acc31:3 OUT_SRC_PTR OUT_SRC_PTR entry. A write to this field does not

actually perform a write to the FIFO until OUT_SAI is written to.

Yes W


Table 18-30 FIFO holding OUT_DST_PTR entries Register


Dyn Acc

31:3 OUT_DST_PTR OUT_DST_PTR entry. A write to this field does not actually perform a write to the FIFO until OUT_SAI is written to.

Undef Yes W


Table 18-31 FIFO holding OUT_SAI entries Register


Dyn Acc

31:7 OUT_SAI OUT_SAI entry. A write to this field validates the data previously written into the SRC_PTR and DST_PTR addresses, and actually writes all the configurations into the FIFO, at the next available entry.

Yes W


M821xx Data Sheet


18.8.4 FIFO holding OUT_STAT entries (OUT_STAT_FIFO)

Default Value: N/A

18.8.5 FIFO holding IN_SRC_PTR entries (IN_SRC_PTR_FIFO)Default Value: Underf

18.8.6 FIFO holding IN_DST_PTR entries (IN_DST_PTR_FIFO)


Table 18-32 FIFO holding OUT_STAT entries Register


Dyn Acc


27:24 OUT_STAT_RET_CODE OUT_STAT entry, RET_CODE field.A read to this field performs a read to the FIFO, at the next available entry. Additional wait states are required for read from this register.

Undef Yes R


15:0 OUT_STAT_LENGTH OUT_STAT entry, LENGTH field.A read to this field performs a read to the FIFO, at the next available entry. Additional wait states are required for read from this register.

Undef Yes R

Table 18-33 FIFO holding IN_SRC_PTR entries Register


Dyn Acc

31:3 IN_SRC_PTR IN_SRC_PTR entry. A write to this field does not actually perform a write to the FIFO until IN_SAI is written to.

Undef Yes W


Table 18-34 FIFO holding IN_DST_PTR enteries Register


Dyn Acc

31:3 IN_DST_PTR IN_DST_PTR entry. A write to this field does not actually perform a write to the FIFO until IN_SAI is written to.

Undef Yes W


M821xx Data Sheet


18.8.7 FIFO holding IN_SAI entries (IN_SAI_FIFO)

Default Value: N/A

18.8.8 FIFO holding IN_STAT entries (IN_STAT_FIFO)

Default Value: N/A

Table 18-35 FIFO holding IN_SAI entries (IN_SAI_FIFO)


Dyn Acc

31:7 IN_SAI IN_SAI entry. A write to this field validates the data previously written into the SRC_PTR and DST_PTR addresses, and actually writes all the configurations into the FIFO, at the next available entry.

Yes W


Table 18-36 FIFO holding IN_STAT entries (IN_STAT_FIFO)


Dyn Acc


27:24 IN_STAT_RET_CODE IN_STAT entry, RET_CODE field.A read to this field performs a read to the FIFO, at the next available entry. Additional wait states are required for read from this register.

Undef Yes R


15:0 IN_STAT_LENGTH IN_STAT entry, LENGTH field.A read to this field performs a read to the FIFO, at the next available entry. Additional wait states are required for read from this register.

Undef Yes R

.


19.0 Serial Peripheral Interface (SPI)

The multi-chain Serial Peripheral Interface (SPI) provides a common interface mechanism to SLICs from multiple vendors and is used to setup such parameters as µ-law / a-law PCM conversion. This section starts with an overview of SPI interface features followed by a high-level functional description. Subsections 11.3 through 11.12 provide details on SPI timing and implementation.

For a view of the Serial Peripheral Interface within the top-level block diagram, see Figure 2-1.

19.1 Features• Serial interface operation – Motorola SPI.

• Clock bit-rate – User can dynamically control the serial bit-rate of the data transfer.

• Serial Master – Enables serial communication with serial slave peripheral devices.

• Independent masking of interrupts – transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.

• Data frame size (4 to 16 bits) – The frame size of each data transfer is under the control of the programmer.

• FIFO depth – the depth of the transmit and receive FIFO buffers is 8 words. The FIFO width is fixed at 16 bits.

• Number of slave select outputs – 4 serial slave select output signals can be generated (NOTE: SPI select signals SPI_SS0# and SPI_SS1# are muxed with GPIO27 and GPIO28 respectively).

• Hardware/software slave-select – Dedicated hardware slave-select lines can be used or software control can be used to target the serial slave device.

19.2 Functional DescriptionThe M821xx SPI interface can connect to any serial slave peripheral device that supports the Motorola Serial Peripheral Interface (SPI) – a four-wire, full-duplex, serial protocol. There are four possible combinations for the serial clock’s phase and polarity. The clock phase (SCPH) determines whether the serial transfer begins with the falling edge of the slave select signal or the first edge of the serial clock. The slave select line is held high when the SPI interface is idle or disabled. Figure 19-1 presents a high-level block diagram of the M821xx SPI Interface.

M821xx Data Sheet


The M821xx SPI interface allows for serial slave to be selected/addressed using either hardware or software. When implemented in hardware, serial slaves are selected under the control of dedicated hardware select lines. The number of select lines generated from the serial master is equal to the number of serial slaves present on the bus. The serial master device asserts the select line of the target serial slave before data transfer begins. This architecture is illustrated in Figure 19-2 A.

Figure 19-1 Block Diagram of SPI block

M821xx Data Sheet


When implemented in software, the input select line of each serial slave can either originate for a single slave select output pin on the serial master (user must configure the master to have one slave select output) or be permanently grounded. The main program in the software domain controls the selection of the target slave device. This architecture is illustrated in Figure 19-2 B. The M821xx SPI interface does not enforce hardware or software control, the user can configure the interface for either implementation.

Figure 19-3 presents an example of an M821xx using SPI to interface to multiple SLIC devices.

19.3 Signal DescriptionsTable 19-1 M821xx SPI Interface Signals

Figure 19-2 Hardware/Software Slave Selection

Signal Name Dir. Description

SPI_SCLK O The serial bit rate clock generated by the M821xx interface.

SPI_TXD O Output data is transmitted on this line.

SPI_RXD I Input data is received on this line.

SPI_SS[3:0]# O Active low. Hardware slave select signals. The width of the signal is equal to the number of slaves present on the serial bus. SPI_SS0 is used for boot device when configured for SPI boot.

M821xx Data Sheet


Figure 19-3 Example SPI Bus Connection to SLIC Devices

CLKDriv erSPI_SCLK

SPI_CLK0_0

SPI_CLK1_0

SPI_CLK2_0

SPI_CLK3_0

DualSLIC2, 3

DualSLIC

18, 19

DualSLIC

34, 35

DualSLIC

50, 51

DualSLIC0, 1

DualSLIC

16, 17

DualSLIC

32, 33

DualSLIC

48, 49

DualSLIC

14, 15

DualSLIC

30, 31

DualSLIC

46, 47

DualSLIC

62, 63

3StateBuf f er

3StateBuf f er

3StateBuf f er

3StateBuf f er

SPI_TXD

SPI_RXD

SPI_SS0#

SPI_SS1#

SPI_SS2#

SPI_SS3#

SPI_TXD

SPI_SS0# SPI_SS1# SPI_SS2# SPI_SS3#

SPI_SS0#

SPI_SS1#

SPI_SS2#

SPI_SS3#

SPI_CLK0_0

SPI_CLK0_0

SPI_CLK0_1

SPI_CLK1_0

SPI_CLK1_0

SPI_CLK1_1

SPI_CLK2_0

SPI_CLK2_0

SPI_CLK2_1

SPI_CLK3_0

SPI_CLK3_0

SPI_CLK3_1

CS

CS

CS

CS

CS

CS

CS

CS

CS

CS

CS

CS

DI

DI

DI

DI

DI

DI

DI

DI

DI

DI

DI

DI

DI Thru

DI Thru

DI Thru

DI Thru

DI Thru

DI Thru

DI Thru

DI Thru

DO

DO

DO

DO

DO

DO

DO

DO

DO

DO

DO

DO

SPI_RXD_0

SPI_RXD_1

SPI_RXD_2

SPI_RXD_3

SPI_RXD_3

SPI_RXD_2

SPI_RXD_1

SPI_RXD_0

SPI_CLK0_1

SPI_CLK1_1

SPI_CLK2_1

SPI_CLK3_1

Bank 0 Bank 1 Bank 2 Bank 3

MindspeedDevice

M821xx Data Sheet


19.4 SPI TimingFigure 19-4 SPI Timing Waveforms

Table 19-2 SPI Setup and Hold Times


SPI_SCLK Frequency 4 MHz

Clock Duty Cycle (All Clocks) 35 65 %

Tis Input Setup TimeSPI_RXD

20 ns 3

Tih Input Hold TimeSPI_RXD

2 ns 3

Tod Output Delay TimeSPI_TXD

8 ns 3

Toh Output Hold TimeSPI_TXD

-5 ns 1, 3

1. Input can be referenced to either the rising or falling edge of the clock. Output is always reference to the opposite edge then that of the input.

2. SPI_SS# signals are configured when output clock is not active, thus have no AC requirements.

3. Maxium capacitive load is 54 pF.

4. Maximum capactive load for SPI_SSn# is 36 pF.

M821xx Data Sheet


19.5 Transmit and Receive FIFO BuffersTwo FIFO memories are used to buffer the transmit and receive data paths. The FIFO depth is 8, allowing 8x16-bit values to be stored independently in both transmit and receive modes. Transmit data is loaded from the transmit FIFO, serialized, and sent over the serial line (txd) to the target peripheral. Receive data from the peripheral (on rxd) is converted to parallel words and loaded into the receive FIFO buffer. Serial data is propagated on one edge of the serial clock and captured on the opposite edge when the data is stable. Each data word that is transferred on the serial bus is referred to as a data frame. The serial data frame may range from 4 to 16 bits in length.

19.6 SPI InterruptsThe M821xx SPI interface supports combined interrupt requests. The combined interrupt request is the OR'ed result of all other SPI interrupts after masking. All SPI interrupts have the same active high polarity level.

• Transmit FIFO Empty Interrupt: Set when the transmit FIFO is equal to or below its threshold value and requires service to prevent an under-run. The threshold value, set via a SW-programmable register, is used to determine the level of transmit FIFO entries at which an interrupt is generated. This interrupt is cleared by hardware when data is written into the transmit FIFO buffer, bringing it over the threshold level.

• Transmit FIFO Overflow Interrupt: Set when a processor access attempts to write into the transmit FIFO after it has been completely filled. When set, data written from the processor is discarded. This interrupt remains set until the user reads the transmit FIFO overflow interrupt clear register (TXOICR).

• Receive FIFO Full Interrupt: Set when the receive FIFO is equal to or above its threshold value plus 1 and requires service to prevent an overflow. The threshold value, set via a SW-programmable register, is used to determine the level of receive FIFO entries at which an interrupt is generated. This interrupt is cleared by hardware when data is read from the receive FIFO buffer, bringing it below the threshold level.

• Receive FIFO Overflow Interrupt: Set when the receive logic attempts to place data into the receive FIFO after it has been completely filled. When set newly received data is discarded. This interrupt remains set until the user reads the receive FIFO overflow interrupt clear register (RXOICR).

• Receive FIFO Underflow Interrupt: Set when a processor access attempts to read from the receive FIFO when it is empty. When set, zeros are read back from the receive FIFO. This interrupt remains set until the processor reads the receive FIFO underflow interrupt clear register (RXUICR).

• Combined Interrupt Request: This interrupt is the OR'ed result of all the above interrupt requests after masking. To mask this interrupt signal the user must mask all other SPI interface interrupt requests.

NOTE: The transmit and receive FIFO buffers are cleared when the SPI interface is disabled (SSI_EN=0) or reset.

M821xx Data Sheet


19.7 Transfer ModesThe M821xx SPI interface operates in three modes:

• Transmit and Receive

• Transmit Only

• Receive Only

To set the transfer mode (TMOD) write to control register 0 (CTRLR0).

19.7.1 Transmit and ReceiveWhen TMOD = 2‘b00, both transmit and receive logic are valid. The data transfer occurs as normal according the selected frame format (that is, serial protocol). Transmit data is popped from the transmit FIFO and sent via the txd line to the target device, which replies with data on the rxd line. The receive data from the target device is moved from the receive shift register into the receive FIFO at the end of each data frame. Error flags related to the transmit and receive FIFO logic are enabled in this mode.

19.7.2 Transmit OnlyWhen TMOD = 2‘b01, the receive data is invalid and should not be stored in the receive FIFO. The data transfer occurs as normal, according to the selected frame format (that is, serial protocol). Transmit data is popped from the transmit FIFO and sent via the txd line to the target device, which replies with data on the rxd line. At the end of the data frame, the receive shift register does not load its newly received data into the receive FIFO. The data in the receive shift register is overwritten by the next transfer. Error flags related to the receive FIFO logic are disabled in this mode. Interrupts originating from the receive logic should be masked by the software when this mode is entered.

19.7.3 Receive OnlyWhen TMOD = 2‘b10, the transmit data is invalid. When configured as a slave, the transmit FIFO is never popped in Receive Only mode. Data from a previous transfer is re-transmitted from the Shift Register. The data transfer occurs as normal according to the selected frame format (serial protocol). The receive data from the target device is moved from the receive shift register into the receive FIFO at the end of each data frame. Error flags related to the transmit FIFO logic are disabled in this mode. Interrupts originating from the transmit logic should be masked by the user when this mode is entered.

NOTE: The transfer mode setting does not affect the duplex of the serial transfer.

M821xx Data Sheet


Comcerto SPI Interface

19.8 Operational ModesThe M821xx SPI interface operates only in “Serial Master Mode”.

This mode enables serial communication with serial slave peripheral devices. Figure 19-5 shows an example of the SPI interface configured as a serial master with all other devices on the serial bus configured as serial slaves.

As a serial master device, the Comcerto SPI interface generates the serial clock that regulates the flow of data bits. The serial clock, when driven from the Comcerto SPI interface master, only toggles during active data transfers. The number of active clock edges is equal to the number of bits driven on the data lines. At other times, the serial clock is held in an inactive state as defined by the protocol under which it operates. The serial master may transmit data at a variety of baud rates, which are under the control of a software programmable control register.

The baud rate is calculated from the following formula AHB Clock / SCKDV, where AHB clock is the frequency of the internal AHB clock (controlled by the clock and reset block), and SCKDV is any even value between 2 and 65534. SCKDV is set by writing to the BAUDR register.

The M821xx SPI interface can assert all of its slave select output lines (when hardware is used to select target slaves) to broadcast to all slaves on the bus. In response, only one serial slave drives data back onto the master’s RXD line. The serial master can transmit data to all serial slaves on the bus simultaneously when the slave peripherals select lines have been enabled in the SER egister. Throughout the remainder of this chapter, the term broadcast mode will be referred to the situation when the master is transmitting data to all serial slaves on the bus.

Data transfers are started by the SPI interface when at least one valid data entry is present in the transmit FIFO and a serial slave device is selected. When actively transferring data, the busy flag (BUSY) in the status register (SR) is set. The software driver must wait until the busy flag is cleared before attempting to begin a new serial transfer.

Figure 19-5 M821xx Configured as Master Device

Comcerto SPI Interface

SCLK

RXD

TXD

SPI_SS0#

SPI_SSn#

M821xx Data Sheet


When the transfer mode is transmit and receive (TMOD=2‘b00) or transmit only (TMOD=2‘b01), transfers are terminated by the shift control logic when the transmit FIFO is empty. For continuous data transfers, the user must ensure that the transmit FIFO buffer does not become empty before all the data has been transmitted. The transmit FIFO threshold level (see TXFLR), can be used to early interrupt the Applicatin and Control Processor, indicating that the transmit FIFO buffer is nearly empty. The user may also write a block of data (at least 2 FIFO entries) into the transmit FIFO before enabling a serial-slave. This ensures that serial transmission does not begin until the number of data frames that make up the continuous transfer are present in the transmit FIFO.

A typical software flow for completing a continuous serial transfer from the M821xx SPI interface to a serial-slave peripheral, when TMOD=2‘b00 or TMOD=2‘b01 is described as follows:

1. If the SPI interface is enabled, disable it by writing ‘0’ to SSIENR.2. Write to the CTRL0 register, setting the frame format, transfer mode, data frame size, and so on.3. Set the baud rate of the serial transfer by writing to the BAUDR register.4. Not Used. (If the serial protocol is Microwire, set Microwire transfer options by writing to MWCR

register.)5. Set the transmit and receive FIFO threshold levels by writing to the TXFTLR and RXFTLR registers.6. Enable the target slave by writing to the SER register.7. Set the interrupt masks by writing the IMR register.8. Enable the SPI interface by writing ‘1’ to the SSIENR register.9. Fill the transmit FIFO with the data for serial transfer. The serial transfer will begin as soon as the first

data word is present in the transmit FIFO.10. Poll the BUSY bit by reading the SR register, or you can, use interrupts. If a transmit FIFO empty

interrupt request is made, write the transmit FIFO. If a receive FIFO full interrupt request is made, read the receive FIFO.

11. The transfer is stopped by the shift control logic when the transmit FIFO is empty. When the transfer is done, the BUSY status is reset to 0.

12. Read the receive FIFO until empty— if TMOD!= 2‘b01.

When the transfer mode is receive only (TMOD=2‘b10), a serial transfer is started by writing one “dummy” data word into the transmit FIFO when a serial-slave is elected.

If the serial transfer is continuous, this same data word is retransmitted until the serial transfer is completed.

The transmit FIFO is popped only once at the beginning and may remain empty for the duration of the serial transfer. The end of the serial transfer is controlled by the number of frames (NDF) field in control register 1 (CTRLR1). If for example the user wishes to receive 24 data frames from a serial-slave peripheral, the NDF field should be programmed with the value 23. The receive logic will terminate the serial transfer when the number of frames received is equal to the NDF value + 1.

This transfer mode increases the bandwidth of the internal Comcerto peripheral bus because the transmit FIFO will never need to be serviced during the transfer. The receive FIFO buffer should be read each time the receive FIFO generates a FIFO full interrupt request to prevent an overflow. The receive FIFO threshold level (RXFTLR) can be used to give early indication that the receive FIFO is nearly full.

A typical software flow for completing a continuous serial transfer from the SPI interface to a serial-slave peripheral, when TMOD=2‘b10, is described as follows.

1. If the SPI interface is enabled, disable it by writing ‘0’ to the SSIENR register.2. Write to the CTRLR0 register, setting the frame format, transfer mode, data frame size, and so on.3. Set the baud rate of the serial transfer by writing to the BAUDR register.

M821xx Data Sheet


4. Not used. (If the serial protocol is Microwire, set Microwire transfer options by writing to MWCR register.)

5. Set the transmit and receive FIFO threshold levels by writing to the TXFTLR and RXFTLR registers.6. Set the NDF field in control register 1 (CTLR1) to the number of data frames that are to be received

(1).7. Set the interrupt masks by writing the IMR register.8. Enable the target slave by writing to the SER register.9. Enable the SPI interface by writing ‘1’ to the SSIENR register.10. Write a dummy data word into the transmit FIFO. Serial transfers begin as soon as the word is

present in the transmit FIFO.11. Poll the BUSY signal by reading the SR register. If a receive FIFO full request is made, read the

receive FIFO.12. The transfer is stopped by the shift control logic when the number of words received is equal to NDF–

1. When the transfer is done, the BUSY status is reset to 0.13. Read the receive FIFO until empty.

M821xx Data Sheet


Figure 19-6 shows a typical software flow for starting a SPI master serial transfer.

Figure 19-6 SPI block Master Transfer Flow

SSIENRSSIENR

Hardware flow inside the SPI block.

SSIENR

Software Flow

M821xx Data Sheet


19.9 SPI Clock Polarity and Phase SettingsWith the SPI, the clock polarity (SCPOL) determines whether the inactive state of the serial clock is high or low. To transmit data, both SPI devices must have identical SCPH (serial clock phase) and SCPOL values. In the Comcerto M821xx SPI interface, these values are set in the CTLR0 register. The data frame can be 4 to 16 bits in length. When the SCPH = 0, data transmission begins on the falling edge of the slave select signal. The first data bit is captured by the master and slave peripherals on the first edge of the serial clock, therefore, valid data must be present on the txd and rxd lines prior to the first serial clock edge. Figure 19-7 shows a timing diagram for a single SPI data transfer with SCPH = 0. The serial clock is shown for SCPOL = 0 and SCPOL = 1.

The following signals are illustrated in the timing diagrams in this section:

• sclk_out serial clock from the SPI interface.• ss_n slave select signal from the SPI interface• txd transmit data line for the SPI interface• rxd receive data line for the SPI interface

As data transmission starts on the falling edge of the slave select signal when SCPH = 0, continuous data transfers require the slave select signal to toggle before beginning the next data frame. This is illustrated in Figure 19-8.

Figure 19-7 SPI Serial Format (SCPH = 0)

Figure 19-8 SPI Serial Format Continuous Transfers (SCPH = 0)

M821xx Data Sheet


When SCPH = 1, both master and slave peripherals begin transmitting data on the first serial clock edge after the slave select line is activated. The first data bit is captured on the second serial clock edge. During continuous data frame transfers, the slave select line may be held active low until the last bit of the last frame has been captured. Figure 19-9 shows the timing diagram for the SPI format when SCPH = 1.

Continuous data frames are transferred in the same as single frames, with the MSB of the next frame following directly after the least significant bit (LSB) of the current frame. The slave-select signal is held active for the duration of the transfer. Figure 19-11 shows the timing diagram for continuous SPI transfers when SCPH=1.

Figure 19-9 SPI Serial Format (SCPH = 1)

Figure 19-10 SPI Serial Format Continuous Transfer (SCPH = 1)

M821xx Data Sheet


19.10 Clock RatiosThe maximum frequency of the bit rate clock (sclk_out) is one-half the frequency of the internal bus, AHB. This allows the shift control logic to capture data on one clock edge of sclk_out and propagate data on the opposite edge; this is illustrated in Figure 19-11.

The sclk_out line only toggles when an active transfer is in progress. At all other times, it is held in an inactive state as defined by the serial protocol under which it operates. SCKDV is a programmable register holding any even value from 0 to 65,534. If SCKDV=0, sclk_out is disabled.

A summary of the frequency ratio restrictions between the bit-rate clock (sclk_out/sclk_in) and the internal Comcerto AHB clock are described as:

• Master: AHB clock >= 2 × (maximum Fsclk_out)

19.11 SPI RegistersFor a detailed description of registers, see Section 20.0 Serial Peripheral Interface (SPI) Registers on page 377.

Figure 19-11 Maximum sclk_out/AHB Ratio

AHB clock

.


20.0 Serial Peripheral Interface (SPI) Registers

20.1 RegistersThe following table provides the details of the SPI interface memory map. All registers in the SPI interface are addressed at 32-bit boundaries to remain consistent with the AHB bus. Where the physical size of any register is less than 32-bits wide, the upper unused bits of the 32-bit boundary are reserved. Writing to these bits will have no effect; reading from these bits will return zero.

NOTE: The memory addressing of the SPI configuration registers is offset from the base address: 0x 1009 8000.

Table 20-1 Memory Map of SPI block

Name Description Address Offset Width Reset Value

CTRLR0 Control Register 0 0x00 16 0x7

CTRLR1 Control Register 1 0x04 16 0x0

SSIENR SSI Enable Register 0x08 1 0x0

MWCR(3) Microwire Control Register 0x0C 1 0x0

SER Slave Enable Register 0x10 4 0x0

BAUDR Baud Rate Select 0x14 16 0x0

TXFTLR Transmit FIFO Threshold Level 0x18 3 0x0

RXFTLR Receive FIFO Threshold level 0x1C 3 0x0

TXFLR Transmit FIFO Level Register 0x20 4 0x0

RXFLR Receive FIFO Level Register 0x24 4 0x0

SR Status Register 0x28 7 0x0

IMR Interrupt Mask Register 0x2C 6 0x3F

ISR Interrupt Status Register 0x30 6 0x0

RISR Raw Interrupt Status Register 0x34 6 0x0

TXOICR Transmit FIFO Overflow Interrupt Clear Register

0x38 1 0x0

RXOICR Receive FIFO Overflow Interrupt Clear Register

0x3C 1 0x0

RXUICR Receive FIFO Underflow Interrupt Clear Register

0x40 1 0x0

MSTICR (2) Multi-Master Interrupt Clear Register

0x44 1 0x0

ICR Interrupt Clear Register 0x48 1 0x0

M821xx Data Sheet


Notes:

1. If the Data Register (DR) is accessed from an AHB master (such as a DMA controller or a processor), the AHB transfer type may be a burst. During AHB burst transfers, the address is incremented after each beat of the burst. To facilitate an AHB burst, read/write operation to the transmit or receive FIFO, the Data Register occupies 16 32-bit address locations of the memory map. Each of the 16-bit address locations are aliased to the DR; single accesses to the DR may use any of the 16-bit address locations.

2. Not enabled on the M821xx.

3. Used to support Microwire (not used on 821xx devices).

IDR Identification Register 0x58 32 Not affected by reset

N/A Reserved 0x5C N/A N/A

DR(1) Data Register 0x60 -0x9C 16 0x0

1.

Table 20-1 Memory Map of SPI block (Continued)

Name Description Address Offset Width Reset Value

M821xx Data Sheet


20.1.1 CTRLR0

Address Offset: 0x00

This register is used to control the serial data transfer. It is not possible to write to this register when the SPI interface is enabled (SSI_EN bit of the SSIENR register is set to 1). The SPI interface is enabled and disabled by writing to the SSIENR register.

NOTE: A read operation to an address location that contains unused bits results in a 0 value being returned on each of the unused bits.

Table 20-2 Control Register 0

Bits Name Direction Reset Description

15:12 Reserved R/W 0x0 Reserved.

11 SRL R/W 0x0 Shift Register Loop. Used for testing purposes only. When active internally, connects the transmit shift register output to the receive shift register input. 0 - Normal Mode Operation 1 - Test Mode Operation

10 SLV_OE R/W 0x0 Slave Output Enable. Used to enable the txd line for the slave device. This is useful when the master is transmitting data to all slave devices (broadcast mode). Only one slave may respond with data on the master's rxd line. This bit is enabled after reset and must be disabled by software (when broadcast mode is used) if user does not want this device to respond with data. 0 - Slave txd is enabled 1 - Slave txd is disabled

9:8 TMOD R/W 0x0 Transfer Mode. Used to select the mode of transfer for serial communication. This field does not affect the transfer's duplex. Only indicates whether the receive/transmit data is valid. In “transmit only” mode, data received from the external device is not valid and is not stored into the receive FIFO memory. It is overwritten on the next transfer. In “receive only” mode, transmitted data is not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer. In “transmit and receive” mode, both transmit and receive data are valid. The transfer will continue until the transmit FIFO is empty. Data received from the external device is stored into the receive FIFO memory, where it can be accessed by the host processor. 00 - Transmit & Receive 01 - Transmit Only 10 - Receive Only 11 - Reserved

7 SCPOL R/W 0x0 Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock. The serial clock is held inactive when the SPI block master is not actively transferring data on the serial bus. 0 - Inactive state of serial clock is low 1 - Inactive state of serial clock is high

M821xx Data Sheet


6 SCPH R/W 0x0 Serial Clock Phase.Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0, data is captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data is captured on the second edge of the serial clock.0 - Serial Clock toggles in the middle of the first data bit 1 - Serial Clock toggles at the start of the first data bit

5:4 FRF R/W 0x0 Frame Format. Used to select which serial protocol is used to transfer the data. 00 - Motorola SPI 01 - Reserved.10 - Reserved.11 - Reserved

3:0 DFS R/W 0x7 Data Frame Size. Used to select the data frame length. When the data frame size is programmed to be less than 16 bits, the receive data is automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. Transmit data must be right-justified by the user before writing into the transmit FIFO. The transmit logic will ignore the upper unused bits when transmitting the data. Refer to Table 20-3 for the field decode.

Table 20-3 DFS Decode

DFS Value Description

0000 Reserved - undefined operation



0011 4-bit serial data transfer













Table 20-2 Control Register 0 (Continued)


M821xx Data Sheet


20.1.2 CTRLR1Address offset: 0x04

Control register 1 is used to control the end of serial transfers when in “receive only” mode. It is not possible to write to this register when the when the SPI block is enabled (SSI_EN bit of the SSIENR register is set to 1). The SPI block is enabled and disabled by writing to the SSIENR register.

Table 20-4 Control Register 1


15:0 NDF R/W 0x0 Number of Data Frames. Hardware disables the user from writing zero into this register field. For example, LSB = 1. When TMOD = 2'b10, this register field is used to set the number of data frames to be received continuously by the SPI interface. The SPI interface will continue to receive serial data until the number of data frames received is equal to this register value. This allows the user to receive up to 64 KB of data in a continuous transfer.

M821xx Data Sheet


20.1.3 SSIENRAddress offset: 0x08

This register is used to enable and disable the SPI interface.

20.1.4 MWCR

Address offset: 0x0C

This register is used to control the direction of the data word for the half-duplex Microwire serial protocol. It is not possible to write to this register when the SPI interface is enabled (SSI_EN bit of the SSIENR register is set to 1). The SPI interface is enabled and disabled by writing to the SSIENR register.

Table 20-5 SSIENR Register


1 SSI_EN R/W 0x0 SSI Enable. Used to enable and disable all SPI interface operations. When disabled, all serial transfers are halted immediately. Transmit and receive FIFO buffer are cleared when the device is disabled. It is not possible to program some of the SPI interface control registers when enabled.

NOTE: This register is used to support Microwire (not supported by the 821xx).

Table 20-6 MWCR Register


1 MDD R/W 0x0 Microwire Control. Used to define the direction of the data word when the Microwire serial protocol is used. When this bit is set to zero, the data word is received by the SPI block from the external serial device. When this bit is set to one, the data word is transmitted from the SPI block to the external serial device.

0 MWMOD R/W 0x0 Microwire Transfer Mode. Defines whether the Microwire transfer is sequential or non-sequential. When sequential mode is used, only one control word is needed to transmit or receive a block of data words. When non-sequential mode is used, there must be a control word for each data word that is transmitted or received. 0: non-sequential transfer 1: sequential transfer

M821xx Data Sheet


20.1.5 SERAddress offset: 0x10

The register is used to enable the individual slave select output lines from the SPI interface. Up to 16 slave-selects are available through the use of external logic. The user cannot write to this register when SPI interface is busy and when SSI_EN = 1.

20.1.6 BAUDRAddress offset: 0x14

The register is used to derive the frequency of the serial clock that regulates the data transfer. The 16-bit field in this register defines the AHB divider value. It is not possible to write to this register when the SPI interface is enabled (SSI_EN bit of the SSIENR register is set to 1). The SPI interface is enabled and disabled by writing to the SSIENR register.

Table 20-7 Slave Enable Register


31:4 Reserved N/A N/A Reserved

3:0 SER R/W 0x0 Slave Select Enable Field. This field is used to select serial slaves on the bus. Each bit in this field corresponds to one of the slave select outputs on the device: SPI_SS(3:0)#. External logic may be used to derive 16 slave selects. 0 - Not Selected 1 - Selected

Table 20-8 Baud Rate Select Register


15:0 SCKDV R/W 0x0 SSI Clock Divider. The LSB for this field is always set to 0 and is unaffected by a write operation. This ensures an even value is held in this register. If the value is zero, the serial output clock (sclk_out) is disabled. The frequency of the sclk_out is derived from the following equation: Fsclk_out = AHB clock / SCKDV where SCKDV is any even value between 2 and 65534. For example, for AHB clock = 3.6864MHz and SCKDV =2 Fsclk_out = 3.6864/2 = 1.8432MHz NOTE: Typically AHB Clock = 165 MHz.

M821xx Data Sheet


20.1.7 TXFTLRAddress offset: 0x18

This register is used to control the threshold value for the transmit FIFO memory. Writing to this register when the SPI interface is enabled (SSI_EN in CTRLR0 is logic 1) will have no effect. The user must disable the SPI interface before attempting to write to this register.

Table 20-9 Transmit FIFO Threshold Level Register



2:0 TXFTLRL R/W 0x0 Transmit FIFO Threshold. Used to control the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. The FIFO depth is set at 8 (thus TX_ABW = 0x3); this register is sized to the number of address bits needed to access the FIFO. If the user attempts to set this value greater than or equal to the depth of the FIFO, this field will not be written and will retain its current value. When the number of transmit FIFO entries is less than or equal to this value, the transmit FIFO empty interrupt is triggered. Refer to Table 20-10 for field decode.

Table 20-10 TXFTLR Decode

TXFTLRL Value Description

0000_0000 ssi_txe_intr is asserted when 0 valid data entries are present in the receive FIFO

0000_0001 ssi_txe_intr is asserted when 1 or less valid data entry is present in the receive FIFO







M821xx Data Sheet


20.1.8 RXFTLRAddress offset: 0x1C

This register is used to control the threshold value for the receive FIFO memory. Writing to this register when the SPI interface is enabled (SSI_EN in CTRLR0 is logic 1) will have no effect. The user must disable the SPI interface before attempting to write to this register.

20.1.9 TXFLRAddress offset: 0x20

This register contains the number of valid data entries in the transmit FIFO memory.

Table 20-11 Receive FIFO Threshold Level Register



2:0 RXFTLRL R/W 0x0 Receive FIFO Threshold. Used to control the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is set at 8 (thus RX_ABW = 0x3). This register is sized to the number of address bits needed to access the FIFO. If the user attempts to set this value greater than the depth of the FIFO, this field will not be written and will retain its current value. When the number of receive FIFO entries is greater than or equal to this value + 1, the receive FIFO full interrupt is triggered. Refer to Table 20-12 for field decode.

Table 20-12 RXFTLR

TXFTLRL Value Description

0000_0000 ssi_rxf_intr is asserted when 1 or more valid data entry is present in the receive FIFO

0000_0001 ssi_rxf_intr is asserted when 2 or more valid data entries are present in the receive FIFO






0000_0111 ssi_rxf_intr is asserted when 8 valid data entries are present in the receive FIFO.

Table 20-13 Transmit FIFO Level Register



3:0 TXTFL R 0x0 Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. FIFO depth is 8, thus TX_ABW = 3.

M821xx Data Sheet


20.1.10 RXFLRAddress offset: 0x24

This register contains the number of valid data entries in the transmit FIFO memory. This register can be read at any time.

20.1.11 SRAddress offset: 0x28

This is a read only register used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. The status register may be read at any time. None of the bits in this register request an interrupt.

Table 20-14 Receive FIFO Level Register



3:0 RXTFL R 0x0 Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. FIFO depth is 8, thus RX_ABW = 3.

Table 20-15 SSI Status Register


5 TXE R 0x0 Transmission Error. Set if the transmit FIFO is empty when a transfer is started. This bit can only be set when the SPI interface is configured as a slave device. Data from the previous transmission is resent on the txd line. This bit is cleared when read. 0 - No error 1 - Transmission error

4 RFF R 0x0 Receive FIFO Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more entries that do not contain valid data, this bit is cleared. This bit field does not request an interrupt. 0 - Receive FIFO is not full 1 - Receive FIFO is full

3 RFNE R 0x0 Receive FIFO Not Empty.Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO. 0 - Receive FIFO is empty 1 - Receive FIFO is not empty

2 TFE R 0x1 Transmit FIFO Empty. When the transmit FIFO is completely empty, this bit is set. When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0 - Transmit FIFO is not empty1 - Transmit FIFO is empty

M821xx Data Sheet


20.1.12 IMRAddress offset: 0x2C

This read/write register is used to mask or enable all interrupts generated by the SPI interface.

1 TFNF R 0x1 Transmit FIFO Not Full. Set when the transmit FIFO contains one or more entries that do not contain valid data and is cleared when the FIFO is full. This bit can be polled by software to completely fill the transmit FIFO. 0 - Transmit FIFO is full 1 - Transmit FIFO is not full

0 BUSY R 0x0 SSI Busy Flag. When set, indicates that a serial transfer is in progress; when cleared indicates that the SPI interface is idle or disabled. 0 - SPI interface is idle or disabled 1 - SPI interface is actively transferring data

Table 20-16 Interrupt Mask Register



5 Reserved N/A 0x1 Reserved.

4 RXFIM R/W 0x1 Receive FIFO Full Interrupt Mask 0 - ssi_rxf_intr interrupt is masked 1 - ssi_rxf_intr interrupt is not masked

3 RXOIM R/W 0x1 Receive FIFO Overflow Interrupt Mask 0 - ssi_rxo_intr interrupt is masked 1 - ssi_rxo_intr interrupt is not masked

2 RXUIM R/W 0x1 Receive FIFO Underflow Interrupt Mask 0 - ssi_rxu_intr interrupt is masked 1 - ssi_rxu_intr interrupt is not masked

1 TXOIM RW 0x1 Transmit FIFO Overflow Interrupt Mask 0 - ssi_txo_intr interrupt is masked 1 - ssi_txo_intr interrupt is not masked

0 TXEIM RW 0x1 Transmit FIFO Empty Interrupt Mask0 - ssi_txe_intr interrupt is masked 1 - ssi_txe_intr interrupt is not masked

Table 20-15 SSI Status Register (Continued)


M821xx Data Sheet


20.1.13 ISRAddress offset: 0x30

This register reports the status of the SPI interface interrupts after they have been masked.




4 RXFIS R 0x0 Receive FIFO Full Interrupt Status 0 = ssi_rxf_intr interrupt is not active after masking1 = ssi_rxf_intr interrupt is full after masking

3 RXOIS R 0x0 Receive FIFO Overflow Interrupt Status 0 = ssi_rxo_intr interrupt is not active after masking1 = ssi_rxo_intr interrupt is active after masking

2 RXUIS R 0x0 Receive FIFO Underflow Interrupt Status 0 = ssi_rxu_intr interrupt is not active after masking1 = ssi_rxu_intr interrupt is active after masking

1 TXOIS R 0x0 Transmit FIFO Overflow Interrupt Status 0 = ssi_txo_intr interrupt is not active after masking 1 = ssi_txo_intr interrupt is active after masking

0 TXEIS R 0x0 Transmit FIFO Empty Interrupt Status 0 = ssi_txe_intr interrupt is not active after masking1 = ssi_txe_intr interrupt is active after masking

M821xx Data Sheet


20.1.14 RISRAddress offset: 0x34

This read only register reports the status of the SPI interface interrupts prior to masking.

20.1.15 TXOICRAddress offset: 0x38

Table 20-18 Raw Interrupt Status Register



4 RXFIR R 0x0 Receive FIFO Full Raw Interrupt Status 0 = ssi_rxf_intr interrupt is not active prior to masking1 = ssi_rxf_intr interrupt is active prior to masking

3 RXOIR R 0x0 Receive FIFO Overflow Raw Interrupt Status0 = ssi_rxo_intr interrupt is not active prior to masking 1 = ssi_rxo_intr interrupt is active prior masking

2 RXUIR R 0x0 Receive FIFO Underflow Raw Interrupt Status0 = ssi_rxu_intr interrupt is not active prior to masking 1 = ssi_rxu_intr interrupt is active prior to masking

1 TXOIR R 0x0 Transmit FIFO Overflow Raw Interrupt Status 0 = ssi_txo_intr interrupt is not active prior to masking 1 = ssi_txo_intr interrupt is active prior masking

0 TXEIR R 0x0 Transmit FIFO Empty Raw Interrupt Status 0 = ssi_txe_intr interrupt is not active prior to masking 1 = ssi_txe_intr interrupt is active prior masking

Table 20-19 Transmit FIFO Overflow Interrupt Clear Register


0 TXOICR ROR 0x0 Clear Transmit FIFO Overflow Interrupt. This register will reflect the status of the interrupt. A read from this register clears the ssi_txo_intr interrupt; writing has no effect.

.


21.0 TDM Bus Interface Description

The TDM Bus interface provides a full-duplex, serial time-division multiplexed (TDM) bus for digital data transfer between the Network Interface Device (e.g., T1/E1 Framer, Time Slot Interchanger, etc.) and the Mindspeed Comcerto Device. This section presents TDM Bus features, functional description, and interface timing. For a view of the TDM interface within the top-level block diagram, see Figure 2-1.

Also included in this TDM bus interface description is an overview of the TDM DMA block (TDMA) which buffers data flowing beteen the TDM Bus Interface and the M821xx’s internal AHB (AMBA Advanced High Performance Bus). Section 22.0 TDM Registers details registers in both the TDM Bus Interface and the TDM DMA block.

21.1 Features• Full-duplex, serial time division multiplexed bus for digital transfer with network interface device (e.g.

T1/E1 framer, time slot interchanger etc.)

• A single TDM bus providing a maximum of 24/32/64/128 time slots (running at 1.536 or 1.544 MHz, 2.048 MHz, 4.096 MHz, or 8.192 MHz, accordingly), or any configured number when running off another clock

• Clock rate can be x1 or x2 data rate (going up 16.384 MHz for x2). In x2 mode, data is sampled every 2 clock cycles. This mode enables compliancy with H.100 and H.110

• Provides a programmable timing parameters interface

• Data can optionally not be driven during inactive timeslot

• Internal loopback of TDM DX to TDM DR (uses TDM_CK and TDM_FS)

• External loopback of TDM DR to TDM DX ( see Section 21.6 TDM Loopback Timing)

NOTE: Slower CLK frequencies can be used, for fewer timeslots.For example:4096 MHz for 64 timeslots per bus.2048 MHz for 32 timeslots per bus.1544 MHz for 24 timeslots per bus.

NOTE: TDM_CK and TDM_FS must be stable and within specification before reset signal to the TDM block ends.

M821xx Data Sheet


21.2 Signal DescriptionThe TDM timing signals: Clock and Frame Sync, may be sourced by the M821xx device or received from the network. The source of Clock is determined by the logic level of the TM_TDM_CLKSRC_EN input when it is latched at device reset. The source of Frame Sync is determined by a register in the GPIO block ( see Table 30-5).

Table 21-1 M821xx TDM Signals

21.3 Functional DescriptionThe TDM bus supports speeds of 1.536 MHz to 8.192 MHz, allowing between 24 and 128 timeslots. The device processing throughput is not designed to uphold processing of this many active channels. Dual rate clock is also supported (up to 16.384 MHz), where data is held for 2 clock cycles. Support is also included for 1.544 MHz clock (193 bit frame) through configuration allowing ignore of the first bit in a frame.

The TDM interface can be set to support both internal and external loopback testing through a GPIO register setting (see Table 30-4).

The parameters of the TDM bus are configurable. The FS, DX, and DR can be sampled on falling or rising edges controlled by parameters FE , XCE and RCE respectively. Data transmission can begin on any clock cycle relative to cycle 0 by programming the appropriate cycle value in the CYCX and CYCR parameters; and the interface can operate in single-clock or double-clock mode where one data bit is transmitted or received every TDM_CK period or every two TDM_CK periods.

The TDM DMA block (TDMA) manages the flow of data between the TDM bus interface and external system memory via the AMBA Advance High Peformance Bus and the DDR SDRAM controller. Both the TDM bus interface and the TDMA registers are configured via the AMBA Advanced Peripheral Bus (APB). Registers for both blocks are described in Section 22.0 TDM Registers.

Signal Name Dir. Description

TDM_CK B Data clock input from network, or from device if it is the source of the clock.

TDM_FS B Frame synchronization input from the network or from device.

TDM_DX O Data transmit from the device.

TDM_DR I Data receive input from the network.

NOTE: When the M821xx is configured to outputTDM_CK, this signal will stop toggling when the system puts the device into hard reset by asserting RESET_N.

M821xx Data Sheet


21.4 TDM Bus Interface TimingFigure 10-1 through Figure 10-8 show show the TDM Bus timing and how clock edges are counted in cycles. Cycles are defined as always beginning (with cycle 0) on the rising TDM_CK edge relative to the clock edge on which TDM_FS is sampled. Data transmission can begin on any clock cycle relative to cycle 0 by programming the appropriate cycle value in the CYCX parameter in the Transmitter Operating Configuration Register and CYCR parameter in the Receiver Operating Configuration Register. Each TDM Bus interface can operate in single-clock or double-clock mode. One data bit is transmitted or received every TDM_CK period or every two TDM_CK periods as programmed by the CMSX bit in the Transmitter Operating Configuration Register and CMSR bit in the Receiver Operating Configuration Register.

For additional information, refer to the following Application Note - Recommended H.100 TDM Timing Example for the M826xx Device App Note (826xx-APP-003).

Figure 21-1 Transmit Timing (FE = 1, CMSX = 0)

TDM_FS

TDM_DX(XCE=1)

TDM_DX(XCE=0)

TDM_CK

3-STATE

3-STATE

FIRST TRANSMIT BIT OFTHE FRAME IF

TRANSMITTING ONRISING OR FALLING

EDGE WHEN CYCX=1

CYCLE 0 CYCLE1

FS SAMPLED ON THIS EDGE (FE=1)

M821xx Data Sheet



Figure 21-3 Received Timing (FE = 1, CMSR = 0)


TDM_CK

TDM_FS

TDM_DX(XCE=1)

TDM_DX(XCE=0)

CYCLE 0 CYCLE1



EDGE WHEN CYCX=1

3-STATE

3-STATE

DON'T CARE

TDM_CK

TDM_FS

TDM_DR(RCE=1)

TDM_DR(RCE=0)

CYCLE 0 CYCLE1


FIRST RECEIVED BIT OFFRAME WHEN CYCR=0

DON'T CARE

M821xx Data Sheet




DON'T CARE


TDM_CK

TDM_FS

TDM_DR(RCE=1)

TDM_DR(RCE=0)

CYCLE 0 CYCLE1

FIRST RECEIVED BIT OFFRAME WHEN CYCR=0

DON'T CARE

TDM_CK

TDM_FS

TDM_DX(XCE=1)

TDM_DX(XCE=0)

CYCLE -1 CYCLE 0

3-STATE

3-STATE




EDGE WHEN CYCX=0

M821xx Data Sheet




TDM_CK

TDM_FS

TDM_DX(XCE=1)

TDM_DX(XCE=0)

CYCLE -1 CYCLE 0

3-STATE

3-STATE




EDGE WHEN CYCX=0


DON'T CARE

TDM_CK

TDM_FS

TDM_DR(RCE=1)

TDM_DR(RCE=0)

FIRST RECEIVED BIT OFFRAME WHEN CYCR= -1

CYCLE -1 CYCLE 0

DON'T CARE

M821xx Data Sheet



TDM_CK

TDM_FS

TDM_DR(RCE=1)

TDM_DR(RCE=0)


DON'T CARE

FIRST RECEIVED BIT OFFRAME WHEN CYCR=-1

CYCLE -1 CYCLE 0

DON'T CARE

M821xx Data Sheet


21.5 TDM Interface TimingThe TDM Interface timing parameters are programmable, and can be configured for H.100, H110, and H-MVIP bus standards using the SUPVSR_SET_TDM_PARAMS message (described in the Comcerto 800 Command Reference Manual).

Figure 21-9 TDM Bus Timing

Table 21-2 TDM Bus Timing


Clock edge rate (All Clocks) 0.25 2 V/ns 1

Tcp CK Clock Period1:1 clock to data rate ratio2:1 clock to data rate ratio

12261

ns

Tch CK Clock Duty Cycle 40 60 %

Tfs Frame Synch Input Setup Time 20 ns 4, 5, 6

Tfh Frame Synch Input Hold Time 20 ns 4, 5, 6

Tdis DR Input Setup Time 25 ns 3, 4

Tdih DR Input Hold Time 4 ns 2, 4

Tdod DX/FS Output Delay Time — 20 ns 2,4,6

Tdoh DX/FS Output Hold Time 0 ns 2,4,6

Tdoz DX Output Hi Z Time 2 20 ns 2,4,6

TDM_CK

TDM_FS

TDM_DR

TDM_DX

Tfs Tfh

Tdsh Tdih

Tdod Tdoh

Tdoz

M821xx Data Sheet


21.6 TDM Loopback TimingThis is an external, remote loopback. When it is enabled TDM_DR is looped back to TDM_DX without any sampling.

Table 21-3 TDM Loopback Setup and Hold Times

21.7 H.100 TDM Timing Example Using TDM_CK = 2 Cycles per BitPlease refer to the Recommended H.100 TDM Timing Example for the M826xx Device App Note (826xx-APP-003).

NOTES:1. The rise and fall times are determined by the edge rate in V/ns. A “Max” edge rate is the fastest rate at which a clock

transitions. 2. Measured at the transmitter.3. Measured at the receiver.4. Please note that all inputs can be programmed to be sampled at either rising or falling edge of the clock. All outputs can be

independently programmed to be generated at either rising or falling edge of the clock5. Please note that the Frame Synch can be programmed as either active low or active high. 6. TDM_FS may be either input or output. If input, Tfs and Tth apply. If output, Tdod and Tdoh apply.

Figure 21-10 TDM Loopback Timing Diagram


Tdel Input to output delay 2 — 20 ns

Table 21-2 TDM Bus Timing (Continued)


Inputs

Outputs

Tdel

.


22.0 TDM Registers

22.1 IntroductionThis section presents registers in both the TDM Bus Interface and the TDMA blocks. Both register sets are accessible via the AMBA Advanced Peripheral Bus (APB).

22.2 TDM Bus Interface RegistersTDM port accommodates up to 128 TDM time slots. All registers are accessible (from lowest byte) as a long word (32 bits).

22.2.1 Network Frame Parameters 0x04 - 0x07 R/WTable 22-1 Network Frame Parameter Register

NOTE: The memory addressing of the TDM configuration registers is offset from the base address: 0x 1000 0000.

Bit Number Name Description

31 LOOPBACKEN Enable TDM port to loop back internally with TDM clock is divided by four from system clock.


15 RGFE Frame Edge, when set indicated sampled on clock rising edge.

14 RGFEINV Inverted Frame Signal, when set indicate inverted frame.

0-12 RGCPF Cycles Per Frame, (Number of time slot times 8 ) – 1

M821xx Data Sheet


22.2.2 Transmitter Operating Configurations 0x10 - 0x13 R/WTable 22-2 Transmitter Operating Configurations

22.2.3 Transmitter Active Slot Selections 0x14 - 0x17 R/WTable 22-3 Transmitter Active Slot Selections

22.2.4 Transmitter Active Slot Selections 0x18 - 0x1B R/WTable 22-4 Transmitter Active Slot Selections



18 RGXIXEN Transmitter Enable, set when enable driving of TDMDX

17 RGXICMSX Clock Mode Select, set for 2 clock per data bit

16 RGXIDIX Data Invert, set when transmitted data is inverted.

15 RGBOX Bit order, bit order, set when msb is transmitted first.

14 RGXIXCE Clock Edge, set when data is transmitted on rising edge

0-13 RGCYCX Number of cycles delay from rising edge of frame.


24-31 RGXIACT(24..31) Active Transmit Time Slot 24 to 31, set when channel is active









M821xx Data Sheet


22.2.5 Transmitter Active Slot Selections 0x1C - 0x1F R/WTable 22-5 Transmitter Active Slot Selections

22.2.6 Transmitter Active Slot Selections 0x20 - 0x23 R/WTable 22-6 Transmitter Active Slot Selections











M821xx Data Sheet


22.2.7 Receiver Operating Configurations 0x30 - 0x33 R/WTable 22-7 Receiver Operating Configurations

22.2.8 Receiver Active Slot Selections 0x34 - 0x37 R/WTable 22-8 Receiver Active Slot Selections

22.2.9 Receiver Active Slot Selections 0x38 - 0x3B R/WTable 22-9 Receiver Active Slot Selections


18-31 Reserved

18 RGRIREN Receiver Enable, set when enable driving of TDMDX

17 RGRICMSR Clock Mode Select, set for 2 clock per data bit

16 RGRIDIR Data Invert, set when received data is inverted.

15 RGBOR Bit order, bit order, set when msb is received first.

14 RGRIRCE Clock Edge, set when data is received on rising edge

0-13 RGCYCR Number of cycles delay from rising edge of frame.


24-31 RGRIACT(24..31) Active Receive Time Slot 24 to 31, set when channel is active









M821xx Data Sheet


22.2.10 Receiver Active Slot Selections 0x3C - 0x3F R/WTable 22-10 Receiver Active Slot Selections

22.2.11 Receiver Active Slot Selections 0x40 - 0x43 R/WTable 22-11 Receiver Active Slot Selections











M821xx Data Sheet


22.3 TDMA RegistersTDMA registers are accessible over the APB bus (from lowest byte) as long words (32 bits).

22.3.1 Memory Segment0x0000 R/W]Table 22-12 Memory Segment Register

22.3.2 Rx DMA Enable0x0004 R/WTable 22-13 Rx DMA Enable

22.3.3 Tx DMA Enable0x0008 R/WTable 22-14 Tx DMA Enable

NOTE: The memory addressing of the TDMA configuration registers is offset from the base address: 0x 1002 0000.

Bit No. Name Description

31 - 8 Reserved Unused = 0

7 - 0 MEMSEG Memory Segment. It is memory address bit 31 to 24.

BIT No. Name Description

31 - 1 Unused = 0

0 TDMRXDMAEN Enable DMA Controller to request for AHB bus. When this bit is on, APB accesses to the Rx Buffer will be blocked.


31 - 1 Unused = 0

0 TDMTXDMAEN Enable DMA Controller to request for AHB bus. When this bit is on, APB accesses to the Tx Buffer will be blocked.

M821xx Data Sheet


22.3.4 IRQ2TDMA Interrupt Status0x000C R/WTable 22-15. IRQ2TDMA Interrupt Status

22.3.5 IRQ2TDMA Interrupt Enable0x0010 R/WTable 22-16 IRQ2TDMA Interrupt Enable

22.3.6 TDM Block Size0x0020 R/WTable 22-17 TDM Block Size


31 - 4 Unused = 0

3 TxEMT Transmit Buffer Empty. Write a 1 to clear.

2 RxFUL Receive Buffer Full. Write a 1 to clear.

1 TxUDR Transmit Buffer Under run. Write a 1 to clear.

0 RxOVR Receive Buffer Overflow. Write a 1 to clear.


31 - 4 Unused = 0

3 TxEMT Enable the Transmit Buffer Empty signal to generate IRQ2TDMA

2 RxFUL Enable the Receive Buffer Full signal to generate IRQ2TDMA.

1 TxUDR Enable the Transmit Buffer Underrun signal to generate IRQ2TDMA.

0 RxOVR Enable the Receive Buffer Overflow signal to generate IRQ2TDMA.


31 - 10 Unused = 0

9 - 0 TDBLSZ TDM Block Size: Number of words - 1. Maximum 1K words. All channels use this register.

M821xx Data Sheet


22.3.7 Interrupt Size0x0024 R/WTable 22-18 Interrupt Size

22.3.8 Rx Word Pointers 0x0028 R/WTable 22-19 Rx Word Pointers

22.3.9 Tx Word Pointers0x002C R/WTable 22-20 Tx Word Pointers


31 - 10 Unused = 0

9 - 0 TDIRQSZ The number of words to be DMA transferred to or from memory before TDRxChk or TDTxChk interrupt is generated. The programmed value is the intended number of words minus 1. Maximum 1K words. A word is 32-bit for Low Latency mode and 64-bit for High Latency Mode.All channels use this register.


31 - 10 Unused = 0

9 - 0 TDRXPtr TDM word pointer for the Receive Buffer in the core memory. All Receive channels use this register. Maximum 1K words.This register can be written for testing purposes only.


31 - 10 Unused = 0

9 - 0 TDTXPtr TDM word pointer for the Transmit Buffer in the core memory. All Transmit channels use this register. Maximum 1K words.This register can be written for testing purposes only.

M821xx Data Sheet


22.3.10 Backward Compatibility Control 0x0030 R/WTable 22-21 Backward Compatibility Control

22.3.11 TDM Rx Channel Enable0x0060 – 0x006F R/WTable 22-22 TDM Rx Channel Enable

22.3.12 TDM Tx Channel Enable 0x0070 – 0x007F R/WTable 22-23 TDM Tx Channel Enable


31 - 2 Unused = 0

1 RSVD Reserved. Always clear to 0.

0 LATENCY 1: High Latency. DMA at every 8 frames. 0: Low Latency. DMA at every 4 frames. Default value.


127 - 0 TDRXCHEN Rx Channel Enable: One bit per channel. Channel 0 to 127. Set to enable, reset to disable.


127 - 0 TDTXCHEN Tx Channel Enable: One bit per channel. Channel 0 to 127. Set to enable, reset to disable.

M821xx Data Sheet


22.3.13 Channel 0 to 127 Receive Base Memory Address Registers 0x000 – 0x07F R/W

Do not write to these registers while any DMA is enabled. The safe way is to program all of these registers before enabling DMA (APB address 1002 0004 and 1002 0008). Note that the channels can be turned on or off by the Rx and Tx Channel Enable Registers.

Each of the 128 registers has the following format:

Table 22-24 Channel 0 to 127 Receive Base Memory Address Registers

To support wide channels, all channels that make up a wide channel must have the same TDRXBAS and thechannel numbers must be consecutive.

For example, if Channel 3, 4, and 5 make up a wide channel then they have the same value in the TDRXBAS field.The CHNW is 3 for all. The CHNCs are 0, 1, and 2 respectively.


31 - 28 Unused = 0.

27 - 26 CHNW Channel Width: Number of components belonged to this channel. Valid numbers are 1, 2, and 3.

25 - 24 CHNC Component Number: Valid numbers are 0, 1, and 2

23 - 2 TDRXBAS Base Address for the TDM Receive Buffer in the system memory. Word aligned. Bit 2 is 0 at High-Latency mode.

1 - 0 Unused = 0.

M821xx Data Sheet


22.3.14 Channel 0 to 127 Transmit Base Address Register0x0200 – 0x007F R/W

Do not write to these registers while any DMA is enabled. The safe way is to program all of these registersbefore enabling DMA (APB address 1002 0004 and 1002 0008). Note that the channel can be turned on or off bythe Rx and Tx Channel Enable.

Each of the 128 registers has the following format:

Table 22-25 Transmit Base Address Register

To support wide channels, all channels that make up a wide channel must have the TDTXBAS and the channelnumbers must be consecutive.

For example, if Channel 3, 4, and 5 make up a wide channel then they have the same value in the TDTXBAS field.The CHNW is 3 for all. The CHNCs are 0, 1, and 2 respectively.

22.3.15 Rx Look-up Table0x0400 – 0x047F and 0x0C00 - 0x0C7FEach of these 128 registers has the following format:

Table 22-26 Rx Look-Up Table


31 – 28 Unused = 0

27 – 26 CHNW Channel Width: Number of components belonged to this channel. Valid numbers are 1, 2, and 3.

25 – 24 CHNC Component Number: Valid numbers are 0, 1, and 2

23 – 2 TDTXBAS Base Address for the TDM Transmit Buffer in the system memory. Word aligned. Bit 2 is 0 at High-Latency mode.

1 – 0 Unused = 0


31 - 12 Unused = 0

11 - 4 CHNN Channel number: From 0 to 127

3 - 2 CHNW Channel Width: Number of components belonged to this CHNN channel. Valid numbers are 1, 2, and 3.


M821xx Data Sheet


22.3.16 Tx Look-up Table0x600 – 0x067F and 0x0E00 - 0x0E7F

Each of these 128 registers has the following format:

Table 22-27 Tx Look-up Table

22.3.17 Base Address RAM BIST 0x0014 ROTable 22-28 Base Address RAM BIST


31 - 12 Unused = 0

11 - 4 CHNN Channel number: From 0 to 127

3 - 2 CHNW Channel Width: Number of components belonged to this CHNN channel. Valid numbers are 1, 2, and 3.



31 - 7 Unused = 0

6 BIST_START_RETURN Start return. Read only.

5 BIST_FAIL Fail. Read only bit.

4 BIST_DONE Done. Read only bit.

3 BIST_RESUME_RETURN Resume. Write only.

2 BIST_DEBUG Debug enable.

1 BIST_TEST Test enable.

0 BIST_RESET Reset.

M821xx Data Sheet


22.3.18 TDM RX Buffer RAM BIST0x0018 R/W]Table 22-29 RDM RX Buffer RAM BIST

22.3.19 TDM TX Buffer RAM BIST0x001C R/WTable 22-30 TDM TX Buffer RAM BIST


31 - 7 Unused = 0







0 BIST_RESET Reset.


31 - 7 Unused = 0







0 BIST_RESET Reset.

M821xx Data Sheet


22.3.20 Test RegistersAn APB host can access the TDM Rx and Tx buffers when the DMA is disabled. This feature provides a path to bypass DMA.

Table 22-31 Test Registers

Description APB Address in Hex Default value

TDM Rx Buffer, 1 K words 101D (n+0) 000 - FFF Undetermined

TDM Tx Buffer, 1 K words 101D (n+1) 000 - FFF Undetermined

.


23.0 Universal Asynchronous Receiver Transmitter (UART)

This section describes the Comcerto M821xx standard (WD16550 compatible) UART and provides details to support software driver developers. For a view of the Clock / Reset block within the top-level block diagram, see Figure 2-1.

23.1 IntroductionThe M821xx devices provide two UART interfaces, with FIFOs. Only the Rx and Tx signals are provided which can be connected to an RS232 driver for standard serial port operation. The UART Interfaces provide a useful Console Port and can also be used as a software debug port.

The UART module contains two programmable blocks that are modeled after the industry-standard 16550. This section provides the interface register details and explains how to use the UART features in an application. The ‘application’ here refers to the software executing on the Application and Control Processorthat is responsible for initializing and managing data transfer on the UART.

23.2 Features • Two UARTs Modeled after the industry standard 16550 architecture.

• Asynchronous mode.

• The receiver is normally programmed to automatically determine the baud rate of the transmitter. The receiver relocates the center of the start bit of each new word or byte. This feature enables the asynchronous mode to operate without sharing the actual baud rate clock.

• Transmitter adds start, stop, parity bits to the serial data.

• Receiver rejects false start bits.

• 5, 6, 7, or 8 bit characters.

• Even, odd, or no parity bit generation or detection.

• 1 or 2 stop bit generation, programmable short stop bit control.

• Transmitter buffer empty flag or under-run status generation.

• Receiver buffer full detection.

• Receiver status error flags: over-run, parity, frame, and break interrupt.

• FIFO depth of 16 bytes.

• Internal loopback from TX to RX.

M821xx Data Sheet


23.3 Functional DescriptionThe M821xx UART serial receives and transmits data to a peripheral. The transmitter performs the parallel to serial conversion adding start, stop, and parity bits to the serial data. The receiver uses the stop/start transition to approximate the center of the data, parity, and stop bits that follow.

In the asynchronous mode, the transmitter and receiver are set to operate at a given baud rate from a table of standard baud rates. Other than the baud information, no clock is passed between them. The receiver is normally programmed to automatically determine the baud rate of the transmitter. Absolute baud rate accuracy is not required because the receiver relocates the center of the start bit of each new word or byte. It is this feature that enables the asynchronous mode to operate without sharing the actual baud rate clock. The receiver rejects false start bits.

The asynchronous mode is programmable as follows:

• 5-, 6-, 7-, or 8-bit characters

• Even, odd, or no parity bit generation and detection

• 1 or 2 stop bit generation, programmable short stop bit control

• Transmitter buffer empty flag and under-run status generation

• Receiver buffer full detection

• Receiver status error flags: over-run, parity, frame and break interrupt

• Interrupt enable control bits

On the Rx direction, there is a read-only register (called RBR) containing the data byte (data character) received on the serial input port (SIN). there are also FIFOs on the receive side and the FIFOs can be enabled or disabled by software. When FIFOs are disabled, the data in RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. When FIFOs are enabled, RBR accesses the head of the receiver FIFO. If the receive FIFO is full and RBR is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur.

On the TX direction, there is a transmit holding register (called THR) that contains the data to be transmitted on the serial output port (SOUT). There are also FIFOs on the transmit side and FIFOs can be enabled or disabled by the software. When FIFOs are disabled, a single character will be written to THR when THR is empty. Any additional writes to the THR before it is empty again cause the previous data in THR to be overwritten. When FIFOs are enabled, data characters can be written to the transmit FIFO when it is not full. Any attempt to write data when the FIFO is full results in loosing the written data.

23.4 Signal DescriptionTable 23-1 M821xx UART Interface Signals

23.5 Register Address Map and DescriptionsFor register details, see Section 24.0 Universal Asynchronous Receiver Transmitter (UART) Registers on page 415.

Signal Name Dir. Size Signal Description

UART[1:0]_RX I 2 UART serial input.

UART[1:0]_TX O 2 UART serial output

.

821xx-DSH-002-F Mindspeed Technologies® 415Mindspeed Proprietary and Confidential

24.0 Universal Asynchronous Receiver Transmitter (UART) Registers

24.1 Register Address Map and Descriptions

The following tables summarize the register map for the dual UART interfaces.

NOTE: The memory addressing of the UART registers is offset from the base address: 0x 1009 0000 for UART00x 1009 4000 for UART1

Table 24-1 Register Bit Map

Reg 7 6 5 4 3 2 1 0

IER Reserved EDSSI ELSI ETBEI ERBFI

IIR FIFO Status (b)11 = FIFO Enabled00 = FIFO Disabled 0

Interrupt ID0000 = Modem Status Changed0001 = No interrupt pending0010 = THR empty0100 = Received Data available0110 = Receiver Status1100 = Character Time Out

FCR RCVR Trigger00=1 char in FIFO01=FIFO 1/4 full10=FIFO 1/2 full11=FIFO 2 less full

Reserved DMA Mode XMIT FIFO Reset

RCVR FIFO Reset

FIFO Enable

LCR DLAB Break Stick Parity (not used)

EPS PEN STOP bits0=1 bit1=2 bits

CLS00=5 bits01=6 bits10=7 bits11=8 bits

MCR Reserved Reserved LoopBack

OUT2 OUT1 RTS DTR

LSR RX FIFO Error TEMT (f) THRE (g) BI FE PE OE DR

MSR DCD RI DSR CTS DDCD TERI DDSR DCTS

M821xx Data Sheet


Table 24-2 UART 0 Register Map

DLABa Address Access Name Abbreviation

0 0x10090000 Read only Receive Buffer Register RBR

0 Write-only Transmit Holding Register THR

1 Read/write Divisor Latch (Low) DLL

0 0x10090004 Read/write Interrupt Enable Register IER

1 Read/write Divisor Latch (High) DLH

X 0x10090008 Read only Interrupt Identity Register IIR

X Write-only FIFO Control Register FCR

X 0x1009000c Read/write Line Control Register LCR

X 0x10090010 Read/write Modem Control Register MCR

X 0x10090014 Read only Line Status Register LSR

X 0x10090018 Read only Modem Status Register MSR

X 0x1009001c Read/write Scratch Register SCR

Note:(a) The Divisor Latch Address Bit (DLAB) is bit 7 of the Line Control Register (LCR). It enables reading and writing of the Divisor Latch Registers (DLL and DLH) to set the baud rate of the UART. See the description for “Line Control Register (LCR)” for more details.

Table 24-3 UART 1 Register Map

DLABa Address Access Name Abbreviation

0 0x10094000 Read only Receive Buffer Register RBR

0 Write-only Transmit Holding Register THR

1 Read/write Divisor Latch (Low) DLL

0 0x10094004 Read/write Interrupt Enable Register IER

1 Read/write Divisor Latch (High) DLH

X 0x10094008 Read only Interrupt Identity Register IIR

X Write-only FIFO Control Register FCR

X 0x1009400c Read/write Line Control Register LCR

X 0x10094010 Read/write Modem Control Register MCR

X 0x10094014 Read only Line Status Register LSR

X 0x10094018 Read only Modem Status Register MSR

X 0x1009401c Read/write Scratch Register SCR

Note:(a) The Divisor Latch Address Bit (DLAB) is bit 7 of the Line Control Register (LCR). It enables reading and writing of the Divisor Latch Registers (DLL and DLH) to set the baud rate of the UART. See the description for “Line Control Register (LCR)” for more details.

M821xx Data Sheet


24.1.1 Register Bitmap DescriptionDetails of interrupt operation are contained below.

a. FIFO enabled bits.

b. Transmit Empty value upon reset equals 1 - all other bits are equal to 0 upon reset.

c. Transmit Hold Register Enable (THRE) Value upon reset equals 1 - all other bits are equal to 0 upon reset. Also, functionality altered when FIFOs and Programmable THRE Interrupt mode enabled and active.

24.1.2 Receive Buffer Register (RBR)The RBR is a read only register that contains the data byte received on the serial input port. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. In the non-FIFO mode (Fifo Depth == NONE) or when the FIFOs are programmed OFF, the data in the RBR must be read before the next data arrives; otherwise it will be overwritten, resulting in an overrun error. In the FIFO mode (Fifo Depth != NONE) and FIFOs programmed ON, this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur.

24.1.3 Transmit Holding Register (THR)The THR is a write-only register that contains data to be transmitted on the serial output port. Data can be written to the THR any time that the THR Empty (THRE) bit of the Line Status Register (LSR) is set.

If FIFOs are not enabled and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten.

If FIFOs are enabled and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.

24.1.4 Divisor Latch High and Low (DLH, DLL)The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register forms a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud rate is equal to the AHB frequency divided by sixteen times the value of the baud rate divisor, as follows:

baud rate = (AHB = 165 MHz) / (16 * divisor)

divisor = (AHB = 165 MHz) / (16 * baud rate)

NOTE: 1) Once both Divisor Latch Registers are set, at least (2x divisor x 16) clock cycles of the slowest clock should be allowed to pass before transmitting or receiving data.

2) Large Baud Rates cause high interrupt rates that the software must handle.

M821xx Data Sheet


24.1.5 Interrupt Enable Register (IER)The IER is a read/write register that contains four bits that enable the generation of interrupts. These four bits are the Enable Received Data Available Interrupt (ERBFI), the Enable Transmitter Holding Register Empty Interrupt (ETBEI), the Enable Receiver Line Status Interrupt (ELSI), and the Enable Modem Status Interrupt (EDSSI).

24.1.6 Interrupt Identity Register (IIR)The Interrupt Identity Register is a read only register that identifies the source of an interrupt. The upper two bits of the register are FIFO-enabled bits. These bits will be “00” if the FIFO’s are disabled and “11 if they are enabled. The lower four bits identify the highest priority pending interrupt.

NOTE: The UART interrupts are handled through Status_Register_1 of the interrupt controller.

Table 24-4 Interrupt Identity Register IIR Bit Map Description

FIFOModeOnly

InterruptIdentification

Register Interrupt Set and Reset Functions

Bit 3 Bit 2 Bit 1 Bit 0 PriorityLevel

Interrupt Type

InterruptSource

InterruptReset Control

0 0 0 1 - None None -

0 1 1 0 Highest ReceiverLine

Status

Overrun/parity/ framing errors or break interrupt

Reading the line status register

0 1 0 0 Second Received data available

Receiver data available (FIFOs disabled) or RX FIFO trigger

level reached (FIFOs enabled)

Reading the receiver buffer register (FIFOs disabled) or the FIFO

drops below the trigger level (FIFOs enabled)

1 1 0 0 Second Character timeout

indication

No characters in or out of the RCVR FIFO during the last 4

character times and there is at least 1 character in it during

this time

Reading the receiver buffer register

0 0 1 0 Third Transmitter holding register empty

Transmitter holding register empty (Prog. THRE Mode disabled) or TX FIFO at or

below threshold (Prog. THRE Mode enabled)

Reading the IIR register (if source of interrupt) or

writing into THR (FIFOs or THRE Mode disabled) or TX FIFO above threshold (FIFOs and THRE Mode

enabled).

0 0 0 0 Fourth Modem status

Clear to send or data set ready or ring indicator or data center

detect

Reading the Modem status register

Note:a) Indicates an interrupt can only occur when the FIFO’s are enabled and is used to distinguish a Character Timeout condition interrupt.

M821xx Data Sheet


24.1.7 FIFO Control Register (FCR)The FIFO control register is a write-only register. If (Fifo Depth == NONE), this register has no effect. Otherwise, this register controls the read and writes data FIFO operation and the mode of operation for the DMA signals txrdy_n and rxrdy_n. When FIFOs and Programmable THRE Interrupt mode are enabled, this register also controls the THRE Interrupt empty threshold level.Setting bit 0 of the FCR enables the transmit and receive FIFOs. Writing a 1 value to bit 1 of the FCR resets and flushes data in the receive FIFO. Note that this bit is ‘self-clearing’ and it is not necessary to clear this bit. Writing a 1 value to bit 2 of the FCR resets and flushes data in the transmit FIFO. The FIFOs are also reset anytime bit 0 of the FCR changes value.

These threshold levels are also described in Table 24-4. If the FIFO mode is enabled (Fifo Depth != 1 and bit 0 of the FCR is set to 1) bits 3, 6, and 7 are active. Bit 3 determines the DMA signalling mode for txrdy_n and rxrdy_n output signals. As described in Table 24-4, bit 6 and bit 7 set the trigger level in the receiver IFO for both the rxrdy_n signal and the Enable Received Data Available Interrupt (ERBFI).

24.1.8 Line Control Register (LCR)The Line Control Register controls the format of the data that is transmitted and received. LCR bits 0 and 1 control the number of bits per character. Details are shown in Table 24-1. LCR bit 2 controls the number of stop bits transmitted. If bit 2 is ‘0’, one stop bit is transmitted in the serial data. If bit 2 is ‘1’ and the data bits are set to 5, one and a half stop bits are generated. Otherwise, two stop bits are generated and transmitted in the serial data out LCR bit 3 is the Parity Enable bit. Parity is enabled when this bit is set.LCR bit 4 is the Parity Select bit.

If parity is enabled, bit 4 selects between even and odd parity. If bit 4 is ‘1’, an even number of logic ‘1’s is transmitted or checked. If bit 4 is ‘0’, an odd number of logic ‘1’s is transmitted or checked. LCR bit 5 is the Stick Parity bit. The UART does not support the “stick parity” feature so bit 5 of the LCR has no affect. LCR bit 6 is the Break Control bit.

Setting the Break bit sends a break signal by holding the sout line low (when not in Loop back Mode, as determined by Modem Control Register bit 4), until the Break bit is cleared. When in Loop Back Mode, the break condition is internally looped back to the receiver LCR bit 7 is the Divisor Latch Address bit. Setting this bit enables reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers.

24.1.9 Modem Control Register (MCR)The lower four bits of the MCR directly manipulate the outputs of the UART. Details are shown in Table 24-4. The DTR (bit 0), RTS (bit 1), OUT1 (bit 2), and OUT2 (bit 3) bits are inverted and then drive the corresponding UART outputs, dtr_n, rts_n, out1_n and out2_n. MCR 4 is the LOOPBACK bit. When set, data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. This feature is used for diagnostic purposes.

Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the four modem control outputs (dtr_n, rts_n, out1_n, out1_n) are looped back to the inputs, internally.

M821xx Data Sheet


24.1.10 Line Status Register (LSR)The Line Status Register contains status of the receiver and transmitter data transfers. This status can be read by the programmer at anytime. Details are shown in Table 24-1. LSR bit 0 is the Data Ready (DR) bit. When set, this bit indicates the receiver contains at least one character in the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the non-FIFO mode, or when the receiver FIFO is empty, in the FIFO mode. LSR bit 1 is the overrun error (OE) bit. When set, this bit indicates an overrun error has occurred because a new data character was received before the previous data was read.

In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. LSR bit 2 is the Parity Error (PE) bit. This bit is set whenever there is a parity error in the receiver if the Parity Enable (PEN) bit in the LCR is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO.

LSR bit 3 is the Framing Error (FE) bit. This bit is set whenever there is a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. The OE, PE and FE bits are reset when a read of the LSR is performed. LSR bit 4 is the Break Interrupt (BI) bit. This bit is set whenever the serial input (sin) is held in a logic ‘0’ state for longer than the sum of start time + data bits + parity + stop bits.

A break condition on sin causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non FIFO mode, the BI indication occurs immediately and persists until the LSR is read. LSR 5 is the Transmitter Holding Register Empty (THRE) bit.

When Programmable THRE Interrupt mode is disabled or inactive, this bit indicates that the UART can accept a new character for transmission. This bit is set whenever data is transferred from the THR to the transmitter shift register and no new data has been written to the THR. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. When FIFOs and Programmable THRE Interrupt mode synthesis parameters are enabled and the mode is active, LSR 5 functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE Interrupts, which are then controlled by the FCR[5:4] threshold setting. LSR bit 6 is the Transmitter Empty (TEMT) bit. In the FIFO mode, this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. In the non-FIFO mode, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. This bit is typically used to make sure it is safe to change control registers. Changing control registers while the transmitter is busy can result in corrupt data being transmitted. LSR bit 7 is the Error in Receiver FIFO (FERR) bit. This bit is only active when FIFOs are enabled. It is set when there is at least one parity error, framing error, or break indication in the FIFO. This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO.

M821xx Data Sheet


24.1.11 Modem Status Register (MSR)The Modem Status Register contains the current status of the modem control input lines and if they changed. Details are shown in Table 24-1.

DCTS (bit 0), DDSR (bit 1) and DDCD (bit 3) bits record whether the modem control lines have changed since the last time the CPU read the MSR. TERI (bit 2) indicates ri_n has changed from an active low, to an inactive high state since the last time the MSR was read. In Loopback Mode, DCTS reflects changes on MCR bit 1 (RTS), DDSR reflects changes on MCR bit 0 (DTR) and DDCD reflects changes on MCR bit 3 (Out2), while TERI reflects when MCR bit 2 (Out1) has changed state from a high to a low.

The CTS, DSR, RI and DCD Modem Status bits contain information on the current state of the modem control lines. CTS (bit 4) is the compliment of cts_n, DSR (bit 5) is the compliment of dsr_n, RI (bit 6) is the compliment of ri_n and DCD (bit 7) is the compliment of dcd_n. In Loopback Mode, CTS is the same as MCR bit 1 (RTS), DSR is the same as MCR bit 0 (DTR), RI is the same as MCR bit 2 (Out1) and DCD is the same as MCR bit 3 (Out2).

24.1.12 Scratchpad Register (SCR)The SCR register is an 8-bit read/write register for programmers to use as a temporary storage space. It has no defined purpose in the UART block.

.


25.0 Inter-IC (I2C) Interface

25.1 Features• Conforms to version 2.1 of the I2C specification.

• Master or slave operation.

• Multi-master systems supported.

• Supports both 7-bit and 10-bit addressing.

• Own address and general call (data broadcast) address detection.

• Built-in collision detection.

• Performs arbitration and clock arbitration.

• Interrupt on address detection.

• Supports High Speed (HS), Fast and Standard transfer rates.

• Bus isolation support.

• Allows operations from a wide range on input clock frequencies.

25.2 Functional DescriptionI2C is an industry-standard, low-bandwidth, short distance protocol for on-board communications. All devices are connected through two wires: serial data (SDA) and serial clock (SCL). Available Mindspeed drivers allow Comcerto M821xx devices to boot from a serial EEPROM through the I2C interface. All I2C devices must have a unique address to identify it on the bus. Slave devices have a predefined address, but the lower bits of the address can be assigned to allow for multiples of the same devices on the bus.

The Comcerto device operates as a master, a slave, or in multi-master mode. It supports all I2C speeds: standard (100 kbps), fast (400 kbps) and high speed (3.4 Mbps). The Comcerto I2C interface includes a programmable clock divider to allow adjustment of data speed over a wide range. However, the Comcerto I2C interface does not include an output signal for direct control of a bridge between fast/standard and high-speed bus segments. Thus, the Comcerto I2C interface is typically configured to accommodate the slowest device on the bus.

25.3 Signal DescriptionsTable 25-1 M821xx SPI Interface Signals


I2C_SCL I 1 I2C Input/Output Clock Line (multiplexed with GPIO18. See “GPIO Interface Signals” on page 527.)

I2C_SDA O 1 I2C Input/Output Data Line (multiplexed with GPIO19, See “GPIO Interface Signals” on page 527.)

M821xx Data Sheet


25.4 I2C Timing

Table 25-2 I2C Setup and Hold Times

Figure 25-1 I2C Timing Waveforms


I2C_SCL Frequency 3.4 MHz

Clock Duty Cycle (All Clocks)Low periodHigh period

16060

nsns

Tsu;sta START condition setup time 160 ns 1, 2

Ths;sta START condition hold time 160 ns 1, 2

Tsu;sto STOP condition setup time 160 ns 1, 2

Tis Input Setup Time (I2C_input) 10 ns

Tih Input Hold Time (I2C_input) 0 ns

Tod Output Delay Time (I2C_output) 60 ns 3

Toh Output Hold Time (I2C_output) 0 ns

NOTES:1) These numbers can be extended when using a slower output clock (master mode).2) This number increases as clock frequency slows down, according to the formula:

Tsu;Tsta(min) = Thd;sta(min) = Tsu;sto(min) = 2N x TAHB where TAHB is the AHB clock period, and N is a parameter that is used to set the I2C clock frequency according to the AHB clock frequency.

3) This number increases as clock frequency is slower, according to the following formula:Tod(max) = 2N+1 x (M+1) x TAHB

where TAHB is the AHB clock period, and N and M are parameters that are used to set the I2C clock frequency according to the AHB clock frequency.

M821xx Data Sheet


25.5 Register DescriptionsFor register descriptions, see Section 26.0 I2C Interface Registers on page 431.

25.6 High Speed ModeA Master may arbitrate and select High speed operation by transmitting one of the reserved 7-bit addresses of the form 00001xxxb. The first five bits of this address are significant: the remaining three bits may be used to identify different Hs-mode masters on the same I2C bus.

On detecting a code of this form, the I2C interface enters High speed mode. It will revert to F/S mode on detection of a STOP condition on the I2C bus.

25.7 Clock SynchronizationIf another device on the I2C bus drives the clock line when the I2C interface is in master mode, the I2C interface will synchronize its clock to the I2C bus clock. The high period of the clock will be determined by the device that generates the shortest high clock period. The low period of the clock will be determined by the device that generates the longest low clock period.

When the I2C interface is in master mode and is communicating with a slow slave, the slave can stretch each bit period by holding the SCL line low until it is ready for the next bit. When the I2C interface is in slave mode, it will hold the SCL line low after each byte has been transferred until the IFLG has been cleared in the CNTL register.

25.8 Bus ArbitrationIn master mode, the I2C interface will check that each transmitted logic 1 appears on the I2C bus as a logic 1. If another device on the bus over-rules and pulls the SDA line low, arbitration is lost. If arbitration is lost during the transmission of a data byte or a Not ACK bit, the I2C interface will return to the idle state. If arbitration is lost during the transmission of an address, the I2C interface will switch to slave mode so that it can recognize its own slave address or the general call address.

25.9 TroubleshootingIf there is an interruption in the I2C protocol while booting from an EEPROM (e.g. reset is asserted) then the external EEPROM device might get stuck and the system PCB must be powered down before restarting the boot process.

M821xx Data Sheet


25.10 Operating ModesThe JTAG Interface complies with the IEEE 1149.1 JTAG specification.

25.10.1 Master TransmitIn the master transmit mode, the I2C interface will transmit a number of bytes to a slave receiver.

The master transmit mode is entered by setting the STA bit in the CNTR register to one. The I2C interface will then test the I2C bus and will transmit a START condition when the bus is free. When the START condition has been transmitted, the IFLG bit will be set and the status code in the STAT register will be 08h. (If a repeated START condition has been transmitted, the status code will be 10h instead of 08h.) Before this interrupt is serviced, the DATA register must be loaded with either a 7-bit slave address or the first part of a 10-bit slave address, with the LSB cleared to zero (i.e. with an added Write bit) to specify transmit mode. The IFLG bit should now be cleared to zero to prompt the transfer to continue.

After the 7-bit slave address (or the first part of a 10-bit address) plus the Write bit have been transmitted, the IFLG will be set again. A number of status codes are possible in the STAT register:

Table 25-3 STAT Register Contents 1

If 10-bit addressing is being used, then after the first part of a 10-bit address plus the Write bit have been successfully transmitted, the status code will be 18h or 20h.

CODE I2C INTERFACE STATE MICROPROCESSOR RESPONSE

NEXT I2C INTERFACE ACTION

18h Addr+W transmitted, ACK received

For a 7-bit address: Write byte to DATA, clear IFLG Or set STA, clear IFLG Or set STP, clear IFLG Or set STA & STP, clear IFLG For a 10-bit address: Write extended address byte to DATA, clear IFLG

Transmit data byte, receive ACK. Transmit repeated START Transmit STOP Transmit STOP then START Transmit extended address byte

20h Addr+W transmitted, Not ACK received

As for code 18h As for code 18h

38h Arbitration lost Clear IFLG Or set STA, clear IFLG

Return to idle Transmit START when bus free

68h Arbitration lost, SLAA+W received, ACK transmitted

Clear IFLG, AAK=0 Or clear IFLG, AAK=1

Receive data byte, transmit Not ACK Receive data byte, transmit ACK

78h Arbitration lost, general call address received, ACK transmitted


B0h Arbitration lost, SLAA+R received, ACK transmitted

Write byte to DATA, clear IFLG, AAK=0 Or write byte to DATA, clear IFLG, AAK=1

Transmit last byte, receive ACK Transmit data byte, receive ACK

NOTE: ‘W’= Write bit i.e. LSB cleared to zero; ‘R’ = Read bit i.e. LSB set to ‘1’.

M821xx Data Sheet


After this interrupt has been serviced and the second part of the address transmitted, the STAT register will contain one of the following codes:


After each data byte has been transmitted, the IFLG will be set and one of three status codes will be in the STAT register:


When all bytes have been transmitted, the STP bit should be set by writing a 1 to this bit in the CNTR register. The I2C interface will then transmit a STOP condition, clear the STP bit and return to the idle state.

CODE I2C INTERFACE STATE MICROPROCESSOR RESPONSE NEXT I2C INTERFACE ACTION



68h Arbitration lost, SLAX+W received, ACK transmitted



B0h Arbitration lost, SLAX+R received, ACK transmitted



E0h Second Address byte ACK received

Write byte to DATA, clear IFLG Or set STA, clear IFLG Or set STP, clear IFLG Or set STA & STP, clear IFLG

Transmit data byte, receive ACK Transmit repeated START Transmit STOP Transmit STOP then START

E8h Second Address byte Not ACK received

As for code E0h As for code E0h



28h Data byte transmitted, ACK received


Transmit data byte, receive ACK Transmit repeated START Transmit STOP Transmit START then STOP

30h Data byte transmitted, Not ACK received




M821xx Data Sheet


25.10.2 Master ReceiveIn the master receive mode, the I2C interface will receive a number of bytes from a slave transmitter.

After the START condition has been transmitted, the IFLG bit will be set and status code 08h will be in the STAT register. (If a repeated START condition has been transmitted, the status code will be 10h instead of 08h.) The DATA register should now be loaded with the slave address (or the first part of a 10-bit slave address), with the LSB set to one to signify a Read. The IFLG bit should now be cleared to zero to prompt the transfer to continue.

When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit have been transmitted, the IFLG bit will be set again. A number of status codes are possible in the STAT register:


If 10-bit addressing is being used, the slave is first addressed using the full 10-bit address plus the Write bit. The master then issues a repeated START followed by the first part of the 10-bit address again, but plus the Read bit – after which, the status code will be 40h or 48h. It is the responsibility of the slave to remember that it had been selected prior to the repeated START.

After each data byte has been received, the IFLG will be set and one of three status codes will be in the STAT register:



40h Addr + R transmitted, ACK received

For a 7-bit/10-bit address: Clear IFLG, AAK = 0 Or clear IFLG, AAK = 1


48h Addr + R transmitted, Not ACK received

For a 7-bit/ 10-bit address: Set STA, clear IFLG Or set STP, clear IFLG Or set STA & STP, clear IFLG

Transmit repeated START Transmit STOP Transmit STOP then START

38h As for master transmit As for master transmit As for master transmit



B0h As for master transmit As for master transmit As for master transmit

M821xx Data Sheet



When all bytes have been received, a Not ACK (high level on SDA) should be transmitted then the STP bit should be set by writing a 1 to this bit in the CNTR register. The I2C interface will transmit a STOP condition, clear the STP bit and return to the idle state.

25.10.3 Slave TransmitIn the slave transmit mode, a number of bytes are transmitted to a master receiver. For the I2C interface to respond, the AAK bit in the CNTR register needs to be set.

The I2C interface will enter slave transmit mode when it receives its own slave address and a Read bit after a START condition. The I2C interface will then transmit an ACK (low level on SDA) and set the IFLG bit in the CNTR register. The STAT register will contain the status code A8h.

Slave transmit mode can also be entered directly from a master mode if arbitration is lost in master mode during the transmission of an address, and the slave address and a Read bit are received. The status code in the STAT register will then be B0h.

The data byte to be transmitted should then be loaded into the DATA register and the IFLG cleared. When the I2C interface has transmitted the byte and received an ACK, the IFLG will be set and the STAT register will contain B8h. Once the last byte to be transmitted has been loaded into the DATA register, the AAK bit should be cleared when the IFLG is cleared. After the last byte has been transmitted, the IFLG will be set and the STAT register will contain C8h. The I2C interface will then return to the idle state and the AAK bit must be set to one before slave mode can be entered again.

If no acknowledge is received after transmitting a byte, the IFLG will be set and the STAT register will contain C0h. The I2C interface will then return to the idle state.

If the STOP condition is detected after an ACK bit, the I2C interface will return to the idle state.



50h Data byte received, ACK transmitted

Read DATA, clear IFLG, AAK = 0 Or read DATA, clear IFLG, AAK = 1


58h Data byte received, Not ACK transmitted

Read DATA, set STA, clear IFLG Or read DATA, set STP, clear IFLG Or read DATA, set STA & STP, clear IFLG


38h Arbitration lost in Not ACK bit

As for master transmit As for master transmit

NOTE: Where the I2C interface has an extended slave address (signified by 11110b in ADDR[7:3]), it will transmit an acknowledge in response to the address byte received after the repeated START. An interrupt will be generated, IFLG will be set and the status will be A8h. No second address byte will be sent by the master: it is up to the slave to remember that it had been selected prior to the repeated START.

M821xx Data Sheet


It is important that AAK be cleared (“0”) prior to transmission of the last data byte. If this is not done, it is possible to jam the I2C bus by driving SDA = “0”, which prevents the master from sending either stop start or restart and results in a bus error.

25.10.4 Slave ReceiveIn the slave receive mode, a number of data bytes are received from a master transmitter.

The I2C interface will enter slave receive mode when it receives its own slave address and a Write bit (LSB=0) after a START condition. The I2C interface will then transmit an ACK (low level on SDA) and set the IFLG bit in the CNTR register: the STAT register will then contain status code 60h. The I2C interface will also enter slave receive mode when it receives the general call address 00h (if the GCE bit in the ADDR register is set). The status code will then be 70h.

Slave receive mode can also be entered directly from a master mode if arbitration is lost in master mode during the transmission of an address and the slave address and Write bit (or the general call address if bit GCE in the ADDR register is set to one) are received. The status code in the STAT register will then be 68h if the slave address was received or 78h if the general call address was received. The IFLG bit must be cleared to zero to allow the data transfer to continue.

If the AAK bit in the CNTR register is set to one, then after each byte is received, an ACK bit is transmitted and the IFLG bit is set: the STAT register will then contain status code 80h (or 90h if slave receive mode was entered with the general call address). The received data byte can be read from the DATA register and the IFLG bit must be cleared to allow the transfer to continue. When the STOP condition or a repeated START condition is detected after the ACK bit, then the IFLG bit is set and the STAT register will contain status code A0h.

If the AAK bit is cleared to zero during a transfer, the I2C interface will transmit a Not ACK (high level on SDA) after the next byte is received, and set the IFLG bit. The STAT register will contain status code 88h (or 98h if slave receive mode was entered with the general call address). When the IFLG bit has been cleared to zero, the I2C interface will return to the idle state.

NOTE: Where the I2C interface has an extended slave address (signified by 11110b in ADDR[7:3]), it will transmit an ACK after the first address byte is received but no interrupt will be generated, IFLG will not be set and the status will not change. Only after the second address byte has been received will the I2C interface generate an interrupt, set the IFLG bit and the status code as described above.

M821xx Data Sheet


25.10.5 State Diagram

Table 25-8 State Diagram Summary

Figure 25-2 State Diagram

Step Master mode Slave mode

1 Condition for Start detected Start condition detected

2 Interrupt serviced (No action)

3 Arbitration lost Non-matching 7-bit address received

4 7-bit address sent, interrupt serviced 7-bit address valid, interrupt serviced

5 Start of 10-bit address sent, interrupt serviced

Start of 10-bit address received


7 Remainder of 10-bit address sent, interrupt serviced

10-bit address valid, interrupt serviced

8 Arbitration lost

9 Condition for Stop detected Stop condition detected

10 Condition for Re-start detected Re-start condition detected

11 (No action) Interrupt serviced

12 Interrupt serviced Interrupt serviced

Master or Slave Mode

.


26.0 I2C Interface Registers

26.1 AddressingThe 8-bit processor interface provides access to seven registers; four read/write registers, one read-only register and two write-only registers.

Table 26-1 I2C Registers

26.1.1 Resetting the InterfaceAddressing a write to the Software reset address (A = 7h) will idle the I2C outputs and reset the state machine (Figure 26-1) to idle. The software reset set the STAT register to F8h while clearing all the other registers to 00h.

NOTE: The memory addressing of the I2C configuration registers is offset from the base address: 0x 0D00 0000.

ADDRESS R/W REGISTER DESCRIPTION

000b Read/Write ADDR Slave address

001b Read/Write DATA Data byte

010b Read/Write CNTR Control register

011b Read Only STAT Status register

Write Only CCRFS Clock Control register (Full/Standard speed)

100b Read/Write XADDR Extended slave address

101b Write Only CCRH Clock Control register (High speed)

111b Write Only Software reset

M821xx Data Sheet


26.1.2 Addr RegisterRead/Write: Address 000b

Table 26-2 ADDR Register

26.1.2.1 7-bit addressing

ADDR[7:1] records the 7-bit address of the I2C interface (SLAA6 – SLAA0). When the I2C interface receives this address after a START condition, it sends an ACK (low level on SDA), generates an internal interrupt to the Concerto device’s interrupt controller, and enters slave mode. (SLAA6 corresponds to the first bit received from the I2C bus.) If GCE (ADDR[0]) is set to one, the I2C interface will also respond in this way to the general call address (00h).

26.1.2.2 10-bit addressing

When the address received starts with 11110b, the I2C interface recognizes this as the first part of a 10-bit address and if the next two bits match ADDR[2:1] (i.e. SLAX9 and SLAX8 of the device’s extended address), it will send an ACK. (The I2C interface does not generate an internal interrupt at this point.) If the next byte to be received matches the remainder of the I2C interface’s extended address (recorded in the XADDR register), the I2C interface will then send an ACK, generate an internal interrupt to the Concerto device’s interrupt controller, and go into slave mode.

26.1.3 XADDR RegisterRead/Write: Address 100b

Table 26-3 XADDR Register

POSN BIT 7-BIT ADDRESSING DESCRIPTION

BIT 10-BIT ADDRESSING DESCRIPTION

D7 SLAA6 Slave Address 1





D2 SLAA1 Slave Address SLAX9 Extended Slave Address

D1 SLAA0 Slave Address SLAX8 Extended Slave Address

D0 GCE General call address enable GCE General call address enable

POSN BIT DESCRIPTION

D7 SLAX7 Extended Slave Address








M821xx Data Sheet


26.1.4 Data RegisterRead/Write: Address 001b

This register contains the data byte/slave address to be transmitted or the data byte that has just been received. In transmit mode, the byte is sent MSB first. In receive mode, the first bit received will be placed in the MSB of the register.

After each byte is transmitted, the DATA register will contain the byte that was actually present on the bus so in the event of lost arbitration, it will contain the received byte.

26.1.5 CNTR RegisterRead/Write: Address 010b

Table 26-4 CNTR Register

Bits 0 & 1 are read only and are read back as zero.

26.1.5.1 IENWhen IEN is set to one, the interrupt line (INTR) will go high when the IFLG bit is set. When IEN is cleared to zero, the interrupt line will always remain low.

26.1.5.2 ENAB

When ENAB = 1, the I2C interface will respond to calls to its slave address – and to the general call address if the GCE bit in the ADDR register is set. When ENAB = 0, the I2C interface will not respond to any address on the bus.

ENAB does not need to be set while the I2C interface is operating in master mode. However, if ENAB is 0 when arbitration is lost, the status code returned will be 38h regardless of whether the address received was the device’s slave address or the general call address. The address/data received may still be read from the DATA register.

NOTE: Both in slave mode and in master mode, this register should only be read or written when IFLG is set. At any other time, the contents of the register may change.

POSN BIT DESCRIPTION

D7 IEN Interrupt enable

D6 ENAB Bus enable

D5 STA Master mode start

D4 STP Master mode stop

D3 IFLG Interrupt flag

D2 AAK Assert acknowledge

D1 0 Unused

D0 0 Unused

M821xx Data Sheet


26.1.5.3 STAWhen STA is set to one, the I2C interface enters master mode and will send a START condition on the bus when the bus is free. If the STA bit is set to one when the I2C interface is already in master mode and one or more bytes have been transmitted, then a repeated START condition will be sent. If the STA bit is set to one while the I2C interface is being accessed in slave mode, the I2C interface will complete the data transfer in slave mode then enter master mode when the bus has been released.

The STA bit is cleared automatically after a START condition has been sent: writing a zero to this bit has no effect.

26.1.5.4 STPIf STP is set to one in master mode, a STOP condition is transmitted on the I2C bus. If the STP bit is set to one in slave mode, the I2C interface will behave as if a STOP condition has been received, but no STOP condition will be transmitted on the I2C bus. If both STA and STP bits are set, the I2C interface will first transmit the STOP condition (if in master mode) then transmit the START condition. The STP bit is cleared automatically: writing a zero to this bit has no effect.

26.1.5.5 IFLG

IFLG is automatically set to one when any of 29 (out of the possible 30) MI2C states is entered. The only state that does not set IFLG is state F8h (see the section on the STAT Register below).

If IFLG is set to one and the IEN bit is set, the interrupt line goes high. When IFLG is set by the I2C interface, the low period of the I2C bus clock line (SCL) is stretched and the data transfer is suspended. When zero is written to IFLG, the interrupt line goes low and the I2C clock line is released.

26.1.5.6 AAK

When AAK is set to one, an ACK (low level on SDA) will be sent during the acknowledge clock pulse on the I2C bus if:

• Either the whole of a matching 7-bit slave address or the first or the second byte of a matching 10-bit slave address has been received.

• The general call address has been received and the GCE bit in the ADDR register is set to one. • A data byte has been received in master or slave mode.

When AAK is cleared to zero, a Not ACK (high level on SDA) will be sent when a data byte is received in master or slave mode.

If AAK is cleared to zero in the slave transmitter mode, the byte in the DATA register is assumed to be the ‘last byte’. After this byte has been transmitted, the I2C interface will enter state C8h or D0h then go ‘bus idle’, waiting for either a Restart or a Stop. The I2C interface will not respond as a slave unless AAK is set.

M821xx Data Sheet


26.1.6 STAT RegisterRead Only: Address 011b

This register contains a 5-bit status code in the five MSBs: the three LSBs are always zero.

There are 32 possible codes, 30 of which are used as status codes and two of which are unused.

When STAT contains the status code F8h, no relevant status information is available, no interrupt is generated and the IFLG bit in the CNTR register is not set. All other status codes correspond to a defined state of the I2C interface. When any of these states is entered, the corresponding status code appears in this register and the IFLG bit in the CNTR register is set. When the IFLG bit is cleared, the status code returns to F8h.

M821xx Data Sheet


Table 26-5 TSTAT Register

Code Status

00h Bus error (Master mode only)

08h START condition transmitted

10h Repeated START condition transmitted

18h Address + Write bit transmitted, ACK received

20h Address + Write bit transmitted, Not ACK received

28h Data byte transmitted in master mode, ACK received

30h Data byte transmitted in master mode, Not ACK received

38h Arbitration lost in address or data byte

40h Address + Read bit transmitted, ACK received

48h Address + Read bit transmitted, Not ACK received

50h Data byte received in master mode, ACK transmitted

58h Data byte received in master mode, Not ACK transmitted

60h Slave address + Write bit received, ACK transmitted

68h Arbitration lost in address as master, slave address + Write bit received, ACK transmitted

70h General Call Address received, ACK transmitted

78h Arbitration lost in address as master, General Call Address received, ACK transmitted

80h Data byte received after slave address received, ACK transmitted

88h Data byte received after slave address received, Not ACK transmitted

90h Data byte received after General Call Address received, ACK transmitted

98h Data byte received after General Call Address received, Not ACK transmitted

A0h STOP or repeated START condition received in slave mode

A8h Slave address + Read bit received, ACK transmitted

B0h Arbitration lost in address as master, slave address + Read bit received, ACK transmitted

B8h Data byte transmitted in slave mode, ACK received

C0h Data byte transmitted in slave mode, Not ACK received

C8h Last byte transmitted in slave mode, ACK received

D0h Last byte transmitted in slave mode, Not ACK received

D8h Unused

E0h Second Address byte transmitted, ACK received

E8h Second Address byte transmitted, Not ACK received

F0h Unused

F8h No relevant status information, IFLG=0

M821xx Data Sheet


If an illegal condition occurs on the I2C bus, the bus error state is entered (status code 00h). To recover from this state, the STP bit in the CNTR register must be set and the IFLG bit cleared. The I2C interface will then return to the idle state: no STOP condition will be transmitted on the I2C bus.

26.1.7 CCRFS and CCRH RegistersWrite Only: Address 011b and 101b, respectively

The value recorded in the CCRFS register applies when the I2C interface is operating in Fast/Standard mode. The value recorded in the CCRH register applies when the I2C interface is operating in High Speed mode. The seven LSBs of these registers control the frequency at which the I2C bus is sampled and the frequency of the I2C clock line. The way the values recorded in the registers are interpreted is as follows:

Table 26-6 CCRFS and CCRH Bit Assignments

NOTE: To restart transmission as soon as possible, set the STP bit to 1 to clear the bus error and the STA bit to 1 to re-start transmission at the same time: transmission will then re-start as soon as the bus becomes available.

POSN BIT

D7 –

D6 M3

D5 M2

D4 M1

D3 M0

D2 N2

D1 N1

D0 N0

M821xx Data Sheet


The input clock frequency (i.e. the frequency of CLOCK) is first divided by a factor of 2N, where N is the value defined by bits 2 – 0 of the register. When the value from the CCRFS register is applied, the output from this first clock divider is FSEN. When the value from the CCRH register is applied, the output from this first clock divider is HSEN.

The frequency of this FSEN/HSEN output is then divided by a further factor of M+1, where M is the value defined by bits 6 – 3 of the register. The output from the second clock divider is MA_FSEN/MA_HSEN respectively.

The I2C bus is sampled by the I2C interface at the frequency defined by the output from the first divider, i.e.

FSAMP = FHSEN/FSEN = FCLOCK / 2N

Typically, the software initialization of DPLL subsystem on the Comcerto 800 Device puts FCLOCK at 132.5 MHz.

The OSCL output frequency, when the I2C interface is in master mode, is the output from the second divider divided by 10:

FOSCL = FMA_HSEN/MA_FSEN / 10 = FCLOCK / (2N.(M + 1).10)

The use of two separately programmable dividers allows the master mode output frequency to be set independently of the frequency at which the I2C bus is sampled. This is particularly useful in multi-master systems because the frequency at which the I2C bus is sampled must be at least 10 times the maximum SCL frequency to ensure that START and STOP conditions are always detected. By using two programmable clock divider stages, a high sampling frequency can be ensured while allowing the master mode output to be set to a lower frequency.

26.2 High Speed ModeA Master may arbitrate and select High speed operation by transmitting one of the reserved 7-bit addresses of the form 00001xxxb. The first five bits of this address are significant: the remaining three bits may be used to identify different Hs-mode masters on the same I2C bus.

On detecting a code of this form, the I2C interface enters High speed mode. It will revert to F/S mode on detection of a STOP condition on the I2C bus.

If 10-bit addressing is being used, then after the first part of a 10-bit address plus the Write bit have been successfully transmitted, the status code will be 18h or 20h.

After this interrupt has been serviced and the second part of the address transmitted, the STAT register will contain one of the following codes:

NOTE: ‘W’= Write bit i.e. LSB cleared to zero; ‘R’ = Read bit i.e. LSB set to ‘1’.

M821xx Data Sheet



After each data byte has been transmitted, the IFLG will be set and one of three status codes will be in the STAT register:


When all bytes have been transmitted, the STP bit should be set by writing a 1 to this bit in the CNTR register. The I2C interface will then transmit a STOP condition, clear the STP bit and return to the idle state.

CODE I2C INTERFACE STATE MICROPROCESSOR RESPONSE NEXT I2C INTERFACE ACTION



68h Arbitration lost, SLAX+W received, ACK transmitted



B0h Arbitration lost, SLAX+R received, ACK transmitted



E0h Second Address byte ACK received


Transmit data byte, receive ACK Transmit repeated START Transmit STOP Transmit STOP then START

E8h Second Address byte Not ACK received

As for code E0h As for code E0h



28h Data byte transmitted, ACK received


Transmit data byte, receive ACK Transmit repeated START Transmit STOP Transmit START then STOP

30h Data byte transmitted, Not ACK received




M821xx Data Sheet


26.2.1 Master ReceiveIn the master receive mode, the I2C interface will receive a number of bytes from a slave transmitter.

After the START condition has been transmitted, the IFLG bit will be set and status code 08h will be in the STAT register. (If a repeated START condition has been transmitted, the status code will be 10h instead of 08h.) The DATA register should now be loaded with the slave address (or the first part of a 10-bit slave address), with the LSB set to one to signify a Read. The IFLG bit should now be cleared to zero to prompt the transfer to continue.

When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit have been transmitted, the IFLG bit will be set again. A number of status codes are possible in the STAT register:


If 10-bit addressing is being used, the slave is first addressed using the full 10-bit address plus the Write bit. The master then issues a repeated START followed by the first part of the 10-bit address again, but plus the Read bit – after which, the status code will be 40h or 48h. It is the responsibility of the slave to remember that it had been selected prior to the repeated START.

After each data byte has been received, the IFLG will be set and one of three status codes will be in the STAT register:



40h Addr + R transmitted, ACK received

For a 7-bit/10-bit address: Clear IFLG, AAK = 0 Or clear IFLG, AAK = 1


48h Addr + R transmitted, Not ACK received

For a 7-bit/ 10-bit address: Set STA, clear IFLG Or set STP, clear IFLG Or set STA & STP, clear IFLG





B0h As for master transmit As for master transmit As for master transmit

M821xx Data Sheet



When all bytes have been received, a Not ACK (high level on SDA) should be transmitted then the STP bit should be set by writing a 1 to this bit in the CNTR register. The I2C interface will transmit a STOP condition, clear the STP bit and return to the idle state.

26.2.2 Slave TransmitIn the slave transmit mode, a number of bytes are transmitted to a master receiver. For the I2C interface to respond, the AAK bit in the CNTR register needs to be set.

The I2C interface will enter slave transmit mode when it receives its own slave address and a Read bit after a START condition. The I2C interface will then transmit an ACK (low level on SDA) and set the IFLG bit in the CNTR register. The STAT register will contain the status code A8h.

Slave transmit mode can also be entered directly from a master mode if arbitration is lost in master mode during the transmission of an address, and the slave address and a Read bit are received. The status code in the STAT register will then be B0h.

The data byte to be transmitted should then be loaded into the DATA register and the IFLG cleared. When the I2C interface has transmitted the byte and received an ACK, the IFLG will be set and the STAT register will contain B8h. Once the last byte to be transmitted has been loaded into the DATA register, the AAK bit should be cleared when the IFLG is cleared. After the last byte has been transmitted, the IFLG will be set and the STAT register will contain C8h. The I2C interface will then return to the idle state and the AAK bit must be set to one before slave mode can be entered again.

If no acknowledge is received after transmitting a byte, the IFLG will be set and the STAT register will contain C0h. The I2C interface will then return to the idle state.

If the STOP condition is detected after an ACK bit, the I2C interface will return to the idle state.

It is important that AAK be cleared (“0”) prior to transmission of the last data byte. If this is not done, it is possible to jam the I2C bus by driving SDA = “0”, which prevents the master from sending either stop start or restart and results in a bus error.



50h Data byte received, ACK transmitted

Read DATA, clear IFLG, AAK = 0 Or read DATA, clear IFLG, AAK = 1


58h Data byte received, Not ACK transmitted

Read DATA, set STA, clear IFLG Or read DATA, set STP, clear IFLG Or read DATA, set STA & STP, clear IFLG


38h Arbitration lost in Not ACK bit

As for master transmit As for master transmit

NOTE: Where the I2C interface has an extended slave address (signified by 11110b in ADDR[7:3]), it will transmit an acknowledge in response to the address byte received after the repeated START. An interrupt will be generated, IFLG will be set and the status will be A8h. No second address byte will be sent by the master: it is up to the slave to remember that it had been selected prior to the repeated START.

M821xx Data Sheet


26.2.3 Slave ReceiveIn the slave receive mode, a number of data bytes are received from a master transmitter.

The I2C interface will enter slave receive mode when it receives its own slave address and a Write bit (LSB=0) after a START condition. The I2C interface will then transmit an ACK (low level on SDA) and set the IFLG bit in the CNTR register: the STAT register will then contain status code 60h. The I2C interface will also enter slave receive mode when it receives the general call address 00h (if the GCE bit in the ADDR register is set). The status code will then be 70h.

Slave receive mode can also be entered directly from a master mode if arbitration is lost in master mode during the transmission of an address and the slave address and Write bit (or the general call address if bit GCE in the ADDR register is set to one) are received. The status code in the STAT register will then be 68h if the slave address was received or 78h if the general call address was received. The IFLG bit must be cleared to zero to allow the data transfer to continue.

If the AAK bit in the CNTR register is set to one, then after each byte is received, an ACK bit is transmitted and the IFLG bit is set: the STAT register will then contain status code 80h (or 90h if slave receive mode was entered with the general call address). The received data byte can be read from the DATA register and the IFLG bit must be cleared to allow the transfer to continue. When the STOP condition or a repeated START condition is detected after the ACK bit, then the IFLG bit is set and the STAT register will contain status code A0h.

If the AAK bit is cleared to zero during a transfer, the I2C interface will transmit a Not ACK (high level on SDA) after the next byte is received, and set the IFLG bit. The STAT register will contain status code 88h (or 98h if slave receive mode was entered with the general call address). When the IFLG bit has been cleared to zero, the I2C interface will return to the idle state.

NOTE: Where the I2C interface has an extended slave address (signified by 11110b in ADDR[7:3]), it will transmit an ACK after the first address byte is received but no interrupt will be generated, IFLG will not be set and the status will not change. Only after the second address byte has been received will the I2C interface generate an interrupt, set the IFLG bit and the status code as described above.

M821xx Data Sheet


26.2.4 State Diagram

Table 26-11 State Diagram Summary

Figure 26-1. State Diagram

Step Master mode Slave mode

1 Condition for Start detected Start condition detected

2 Interrupt serviced (No action)


4 7-bit address sent, interrupt serviced 7-bit address valid, interrupt serviced

5 Start of 10-bit address sent, interrupt serviced

Start of 10-bit address received


7 Remainder of 10-bit address sent, interrupt serviced

10-bit address valid, interrupt serviced

8 Arbitration lost

9 Condition for Stop detected Stop condition detected

10 Condition for Re-start detected Re-start condition detected

11 (No action) Interrupt serviced

12 Interrupt serviced Interrupt serviced

Master or Slave Mode

.


27.0 USB Interface

The Universal Serial Bus (USB) interface complies with the USB 2.0 standard. The two USB controllers handle control flow, data flow, status collection, and power management.

Except for the voice-only M8210x devices, all the M821xx devices provide two USB 2.0 Host Interfaces. Each USB 2.0 interface supports HS (480 Mbps) mode, and is backwards compatible with USB1.1.

The controller for each Universal Serial Bus interface handles all of the USB 2.0 protocol and provides a simple read/write protocol to the application software.

In host mode, the M821xx USB interaces comply with the Intel’s Enhanced Host Controller Interface Specification, rev 1.3, The M821xx device mode operational model is described in Section 27.4 Device Operational Mode.

For a view of the USB interfaces within the top-level block diagram, see Figure 2-1.

For information on the USB controller register set. see: Section 28.2 Register Set Overview. For a summary of EHCI deviations, see Section 27.5.

27.1 Features • USB 2.0 compliance

• Line interface: Differential D+/D-

• Integrated termination

• Data and clock recovery

• Bit stuffing/unstuffing

• Sync detection

• NRZI encoding/decoding

• Support for USB 2.0 LS, FS, anf HS modes

• USB interface controller implements an EHCI-aware link-list DMA engine to reduce software intervention

NOTE: The voice-only M82104 and MM82108 do not support USB.

M821xx Data Sheet


27.2 USB Interface Signals

27.3 USB Design and Layout RequirmentsUSB 2.0 requires careful attention to layout. Successful board-level implementation must respond to two challenges:

• Capacitance on data lines must be kept to a minimum

– Capacitance from each data line to ground with the other data line disconnected must not exceed 10 pF.

– Matching of capcacitances to ground must be within 1 pF.

– The differentilal capacitance across transciever inputs must be no more than 5.0 pF.

• The impedance of data lines with respect to GND must vary with Low Speed, Full Speed, and High Speed Modes

Board-level design must comply with requirements of the Universal Serial Bus Specification Revision 2.0, chapter 7, “Electrical”.

For details on board level implemetation of M821xx USB, refer to M821xx Hardware Requriements (821xx-APP-002), section 3.11 USB Interface Layout.

Table 27-1 USB Interface Signals


USB_DP B 1 Positive channel connected to the serial USB cable. 3.3V analog signal.

USB_DM B 1 Negative channel connected to the serial USB cable. 3.3V analog signal.

USB_VBUS — — 5V, 500 mA power supply.Required by the USB specification. NOTE: Not connected to the M821xx device, but necessary to support external interface.

USB_GND — — Ground for USB.NOTE: Not connected to the M821xx device, but necessary to support external interface

USB_REF B 1 External resistor connection for current reference.

USB_VBUS_STAT I 1 VBUS Status is an indicator of the internal USB VBUS. When the M821xx USB controller is in host mode this signal goes low to indicate a power fault condition (such as over-current) on the sourced VBUS. When the M821xxx USB controller is in device mode this signal goes low to indicate a device mode error.

M821xx Data Sheet


27.4 Device Operational ModeThe function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus. Using a set of linked list transfer descriptors, pointed to by a queue head, the device controller will perform the data transfers. The following sections explain the use of the device controller from the device controller driver (DCD) point-of-view and further describe how specific USB bus events relate to status changes in the device controller programmer's interface.

27.4.1 Device Controller Initialization After hardware reset, the device is disabled until the Run/Stop bit is set to a ‘1’. In the disabled state, the pull-up on the USB D+ is not active which prevents an attach event from occurring. At a minimum, it is necessary to have the queue heads setup for endpoint zero before the device attach occurs. Shortly after the device is enabled, a USB reset will occur followed by setup packet arriving at endpoint 0. A Queue head must be prepared so that the device controller can store the incoming setup packet. In order to initialize a device, the software should perform the following steps:

1. Set Controller Mode in the USBMODE register to device mode.

NOTE Transitioning from host mode to device mode requires a device controller reset before modifying USBMODE.

2. Allocate and Initialize device queue heads in system memory.

• Minimum: Initialize device queue heads 0 Tx & 0 Rx.

NOTE All device queue heads associated with control endpoints must be initialized before the control endpoint is enabled. Non-Control device queue heads must be initialized before the endpoint is used but not necessarily before the endpoint is enabled.

• For information on device queue heads, refer to Section 27.6 Device Data Structures.

3. Configure ENDPOINTLISTADDR Pointer.

• For additional information on ENDPOINTLISTADDR, refer to the Section 28.2.1 Register Map.

4. Enable the ARM interrupt — see Section 31.0 Interrupt Controller.

• Recommended: enable all device interrupts including: USBINT, USBERRINT, Port Change Detect, USB Reset Received, DCSuspend.

• For a list of available interrupts refer to the USBINT — USB Interrupt Enable and the USBSTS — USB Status register tables.

5. Set Run/Stop bit to Run Mode.

• After the Run bit is set, a device reset will occur. The DCD must monitor the reset event and adjust the software state as described in the Bus Reset section of the following Port State and

It is also not necessary to initially prime Endpoint 0 because the first packet received will always be a setup packet. The contents of the first setup packet will require a response in accordance with USB device framework command set.

M821xx Data Sheet


27.4.2 Port State and Control From a chip or system reset, the device controller enters the powered state. A transition from the powered state to the attach state occurs when the Run/Stop bit is set to a ‘1’. After receiving a reset on the bus, the port will enter the defaultFS or defaultHS state in accordance with the reset protocol described in Appendix C.2 of the USB Specification Rev. 2.0. The following state diagram depicts the state of a USB 2.0 device.

Active State Inactive State

States powered, attach, defaultFS/HS, suspendFS/HS are implemented in the device controller and are communicated to the DCD using the following status bits:

Table 27-2 Device Controller State Information Bits

Figure 27-1 Device Mode State Diagram

Bit Register

DCSuspend USBSTS

USB Reset Received USBSTS

Port Change Detect USBSTS

High-Speed Port PORTSC

M821xx Data Sheet


It is the responsibility of the DCD to maintain a state variable to differentiate between the DefaultFS/HS state and the Address/Configured states. Change of state from Default to Address and the Configured states is part of the enumeration process described in the device framework section of the USB 2.0 Specification. As a result of entering the Address state, the device address register (DEVICEADDR) must be programmed by the DCD.

Entry into the Configured indicates that all endpoints to be used in the operation of the device have been properly initialized by programming the ENDPTCTRLx registers and initializing the associated queue heads.

27.4.3 Bus ResetA bus reset is used by the host to initialize downstream devices. When a bus reset is detected, the device controller will renegotiate its attachment speed, reset the device address to 0, and notify the DCD by interrupt (assuming the USB Reset Interrupt Enable is set). After a reset is received, all endpoints (except endpoint 0) are disabled and any primed transactions will be cancelled by the device controller. The concept of priming is clarified below, but the DCD must perform the following tasks when a reset is received:

• Clear all setup token semaphores by reading the ENDPTSETUPSTAT register and writing the same value back to the ENDPTSETUPSTAT register.

• Clear all the endpoint complete status bits by reading the ENDPTCOMPLETE register and writing the same value back to the ENDPTCOMPLETE register. Cancel all primed status by waiting until all bits in the ENDPTPRIME are 0 and then writing 0xFFFFFFFF to ENDPTFLUSH. Read the reset bit in the PORTSCx register and make sure that it is still active. A USB reset will occur for a minimum of 3 ms and the DCD must reach this point in the reset cleanup before end of the reset occurs, otherwise a hardware reset of the device controller is recommended (rare.)

• A hardware reset can be performed by writing a one to the device controller reset bit in the USBCMD reset. Note that a hardware reset will cause the device to detach from the bus by clearing the Run/Stop bit. Thus, the DCD must completely re-initialize the device controller after a hardware reset.

Free all allocated dTDs because they will no longer be executed by the device controller. If this is the first time the DCD is processing a USB reset event, then it is likely that no dTDs have been allocated. At this time, the DCD may release control back to the OS because no further changes to the device controller are permitted until a Port Change Detect is indicated.

After a Port Change Detect, the device has reached the default state and the DCD can read the PORTSCx to determine if the device is operating in FS or HS mode. At this time, the device controller has reached normal operating mode and DCD can begin enumeration according to the USB standard.

In some applications, it may not be possible to enable one or more pipes while in FS mode.

Beyond the data rate issue, there is no difference in DCD operation between FS and HS modes.

NOTE: The device DCD may use the FS/HS mode information to determine the bandwidth mode of the device.

M821xx Data Sheet


27.4.4 Suspend/Resume

27.4.4.1 Suspend

27.4.4.1.1 Suspend Description

In order to conserve power, USB devices automatically enter the suspended state when the device has observed no bus traffic for a specified period. When suspended, the USB device maintains any internal status, including its address and configuration. Attached devices must be prepared to suspend at any time they are powered, regardless of if they have been assigned a non-default address, are configured, or neither. Bus activity may cease due to the host entering a suspend mode of its own. In addition, a USB device shall also enter the suspended state when the hub port it is attached to is disabled.

A USB device exits suspend mode when there is bus activity. A USB device may also request the host to exit suspend mode or selective suspend by using electrical signaling to indicate remote wakeup. The ability of a device to signal remote wakeup is optional. If the USB device is capable of remote wakeup signaling, the device must support the ability of the host to enable and disable this capability. When the device is reset, remote wakeup signaling must be disabled.

27.4.4.1.2 Suspend Operational Model

The device controller moves into the suspend state when suspend signaling is detected or activity is missing on the upstream port for more than a specific period. After the device controller enters the suspend state, the DCD is notified by an interrupt (assuming DC Suspend Interrupt is enabled). When the DCSuspend bit in the PORTSCx is set to a ‘1’, the device controller is suspended.

DCD response when the device controller is suspended is application specific and may involve switching to low power operation. Information on the bus power limits in suspend state can be found in USB 2.0 specification.

27.4.4.2 Resume

If the device controller is suspended, its operation is resumed when any non-idle signaling is received on its upstream facing port. In addition, the device can signal the system to resume operation by forcing resume signaling to the upstream port. Resume signaling is sent upstream by writing a ‘1’ to the Resume bit in the in the PORTSCx while the device is in suspend state. Sending resume signal to an upstream port should cause the host to issue resume signaling and bring the suspended bus segment (one more devices) back to the active condition.

NOTE: Review system level clocking issues defined for the clocking requirements of a suspended device controller.

NOTE: Before resume signaling can be used, the host must enable it by using the Set Feature command defined in device framework (chapter 9) of the USB 2.0 Specification.

M821xx Data Sheet


27.4.5 Managing Endpoints The USB 2.0 specification defines an endpoint, also called a device endpoint or an address endpoint as a uniquely addressable portion of a USB device that can source or sink data in a communications channel between the host and the device. The endpoint address is specified by the combination of the endpoint number and the endpoint direction.

The channel between the host and an endpoint at a specific device represents a data pipe. Endpoint 0 for a device is always a control type data channel used for device discovery and enumeration. Other types of endpoints support by USB include bulk, interrupt, and isochronous. Each endpoint type has specific behavior related to packet response and error handling. More detail on endpoint operation can be found in the USB 2.0 specification.

The USB-HS device controller hardware supports up to the USB 2.0 maximum of 32 endpoint specified numbers. Each additional endpoint beyond the required endpoint position adds additional hardware logic. The maximum number of endpoint numbers available to the DCD is configured at hardware synthesis timer. After synthesis, the DCD can enable, disable and configure endpoint type up to the maximum selected during synthesis.

Each endpoint direction is essentially independent and can be configured with differing behavior in each direction. For example, the DCD can configure endpoint 1-IN to be a bulk endpoint and endpoint 1OUT to be an isochronous endpoint. This helps to conserve the total number of endpoints required for device operation. The only exception is that control endpoints must use both directions on a single endpoint number to function as a control endpoint. Endpoint 0 is, for example, is always a control endpoint and uses the pair of directions.

Each endpoint direction requires a queue head allocated in memory. If the maximum of 16 endpoint numbers, one for each endpoint direction are being used by the device controller, then 32 queue heads are required. The operation of an endpoint and use of queue heads are described later in this document.

27.4.5.1 Endpoint Initialization

After hardware reset, all endpoints except endpoint zero are uninitialized and disabled. The DCD must configure and enable each endpoint by writing to configuration bit in the ENDPTCTRLx register. Each 32-bit ENDPTCTRLx is split into an upper and lower half. The lower half of ENDPTCTRLx is used to configure the receive or OUT endpoint and the upper half is likewise used to configure the corresponding transmit or IN endpoint. Control endpoints must be configured the same in both the upper and lower half of the ENDPTCTRLx register otherwise the behavior is undefined. The following table shows how to construct a configuration word for endpoint initialization.

Table 27-3 Device Controller Endpoint Initialization

Field Value

Data Toggle Reset ‘1’

Data Toggle Inhibit ‘0’

Endpoint Type “00” – Control

“01” – Isochronous

“10” – Bulk

“11” – Interrupt

Endpoint Stall ‘0’

M821xx Data Sheet


27.4.6 Stalling There are two occasions where the device controller may need to return to the host a STALL The first occasion is the functional stall, which is a condition set by the DCD as described in the USB 2.0 device framework (chapter 9). A functional stall is only used on non-control endpoints and can be enabled in the device controller by setting the endpoint stall bit in the ENDPTCTRLx register associated with the given endpoint and the given direction. In a functional stall condition, the device controller will continue to return STALL responses to all transactions occurring on the respective endpoint and direction until the endpoint stall bit is cleared by the DCD.

A protocol stall, unlike a function stall, is used on control endpoints is automatically cleared by the device controller at the start of a new control transaction (setup phase). When enabling a protocol stall, the DCD should enable the stall bits (both directions) as a pair. A single write to the ENDPTCTRLx register can ensure that both stall bits are set at the same instant.

Table 27-4 Device Controller Stall Response Matrix

NOTE: Any write to the ENDPTCTRLx register during operational mode mustpreserve the endpoint type field (i.e. perform a read-modify-write).

USB Packet Endpoint Stall Bit. Effect on STALL bit. USB Response

SETUP packet received by a non-control endpoint.

N/A None. STALL

IN/OUT/PING packet received by a non-control endpoint.

‘1’ None. STALL

IN/OUT/PING packet received by a non-control endpoint.

‘0’ None. ACK/ NAK/ NYET

SETUP packet received by a control endpoint.

N/A Cleared ACK

IN/OUT/PING packet received by a control endpoint

‘1’ None STALL

IN/OUT/PING packet received by a control endpoint.

‘0’ None. ACK/ NAK/ NYET

M821xx Data Sheet


27.4.7 Data Toggle Data toggle is a mechanism to maintain data coherency between host and device for any given data pipe. For more information on data toggle, refer to the USB 2.0 specification.

27.4.7.1 Data Toggle Reset

The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device controller by writing a ‘1’ to the data toggle reset bit in the ENDPTCTRLx register. This should only be necessary when configuring/initializing an endpoint or returning from a STALL condition.

27.4.7.2 Data Toggle Inhibit

This feature is for test purposes only and should never be used during normal device controller operation.

Setting the data toggle Inhibit bit active (‘1’) causes the device controller to ignore the data toggle pattern that is normally sent and accept all incoming data packets regardless of the data toggle state. In normal operation, the device controller checks the DATA0/DATA1 bit against the data toggle to determine if the packet is valid. If Data PID does not match the data toggle state bit maintained by the device controller for that endpoint, the Data toggle is considered not valid. If the data toggle is not valid, the device controller assumes the packet was already received and discards the packet (not reporting it to the DCD). To prevent the host controller from re-sending the same packet, the device controller will respond to the error packet by acknowledging it with either an ACK or NYET response.

27.4.8 Operational Model For Packet Transfers All transactions on the USB bus are initiated by the host and in turn, the device must respond to any request from the host within the turnaround time stated in the USB 2.0 Specification. At USB 1.1 Full or Low Speed rates, this turnaround time was significant and the USB 1.1 device controllers were architected so that the device controller could access main memory or interrupt a host protocol processor in order to respond to the USB 1.1 transaction. The architecture of the USB 2.0 device controller must be different because same methods will not meet USB 2.0 High-speed turnaround time requirements by simply increasing clock rate.

A USB host will send requests to the device controller in an order that can not be precisely predicted as a single pipeline, so it is not possible to prepare a single packet for the device controller to execute. However, the order of packet requests is predictable when the endpoint number and direction is considered. For example, if endpoint 3 (transmit direction) is configured as a bulk pipe, then we can expect the host will send IN requests to that endpoint. This device controller is architected in such a way that it can prepare packets for each endpoint/direction in anticipation of the host request. The process of preparing the device controller to send or receive data in response to host initiated transaction on the bus is referred to as “priming” the endpoint. This term will be used throughout the following documentation to describe the device controller operation so the DCD can be architected properly use priming. Further, note that the term “flushing” is used to describe the action of clearing a packet that was queued for execution.

M821xx Data Sheet


27.4.9 Priming Transmit Endpoints Priming a transmit endpoint will cause the device controller to fetch the device transfer descriptor (dTD) for the transaction pointed to by the device queue head (dQH). After the dTD is fetched, it will be stored in the dQH until the device controller completes the transfer described by the dTD. Storing the dTD in the dQH allows the device controller to fetch the operating context needed to handle a request from the host without the need to follow the linked list, starting at the dQH when the host request is received. After the device has loaded the dTD, the leading data in the packet is stored in a FIFO in the device controller. This FIFO is split into virtual channels so that the leading data can be stored for any endpoint up to the maximum number of endpoints configured at device synthesis time.

After a priming request is complete, an endpoint state of primed is indicated in the ENDPTSTATUS register. For a primed transmit endpoint, the device controller can respond to an IN request from the host and meet the stringent bus turnaround time of High Speed USB.

Since only the leading data is stored in the device controller FIFO, it is necessary for the device controller to begin filling in behind leading data after the transaction starts. The FIFO must be sized to account for the maximum latency that can be incurred by the system memory bus. More information about FIFO sizing is presented in section Bandwidth and Latency Issues.

27.4.9.1 Priming Receive Endpoints

Priming receive endpoints is identical to priming of transmit endpoints from the point of view of the DCD. At the device controller the major difference in the operational model is that there is no data movement of the leading packet data simply because the data is to be received from the host. Note as part of the architecture, the FIFO for the receive endpoints is not partitioned into multiple channels like the transmit FIFO. Thus, the size of the RX FIFO does not scale with the number of endpoints.

27.4.10 Interrupt/Bulk Endpoint Operational Model The behaviors of the device controller for interrupt and bulk endpoints are identical. All valid IN and OUT transactions to bulk pipes will handshake with a NAK unless the endpoint had been primed. Once the endpoint has been primed, data delivery will commence.

A dTD will be retired by the device controller when the packets described in the transfer descriptor have been completed. Each dTD describes N packets to be transferred according to the USB Variable Length transfer protocol. The formula and table on the following page describe how the device controller computes the number and length of the packets to be sent/received by the USB vary according to the total number of bytes and maximum packet length. With Zero Length Termination (ZLT) = 0

N = INT(Number Of Bytes/Max. Packet Length) + 1

With Zero Length Termination (ZLT) = 1

N = MAXINT(Number Of Bytes/Max. Packet Length)

M821xx Data Sheet


Table 27-5 Variable Length Transfer Protocol (ZLT = 0)

Table 27-6 Variable Length Transfer Protocol (ZLT = 1)

TX-dTD is complete when:

• All packets described dTD were successfully transmitted. *** Total bytes in dTD will equal zero when this occurs.

RX-dTD is complete when:

• All packets described in dTD were successfully received. *** Total bytes in dTD will equal zero when this occurs.

• A short packet (number of bytes < maximum packet length) was received. *** This is a successful transfer completion; DCD must check Total Bytes in dTD to determine the number of bytes that are remaining. From the total bytes remaining in the dTD, the DCD can compute the actual bytes received.

• A long packet was received (number of bytes > maximum packet size) OR (total bytes received > total bytes specified). *** This is an error condition. The device controller will discard the remaining packet, and set the Buffer Error bit in the dTD. In addition, the endpoint will be flushed and the USBERR interrupt will become active.

On the successful completion of the packet(s) described by the dTD, the active bit in the dTD will be cleared and the next pointer will be followed when the Terminate bit is clear. When the Terminate bit is set, the device controller will flush the endpoint/direction and cease operations for that endpoint/direction. On the unsuccessful completion of a packet (see long packet above), the dQH will be left pointing to the dTD that was in error. In order to recover from this error condition, the DCD must properly reinitialize the dQH by clearing the active bit and update the nextTD pointer before attempting to re-prime the endpoint.

There is no required interaction with the DCD for handling such errors.

Bytes (dTD) Max. Packet Length (dQH) N P1 P2 P3

511 256 2 256 255

512 256 3 256 256 0

512 512 2 512 0

Bytes (dTD) Max. Packet Length (dQH) N P1 P2 P3

511 256 2 256 255

512 256 2 256 256

512 512 1 512

NOTE: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control endpoints.

NOTE: All packet level errors such as a missing handshake or CRC error will beretried automatically by the device controller.

M821xx Data Sheet


27.4.10.1 Interrupt/Bulk Endpoint Bus Response Matrix Table 27-7 Interrupt/Bulk Endpoint Bus Response Matrix

BS Error = Force Bit Stuff Error

NYET/ACK – NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK.

SYSERR – System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive.

27.4.11 Control Endpoint Operation Model

27.4.11.1 Setup Phase

All requests to a control endpoint begin with a setup phase followed by an optional data phase and a required status phase. The device controller will always accept the setup phase unless the setup lockout is engaged.

The setup lockout will engage so that future setup packets are ignored. Lockout of setup packets ensures that while software is reading the setup packet stored in the queue head, that data is not written as it is being read potentially causing an invalid setup packet.

In hardware versions 2.3 and later, the setup lockout mechanism can be disabled and a new tripwire type semaphore will ensure that the setup packet payload is extracted from the queue head without being corrupted be an incoming setup packet. This is the preferred behavior because ignoring repeated setup packets due to long software interrupt latency would be a compliance issue.

27.4.11.1.1 Setup Packet Handling (Pre-2.3 hardware)

After receiving an interrupt and inspecting USBMODE to determine that a setup packet was received on a particular pipe:

1. Duplicate contents of dQH.SsetupBuffer into local software byte array.

2. Write '1' to clear corresponding ENDPTSETUPSTAT bit and thereby disabling Setup Lockout. (i.e. the Setup Lockout activates as soon as a setup arrives. By writing to the ENDPTSETUPSTAT, the device controller will accept new setup packets.) -

3. Process setup packet using local software byte array copy and execute status/handshake phases.

• Note that after receiving a new setup packet the status and/or handshake phases may still be pending from a previous control sequence. These should be flushed & deallocated before linking a new status and/or handshake dTD for the most recent setup packet.

Stall Not Primed Primed Underflow Overflow

Setup Ignore Ignore Ignore N/A N/A

In STALL NAK Transmit BS Error N/A

Out STALL NAKReceive +NYET/ACK N/A NAK

Ping STALL NAK ACK N/A N/A

Invalid Ignore Ignore Ignore Ignore Ignore

M821xx Data Sheet


4. Before priming for status/handshake phases ensure that ENDPTSETUPSTAT is ‘0’.

• The time from writing a ‘1’ to ENDPTSETUPSTAT and reading back a ‘0’ may vary according to the type of traffic on the bus up to nearly a 1ms, however the it is absolutely necessary to ensure ENDPTSETUPSTAT has transitioned to ‘0’ after step 1) and before priming for the status/handshake phases.

27.4.11.1.2 Setup Packet Handling (2.3 hardware and later)

Disable Setup Lockout by writing ‘1’ to Setup Lockout Mode (SLOM) in USBMODE. (once at initialization). Setup lockout is not necessary when using the tripwire as described below.

NOTE Leaving the Setup Lockout Mode As ‘0’ will result in pre-2.3 hardware behavior..

After receiving an interrupt and inspecting ENDPTSETUPSTAT to determine that a setup packet was received on a particular pipe:

1. Write '1' to clear corresponding bit ENDPTSETUPSTAT.

2. Write ‘1’ to Setup Tripwire (SUTW) in USBCMD register.

3. Duplicate contents of dQH.SetupBuffer into local software byte array.

4. Read Setup TripWire (SUTW) in USBCMD register. (if set -continue; if cleared -goto 2)

5. Write '0' to clear Setup Tripwire (SUTW) in USBCMD register.

6. Process setup packet using local software byte array copy and execute status/handshake phases.

7. Before priming for status/handshake phases ensure that ENDPTSETUPSTAT is ‘0’.

• A poll loop should be used to wait until ENDPTSETUPSTAT transitions to ‘0’ after step 1) above and before priming for the status/handshake phases.

• In core versions 3.2 and later, the time from writing a ‘1’ to ENDPTSETUPSTAT and reading back a ‘0’ is very short (~1-2 us) so a poll loop in the DCD will not be harmful.

• In core versions 3.1 and earlier, the time from writing a ‘1’ to ENDPTSETUPSTAT and reading back a ‘0’ may vary according to the type of traffic on the bus up to nearly a 1ms, however the it is absolutely necessary to ensure ENDPTSETUPSTAT has transitioned to ‘0’ after step 1) and before priming for the status/handshake phases.

NOTE: To limit the exposure of setup packets to the setup lockout mechanism (ifused), the DCD should designate the priority of responding to setup packetsabove responding to other packet completions.

NOTE: After receiving a new setup packet the status and/or handshake phases may still be pending from a previous control sequence. These should be flushed & deallocated before linking a new status and/or handshake dTD for the most recent setup packet.

M821xx Data Sheet


27.4.11.2 Data Phase

Following the setup phase, the DCD must create a device transfer descriptor for the data phase and prime the transfer.

After priming the packet, the DCD must verify a new setup packet has not been received by reading the ENDPTSETUPSTAT register immediately verifying that the prime had completed. A prime will complete when the associated bit in the ENDPTPRIME register is zero and the associated bit in the ENDPTSTATUS register is a one. If a prime fails, ie. The ENDPTPRIME bit goes to zero and the ENDPTSTATUS bit is not set, then the prime has failed. This can only be due to improper setup of the dQH, dTD or a setup arriving during the prime operation. If a new setup packet is indicated after the ENDPTPRIME bit is cleared, then the transfer descriptor can be freed and the DCD must reinterpret the setup packet.

Should a setup arrive after the data stage is primed, the device controller will automatically clear the prime status (ENDPTSTATUS) to enforce data coherency with the setup packet.

27.4.11.3 Status Phase

Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and prime the endpoint for the status phase. The DCD must also perform the same checks of the ENDPTSETUPSTAT as described above in the data phase.

27.4.11.4 Control Endpoint Bus Response Matrix

Shown in the following table is the device controller response to packets on a control endpoint according to the device controller state.

Table 27-8 Control Endpoint Bus Response Matrix



NOTE: Error handling of data phase packets is the same as bulk packets described previously.


NOTE: Error handling of data phase packets is the same as bulk packets described previously.

Token Type Endpoint State Setup Lockout


Setup ACK ACK ACK N/A SYSERR

In STALL NAK Transmit BS Error N/A N/A

OutSTALL NAK

Receive +NYET/ACK N/A NAK

N/A

Ping STALL NAK ACK N?A N?A N?A

Invalid Ignore Ignore Ignore Ignore Ignore Ignore

M821xx Data Sheet


NYET/ACK – NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK.

SYSERR – System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive.

27.4.12 Isochronous Endpoint Operational Model Isochronous endpoints are used for real-time scheduled delivery of data and their operational model is significantly different than the host throttled Bulk, Interrupt, and Control data pipes. Real time delivery by the device controller will is accomplished by the following:

• Exactly MULT Packets per (micro)Frame are transmitted/received. Note: MULT is a two-bit field in the device Queue Head. The variable length packet protocol is not used on isochronous endpoints.

• NAK responses are not used. Instead, zero length packets and sent in response to an IN request to an unprimed endpoints. For unprimed RX endpoints, the response to an OUT transaction is to ignore the packet within the device controller.

• Prime requests always schedule the transfer described in the dTD for the next (micro)frame. If the ISO-dTD is still active after that frame, then the ISO-dTD will be held ready until executed or canceled by the DCD.

An EHCI compatible host controller uses the periodic frame list to schedule data exchanges to Isochronous endpoints. The operational model for device mode does not use such a data structure. Instead, the same dTD used for Control/Bulk/Interrupt endpoints is also used for isochronous endpoints. The difference is in the handling of the dTD.

The first difference between bulk and ISO-endpoints is that priming an ISO-endpoint is a delayed operation such that an endpoint will become primed only after a SOF is received. After the DCD writes the prime bit, the prime bit will be cleared as usual to indicate to software that the device controller completed a priming the dTD for transfer. Internal to the design, the device controller hardware masks that prime start until the next frame boundary. This behavior is hidden from the DCD but occurs so that the device controller can match the dTD to a specific (micro)frame.

Another difference with isochronous endpoints is that the transaction must wholly complete in a (micro)frame. Once an ISO transaction is started in a (micro)frame it will retire the corresponding dTD when MULT transactions occur or the device controller finds a fulfillment condition. The transaction error bit set in the status field indicates a fulfillment error condition. When a fulfillment error occurs, the frame after the transfer failed to complete wholly, the device controller will force retire the ISO-dTD and move to the next ISO-dTD.

It is important to note that fulfillment errors are only caused due to partially completed packets. If no activity occurs to a primed ISO-dTD, the transaction will stay primed indefinitely. This means it is up to software discard transmit ISO-dTDs that pile up from a failure of the host to move the data. Finally, the last difference with ISO packets is in the data level error handling. When a CRC error occurs on a received packet, the packet is not retried similar to bulk and control endpoints. Instead, the CRC is noted by setting the Transaction Error bit and the data is stored as usual for the application software to sort out.

• TX Packet Retired

• MULT counter reaches zero.

• Fulfillment Error [Transaction Error bit is set]

– Packets Occurred > 0 AND # Packets Occurred < MULT

M821xx Data Sheet


• RX Packet Retired:

• MULT counter reaches zero.

• Non-MDATA Data PID is received**

– Exit criteria only valid in hardware version 2.3 or later. Previous to hardware version 2.3, any PID sequence that did not match the MULT field exactly would be flagged as a transaction error due to PID mismatch or fulfillment error.

• Overflow Error:

– Packet received is > maximum packet length. [Buffer Error bit is set]

– Packet received exceeds total bytes allocated in dTD. [Buffer Error bit is set]

• -Fulfillment Error [Transaction Error bit is set]

– # Packets Occurred > 0 AND # Packets Occurred < MULT

• CRC Error [Transaction Error bit is set]

27.4.12.1 Isochronous Pipe Synchronization

When it is necessary to synchronize an isochroous data pipe to the host, the (micro)frame number (FRINDEX register) can be used as a marker. To cause a packet transfer to occur at a specific (micro)frame number [N], the DCD should interrupt on SOF during frame N-1. When the FRINDEX=N–1, the DCD must write the prime bit. The device controller will prime the isochronous endpoint in (micro)frame N–1 so that the device controller will execute delivery during (micro)frane N,

CAUTION: Priming an endpoint towards the end of (micro)frame N01 will not guarantee deliver in (micro)frame N. The delivery may actually occur in (micro)frame N+1 if device controller does not have enough time to complete the prime before the SOF for packet N is recieved.

NOTE: For TX-ISO, MULT Counter can be loaded with a lesser value in the dTD Multiplier Override field in hardware versions 2.3 and later. If the Multiplier Override is zero, the MULT Counter is initialized to the Multiplier in the QH..

NOTE: For ISO, when a dTD is retired, the next dTD is primed for the next frame. For continuous (micro)frame to (micro)frame operation the DCD should ensure that the dTD linked-list is out ahead of the device controller by at least two (micro)frames..

NOTE: For TX-ISO, MULT Counter can be loaded with a lesser value in the dTD Multiplier Override field in hardware versions 2.3 and later. If the Multiplier Override is zero, the MULT Counter is initialized to the Multiplier in the QH..

M821xx Data Sheet


27.4.13 Isochronous Endpoint Bus Response Matrix Table 27-9 Isochronous Encpoint Bus Response Matrix

27.4.14 Managing Queue HeadsThe device queue head (dQH) points to the linked list of transfer tasks, each depicted by the device Transfer Descriptor (dTD). An area of memory pointed to by ENDPOINTLISTADDR contains a group of all dQH’s in a sequential list as shown in Figure 82. The even elements in the list of dQH’s are used for receive endpoints (OUT/SETUP) and the odd elements are used for transmit endpoints (IN/INTERRUPT). Device transfer descriptors are linked head to tail starting at the queue head and ending at a terminate bit. Once the dTD has been retired, it will no longer be part of the linked list from the queue head. Therefore, software is required to track all transfer descriptors since pointers will no longer exist within the queue head once the dTD is retired (see section Software Link Pointers).


Setup STALL STALL STALL N/A N/A

In NULL NULL Transmit BS Error N/A

Packet Packet

Out Ignore Ignore Receive N/A Drop Packet

Ping Ignore Ignore Ignore Ignore Ignore

Invalid Ignore Ignore Ignore Ignore Ignore


NULL Packet = Zero Length Packet

M821xx Data Sheet


In addition to the current and next pointers and the dTD overlay examined in section Operational Model For Packet Transfers, the dQH also contains the following parameters for the associated endpoint: Multipler, Maximum Packet Length, Interrupt On Setup. The complete initialization of the dQH including these fields is demonstrated in the next section.

27.4.15 Queue Head Initialization One pair of device queue heads must be initialized for each active endpoint. To initialize a device queue head:

• Write the wMaxPacketSize field as required by the USB Chapter 9 or application specific protocol.

• Write the multiplier field to 0 for control, bulk, and interrupt endpoints. For ISO endpoints, set the multiplier to 1,2, or 3 as required bandwidth an in conjuction with the USB Chapter 9 protocol. Note: In FS mode, the multiplier field can only be 1 for ISO endpoints.

• Write the next dTD Terminate bit field to “1”.

• Write the Active bit in the status field to “0”.

• Write the Halt bit in the status field to “0”.

NOTEThe DCD must only modify dQH if the associated endpoint is not primed and there are no outstanding dTD’s.

Figure 27-2 Endpoint Queue Head Diagram

M821xx Data Sheet


27.4.16 Operational Model For Setup Transfers As discussed in section Control Endpoint Operation Model, setup transfer requires special treatment by the DCD. A setup transfer does not use a dTD but instead stores the incoming data from a setup packet in an 8-byte buffer within the dQH.

Upon receiving notification of the setup packet, the DCD should handle the setup transfer as demonstrated here:

1. Copy setup buffer contents from dQH -RX to software buffer. .

2. Acknowledge setup backup by writing a “1” to the corresponding bit in ENDPTSETUPSTAT.

3. Check for pending data or status dTD’s from previous control transfers and flush if any exist as discussed in section Flushing/De-priming an Endpoint.

4. Decode setup packet and prepare data phase [optional] and status phase transfer as required by the USB Chapter 9 or application specific protocol.

NOTE: The acknowledgement muct occur before continuing to process the setup packet, .

NOTE: After the acknowledge has occurred, the DCD must not attempt to access the setup buffer in the dQH – RX. Only the local software copy should be examined.

NOTE: It is possible for the device controller to receive setup packets before previous control transfers complete. Existing control packets in progress must be flushed and the new control packet completed.

M821xx Data Sheet


27.4.17 Managing Transfers with Transfer Descriptors

27.4.17.1 Software Link Pointers

It is necessary for the DCD software to maintain head and tail pointers for the linked list of dTDs for each respective queue head. This is necessary because the dQH only maintains pointers to the current working dTD and the next dTD to be executed. The operations described in next section for managing dTD will assume the DCD can use reference the head and tail of the dTD linked list.

27.4.18 Building a Transfer Descriptor Before a transfer can be executed from the linked list, a dTD must be built to describe the transfer. Use the following procedure for building dTDs. Allocate 8-DWord dTD block of memory aligned to 8-DWord boundaries. Example: bit address 4:0 would be equal to “00000”

Write the following fields:

1. Initialize first 7 DWords to 0.

2. Set the terminate bit to “1”.

3. Fill in total bytes with transfer size.

4. Set the interrupt on complete if desired.

5. Initialize the status field with the active bit set to “1” and all remaining status bits set to “0”.

6. Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer.

7. Initialize buffer pointer page 1 through page 4 to be one greater than each of the previous buffer pointer.

NOTE: To conserve memory, the reserved fields at the end of the dQH can be used to store the Head & Tail pointers but it still remains the responsibility of the DCD to maintain the pointers.

Figure 27-3 Software Link Pointers

M821xx Data Sheet


27.4.19 Executing A Transfer Descriptor To safely add a dTD, the DCD must be follow this procedure which will handle the event where the device controller reaches the end of the dTD list at the same time a new dTD is being added to the end of the list.

Determine whether the link list is empty:

• Check DCD driver to see if pipe is empty (internal representation of linked-list should indicate if any packets are outstanding)

• Case 1: Link list is empty

• 1. Write dQH next pointer AND dQH terminate bit to 0 as a single DWord operation.

• 2. Clear active & halt bit in dQH (in case set from a previous error).

• 3. Prime endpoint by writing ‘1’ to correct bit position in ENDPTPRIME.

• Case 2: Link list is not empty

• 1. Add dTD to end of linked list.

• 2. Read correct prime bit in ENDPTPRIME – if ‘1’ DONE.

• 3. Set ATDTW bit in USBCMD register to ‘1’.

• 4. Read correct tatus bit in ENDPTSTAT. (store in tmp. variable for later)

• 5. Read ATDTW bit in USBCMD register.

- If ‘0’ goto 3.

- If ‘1’ continue to 6.• 6. Write ATDTW bit in USBCMD register to ‘0’.

• 7. If status bit read in (3) is ‘1’ DONE.

• 8. If status bit read in (3) is ‘0’ then Goto Case 1: Step 1.

27.4.20 Transfer Completion After a dTD has been initialized and the associated endpoint primed the device controller will execute the transfer upon the host-initiated request. The DCD will be notified with a USB interrupt if the Interrupt On Complete bit was set or alternately, the DCD can poll the endpoint complete register to find when the dTD had been executed. After a dTD has been executed, DCD can check the status bits to determine success or failure.

CAUTION Multiple dTD can be completed in a single endpoint complete notification. After clearing the notification, DCD must search the dTD linked list and retire all dTDs that have finished (Active bit cleared).

By reading the status fields of the completed dTDs, the DCD can determine if the transfers completed successfully. Success is determined with the following combination of status bits:

• Active = 0

• Halted = 0

• Transaction Error = 0

M821xx Data Sheet


• Data Buffer Error = 0

Should any combination other than the one shown above exist, the DCD must take proper action. Transfer failure mechanisms are indicated in the Device Error Matrix.

In addition to checking the status bit the DCD must read the Transfer Bytes field to determine the actual bytes transferred. When a transfer is complete, the Total Bytes transferred is by decremented by the actual bytes transferred. For Transmit packets, a packet is only complete after the actual bytes reaches zero, but for receive packets, the host may send fewer bytes in the transfer according the USB variable length packet protocol.

27.4.21 Flushing/De-priming an Endpoint It is necessary for the DCD to flush to de-prime one more endpoints on a USB device reset or during a broken control transfer. There may also be application specific requirements to stop transfers in progress. The following procedure can be used by the DCD to stop a transfer in progress:

1. Write a ‘1’ to the corresponding bit(s) in ENDPTFLUSH.

2. Wait until all bits in ENDPTFLUSH are ‘0’.

– Software note: this operation may take a large amount of time depending on the USB bus activity. It is not desirable to have this wait loop within an interrupt service routine.

3. Read ENDPTSTAT to ensure that for all endpoints commanded to be flushed, that the corresponding bits are now ‘0’. If the corresponding bits are ‘1’ after step #2 has finished, then the flush failed as described in the following:

– Explanation: In very rare cases, a packet is in progress to the particular endpoint when commanded flush using ENDPTFLUSH. A safeguard is in place to refuse the flush to ensure that the packet in progress completes successfully. The DCD may need to repeatedly flush any endpoints that fail to flush be repeating steps 1-3 until each endpoint is successfully flushed.

27.4.22 Device Error Matrix The following table summarizes packet errors that are not automatically handled by the Device Controller.

Table 27-10 Device Error Matrix

Notice that the device controller handles all errors on Bulk/Control/Interrupt Endpoints except for a data buffer overflow. However, for ISO endpoints, errors packets are not retried and errors are tagged as indicated.

Error Direction Packet Data Buffer Transaction

Type Error Bit Error Bit

Overflow ** RX Any 1 0

ISO Packet Error RX ISO 0 1

ISO Fulfillment Error Both ISO 0 1

M821xx Data Sheet


Table 27-11 Error Descriptions

27.4.23 Servicing Interrupts The interrupt service routine must consider that there are high-frequency, low-frequency operations, and error operations and order accordingly.

27.4.23.1 High-Frequency Interrupts

High frequency interrupts in particular should be handed in the order below. The most important of these is listed first because the DCD must acknowledge a setup buffer in the timeliest manner possible.

Table 27-12 Execution Interrupt Action Order

** It is likely that multiple interrupts to stack up on any call to the Interrupt Service Routine AND during the Interrupt Service Routine.

Error Descriptin

Overflow

Number of bytes received exceeded max. packet size or total buffer length **** This error will also set the Halt bit in the dQH and if there are dTDs remaining in the linked list for the endpoint, then those will not be executed.

ISO Packet ErrorCRC Error on received ISO packet. Contents not guaranteed to be correct.

ISO Fullfillment Error

Host failed to complete the number of packets defined in the dQH Error multi field within the given (micro)frame. For scheduled data delivery the DCD may need to readjust the data queue because a fulfillment error will cause Device Controller to cease data transfers on the pipe for one (micro)frame. During the “dead” (micro)frame, the Device Controller reports error on the pipe and primes for the following frame.

Execution Order

Interrupt Action

1a USB Interrupt ** Copy contents of setup buffer and acknowledge setup packet (as indicated in section Managing Queue Heads). Process setup packet according to USB 2.0 Chapter 9 or application specific protocol. Handle completion of dTD as indicated in section Managing Queue Heads.

ENDPTSETUPSTATUS

1b USB Interrupt ** ENDPTCOMPLETE

2 SOF Interrupt Action as deemed necessary by application. This interrupt may not have a use in all applications.

M821xx Data Sheet


27.4.23.2 Low-Frequency Interrupts

The low frequency events include the following interrupts. These interrupt can be handled in any order since they don’t occur often in comparison to the high-frequency interrupts.

Interrupt Action Port Change Change software state information. Sleep Enable (Suspend) Change software state information. Low power handling as necessary. Reset Received Change software state information. Abort pending transfers.

27.4.23.3 Error Interrupts

Error interrupts will be least frequent and should be placed last in the interrupt service routine.

Interrupt Action

USB Error Interrupt. This error is redundant because it combines USB Interrupt and an error status in the dTD. The DCD will more aptly handle packet-level errors by checking dTD status field upon receipt of

USB Interrupt (w/ ENDPTCOMPLETE).

System Error Unrecoverable error. Immediate Reset of core; free transfers buffers in progress and restart the DCD.

27.5 EHCI DeviationsFor the purposes a dual-role Host/Device controller, it is necessary to deviate from the EHCI specification. Device operation is not specified in the EHCI and thus the implementation supported in this core is specific to the M821xx. The host mode operation of the core is near EHCI compatible with few minor differences documented in this section. The particulars of the deviations occur in the areas summarized here:

• Embedded Transaction Translator – Allows direct attachment of FS and LS devices in host mode without the need for a companion controller.

• Device operation -In host mode the device operational registers are generally disabled and thus device mode is mostly transparent when in host mode. However, there are a couple exceptions documented in the following sections.

• Embedded design interface -This core does not a PCI Interface and therefore the PCI configuration registers described in the EHCI specification are not applicable.

27.5.1 Embedded Transaction Translator Function The USB-HS controller supports directly connected full and low speed devices without requiring a companion controller by including the capabilities of a USB 2.0 high speed hub transaction translator. Although there is no separate Transaction Translator block in the system, the transaction translator function normally associated with a high speed hub has been implemented within the DMA and Protocol engine blocks. The embedded transaction translator function is an extension to EHCI interface, but makes use of the standard data structures and operational models that exist in the EHCI specification to support full and low speed devices.

M821xx Data Sheet


27.5.1.1 Capability Registers

The following additions have been added to the capability registers to support the embedded Transaction Translator Function:

• N_TT added to HCSPARAMS – Host Control Structural Parameters • N_PTT added to HCSPARAMS – Host Control Structural Parameters

See HCSPARAMS – EHCI Compliant with extensions for usage information.

27.5.1.2 Operational Registers

The following additions have been added to the operational registers to support the embedded TT:

• TTCTRL is a new register. • Addition of two-bit Port Speed (PSPD) to the PORTSCx register.

27.5.1.3 Discovery

In a standard EHCI controller design, the EHCI host controller driver detects a Full speed (FS) or Low speed (LS) device by noting if the port enable bit is set after the port reset operation. The port enable will only be set in a standard EHCI controller implementation after the port reset operation and when the host and device negotiate a High-Speed connection (i.e. Chirp completes successfully). Since this controller has an embedded Transaction Translator, the port enable will always be set after the port reset operation regardless of the result of the host device chirp result and the resulting port speed will be indicated by the PSPD field in PORTSCx.

Therefore, the standard EHCI host controller driver requires an alteration to handle directly connected Full and Low speed devices or hubs. The change is a fundamental one in that is summarized below:

Standard EHCI EHCI with embedded Transaction Translator

After port enable bit is set following a connection and reset sequence, the device/hub is assumed to HS. FS and LS devices are assumed to be downstream from an HS hub thus, all port-level control is performed through the Hub Class to the nearest Hub.

FS and LS devices are assumed to be downstream from a HS hub with HubAddr=X. [where HubAddr is address of the Hub where the bus transitions from HS to FS/LS (i.e. Split target hub)].

After port enable bit is set following a connection and reset sequence, the device/hub speed is noted from PORTSCx.

FS and LS device can be either downstream from an HS bub or directly attached. When the FS/LS device is downstream from an HS hub, then port-level control is down using the Hub Class through the nearest Hub.. When a FS/LS device is directly attached, then port-level control is accomplished using PORTSCx.

FS and LS device can be either downstream from an HS hub with HubAddr = X [HibAddr>0] or directly attached [where HubAddr = TTHA TTHA is programmable and defaults to 0 and HubAddr is the address of the Roof Hub where the bus transitions from HS to FS/LS (i.e. Split target hub is really the root hub).

M821xx Data Sheet


27.5.1.4 Data Structures

The same data structures used for FS/LS transactions though a HS hub are also used for transactions through the Root Hub with sm embedded Transaction Translator. Here it is demonstrated how the Hub Address and Endpoint Speed fields should be set for directly attached FS/LS devices and hubs:

1. QH (for direct attach FS/LS) – Async. (Bulk/Control Endpoints) Periodic (Interrupt)

• Hub Address = TTHA (default TTHA = 0)

• Transactions to direct attached device/hub.

– • QH.EPS = Port SpeedTransactions to a device downstream from direct attached FS hub.

– • QH.EPS = Downstream Device Speed

NOTE When QH.EPS = 01 (LS) and PORTSCx.PSPD = 00 (FS), a LS-pre-pid will besent before the transmitting LS traffic.

Maximum Packet Size must be less than or equal 64 or undefined behavior may result.

2. 2. siTD (for direct attach FS) – Periodic (ISO Endpoint)

• All FS ISO transactions:

– • Hub Address = (default TTHA = 0)

– • siTD.EPS = 00 (full speed)

Maximum Packet Size must less than or equal to 1023 or undefined behavior may result.

27.5.1.5 Operational Model

The operational models are well defined for the behavior of the Transaction Translator (see USB 2.0 specification) and for the EHCI controller moving packets between system memory and a USB-HS hub. Since the embedded Transaction Translator exists within the host controller there is no physical bus between EHCI host controller driver and the USB FS/LS bus. These sections will briefly discuss the operational model for how the EHCI and Transaction Translator operational models are combined without the physical bus between. The following sections assume the reader is familiar with both the EHCI and USB 2.0 Transaction Translator operational models.

27.5.1.5.1 Micro-frame Pipeline

The EHCI operational model uses the concept of H-frames and B-frames to describe the pipeline between the Host (H) and the Bus (B). The embedded Transaction Translator shall use the same pipeline algorithms specified in the USB 2.0 specification for a Hub-based Transaction Translator. All periodic transfers always begin at B-frame 0 (after SOF) and continue until the stored periodic transfers are complete. As an example of the micro-frame pipeline implemented in the embedded Transaction Translator, all periodic transfers that are tagged in EHCI to execute in H-frame 0 will be ready to execute on the bus in B-frame 0.

It is important to note that when programming the S-mask and C-masks in the EHCI data structures to schedule periodic transfers for the embedded Transaction Translator, the EHCI host controller driver must follow the same rules specified in EHCI for programming the S-mask and C-mask for downstream Hub-based Transaction Translators. Once periodic transfers are exhausted, any stored asynchronous transfer will be moved. Asynchronous transfers are opportunistic in that they shall execute whenever possible and their operation is not tied to H-frame and B-frame boundaries with the exception that an asynchronous transfer can not babble through the SOF (start of B-frame 0.)

M821xx Data Sheet


27.5.1.5.2 Split State Machines

The start and complete split operational model differs from EHCI slightly because there is no bus medium between the EHCI controller and the embedded Transaction Translator. Where a start or complete-split operation would occur by requesting the split to the HS hub, the start/complete split operation is simple an internal operation to the embedded Transaction Translator. The following table summarizes the conditions where handshakes are emulated from internal state instead of actual handshakes to HS split bus traffic.

. Condition Emulate TT Response

The un-shaded cells represent Start-Splits and the shaded cells represent Complete-Splits.

27.5.1.5.3 Asynchronous Transaction Scheduling and Buffer Management

The following USB 2.0 specification items are implemented in the embedded Transaction Translator:

27.5.1.5.3.1 USB 2.0 – 11.17.3 • Sequencing is provided & a packet length estimator ensures no full-speed/low-speed packet babbles into SOF

time.

27.5.1.5.3.2 USB 2.0 – 11.17.4 • Transaction tracking for 2 data pipes.

27.5.1.5.3.3 USB 2.0 – 11.17.5

• Clear_TT_Buffer capability provided though the use of the TTCTRL register.

27.5.1.5.4 Periodic Transaction Scheduling and Buffer Management

The following USB 2.0 specification items are implemented in the embedded Transaction Translator:

27.5.1.6 USB 2.0 – 11.18.6.[1-2] • •Abort of pending start-splits - EOF (and not started in micro-frames 6) - Idle for more than 4 micro-frames

• •Abort of pending complete-splits - EOF - Idle for more than 4 micro-frames

.Start-Split: All asynchronous buffers full. NAK

Start-Split: All periodic buffers full. ERR

Start-Split: Success for start of Async. Transaction ACK

Start-Split: Start Periodic Transaction No Handshake (Ok

Complete-Split: Failed to find transaction in queue. Bus Time Out

Complete-Split: Transaction queue is buisy. NYET

Complete-split: Transaction in Queue is complete. [Actual handshake from LS/FS devices]

M821xx Data Sheet


27.5.1.7 USB 2.0 – 11.18.[7-8] • Transaction tracking for up to 16 data pipes.

• Some applications may not require transaction tracking up to a maximum of 16 periodic data pipes. The option to limit the tracking to only 4 periodic data pipes exists in the by changing the configuration constant VUSB_HS_TT_PERIODIC_CONTEXTS to 4. The result is a significant gate count savings to the core given the limitations implied.

CAUTION Limiting the number of tracking pipes in the EMBedded –TT to four (4) will impose the restriction that no more than 4 periodic transactions (INTERRUPT/ISOCHRONOUS) can be scheduled through the embedded-tt per frame. the number 16 was chosen in the USB specification because it is sufficient to ensure that the high-speed to full-speed periodic pipeline can remain full. keeping the pipeline full puts no constraint on the number of periodic transactions that can be scheduled in a frame and the only limit becomes the flight time of the packets on the bus.

• Complete-split transaction searching.

27.5.1.7.1 Multiple Transaction Translators

The maximum number of embedded Transaction Translators that is currently supported is one as indicated by the N_TT field in the HCSPARAMS – Host Control Structural Parameters register.

27.5.2 Device Operation The co-existence of a device operational controller within the host controller has little effect on EHCI compatibility for host operation except as noted in this section.

27.5.2.1 USBMODE Register

Given that the dual-role controller is initialized in neither host nor device mode, the USBMODE register must be programmed for host operation before the EHCI host controller driver can begin EHCI host operations.

27.5.2.2 Non-Zero Fields the register file.

Some of the reserved fields and reserved addresses in the capability registers and operational register have use in device mode, the following must be adhered to:

• Write operations to all EHCI reserved fields (some of which are device fields) with the operation registers should always be written to zero. This is an EHCI requirement of the device controller driver that must be adhered to.

• Read operations by the host controller must properly mask EHCI reserved fields (some of which are device fields) because fields that are used exclusive for device are undefined in host mode .

27.5.2.3 SOF Interrupt

This SOF Interrupt used for device mode is shared as a free running 125us interrupt for host mode. EHCI does not specify this interrupt but it has been added for convenience and as a potential software time base. See USBSTS and USBINTR registers.

NOTE: There is no data schedule mechanism for these transactions other than themicro-frame pipeline. The embedded TT assumes the number of packetsscheduled in a frame does not exceed the frame duration (1 ms) or elseundefined behavior may result.

M821xx Data Sheet


27.5.3 Embedded Design Interface This is an Embedded USB Host Controller as defined by the EHCI specification and thus does not implement the PCI configuration registers.

27.5.3.1 Frame Adjust Register

Given that the optional PCI configuration registers are not included in this implementation, there is no corresponding bit level timing adjustments like is provided by the Frame Adjust register in the PCI configuration registers. Starts of micro-frames are timed precisely to 125 us using the transceiver clock as a reference clock. i.e. 60 Mhz transceiver clock for 8-bit physical interfaces & full-speed serial interfaces or 30 Mhz transceiver clock for 16-bit physical interfaces.

27.5.4 Miscellaneous variations from EHCI

27.5.4.1 Programmable Physical Interface Behavior

This design supports multiple Physical interfaces which can operate in differing modes when the core is configured with software programmable Physical Interface Modes. See Configuration Constants. Software programmability allows the selection of the Physical interface part during the board design phase instead of during the chip design phase. The control bits for selecting the Physical Interface operating mode have been added to the PORTSCx register providing a capability that is not defined by EHCI.

27.5.4.2 Discovery

27.5.4.2.1 6.4.2.1 Port Reset

The port connect methods specified by EHCI require setting the port reset bit in the PORTSCx register for a duration of 10ms. Due to the complexity required to support the attachment of devices that are not high speed there are counter already present in the design that can count the 10ms reset pulse to alleviate the requirement of the software to measure this duration. Therefore, the basic connection is then summarized as the following:

• [Port Change Interrupt] Port connect change occurs to notify the host controller driver that a device has attached.

• Software shall write a ‘1’ to the reset the device.

• Software shall write a ‘0’ to the reset the device after 10 ms.

– This step, which is necessary in a standard EHCI design, may be omitted with this implementation. Should the EHCI host controller driver attempt to write a ‘0’ to the reset bit while a reset is in progress the write will simple be ignored and the reset will continue until completion.

• [Port Change Interrupt] Port enable change occurs to notify the host controller that the device in now operational and at this point the port speed has been determined.

M821xx Data Sheet


27.5.4.2.2 Port Speed Detection

After the port change interrupt indicates that a port is enabled, the EHCI stack should determine the port speed. Unlike the EHCI implementation which will re-assign the port owner for any device that does not connect at High-Speed, this host controller supports direct attach of non High-Speed devices. Therefore, the following differences are important regarding port speed detection:

• Port Owner is read-only and always reads 0.

• A 2-bit Port Speed indicator has been added to PORTSC to provide the current operating speed of the port to the host controller driver.

• A 1-bit High Speed indicator has been added to PORTSC to signify that the port is in High-Speed vs. Full/Low Speed – This information is redundant with the 2-bit Port Speed indicator above.

27.5.4.3 Port Test Mode

Port Test Control mode behaves fully as described in EHCI since the release of revision 3.2.1. In earlier product revisions, the test packet mode was not EHCI compatible. An alternate host controller driver procedure is no longer necessary or supported.

M821xx Data Sheet


27.6 Device Data StructuresThis section defines the interface data structures used to communicate control, status, and data between Device Controller Driver (DCD) Software and the Device Controller. The data structure definitions in this chapter support a 32-bit memory buffer address space. The interface consists of device Queue Heads and Transfer Descriptors.

The data structures defined in the chapter are (from the device controller’s perspective) a mix of read-only and read/ writeable fields. The device controller must preserve the read-only fields on all data structure writes.

The USB-HS core includes DCD Software called the USB 2.0 Device API. The Device API provides an easy to use Application Program Interface for developing device (peripheral) applications using the USB-HS core. The Device API incorporates and abstracts for the application developer all of the elements of the program interface.

NOTE: Software must ensure that no interface data structure reachable by the Device Controller spans a 4K-page boundary.

Figure 27-4 End Point Queue Head Organization

M821xx Data Sheet


Device queue heads are arranged in an array in a continuous area of memory pointed to by the ENDPOINTLISTADDR pointer. The even – numbered device queue heads in the list support receive endpoints (OUT/SETUP) and the odd-numbered queue heads in the list are used for transmit endpoints (IN/INTERRUPT). The device controller will index into this array based upon the endpoint number received from the USB bus. All information necessary to respond to transactions for all primed transfers is contained in this list so the Device Controller can readily respond to incoming requests without having to traverse a linked list.

27.6.1 Endpoint Queue Head (dQH)The device Endpoint Queue Head (dQH) is where all transfers are managed. The dQH is a 48-byte data structure, but must be aligned on 64-byte boundaries. During priming of an endpoint, the dTD (device transfer descriptor) is copied into the overlay area of the dQH, which starts at the next TD pointer DWord and continues through the end of the buffer pointers DWords. After a transfer is complete, the dTD status DWord is updated in the dTD pointed to by the current TD pointer. While a packet is in progress, the overlay area of the dQH is used as a staging area for the dTD so that the Device Controller can access needed information with little minimal latency.

NOTE: The Endpoint Queue Head List must be aligned to a 2k boundary.

M821xx Data Sheet


27.6.1.1 Endpoint Capabilities/Characteristics

This DWord specifies static information about the endpoint, in other words, this information does not change over the lifetime of the endpoint. Device controller software should not attempt to modify this information while the corresponding endpoint is enabled.

Figure 27-5 End Point Queue Head (dQH)

Table 27-13 USBMODE— USB Device Mode

Bit No. Description31 – 30 Mult. This field is used to indicate the number of packets executed per

transaction description as given by the following:

00 – Execute N Transactions as demonstrated by the USB variable length packet protocol where N is computed using the Maximum Packet Length (dQH) and the Total Bytes field (dTD)

01 – Execute 1 Transaction.10 – Execute 2 Transactions.11 – Execute 3 Transactions.

Note: Non-ISO endpoints must set Mult=”00”.Note: ISO endpoints must set Mult=”01”, “10”, or “11” as needed.

M821xx Data Sheet


27.6.1.2 Transfer Overlay

The seven DWords in the overlay area represent a transaction working space for the device controller. The general operational model is that the device controller can detect whether the overlay area contains a description of an active transfer. If it does not contain an active transfer, then it will not read the associated endpoint.

After an endpoint is readied, the dTD will be copied into this queue head overlay area by the device controller. Until a transfer is expired, software must not write the queue head overlay area or the associated transfer descriptor. When the transfer is complete, the device controller will write the results back to the original transfer descriptor and advance the queue. See dTD for a description of the overlay fields.

27.6.2 Current dTD Pointer The current dTD pointer is used by the device controller to locate the transfer in progress. This word is for Device Controller (hardware) use only and should not be modified by DCD software.

Table 27-14 Next dTD Pointer

27.6.3 Set-up Buffer The set-up buffer is dedicated storage for the 8-byte data that follows a set-up PID.

29 Zero Length Termination Select. This bit is used to indicate when a zero length packet is used to terminate transfers where to total length is a multiple. This bit is not relevant for Isochronous operation.

0 – Enable zero length packet to terminate transfers equal to multiple of the Maximum Packet Length (default).

1 – Disable the zero length packet on transfers that are equal in length to a multiple Maximum Packet Length.

28:27 Reserved: These bit reserved for future use and should be set to zero.

26:16 Maximum Packet Length. This directly corresponds to the maximum packet size of the associated endpoint (MaxPacketSize). The maximum value this field may contain is 0x400 (1024).

15 Interrupt On Setup (IOS). This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.

14:0 Reserved. Bits reserved for future use and should be set to zero.

Bit No. Description31 –:5 Current dTD. This field is a pointer to the dTD that is represented in the transfer overlay

area. This field will be modified by the Device Controller to next dTD pointer during endpoint priming or queue advance.

4:0 Reserved. Bit reserved for future use and should be set to zero.

NOTE: Each endpoint has a TX and an RX dQH associated with it, and only the RX queue head is used for receiving setup data packets.

Table 27-13 USBMODE— USB Device Mode

M821xx Data Sheet


Table 27-15 Multiple Mode Control (HCCPARAMS)

27.6.4 Endpoint Transfer Descriptor (dTD)The dTD describes to the device controller the location and quantity of data to be sent/received for given transfer. The DCD should not attempt to modify any field in an active dTD except the Next Like Pointer, which should only be modified as described in section Managing Transfers with Transfer Descriptors.

Table 27-16 Next dTD Pointer

DWORD Bit No. Description

1 31:0 Setup Buffer 0. This buffer contains bytes 3 to 0 of an incoming setup buffer packet and is written by the device controller to be read by software.

2 31:0 Setup Buffer 1. This buffer contains bytes 7 to 4 of an incoming setup buffer packet and is written by the device controller to be read by software.

Figure 27-6 Endpoint Transfer Descriptor (dTD)

Bit Description

31:5 Next Transfer Element Pointer. This field contains the physical memory address of the next dTD to be processed. The field corresponds to memory address signals [31:5], respectively.


0 Terminate (T). 1=pointer is invalid. 0=Pointer is valid (points to a valid Transfer Element Descriptor). This bit indicates to the Device Controller that there are no more valid entries in the queue.

M821xx Data Sheet


.

Table 27-17 dTD Tolken

Bit No. Description

31 Reserved. Bit reserved for future use and should be set to zero.

30:16

Total Bytes. This field specifies the total number of bytes to be moved with this transfer descriptor. This field is decremented by the number of bytes actually moved during the transaction and only on the successful completion of the transaction. The maximum value software may store in the field is 5*4K(5000H). This is the maximum number of bytes 5 page pointers can access. Although it is possible to create a transfer up to 20K this assumes the 1st offset into the first page is 0. When the offset cannot be predetermined, crossing past the 5th page can be guaranteed by limiting the total bytes to 16K**. Therefore, the maximum recommended transfer is 16K(4000H). If the value of the field is zero when the host controller fetches this transfer descriptor (and the active bit is set), the device controller executes a zero-length transaction and retires the transfer descriptor. It is not a requirement for IN transfers that Total Bytes To Transfer be an even multiple of Maximum Packet Length. If software builds such a transfer descriptor for an IN transfer, the last transaction will always be less that Maximum Packet Length.

15 Interrupt On Complete (IOC). This bit is used to indicate if USBINT is to be set in response to device controller being finished with this dTD.


11:10

Multiplier Override (MultiO). This field can be used for transmit ISO’s (i.e. ISO-IN) override the multiplier in the QH. This field must be zero for all packet types that are not transmit-ISO.

Example:

If QH.multiplier = 3; Maximum packet size = 8; Total Bytes = 15; MultiO = 0 [default]

Three packets are sent: Data2(8); Data1(7); Data0(0)

if QH.multiplier = 3; Maximum packet size = 8; Total Bytes = 15; MultiO = 2

Two packets are sent: Data1(8); Data0(7)

For maximal efficiency, software should compute MultO = greatest integer of (Total

Bytes / Max. Packet Size) except for the case when Total Bytes = 0; then MultO should be 1.

Note: Non-ISO and Non-TX endpoints must set MultO=”00”.


7:0

Status. This field is used by the Device Controller to communicate individual command execution states back to the device controller software. This field contains the status of the last transaction performed on this tDQ. The bit encodings are:Bit Status Field Description7 Adctive 6 Halted5 Data Buffer Error3 Transaction Error4, 2, 0 Reserved.

M821xx Data Sheet


Table 27-18 dTD Buffer Page Pointer List

Bit No. Description

31:12Buffer Pointer. Selects the page offset in memory for the packet buffer. Non virtual memory systems will typically set the buffer pointers to a series of incrementing integers.

0,11 0 Current Offset. Offset into the 4kb buffer where the packet is to begin.

1,10, 0Frame Number. Written by the device controller to indicate the frame number in which a packet finishes. This is typically be used to correlate relative completion times of packets on an ISO endpoint.

M821xx Data Sheet


27.7 USB Power ManagementA device may suspend operations autonomously by disconnecting from the USB, or in response to the suspend signaling on the USB has moved it into the suspend state. A host can suspend operation autonomously, or it can command portions, or the entire USB to transition into the suspend state.

27.7.1 USB Power StatesThe USB provides a mechanism to place segments of the USB or the entire USB into a low power suspend state. USB bus powered devices are required to respond to a 3ms lack of activity on the USB bus by going into a suspend state. In the USB controller software is notified of the suspend condition via the transition in the PORTSC register, optionally an interrupt can be generated which is controlled by the port change Detect Enable bit in the VSBINTR control register. Software then has 7 ms to transition a bus powered device into the suspend state. In the suspend state, a USB device has a maximum USB bus power budget of 500uA. In general, to achieve that level of power conservation, most of the device circuits will need to be switched off, or clock at an extremely low frequency. This can be accomplished by suspending the clock, or additionally by implementing independent power wells in the fabrication of the design. When the clock is disabled to the USB controller core all functions are disabled, but all operational state is retained. The LineState signals can be used to construct a circuit that is able to detect the resume signaling on the bus and restore the clocks to the rest of the circuit. Implementing power wells requires intimate knowledge of the characteristics of the silicon process used to isolate the active and inactive portions of the design in the low power states. Power wells are beyond the scope of this document.

The implementation of low power states in the USB controller core is dependant on the use of the device role (host or peripheral), whether the device is bus powered, and the selected clock architecture of the core. Bus powered peripheral devices are required by the USB specification to support a low power suspend state. Self powered peripheral devices and hosts set their own power management strategies based on their system level requirements. The clocking architecture selected is important to consider as it determines what portions of the design will remain active when transitioned into the low power state. In clock configuration 0 the entire system is clocked from the transceiver clock. In clock architecture 1 the transceiver clock is only used to cross the asynchronous boundary in the transceiver interface. In clock architecture 2 the transceiver clock is used to clock all the port control and protocol Engine functions (for more on supported clock architectures see Core and System Clocking

Before the system clock is suspended or set to a frequency that is below the operational frequency of the USB-HS core, the core must be moved from the operational state to a low power state. The power strategies designed into the USB-HS core allow for the most challenging case, a self powered device that is clocked entirely by the transceiver clock.

27.7.2 Device Power StatesIn the operational state both the transceiver clock and system clocks are running. Software can initiate a low power mode autonomously by disconnecting from the host to go into the disconnect state. Once in this state the software can set the suspend bit to turn off the transceiver clock putting the system in to the disconnect-suspend state. Since software cannot depend on the presents of a clock to clear the suspend bit, a wake-up event must be defined which would clear the suspend bit and allow the transceiver clock to resume.

M821xx Data Sheet


The device can also go into suspend mode as a result of a suspend command from the host. Suspend is signaled on the bus by 3ms of idle time on the bus. This will generate a suspend interrupt to the software at which point the software must prepare to go into suspend then set the suspend bit. Once the suspend bit is set the transceiver clock may turn off and the device will be in the suspended state. The device has two ways of getting out of suspend. If remote wake-up is enabled a wake-up event could be defined which would clear the suspend bit. The software would then initiate the resume by setting the resume bit in the port controller then waiting for a port change interrupt indicating that the port is in an operational state. The other way for a device to get out of suspend is if the host puts resume signaling on the bus. This will clear the suspend bit and generate a port change interrupt when the resume is finished.

Figure 27-7 Device Power State Diagram

M821xx Data Sheet


27.7.3 Host Power StatesFrom an operational state when a host gets a low power request, it must set the suspend bit in the port controller. This will put an idle on the bus, block all traffic through the port and turn off the transceiver clock. There are two ways for a host controller to get out of the suspend state. If it has enabled remote wake-up, a K-state on the bus will turn the transceiver clock and generate an interrupt. The software will then have to wait 20 ms for the resume to complete and the port to go back to an active state. Alternatively an external event could clear the suspend bit and start the transceiver clock running again. The software can then initiate a resume by setting the resume bit in the port controller, or force a reconnect by setting the reset bit in the port controller.

If all devices have disconnected from the host, the host can go into a low power mode by the software setting the suspend bit. From the disconnect-suspend state a connect event would start the transceiver clock and interrupt the software. The software would then need to set the reset bit to start the connect process.

Figure 27-8 Host Power State Diagram

.


28.0 USB Registers

28.1 IntroductionSection 28.2 through Section 28.6 present registers supporting host and device mode. Non-EHCI compatible registers are identified.

Use Table 28-1 to find specific registers.

28.2 Register Set OverviewThe two M821xx USB controller’s register-level interfaces are compatible with the Intel EHCI (Enhanced Host Controller Interface) spcification. The ARMs accesses the USB controller configuration, control, and status registers through slave access across the APB. The base addresses for the two USB controllers are:

• USB0 — 0x0F00 0000

• USB1 — 0x0F80 0000

Register offset definitions are listed in Table 28-1 below. One function of the system address map is the registers base address, which must begin on a DWord (32-bit) boundary. Configuration, control and status registers are divided into three categories, identification, capability and operational registers.

• Identification registers are used to declare the slave interface presence along with the complete set of the hardware configuration parameters.

• Static, read only capability registers define the software limits, restrictions, and capabilities of the host/device controller.

• Operational registers are comprised of dynamic control or status registers that may be read only, read/write, or read/write to clear. The following sections define the use of these registers. EHCI registers are listed alongside device registers to show the complementary nature of host and device control.

28.2.1 Register Map

NOTE: Host mode EHCI compatibility begins at offset 0x100. If it is necessary to begin the EHCI register set at offset 0x000, the identification registers are disabled from the address map by connecting the upper most address bit of the slave interface to a logic level ‘1’ and adjusting the offsets below accordingly.

NOTE: In the following table, rows in Italic Type show registers that deviate from the the EHCI specification.

M821xx Data Sheet


Table 28-1 Memory DMA Register Map

APB AddressOffset

Size in Bytes Mnemonic and Name

000 4 ID

004 4 HWGENERAL

008 4 HWHOST

00C 4 HWDEVICE

010 4 HWTXBUF

014 4 HWRXBUF

018—07C 96 Reserved

080 4 GPTIMER0LD

084 4 GBTIMER0CTRL

088 4 GBTIMER1LD

08C 4 GBTIMER1CTRL

090—0FC 112 Reserved

100 1 CAPLENGTH

101 1 Reserved

102 2 HCIVERSION

104 4 HCSPARAMS

108 4 HCCPARAMS

10C—11F 20 Reserved

120 2 DCIVERSION

122 2 Reserved

124 4 DCCPARAMS

128h —13C 24 Reserved

140 4 USBCMD

144 4 USBSTS

148 4 USBINTR

14C 4 FRINDEX

150 4 Reserved

154 4 PERIODICLISTBASE; DEVICEADDR

158 4 ASYNCLISTADDR, ENDPOINTLISTADDR

15C 4 TTCTRL

160 4 BURSTSIZE

164 4 TXFILLTUNUNG

M821xx Data Sheet


168 — 16C 8Reserved

170 — 174 4

178 4 ENDPTNAK

17C 4 ENDPTNAKEN

180 4 Reserved

184 4 PORTSCx

188 4 PORTSC2

18C 4 PORTSC3

190 4 PORTSC4

194 4 PORTSC5

198 4 PORTSC6

19C 4 PORTSC7

1A0 4 PORTSC8

1A4 4 Reserved.

1A8 4 USBMODE

1AC 4 ENDPTSETUPSTAT

1B0 4 ENDPTPRIME

1B4 4 ENDPTFLUSH

1B8 4 ENDPTSTAT

1BC 4 ENDPTCOMPLETE

1C0 4 ENDPTCTRL1 – ENDPTCTRL15

1C4 4 ENDPTCTRL1

... 4 ENDPTCTRLx

1FC 4 ENDPTCTRL15

Table 28-1 Memory DMA Register Map (Continued)

APB AddressOffset

Size in Bytes Mnemonic and Name

M821xx Data Sheet


28.2.2 Register AccessIn the following register descriptions, access constraints to registers are defined:

• RO — Read Only — If a register is read only, writes have no effect.

• WO — Write Only — If a register is write only, reads return “0”s for all bit positions.

• R/W — Read/ Write — A register with this attribute can be read or written. Note that a R/W register may include bit fields that are Read Only.

• R/W C — Read/Write Clear — A register bit with this attribute can be read or written. However, a write of “1’ clears the register (sets it to “0”) while a write of “0” has no effect.

28.3 Identification RegistersIdentification registers declare the slave interface presence and include a table of the hardware configuration parameters.

28.3.1 IDOffset: 0x000 [Read Only; Default: Implementation dependent]This register provides a simple way to check the USB controller revision level.

Table 28-2 ID — Identification Register

Bit No. Field Name Description31 – 24 RSVD Reserved. These bits are reserved and should be set to zero.

23 – 16 Revision[7:0] Revision number of controller.

15 – 14 RSVD Set to ‘1’.

13 – 8 NID[5:0] Ones complement version of ID[5:0].

7 – 6 RSVD Reserved. These bits are reserved and should be set to zero.

5 – 0 ID Configuration number. Set to 0x05.

M821xx Data Sheet


28.3.2 HWGENERALOffset: 0x004 [Read Only; Default: Implementation dependent]

Presents general hardware parameters for the controller.

Table 28-3 HWGENERAL — General Hardware Parameters

Bit No. Field Name Description31 – 10 RSVD Reserved. Set to ‘0’.

9 SM VUSB_HS_PHY_SERIAL

8 – 6 PHYM VUSB_HS_PHY_TYPE

5 – 4 PHYW VUSB_HS_PHY16_8

3 BWT Reserved for internal testing

2 – 1 CLKC VUSB_HS_CLOCK_CONFIGURATION

0 RT VUSB_HS_RESET

M821xx Data Sheet


28.3.3 HWHOSTOffset: 0x008 [Read Only; Default: Implementation dependent]

Host hardware parameters.

28.3.4 HWDEVICEOffset: 0x00C [Read Only; Default: Implementation dependent]Device hardware parameters..

28.3.5 HWTXBUFOffset: 0x010 [Read Only; Default: Implementation dependent]TX hardware parameters.

Table 28-4 HWHOST — Hardware Host Parameters

Bit No. Field Name Description31 – 24 TTPER VUSB_HS_TT_PERIODIC_CONTEXTS

23-16 TTASY VUSB_HS_TT_ASYNC_CONTEXTS

15– 4 RSVD Reserved. Clear to ‘0’.

3 – 1 NPORT VUSB_HS_NUM_PORT-1

0 HC VUSB_HS_HOST

Table 28-5 HWDEVICE — Device Hardware Parameters

Bit No. Field Name Description31 – 6 RSVD Reserved. Clear to ‘0’.

5 - 1 DEVEP VUSB_HS_DEV_EP

0 DC device capable; [VUSB_HS_DEV /=0]

Table 28-6 ID Register Description

Bit No. Field Name Description31 TXLCR .

30 - 24 RSVD Reserved. Set to ‘0’.

23 - 16 TXCANADD VUSB_HS_TX_CHAN_ADD

15 - 8 TXADD VUSB_HS_TX_ADD

7 - 0 TCBURST VUSB_HS_TX_BURST

M821xx Data Sheet


28.3.6 HWRXBUFOffset: 0x014 [Read Only; Default: Implementation dependent]

RX buffer parameters.

28.4 Device/Host Capability RegistersThe device/host capabilities registers specify the software limits, restrictions, and capabilities of host/device controller implementation.

28.4.1 CAPLENGTH EHCI compliantOffset: 0x100 [Read Only; 0x40]This register is used to indicate which offset to add to the register base address at the beginning of the operational register.

28.4.2 HCIVERSIONEHCI compliant

Offset: 0x102 [Read Only; Default: 0x0100]

The is a two-byte register containing a BCD encoding of the EHCI revision number supported by this controller. The most significant byte of this register represents a major revision and the least significant byte is the minor revision.

Table 28-7 ID Register Description

Bit No. Field Name Description31 – 16 RSVD Reserved.

15 - 8 RXADD VUSB_HS_RX_ADD

7 - 0 TXCANADD VUSB_HS_RX_BURST

Table 28-8 CAPLENGTH — Capability Register Length

Bit No. Field Name Description7 - 0 CAPLENGTH[7:0] Capability register length.

Table 28-9 HCIVERSION — Host Interface Version Number

Bit No. Field Name Description15 - 0 HCIVERSION Host interface version number.

M821xx Data Sheet


28.4.3 HCSPARAMSEHCI compliant with extensions

Offset: 0x104 [Read Only; Default: Implementation dependent] This register defines port steering logic capabilities.

Table 28-10 IHCSPARAMS — Host Control Structural Parameters

Bit No. Field Name Description31 – 28 RSVD Reseved. Set to “0”.

27 – 24 N_TT[3:0] Number of Transaction Translators (N_TT). The number of transaction translators in the controller. For Multi-Port Hosts this field will always equal “0001”. For all other implementations, N_TT = “0000”. This in a non-EHCI field to support embedded TT.

23 – 20 N_PTT[3:0] Number of Ports per Transaction Translator (N_PTT). This field indicates the number of ports assigned to each transaction translator within the controller. For Multi-Port Host this field will always equal N_PORTS. For all other implementations, N_PTT = ‘0000”. This in a non-EHCI field to support embedded TT.

19 –17 RSVD Reserved.

16 PI Port Indicators (P INDICATOR). This bit indicates whether the ports support port indicator control. When set to one, the port status and control registers include a read/writeable field for controlling the state of the port indicator.This field will always be “1”.

15 – 12 N_CC[3:0] Number of Companion Controllers (N_CC). This field gives the number of companion controllers. A “0” in this field shows there are no internal Companion Controllers. Port ownership hand-off is not supported.A value larger than zero in this field indicates there are companion USB1.1 host controller(s) and that port-ownership hand-offs are supported. High-, Full-, and Low-speed devices are supported on the host controller root ports.

11 – 8 N_PCC[3:0] Number of Ports Per Companion Controller. (N_PCC[3:0]). This field indicates the number of ports supported per internal companion controller. It is used to indicate the port routing configuration to the system software. For example, if N-PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3. The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc. In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2. The number in this field must be consistent with N_PORTS and N_CC. For this controller this field is always “0”.

7 – 5 RSVD Reserved.

4 PPC[ Post Power Control. (PPC) This field indicates whether the host controller implementation includes port power control. A one indicates the ports have port power switches. A zero indicates the ports do not have port power switches. The value of this field affects the functionality of the Port Power field in each port status and control register. This field always be “0” for device-only implementations.

M821xx Data Sheet


28.4.4 HCCPARAMSEHCI Compliant

Offset: 0x108 [Read Only; Default: 0x0006]This register identifies multiple mode control (time-base functionality) addressing capability..

3 – 0 N_PORTS Number of Downstream Ports. (N_PORTS) This field specifies the number of physical downstream ports implemented on this host controller. The value of this field determines how many port registers are addressable in the Operational Register. Valid values are in the range of 0x1 to 0xF. A zero in the field is undefined. The number of ports supporting a host implementation may range from 1 to 8. This field will always be 1 for device-only implementation.

Table 28-11 HCCPARAMS — Host Control Capability Parameters

Bit No. Field Name Description31 – 16 RSVD Reserved. Clear to “0”.

15 - 8 EECP[7:0 EHCI Extended Capabilities Pointer. Default = 0. This optional field indicates the existence of a capabilities list. A value of 00h indicates no extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI configuration space of the first EHCI extended capability. The pointer value must be 0x40 or greater if implemented to maintain the consistency of the PCI header defined for the class of device.For this implementation this field is always ‘0’.

7 – 4 IST[7:4] Isochronous Scheduling Threshold. Default = implementation dependent. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronus schedule. When bit[7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. When bit[7] is one, then host software assumes the host controller may cache an isochronous data structure for an entire frame. This field will always be “0”.

3 RSVD Reserved.

2 ASP Asynchronous Schedule Park Capability. Default =”1”. This field is always ‘1’, thus the host controller supports the park feature for high speed queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. This field will always be “1”.

1 PFL Programmed Frame List Flag. If this bit is set to “0”, then the system software must use a frame length list length of 1024 elements with this host controller. The USBCMD register Frame List Size filed is a read-only register and must be set to zero.If set to a one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-page boundary. This requirement ensures that the frame list is always physically contiguous. This field will always be “1’.

Table 28-10 IHCSPARAMS — Host Control Structural Parameters (Continued)

M821xx Data Sheet


28.4.5 DCIVERSION Non-EHCIOffset: 0x120 [Read Only; Default: Implementation dependent]

The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register.

28.4.6 DCCPARAMSNon-EHCIOffset: 0x124 [Read Only; Default: Implementation dependent]These fields describe the overall host/device capability of the controller.

0 ADC 64-bit Addressing Capability. This field is always “0” because no 64-bit addressing capability is supported.

Table 28-12 DCIVERSION — Device Interface Version Number

Bit No. Field Name Description15 – 0 DCIVERSION[15:0] Device Capable. When this bit is one, the controller is capable as operating as a USB

2.0 device.

Table 28-13 DCIVERSION — Device Control Capability Parameters

Bit No. Field Name Description31 – 9 RSVD Reserved. Cleared to “0”.

8 HC Host Capable. When this bit is “1”, this controller is capable of operating as an EHCI compatible USB 2.0 host controller.

7 DC Device Capable. When this bit is one, the controller is capable as operating as a USB 2.0 device.

6 – 5 RSVD Reserved. Cleared to “0”.

4 – 0 DEN[4:0] Device Endpoint Number. This field indicates the number of endpoints built into the device controller. If this controller is not device capable, then this field will be zero. Valid values are 0 — 16.

Table 28-11 HCCPARAMS — Host Control Capability Parameters

M821xx Data Sheet


28.5 Device/Host Timer Registers (Non-EHCI)These timer registers, which are not part of the EHCI specification, allow the host/device controller drivers to measure time-related activities.

28.5.1 GPTIMER0LDNon-EHCIOffset: 0x080 [Read / Write; Default: 0x0000 0000]

The register contains the timer duration or load value. See GBTIMER0CTRL for a description of the timer functions.

28.5.2 GBTIMER0CTRLNon-EHCIOffset: 0x084 [Read Only, Write Only, Read/Write; Default: 0x 0000 0000]This register contains the control for the timer and a data field can be queried to determine the running count value. This timer has granularity of 1 usec and can be set to slighltly over 16 seconds. The timer can be set up in two modes: first as a one shot and second as a looped count (see the following table) When the timer counter value transitions to zero, an interrupt can be generated though the use of the timer interrupts in the USBSTS and USBINTR registers.

Table 28-14 GPTIMER0LD — General Purpose Timer #0 Load Register

Bit No. Field Name Description31 – 24 RSVD Reserved. set to “0”.

23 – 0 GPTLD General Purpose Timer Load Value. This field is the value to be loaded into the GPTCNT countdown timer on a reset action. This value in this register represents the time in microseconds minus 1 for the timer duration.Example: For a one milisecond timer, load 1000-1=999 or 0x0003E7.Note: Max value is 0xFFFFFF or 16.555215 seconds.

Table 28-15 GPTIMER0CTRL — General Purpose Timer #0 Control Register

Bit No. Field Name Description31 GTPRUN General Purpose Timer Run. Read/Write. (0) – Timer stop; (1) – Timer run. This bit

enables the general purpose timer to run. Setting or clearing this bit will not have an effect on the GBTCNT.

30 GPTRST General Purpose Timer Reset. Write-only. (0) – No action; (1) – Load counter value. Writing a one to this bit will reload the GPTCNT with the value in GPTLD.

29 – 25 RSVD Reserved. These bits are set to “0”.

24 GPTMODE General Purpose Timer Mode. Read/Write. (0) – One shot; (1) – Repeat. This bit selects between a single timer countdown and a looped count down. In one-shot mode, the timer will count down to zero, generate and interrupt, and stop until the counter is reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter to start again.

23 0 GPTCNT General Purpose Timer Counter. Read-only. This field is the value of the running timer.

M821xx Data Sheet


28.5.3 GBTIMER1LDNon-EHCIOffset: 0x088 [Read/Write; Default: 0x 0000 0000]

Same as GPTIMER0LD.

28.5.4 GBTIMER1CTRLNon-EHCIOffset: 0x08C [Read Only, Write Only, Read/Write; Default: 0x 0000 0000]

Same as GBTIMER0CTRL.

28.6 Device/Host Operational Registers The following operational registers are comprised of dynamic control or status registers that may be read only, read/write, or read/write to clear. The operational base must be DWord aligned and is calculated by adding the value in the first capabilities register (CAPLENGTH) to the base register of the enhanced host controller register address space.

The following sections define the use of these registers.

28.6.1 USBCMDOffset: 0x140 [Read Only; Read/Write. Write Only (Field Dependent) Default: 0x0008 0B00 (host mode); 0x0008 0000]The serial bus host/device controller executes the command in this register.

Table 28-16 USBCMD — USB Command Register

Bit No. Field Name Description31 – 24 RSVD Reserved. Clear to “0”.

23 – 16 ITC Interrupt Threshold Control — Read/Write. Default 0x08. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below.

Value Maximum Interrupt Interval• 0x00 immedeate (no threshold)• 0x01 1 micro-frame•0x02 2 micro-frames•0x04 4 micro-frames•0x08 8 micro-frames•0x10 16 micro-frames•0x20 32 micro-frames•0x40 64 micro-frames

15 FS2 See bits 3 – 2 in this table/

14 RSVD Reserved.

13 SUTW Setup TripWire – Read Write. [device mode only].

12 ATDTW Add dTD TripWire – Read/Write. [device mode only].

M821xx Data Sheet


11 ASPE Asynchronous Schedule Park Mode Enable (OPTIONAL) — Read/Write. If the Asynchronous Park Capability bit in HCCPARAMS register is a one, then this bit defaults to 0x1 and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero. Park mode is disabled. This field is set to “1” in this implementation.

10 RSVD Reserved. Set to “0”.

9 – 8 ASP[1:0] Asynchronous Schedule Park Mode Count (OPTIONAL) — Read/Write. If the Asynchrounous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 0x3 and is R/W. Otherwise it defaults to zero and is RO. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchrounous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior.

7 LR Light Host / Device Controller Reset (OPTIONAL) — Read only. Not implemented. This field will always be “0”.

6 IAA Interupt on Async Advance Doorbell — Read/Write. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell.

When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINT register is one, then the host controller will assert an interrupt at the next interrupt threshold.

The host controller sets this bit to zero after it sets the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results.

This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results.

This bit is only used in host mode. Writing a one to this bit when device mode is selected will produce unpredictable results.

5 ASE Asynchronous Schedule Enable — Read/Write. Default 0b. This bit controls whether the host controller skips processing the Asynchronous Schedule.

Value Meaning• 0 Do not process the Asynchronous Schedule.• 1 Use the ASYNCLISTADDR register to access the Asynchronous Schedule.

Only the host controller uses this bit.

4 PSE Periodic Schedule Enable — Read/Write. Default 0b. This bit controls whether or not the host controller skips processing the Periodic Schedule.

Value Meaning• 0 Do not process the Periodic Schedule.• 1 Use the PERIODICLISTBASE register to access the Periodic Schedule.

Only the host controller use this bit.

Table 28-16 USBCMD — USB Command Register (Continued)

M821xx Data Sheet


3 – 2 FS[2:0] Frame List Size — (Read/Write or Read Only). Default 000b. This field Read/Write only if Programmable Frame List Flag in the HCCPARAMS register is set to one. This field specifies the size of the frame list that controls which bits in the Frame Index Registers should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2.

Value Meaning• 000 1024 elements (4096 bytes) Default value• 001 512 elements (2048 bytes)•-010 256 elements (1024 bytes)• 011 128 elements (512 bytes)• 100 64 elements• 101 32 elements• 110 16 elements• 111 8 elements

Only the host controller use this field.

1 RST Controller Reset (RESET) — Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the rest process is complete. Software cannot terminate the reset process early by writing a zero to this register.Host Controller:When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Any transaction currently in progress on USB is immediately terminated. A USP reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset a actively running host controller will result in undefined behavior. Device Controller:When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, state machines etc to their initial value. Writing a one to this bit when the device is the attached state is not recommended, since the effect on an attached state is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop but should be set to “0”.

0 RS Run/Stop (RS) – Read/Write. Default 0b 1=Run. 0=Stop.Host Controller:When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless th host controller is in the halted state (i.e. HCHalted in the USBSTS register is a one).

Device Controller:Writing a one to this bit will cause the device controller to enable a pull-up on D+ and intiate an attach event. This control bit is not directly connected to the pull-up enable, as the pullup will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized. Writing a 0 to this will cause a detach event.

Table 28-16 USBCMD — USB Command Register (Continued)

M821xx Data Sheet


28.6.2 USBSTSOffset: 0x144 [Read Only; Read/Write, Read/Write-Clear]

This register indicates various sate of the Host/Device Controller and any pending interrupts. this register does not indicate status resulting from a transaction on the serial bus. Software clears certain bits in this register by writing a “1” to them.

Table 28-17 USBSTS — USB Status


25 Tl1 General Purpose Timer Interrupt 1 (GPTINT1) — R/WC. This bit is set when the counter in the GPTIMER2CTRL (Non-EHCI) register transitions to zero. Writing a one to this bit will clear it.

24 TIO General Purpose Timer Interrupt (GPTINT0) — R/WC. This bit is set when the counter in the GPTIMER0CTRL (Non-EHCI) register transitions to zero. Writing a one to this bit will clear it.

23 – 20 Reserved. Cleared to “0”.

19 UPI USB Host Periodic Interrupt (USBHSTPERINT) —R/WC. This bit is set by the Host Controller when the cause of the interrupt is the completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule.This bit is also set by the Host Controller when a short packet is detected AND the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes.This bit is not used by the device controller and will always be zero.

18 UAI USB Host Asynchronous Interrupt (USBHSTASYNCINT) — R/WC. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule.This bit is also set by the Host when a short packet is detected AND the packet is on the asynchronous schedule. A short packet is when th actual number of bytes received was less than the expected number of bytes. This bit is not used by the device controller and will always be zero.

17 RSVD Reserved. Set to “0”.

16 NAKI NAK Interrupt Bit — Read Only. This bit is read only. It is set by hardware when for a particular end point both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware when the enabled Tx/RX Endpoint NAK bits are cleared.

15 AS Asynchronous Schedule Status — Read Only. 0 = Default. This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status in enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transition the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). Only used by the host controller.

M821xx Data Sheet


14 PS Periodic Schedule Status — Read Only. 0 = Default. This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).Only used by the host controller.

13 RCL Reclamation — Read Only. 0=Default. This is a read-only status bit used to detect an empty asynchronous schedule. Only used by the host controller.

12 HCH HCHalted — Read Only. 1 = Default. This bit is a zero whenever the Run/Stop bit is a one. The Host Controller sets this bit to one after is has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. internal error).Only used by the host controller.


9 RSVD Reserved. These bits are reserved and should be set to zero.

8 SL1 DCSuspend — R/WC. 0 = Default. When a device controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. Only used by the device controller.

7 SR1 SOF Received — R/WC. 0=Default. When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will by synchronized to the actual SOF that is received.Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1 ms during the prelude to connect and chip. In host mode, this bit will be set every 125us and can be used by the host controller driver as a time base. Software writes a 1 to this bit to clear it.NOTE: This is a non-EHCI status bit.

6 URI USB Reset Received — R/WC. 0 = Default. When the device controller detects a USB Reset and enters the default status, this bit will be set to a one. Software can write a:”1” to this bit to clear the USB Reset Received status bit.Only used by the device controller.

5 AAI Interrupt on Async Advance — R/WC. 0=Default. system software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source. Only used by the host controller

4 SEI System Error — R/WC. This bit is not used in this implementation and will always be set to “0”.

Table 28-17 USBSTS — USB Status (Continued)

M821xx Data Sheet


3 FRI Frame List Rollover — R/WC. The host controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USCMD register) is 1024, the Frame List Index register rolls over every time FRINEX[13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FHINDEX 12] toggles.Only used by the host controller.

2 PCI Port Change Detect — R/WC. The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition of the suspended port.The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and DCSuspend bit respectively.Note: This bit is not EHCI compatible.

1 UEI USB Error Interrupt (USBERRINT) — R/WC. When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. See the EHCI specification for a complete list of host interrupt conditions.See section Device Error Matrix in USB-HS DEV reference manual. The device controller detects resume signaling only.

0 UI USB Interrupt (USBINT) — R/WC. This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes.

Table 28-17 USBSTS — USB Status (Continued)

M821xx Data Sheet


28.6.3 USBINTROffset: 0x148 [Read/Write; Default: 0x0000 0000]

The interrupts to software are enabled with this register. An interrupt is generated when a bit is set and the corresponding interrupt is active. The USB Status register (USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, thus allowing polling of interrupt event by the software.

Table 28-18 USBINT — USB Interrupt Enable


25 TlE1 General Purpose Timer Interrupt Enable 1. When this bit is set to one, and the GPTINT1 bit in the UBSTS register is a one, the controller will issue an interrupt. The interrupt is acknowledged by software clearing the GPTINT1 bit.

24 TIEO General Purpose Timer Interrupt Enable 0. When this bit is set to one, and the GPTINT1 bit in the UBSTS register is a one, the controller will issue an interrupt. The interrupt is acknowledged by software clearing the GPTINT0 bit.

23 – 20 RSVD Reserved. Cleared to “0”.

19 UPIE USB Host Periodic Host Periodic Interrupt Enable. When this bit is a one, and the USBHSTPERIONT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit.

18 UAIE USB Host Asynchronous Interupt Enable. When this bit is a one, and the USBHSTASYNCINT bit in the USB register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASSYNCINT bit.

17 RSVD Reserved. Should be set to zero.

16 NAKE NAK Interrupt Enable. This bit is set by software if it wants to enable the hardware interrupt for the NAK interrupt bit. If both this bit and the corresponding NAK bit are set, a hardware interrupt is generated.

15 – 10 RSVD Reserved. Set to “0”.


8 SLE Sleep Enable. When this bit is one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit. Only used by the device controller.

7 SRE SOF Received Enable. When the bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit.

6 URE USB Reset Enable — When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit. Only used by the device controller.

M821xx Data Sheet


5 AAE Interrupt on Async Advance Enable. When this bit is a one, and the Asyc Advance bit in the USBSTS register is one, the host will issue an interupt at the next interrupt threshold. The interrupt is acknowleged by software clearing the Interrupt on Asycn Advance bit. Only used by the host controller.

4 SEE System Error Enable. When this bit is a one, and the System Error bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the System Error bit.

3 FRE Frame List Rollover Enable. When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrrupt bits acknowledged by software clearing the Frame List Rollover bit.Only used by the host controller.

2 PCE Port Change Detect Enable. When this bit is a one, and the Port Change Detect bit the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit.Only used by the host controller.

1 UEE USB Error Interrupt Enable. When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register.

0 UE USB Interrupt Enable. When this bit is set to one, and the USBERINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing the USBINT bit.

Table 28-18 USBINT — USB Interrupt Enable (Continued)

M821xx Data Sheet


28.6.4 FRINDEXOffset: 0x14C [Read/Write in host mode; Default: undefined (free running counter)]

This register is used by the host controller to index the periodic frame list. The register updates once every 125ms (once every micro-frame). Bits [N:3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index on the size of the frame list as set by the system software in the Frame List Size field in the USBCMD register.

This register must be written as a DWORD. Byte writes produce undefined results. This register cannot be written unless the Host Controller is in the ‘Halted’ state as indicated by the HCHalted bit. A write to this register while the Run/Stop bit is set to a one produces undefined results. Writes to this register also affect the SOF value.

Table 28-19 FRINDEX— USB Frame Index


13 – 0 FRINDEX The value, in this register, increments at the end of each time frame (e.g. micro-frame). Bits [N:3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size filed in the USBCMD register, when used in host mode.

USBCMD Frame List Size Elements N• 000 (1024) 12• 001 (512) 11•-010 (256) 10• 011 (128) 09• 100 (64) 08• 101 (32) 07• 110 (16) 06• 111 (8) 05

Bits 2:0 indicate the current microframe.

M821xx Data Sheet


28.6.5 PERIODICLISTBASE; DEVICEADDROffset: 0x154h [Read/Write (Writes must be DWord writes); Default: 0x0000 0000]

This register is shared between the host controller and the device controller operation.

28.6.5.1 Host Controller (PERIODICLISTBASE)

This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. HCD loads this register prior to starting the schedule execution by the Host Controller. The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. the contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence.

28.6.5.2 Device Controller (USB DEVICEADDR)

The upper seven bits of this register represents the device address. After any controller reset or a USB reset, the device address is set to the default address (0). The default address will match all incoming addresses. Software shall reprogram the address after recieving a SET_ADDRESS descriptor.

The USBADDR is used to accelerate the SET_ADDRESS sequence by allowing the DCD to preset the USBADR register before the status phase of SET_ADDRESS descriptor.

PERIODICLISTBASE— Host Controller Frame List Base Address

Bit No. Field Name Description31 – 12 BASEADDR These bits correspond to memory address signals [31:12], respectively.

Only used by the host controller.

11 – 0 RSVD Reserved. Must be written as “0”s. During runtime, undefined.

Table 28-20 DEVICEADDR – Device Controller USB Device Address

Bit No. Field Name Description31 – 25 USBADR These bits correspond to the USB device address.

24 USBADRA Device Address Advance. Default = 0. When this bit is ‘0’ any writes to USBADR are instantaneous. When this bit is written to a ‘1’ at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed. USBADR will be loaded from the holding register. Hardware will automatically clear this bit on th following conditions:1) IN is ACKed to endpoint 0. (USBADR is updated from staging register.)2) OUT/SETUP occur to endpoint 0. (USBADR is not updated).3) Device Reset occurs (USBADR is reset to 0). Note: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write on the device address within 2ms from the SET_ADDRESS status please. If the DCD writes the USBADDR with USBADRA=1 after the SET_ADDRESSES data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement.

23 – 0 reserved Reserved. Must be written as zeros. During runtime, the values of these bits are undefined.

M821xx Data Sheet


28.6.6 ASYNCLISTADDR, ENDPOINTLISTADDROffset: 0x158 [Read/Writes (Writes must be DWord Writes]; Default: 0x0000 0000]

This register is shared between the host controller and the device controller operation.

28.6.6.1 Host Controller (ASYNCLISTADDR)

This 32-bit register contains the address of the next asynchronous queue head to be executed by the host. Bits [4:0] of this register cannot be modified by the system software and will always return a zero when read.

28.6.6.2 Device Controller (ENDPOINTLISTADDR)

In device mode, this register contains the address of the top of the endpoint list in system memory. Bits [10:0] of this register cannot be modified by the system software and will always return a zero when read. The memory structure referenced by this physical memory pointer is assumed 64-byte.

I

Table 28-21 ASYNCLISTADDR — Host Controller Next Asyn Address

Bit No. Field Name Description31 – 5 ASYBASE[31:5] Link Pointer Low (LPL). These bits correspond to memory address signals [31:5],

respectively. This field may only reference a Queue Head (OH). Only used by the host controller.

4– 0 RSVD Reserved. These bits are reserved and their values have no effect on operation.

Table 28-22 ENDPOINTLISTADDR— Device Controller Endpoint List Address

Bit No. Field Name Description31 – 11 EPBASE[31:11] Endpoint List Pointer (Low).These bits correspond to memory address signals [31:11],

respectively. This field will reference a list of up to 32 Queue Heads (QH). i.e.. one queue head per endpoint and direction.)

10 – 0 RSVD Reserved.These bits are reserved and their values have no effect on operation.

M821xx Data Sheet


28.6.7 TTCTRLOffset: 0x15C [Read/Writes (Writes must be DWord Writes)]; Default: 0x0000 0000]

This register contans parameters needed for internal TT operations. This Register is not used in the device controller operation.

I

28.6.8 BURSTSIZEOffset: 0x160 [Read/Writes (Writes must be DWord Writes); Default: Implementation Specific]This register is used to control and dynamically change the burst size used during data movement on the initiator (master) interface.I

Table 28-23 TTCTRL— Host Controller Embedded TT Async Buffer Status

Bit No. Field Name Description31 RSVD Reserved

30 – 24 TTHA

23 – 0 RSVD Reserved

Table 28-24 BURSTSIZE— Bust Size Setting

Bit No. Field Name Description31 RSVD Reserved. These bits are reserved and their value has no effect on operation.

30 TXPBUST Programmble TX Burst Length. (Read/Write). Default is the constant VUSB_HS_TX_BURST. This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus.

0 RXPBUST Programmable RX Burst Length. (Read/Write) Default is the constant VUSB_HS_RX_BUST. This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory.

M821xx Data Sheet


28.6.9 TXFILLTUNUNGOffset: 0x164 [Read/Writes (Writes must be DWord Writes]; Default: 0x0002 0000]

The fields in this register control performance tuning associated with how the host controller posts data into the TX latency FIFO before moving data onto the USB bus. The specific areas of perfomance include the how much data to post into the FIFO and an estimate for how long that operation should take in the target system.

Definitions:

T0 = Standard packet overhead

T1 = Time to send data payload

Tff = Time to fetch packet into TX FIFO up to specified level

Ts = Total Packet Flight Time (send-only) packet

Ts = T0 +T1

Tp = Total Packet Time (fetch and send) packet

Tp= Tff + T0 + T1

Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure Tp remains before the end of the [micro] frame. If so it proceeds to pre-fill the TX FIFO. If at anytime during the pre-fill operation the time remaining the [micro] frame is < Ts then the packet attempt

ceases and the packet is tried at a later time. Although this is not an error condition and the host controller will eventually recover, a mark will be made the scheduler health counter to note the occurance of a “back-off” event. When a back-off event is detected, the partial packet fetched may need to be discarded from the latency buffer to make room for periodic traffic that will begin after the next SOF. Too many back-off events can waste bandwidth and power on the system bus and thus should be minimized (not necessarily eliminated). Back-offs can be minimized with use of the TSCHHEALTH (TFF) described

below.

The register fields are described in the following table.

Table 28-25 TXFILLTUNNING — Transmit Buffer Fill Adjustment

Bit No. Field Name Description31 – 22 RSVD Reserved. These bits are reserved and their values have no effect on operation.

21– 16 TXFIFOTHRES FIFO Burst Threshold. (Read/Write) [Default = 2]. This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins onto the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or sufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replensihed from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set.

15 – 13 RSVD Reserved. These bits are reserved and their values have no effect on operation.

M821xx Data Sheet


28.6.10 ENDPTNAKOffset: 0x178 [Read/Writes Clear; Default: 0x0000 0000].I

12 – 8 TXSCHEALTH Scheduler Health Counter. (Read/Write To Clear) [Default = 0] This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHERS before running out of time to send the packet before the next Start-of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max at 31.

7 – 0 TXSCHOH Scheduler Overhead. (Read/Write) [Default=0] This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as if can needlessly reduce USB utilization.The time unit represented in this register 1.267us when a device is connected in High-Speed Mode for SPH.The time unit represented in this register is 6.333 us when a device is connected in Low/Full Speed Mode for SPH.

Table 28-26 ENDPTNAK — Endpoint NAK

Bit No. Field Name Description31 – 16 EPTN[15:0] TX Endpoint NAK – R/WC. Each TX endpoint has 1 bit in this field. The bit is set when

the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 15 – Endpoint #15Bit 1 – Endpoint #1Bit 0 – Endpoint #0

15 – 0 EPRN[15:0] RX Endpoint NAK – R/WC. Each RX endpoint has 1 bit in this field. the bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint.Bit 15 – Endpoint #15Bit 1 – Endpoint #1Bit 0 – Endpoint #0

Table 28-25 TXFILLTUNNING — Transmit Buffer Fill Adjustment (Continued)

M821xx Data Sheet


28.6.11 ENDPTNAKENOffset: 0x17C [Read/Write Clear; Default: 0x0000 0000].I

28.6.12 PORTSCxOffset: 0x184 + (4*(Port Number – 1)) where Port Number = 1, 2, 3 ....8Access: Read Only, Read/Write, Read/Write Conditional (field dependent)

Default Value: (host mode) 11110000000000000000XX0000000000bI = Implementation dependentX = Unknown

Size: 32 bits

28.6.12.1 Host Controller

A host controller must implement one to eight port registers. The number of port registers implemented by a particular instantiation of a host controller is documented in the HCSPARAMs register. Software uses this information as an input parameter to determine how many ports need service. This register is only reset when power is initially applied or in a response to a controller reset. The initial conditions of a port are:

• No device connected

• Port disabled

If the port has port power control, this state remains until software applies to the port by setting port power to one.

Table 28-27 ENDPTNAKEN— Endpoint NAK Acknowledge

Bit No. Field Name Description31 – 16 EPTNE[15:0] TX Endpoint NAK – R/W. Each bit is an enable bit for the corresponding TX Endpoint

NAK bit. IF this bit is set and the corresponding TX Endpoint NAK bit is set, the NAK interrupt bit is set. Bit 15 – Endpoint #15Bit 1 – Endpoint #1Bit 0 – Endpoint #0

15 – 0 EPRNE[15:0] RX Endpoint NAK – R/W. Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set.Bit 15 – Endpoint #15Bit 1 – Endpoint #1Bit 0 – Endpoint #0

M821xx Data Sheet


28.6.12.2 Device ControllerA device controller must implement only port register one and it does not support power control. Port control in device mode is only used for status port reset, suspend, and current connect status. It is also used to initiate test mode or force signaling and allows software to put the PHY into low power suspend mode and disable the PHY clock. Table 28-28 PORTSCx — Port Status Control[1:8]

Bit No. Field Name Description31 – 30 PTS Read as “00”. Must write as “00”.

29 STS Read as “0”. Must write as “0”.

28 PTW Read as “0”. Must write as “0”

27 – 26 PSPD Port Speed – Read Only. This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine with Embedded Transaction Translator.00 – Full speed 01 – Low speed10 – High speedThis bit is not defined in the EHCI specification.

25 RSVD Reserved.

24 PFSD Port Force Full Speed Connect – Read/Write. Default = 0b. Writing this bit to a 1b will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configuration with a HS host, hub or device.This bit is not defined in the EHCI specification.This bit is for debugging purposes.

23 PHCD PHY Low Power Suspend — Clock Disable (PLPSCD) – Read/Write. Default = 0b. Writing this bit to a 1b will disable the PHY clock. Writing a 0b enables it. Reading this bit will indicate the status of the PHY clock. NOTE: The PHY clock cannot be disabled if it is being used as the system clock.In the device mode, the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of the software.See 10 System Level issues and Core Configuration for more discussion on clock disable and power down issues.This bit is not defined in the EHCI specification/

22 WKOC Wake on Over-current Enable (WKOC_E) – Read/Write.Default = 0b. Writing this bit to a one enables the port to be sensitive to current over-current conditions as wake-up event. This field is zero if Port Power (PP) is zero.This bit is output from the controller as signal pwrctl_wake_overcurrent_en (host only) for use by an external power control circuit.

21 WKDS Wake on Disconnect Enable (WKDSCNNT_E) — Read/Write. Default = 0b. Writing this bit to one enables the port to be sensitive to direct disconnects as wake up events..

M821xx Data Sheet


20 WKCN Wake on Connect Enable (WKCNNT_E) — Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events.This field is zero if Port Power (PP) is zero or in device mode.

19 – 16 PTC[3:0] Port Test Control — Read/Write. Default = 0000b. Any other value than zero indicates that the port is operating is test mode.

Value Specific Test• 0000b TEST_MODE_DISABLE• 0001b J_STATE•-0010b K_STATE• 0011b SE0 (host) / NAK (device)• 0100b Packet• 0101b FORCE_ENABLE_HS• 0110b FORCE_ENABLE_FS• 0111b FORCE_ENABLE_LS•0111b FORCE_ENABLE_LS•1000b to 1111b Reserved

Refer to Chapter 7 of the USB Specification Revision 2.0 for details on each test mode.The FORCE_ENABLE_FS and FORCE_ENABLE_LS are extensions of the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_(HS/FC/LS) values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Note: Low speed operations are not supported as peripheral device.

15 – 14 PIC Port Indicator Control — Read/Write. Default =Ob. Writing to this field has no effect if the P_INDICATOR bit is a one, the bit is:

Bit Value Specific Test• 00b TEST_MODE_DISABLE• 01b J_STATE•-10b K_STATE• 11b SE0 (host) / NAK (device)

Refer to the USB Specification Revision 2.0 [3] for a description on how these bits are to be used.This field is output from the controller as signals port_ind_ctl_1 & port_ind_ctl_0 for use by an external LED driving circuit.

13 PO Port Owner — Read Only. Port owner handoff is not implemented in this design, therefore this bit will always read back as 0. The EHCI definition is included here for reference:

Default = 0. This bit unconditionally goes to a 0 when the configured bit in the CONFIGFLAG register makes a 0 to 1 transition. This bit unconditionally goes to 1 whenever the Configured bit is zero system Software uses this field to release ownership of the port to a selected host controller (in the event the attached device is not a high speed device). Software writes a one to this bit when the attached device is not a high speed device. A one in this bit means that an internal companion controller owns and controls the port.

Table 28-28 PORTSCx — Port Status Control[1:8] (Continued)

M821xx Data Sheet


12 PP Port Power (PP) — Read/Write or Read/Only. The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCPARAMS register. The behavior is:

0b Read Only — A device controller does not have port power control switches.1b/0b — Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on), When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc.

When an over-current condition is detected on a powered port and APPC is a one, the PP bit in each affected port may be transistioned by the host controller driver from a one to a zero (removing power from the port).This feature is implemented in the host controller (PPC=1).In a device only implementation port power control is not necessary, thus PPC and PP=0).This feature is implemented in the host controller (PPC =1).In a device only implementation port power control is not necessary, thus PPC and PP=0.

11 – 10 LS Link Status — Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. the encoding of the bits are:

Bits[11:10] Meaning• 00b SE0• 10b J_STATE•-01b K_STATE• 11b Undefined

In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because the port controller state machine and the port routing manage the connection of LS and FS. In device mode, the use of linestate by the device controller driver is not necessary.

9 HSP High-Speed Port— Read Only. Default = 0b. When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the host/device connected to the port is not a high-speed mode.Note: HSP is redundant with PSPD(27-26) but will remain in the design for compatibility.

8 PR Port Reset This field is zero if PortPowered(PP) is zero. In Host Mode: Read/Write 1 = Port is in Reset. 0=Port is not in Reset. Default 0.When software writes a one to this bit, the bus-sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit a zero after the reset duration is timed in the driver. In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register.


M821xx Data Sheet


7 SUSP Suspend.In Host Mode: Read/Write. 1 = Port is in suspend state. 0=Port not in suspend state. Default = 0.Port Enabled Bit and Suspend bit of this register define the port state as follows:Bits [Port Enabled, Suspend] Port State0x Disable10 Enable11 SuspendWhen in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume direction. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined.This field is zero if Port Power(PP) is zero in host mode. In Device Mode: Read Only. 1 = Port is suspend state. 0=Port not in suspend state. Default=0. In device mode this bit is read only status bit.

6 FPR Force Port Resume — Read/Write. 1 = Resume detected/driven on port. 0 = No resume (K-state) detected/driven on port. Default = 0.In Host Mode:Software sets this bit to one to drive resume signaling. The Host Controller set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume direction is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB specification Revision 2.0. The resume signaling (Full-speed ‘K’) is driven on this port as long as this bit remains a one. This port will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle.This field is zero if Port Power (PP) is zero in host mode. This bit is not-EHCI compatible.In Device Mode:After the device has been is Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in USBSTS register is also set to one.


M821xx Data Sheet


5 OCC Over-current Change — R/WC. Default=0. 1=This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing to a one to this bit position. For host implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition.For device-only implementations this bit shall always be 0.

4 OCA Over-current Active — Read Only. Default 0. 1=This port currently has an over-current condition. 0=This port does not have an over-current condition. This bit will automatically transition from one to zero when the over current condition is removed. For host implementations the user can provide over-current detection to the vbus+pwr-fault input for this condition.For device-only implementations this bit shall always be 0.

3 PEC Port Enable/Disable Change — R/WC. 1= Port enabled/disabled status has changed. 0=No change. Default = 0.In Host Mode:For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to appropriate conditions existing at the EOF2 point (see Chapter 11 of the USB specification). Software clears this by writing a one to it.This field is zero if Port Power(PP) is zero.In Device mode: The device port is always enabled (This bit will be zero).


M821xx Data Sheet


2 PE Port Enabled/Disabled — Read/Write. 1 = Enable. 0 = Disable. Default 0.In Host Mode:Ports can be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port status actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. (0b) downstream propagation of data is blocked except for reset. This field is zero if Port Powered (PP) is zero in host mode.In Device Mode:The device port is always enabled. (This bit will be one).

1 CSC Connect Status Change — R/WC. 1 = Change in current connect status. 0=No change.Default 0.In Host Mode:Indicates a change has occurred in the port’s Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if the system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be ‘setting’ an already-set bit (i.e., the bit will remain set). Software clears the bit by writing a one to it.This field is zero if Port Power(PP) is zero in host mode.In Device Mode:This bit is undefined in device controller mode.

0 CCS Current Connect Status — Read Only.In Host Mode:1= Device is present on port. 0=No device present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.This field is zero if Port Power(PP) is zero in host mode.In Device Mode:1 = Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not match successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended.


M821xx Data Sheet


28.6.13 USBMODEOffset: 0x1A8 [Read Only; Default: 0x0000 0003].Table 28-29 USBMODE— USB Device Mode


5 VBPS Vbus Power Select (0 – Output is 0; 1 – Output is one)This bit is connected to the vbus_pwr_select output and can be used for any generic control but is named to be used by logic that selects between an on-chip Vbus power source (charge pump) and an off-chip source in systems when both are available.

4 SDIS Stream Disable Mode. (0 – Inactive [default]; 1 – Active)Device Mode: Setting to a ‘1’ disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems.Note: In high speed mode, all packets received will be responded to with a NYET handshake when stream drain disable is active.Host Mode: Setting a ‘1’ ensures the overruns/underuns of the latency FIFO are eliminated for low bandwidth system where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packed in launched on the USB bus.Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. Note: The use of this feature substantially limits of the overall USB performance that can be achieved.

3 SLOM Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model.0 – Setup lockouts on (defaults); 1 – Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMD0.

2 ES Endian Select – Read/Write. This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer with in the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.

Bit Meaning• 0 Little Endian [Default] – first byte refernced in least significant

byte of 32-bit word.•-1 Big Endian – first byte referenced in most significant byte of

32-bit word.

M821xx Data Sheet


The default contents given above reflect host mode configuration.

28.6.14 ENDPTSETUPSTATOffset: 0x1AC [R/WC; Default: 0x0000 0000]

1 – 0 CM[1:0] Controller Mode – R/WO. Controller mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host and device capability, the controller will default to an idle state and will need to be initialized to the desired operating mode after reset. For combination host/device controllers. this register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.

Bit Meaning• 00 Idle [Default for combination host/device]•01 Reserved•10 Device Controller [Default for device only controller]•11 Host Controller [Default for host only controller]

Table 28-30 ENDPOINTSETUPSTAT— Endpoint Setup Status


15 – 0 ENDPTSETUPSTAT[15:0] Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup from the Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus timeout while the setup lock in our mechanism is engaged. See Managing Endpoint in the Device Operational ModelThis register is only used in device mode.

Table 28-29 USBMODE— USB Device Mode (Continued)

M821xx Data Sheet


28.6.15 ENDPTPRIMEOffset: 0x1B0 [R/WS; Default: 0x0000 0000]

This register is only used in device mode.I

Table 28-31 ENDPTPRIME— Endpoint Initialization

Bit No. Field Name Description31 – 16 PETB[15:0] Prime Endpoint Transmit Buffer — R/WS. For each endpoint a corresponding bit is

used to request that a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer description to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when associated endpoint(s) is (are) successfully primed. Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired and the dQH is updated. PETB[15] [Endpoint #15]PETB[1] [Endpoint #1]PETB[0] [Endpoint #0]

15 – 0 PERB[15:0] Prime Endpoint Receive Buffer – R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transcriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear the bit when the associated endpoint(s) is (are) successfully primed. Note: These bits will be momentarily set by hardware during hardware re-priming operation s when a dTD is retired, and when the dQH is updated. Bit 15 [Endpoint #15]Bit 1 [Endpoint #1]Bit 0 [Endpoint #0]

M821xx Data Sheet


28.6.16 ENDPTFLUSHOffset: 0x1B4 [R/WS; Default: 0x0000 0000]

This register is used only in device mode.

28.6.17 ENDPTSTATOffset: 0x1B8 [R/WC; Default: 0x0000 0000]This register is used in device mode only.I

Table 28-32 ENDPTFLUSH— Endpoint De-Initialize

Bit No. Field Name Description31 – 16 FETB[15:0] Flush Endpoint Transmit Buffer — R/WS. Writing a one to a bit(s) in this register

will cause the associated endpoints(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful.FETB[15] [Endpoint #15]FETB[1] [Endpoint #1]FETB[0] [Endpoint #0]

15 – 0 FERB[15:0] Flush Endpoint Receive Buffer – R/WS. Writing a one to a bit(s) will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful.Bit 15 [Endpoint #15]Bit 1 [Endpoint #1]Bit 0 [Endpoint #0]

Table 28-33 ENDPTSTAT— Endpoint Status

Bit No. Field Name Description31 – 16 ETBR[15:0] Endpoint Transmit Buffer Ready – Read Only. One pont for each endpont indicates

status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to recieving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME reigster and endpont indicating ready. this delay time varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register.Note: These bits will be mometarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ETBR[15] [Endpoint #15]ETBR[1] [Endpoint #1]ETBR[0] [Endpoint #0]

M821xx Data Sheet


28.6.18 ENDPTCOMPLETEOffset: 0x1BC [R/WC; Default: 0x0000 0000]This register is used in device mode only.I

15 – 0 ERBR[15:0] Endpoint Receive Buffer Ready – Read Only.. One bit for each endpont indicates the status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to a receiving a command from the corresponding bit in the ENDPTPRIME register. There will always be a delay between settling a bit in the ENDPTPRIME register and endpoint incicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIMTE register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. NOTE: These bits will be mometarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated.Bit 15 [Endpoint #15]Bit 1 [Endpoint #1]Bit 0 [Endpoint #0]

Table 28-34 ENDPTCOMPLETE— Endpoint Complete

Bit No. Field Name Description31 – 16 ETCE[15:0] Endpoint Transmit Complete Event – R/WC. Each bit indicates a transmit event (IN/

INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one will clear the corresponding bit in this register.ETCE[15] [Endpoint #15]ETCE[1] [Endpoint #1]ETCE[0] [Endpoint #0]

15 – 0 ERCE[15:0] Endpoint Receive Complete Event – R/WC. Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT.. Writing a one will clear the corresponding bit in this register.

Bit 15 [Endpoint #15]Bit 1 [Endpoint #1]Bit 0 [Endpoint #0]

Table 28-33 ENDPTSTAT— Endpoint Status (Continued)

M821xx Data Sheet


28.6.19 ENDPTCTRL0Offset: 0x1C0 [R/O, Read/Write, R/W/C (field dependent) Default: 0x0800 0008]

Every device will implement Endpoint0 as a control endpoint.]Table 28-35 ENDPTCTRL0— Endpoint Control 0

Bit No. Field Name Description31 – 24 RSVD. Reserved. These bits are reserved and should be set to zero.

23 TXE TX Endpoint Enable.1 – Enabled.

Endpoint0 is always enabled.

22– 20 RSVD Reserved. These bits are reserved and should be set to zero.

19 – 18 TXT[1:0] TX Endpoint Type – Read/Write00 – Control.

Endpoint0 is fixed as a Control End Point.

17 R Reserved. Bit reserved and should be set to zero.

16 TXS TX Endpoint Stall – Read/Write0 – Endpoint OK [default]

1 – End Point StalledSoftware can write one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will be automatically cleared up receipt of a new SETUP request.After receiving a SETUP request, this bit wil continue to be cleared by hardware until the associated ENDPTSETUPSTAT is cleared.NOTE: There is a slight delay (50 clocks max) between the ENDPTSETUPSTAT being cleared and the hardware continuing to clear this bit. In most systems it is unlikely the DCD software will observe this delay. However, should the DCD observe that this stall is not set after writing a one to it then follow this procedure: continually write this stall bit untill it is set or until a new setup has been received by checking the associated ENDPTSETUPSTAT bit.


7 RXE RX Endpoint Enable.1 – Enabled

Endpoint0 is always enabled.


3 – 2 RXT Rx Endpoint Type – Read/Write.00 – Control

Endpoint0 is fixed as a Control Endpoint.

1 R Reserved.

M821xx Data Sheet


0 RXS RX Endpoint Stall – Read/Write0 – End Point OK. [Default]1 – End Point Stalled

Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL untill this bit is either cleared by software or automatically cleared as above for controlled endpoints.After receiving a setup request, this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. NOTE: There is a slight delay (50 clocks max.) between the ENDPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated ENDPTSETUPSTAT bit.

Table 28-35 ENDPTCTRL0— Endpoint Control 0

M821xx Data Sheet


28.6.20 ENDPTCTRL1 – ENDPTCTRL15Offset: 0x1C0 +(4*(EndPoint Number)) [R/W; Default: 0x0000 0000]

CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control type to any other type (IE bulk-type). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint direction.

Table 28-36 ENDPTCTRL1 – ENDPTCTRL15 — Endpoint Control 1 – Endpoint Control 15

Bit No. Field Name Description31 – 24 RSVD Reserved. These bits are reserved and should be set to zero.

23 TXE TX Endpoint Enable.0 – Disabled [Default]1 – Enabled.

An endpoint should be enabled only after it is configured.

22 TXR TX Data Toggle Reset (WS)Write 1– Reset PID Sequence

Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID’s between host and device.

21 TXI TX Data Toggle Inhibit0 – Disabled [Default]1 – Enabled.

This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet.

20 R Bit reserved and should be set to zero.

19:18 TXT[1:0] TX Endpoint Type — Read/Write00 – Control01 – Isochronous10 – Bulk11 – Interrupt

17 TXD TX Endpoint Data Source — Read/Write0 – Dual Port Memory Buffer/DMA Engine [DEFAULT]

Should always be written as 0.

M821xx Data Sheet


16 TXS TX Endpoint Stall — Read/Write00 – End Point OK01 – End Point Stalled

This bit will be cleared automatically up the receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared.Software can write a one to this bit to force the endpoint to return a STALL handshake to the HOST. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. Note: [Control endpoint types only]: There is a slight delay (50 clocks max.) between the ENDSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure and continually write this stall bit until it is set or until a new setup has been received by checking the associated ENDPTSETSTSAT bit.


7 RXE RX Endpoint Enable.0 – Disabled [Default]1 – Enabled

An Endpoint should be enabled only after it has been configured.

6 RXR RX Endpoint Enable.0 – Disabled [Default]1 – Enabled

An Endpoint should be enabled only after it has been configured.

5 RXI RX Data Inhibit 0 – Disabled [Default]1 – Enabled

This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packet regardless of their data PID.


3 – 2 RXT[1:0] Rx Endpoint Type – Read/Write00 – Control01 – Isochronous10 – Bulk11 – Reserved

1 RXD RX Endpoint Stack Data Sink – Read/Write – TBD0 – Dual Port Memory Buffer/DMA Engine[Default]

Should always be written as zero.

Table 28-36 ENDPTCTRL1 – ENDPTCTRL15 — Endpoint Control 1 – Endpoint Control 15 (Continued)

M821xx Data Sheet


0 RXS RX Endpoint Stall – Read/Write0 – End Point OK. [Default]1 – End Point Stalled

This bit is cleared automatically upon receipt of a setup request. If this endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENPPTSETUPSTAT bit is cleared.Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for controlled endpoints.NOTE: [Control Endpoint Types only]: There is a slight delay (50 clocks max.) between the ENDPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to in then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated ENDPTSETUPSTAT bit.

Table 28-36 ENDPTCTRL1 – ENDPTCTRL15 — Endpoint Control 1 – Endpoint Control 15 (Continued)

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29.0 General Purpose I/O

Up to 32 GPIO interface signals are available for use by Mindspeed firmware and Customer Application Software for specific control and signaling purposes. For a view of the GPIO block within the top-level block diagram, see Figure 2-1.

Only GPIO [7:0] can be configured to generate interrupts on rise, fall or dual edge of inputs.

NOTE: Mindspeed firmware utilities and example software drivers use GPIOs.

To make optimal use of the GPIOs, review planned use of Mindspeed utilities and drivers with your Mindspeed representative.

Table 29-1 General Purpose Registers

Signal Name Signal Description / Multiplexing

GPIO_0 General Purpose I/O 0. Not shared or multiplexed with other signals.






GPIO_6 General Purpose I/O 6. Shared with EXP_NAND_RDY/BSY#. Not a real mux. Specific functionality determined by s/w driver.

GPIO_7 General Purpose I/O 7. Shared with EXP_IRQ. Not a real mux. Specific functionality determined by s/w driver.

GPIO_8 General Purpose I/O 8. Mux’d with EXP_A15.

GPIO_9 General Purpose I/O 9.Mux’d with EXP_A16.


GPIO_11 General Purpose I/O 11.Mux’d with EXP_A18.




GPIO_15 General Purpose I/O 15. Mux’d with TIM_EVNT0.

GPIO_16 General Purpose I/O 16. Mux’d with TIM_EVNT1.

GPIO_17 General Purpose I/O 17. Shared with TM_EXT_RESET. Not a real mux. Specific functionality determined by s/w driver.

!

M821xx Data Sheet


29.1 GPIO Interface SignalsThe M821xx devices support up to 32 General Purpose I/O (GPIO) interface signals that are utilized by both the Mindspeed Media Stream software and/or the Customer Application software. The GPIO[7:0] input signals are general purpose and can be programmed to generate interrupts. Some GPIO signals share the pin with signals from other functions depending upon the configuration of the device.

On M821xx devices, all are bi-directional and provide slew control on outputs and hysteresis (i.e. Schmitt triggering) on inputs. The lowest 8, GPIO(7:0) all trigger interrupts, are held high internally, and can handle 16mA. The rest, GPIO(31:8) are pulled down internally. do not trigger interrupts, offer slew control and hysteresis, and 8mA of drive.

29.2 General Purpose Boot Option InputsThe TM_GPBT_OP(3:0) pins are general-purpose, and have no pre-defined function.

These configuration pins are muxed with Expansion Bus address lines:

• TM_GPBT_OP0 — EXP_A_L_11 — Internally pulled down



• TM_GPBT_OP3 — EXP_A_L_5 — Internally pulled high

During reset, the block does not drive these pins, and they can be set to any configured value via pull-ups or pull-downs. Note that, as listed above, these I/O pads have internal pull-up/-down resistors.

So an external pull is required only if the default value made by the internal pull is not the desired one.

GPIO_18 General Purpose I/O 18. Mux’d with I2C_SCL.

GPIO_19 General Purpose I/O 19. Mux’d with I2C_SDA.

GPIO_20 General Purpose I/O 20.Mux’d with UART0_RX.

GPIO_21 General Purpose I/O 21. Mux’d with UART0_TX.

GPIO_22 General Purpose I/O 22. Mux’d with UART1_RX.

GPIO_23 General Purpose I/O 23. Mux’d with UART1_TX.

GPIO_24 General Purpose I/O 24. Mux’d with SPI_SCLK.

GPIO_25 General Purpose I/O 25. Mux’d with SPI_TXD.

GPIO_26 General Purpose I/O 26. Mux’d with SPI_RXD.

GPIO_27 General Purpose I/O 27. Mux’d with SPI_SS#0.

GPIO_28 General Purpose I/O 28. Mux’d with SPI_SS#1.

GPIO_29 General Purpose I/O 29. Shared with EXP_. NAND_CS. Not a real mux. Specific functionality determined by s/w driver.

GPIO_30 General Purpose I/O 30. Shared with EXP_NAND_ALE. Not a real mux. Specific functionality determined by s/w driver.

GPIO_31 General Purpose I/O 31. Shared with EXP_NAND_CLE. Not a real mux. Specific functionality determined by s/w driver.

Table 29-1 General Purpose Registers (Continued)

Signal Name Signal Description / Multiplexing

M821xx Data Sheet


Following reset, the block drives these pins to support Expansion Bus access. The previousl latched value is already stored in a software accessible register (see Section 30.1.8 IO Control Register) from which the value can be read but not changed.

29.3 GPIO Register Memory Map For a detailed description of registers, see Section 30.0 General Purpose I/O Registers on page 529.

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30.0 General Purpose I/O Registers

30.1 GPIO RegistersControl of the GPIO resources is provided through five registers. The base address for the GPIO control is mapped to 0x10070000. The GPIO control registers can be accessed by adding the associated “Offset” to the GPIO base address. Table 30-1 contains a description of the Control Registers and associated Offset values.

The Miscellaneous Registers listed support a variety of system functions.

NOTE: Writing any values to undescribed register locations or unspecified values to Reserved fields within described registers can produce unpredictable results.

Table 30-1 Description of Control Registers and Associated Offset Values

OFFSET R/W DESCRIPTION

GPIO Registers

0x00 R/W 32 bits, GPIO Output Register (power up default: all ‘0’)

0x04 R/W 32 bits, GPIO Output Enable Register (power up default: all ‘0’)

0x08 R/W 8 bits, GPIO[0:7] Rising Edge Interrupt Enable (default: “0000 0000”)

0x0C R/W 8 bits, GPIO[0:7] Falling Edge Interrupt Enable (default: “0000 0000”)

0x10 R 32 bits, GPIO Input Register

Miscellaneous Control Registers

0x14 R/W APB Bus Access Wait Register (default: 0x0000 003F)

0x28 R/W TDM Mux Control Register (default: 0x0000 0000)

0x34 R/W TDM_FS Control and Version ID Register (default: 0x0000 0010)

0x38 W Lock Register (default: 0x0000 0000)

0x44 R/W IO Control Register (default: 0x00C4 8000)

0x4C R/W General Control Register : (default: 0x0000 000A)

Miscellaneous Status Registers

0x1C R System Configuration Status Register

0x30 R ARM ID Register

0x40 R Bootstrap Pin Status Register

M821xx Data Sheet


30.1.1 GPIO Output Register and GPIO Output Enable Register[0x00 R/W] (default: 0x0000 0000) GPIO Output

[0x04 R/W] (default: 0x0000 0000) GPIO Output Enable

The GPIO output register is a 32 bit register located at offset 0x00, and its corresponding “Output Enable Register” is located at offset 0x04. Writing a ‘1’ to any bit in the Output Enable Register (i.e., GPIO Base Address + 0x04) will output enable the corresponding bit in the GPIO Output Register. Writing a ‘1’ to the enabled bit of the GPIO Output Register will generate a logic high level signal on the associated GPIO pin. Writing a ‘0’ to the bit will generate a low voltage signal to the associated GPIO pin.

30.1.2 GPIO Interrupt Enable Register (Rising Edge and Falling Edge)[0x08 R/W] (default: b’0000 0000)

[0x0C R/W] (default: b’0000 0000)

Eight (8) GPIO-based interrupts can be supported. The GPIO interface can be programmed to create interrupts based upon the rising edge, falling edge or both (rising and falling) edges of an input signal. Bit [0: 7] of the Rising or Fall Edge Interrupt Enable Register (or both) must be set to enable each GPIO interrupt. When an external input signal is generated to the associated GPIO pin, an interrupt will be generated.

30.1.3 GPIO Input Register[0x10 R] (default: 0x0000 0000)

The GPIO input register is a 32-bit register located at offset 0x10. When the voltage applied to a GPIO pin is detected as a CMOS logic high, the corresponding bit in the GPIO Input Register will be read as a 1. When the voltage applied to a GPIO pin is detected as a CMOS logic low, the corresponding bit in the GPIO Input Register will be read as a 0.

Table 30-2 defines the GPIO Input Register: Bit Number. Signal Name and associated Signal Description based upon the chosen configuration.

Table 30-2 GPIO Input Register: Bit Number, SIgnal Name, and Description

Bit Number

Signal Name Signal Description

00 GPIO0 General Purpose I/O 0.










M821xx Data Sheet
























Table 30-2 GPIO Input Register: Bit Number, SIgnal Name, and Description (Continued)

Bit Number

Signal Name Signal Description

M821xx Data Sheet


30.1.4 APB Bus Access Wait State Register [0x014 R/W] (default: 0x0000 003F)

This register specifies APB bus slave to which the added wait state will be applied.The number of wait cycles in the APB bus transaction depends on the state of the APB Bus Access Wait State Register. The register is physically located in the GPIO block ), but drives the AABCTRL input of the AHB—APB Bus Bridge block (see . Section 37.0 AHB – APB Bus Bridge).

The bit 6 enables the post write mode. The post write mode is designed to speed up consecutive write transactions by adding pipeline resisters in the AHB bus. The bits 3 and 2, and the bits 1 and 0, control the number of wait cycles in the APB bus for the selected device. The default value of the AAB Control register is set to “00111111” by the AHB bus reset signal.

30.1.5 TDM Mux Control Register [0x028 R/W] (default: 0x0000 0000)

External loopback refers to content arriving from outside the M821xx on TDM_DR looping back out on TDM_DX.

Internal loopback describes TDM_DX leaving the M821xx looping back on TDM_DR.

Table 30-3 APB Bus Access Wait State Register Field Definitions

Bit Function

31:8 Reserved (tied to ‘0’)

7 Not used

6 Post write

5:4 Not used

3:2 Controls the number of wait cycles in EMAC0, EMAC1 and PUI.

1:0 Controls the number of wait cycles in all other blocks.

NOTE: This register should be configured to 0x40 before the GEMAC (Ethernet) block is used.

Table 30-4 TDM Mux Control Register Field Definitons

Bit Function


7 External Loop Back Enable. When enabled, each external TDM_DR input is connected to external TDM_DX output of the same bus. Note that when it is enabled, the TDM_DX pins are always output enabled and they must not be tied to another output pin to avoid contention.‘1’ = Enable, ‘0’ = Disable

M821xx Data Sheet


30.1.6 TDM_FS Control and Version ID Register [0x34 R/W] (default: 0x0000 0010)

30.1.7 Lock Register [0x038 W] (default: 0x0000 0000)

6 Not used

5 Internal Loop Back Enable, when enabled each TDM DX is connected to TDM DR of the same bus.‘1’ = Enable, ‘0’ = Disable

4:0 Not used

Table 30-5 TDM_FS Control and Version ID Register Field Definitions

Bit Description


7:4 Version ID (“0001”)Note: The user can only write “0001” to these four bits.

3 Reserved

2 TDM_FS direction control‘0’ = input‘1’ = output

1: 0 Reserved — leave as ‘0’

Table 30-6 Lock Register Field Definitions

Bit Description

31 : 0 A write with 0x55555555 data to this register will enable the lock for IO Control Register write. Any write to the APB bus or different data value will reset the lock and IO Control Register will not be written successfully.Any software that want to change the IO Control Register has to write to this register with right value first before writing to IO Control Register. The software should check the value of IO Control Register after changing it to make sure that the two writes are consecutive.

Table 30-4 TDM Mux Control Register Field Definitons (Continued)

M821xx Data Sheet


30.1.8 IO Control Register[0x044 R/W] (default: 0x00C4 8000)

To write to this register, the Lock Register (0x038) needs to be unlocked. The control bits in this register will enable or disable each IO bus or bus mode.

NOTE: The GPBT signals (General Purpose Boot Strap) are marked TBD (To Be Determined). The use of these on-reset inputs is left to system designers to determine.The GPBT[3:0] Software or Hardware Control Selection fields support software over-ride of GPBT inputs.

Table 30-7 IO Control Register Field Definitions

Bit Description

31 GPBT[3] software control ‘0’ – TBD (default)‘1’ – TBD

30 GPBT[2] software control or hardware control selection‘0’ – use hardware control (default)‘1’ – use software control






24 HBBUSSIZE hardware or software control selection‘0’ – use hardware control (default)‘1’ – use software control

23:22 Software control bit of HBBUSSIZE[1:0]“11” – (default)

21 TDM_CK_OUT_EN hardware or software control selection.‘0’ – use hardware control (default)‘1’ – use software control

20 Software control bit of TDM_CK_OUT_EN‘0’ – TDM_CK pads are input (default)‘1’ – TDM_CK pads are output

M821xx Data Sheet


19 TM_MII1_MODE[1:0] hardware or software control selection‘0’ – use hardware control (default)‘1’ – use software control

18:17 Software control bit of TM_MII1_MODE[1:0]default = “10”

16 TM_MII0_MODE[1:0] hardware or software control selection‘0’ – use hardware control (default)‘1’ – use software control

15:14 Software control bit of TM_MII0_MODE[1:0]default = “10”

13 PCI bus host mode enable software or hardware control when PCI bus is enabledMicroprocessor Bus Burst Enable software or hardware control when host bus is enabled‘0’ – use hardware control (default)‘1’ – use software control

12 Software control of PCI Bus Host mode when PCI bus is enabled‘0’ – PCI bus not in host mode. (default)‘1’ – PCI bus in host mode.

Software control of Microprocessor Bus Burst Enable when host bus is enabled‘0’ – burst mode enabled . (default)‘1’ – burst mode disabled

11 PCI bus enable hardware or software control selection‘0’ – use hardware control (default)‘1’ – use software control

10 Software control of HBMODE‘0’ – host bus enable (default)‘1’ – PCI bus enabled

9 SPI bus enable control’0’ – GPIO[24:28] enable (default)‘1’ – SPI bus enable

8 UART 1 bus enable control’0’ – GPIO[22:23] enable (default)’1’ – UART 1 bus enable

7 UART 0 bus enable control‘0’ – GPIO[20:21] enable (default)‘1’ – UART 0 bus enable

6 I2C bus enable control ‘0’– GPIO[18:19] enable. (default) ‘1’– I2C bus enable


4 timer event1 enable’0’ – gpio[16] enable (default)’1’ – timer event1 enable

3 timer event0 enable’0’ – gpio[15] enable (default)’1’ – timer event0 enable

Table 30-7 IO Control Register Field Definitions (Continued)

M821xx Data Sheet


30.1.9 General Control Register[0x04C R/W] (default: 0x0000000A)

2 Expansion bus A19~A21 enable ‘0’ – gpio[12:14]enable (default)‘1’ – expansion bus A[19:21] enable

1 Expansion bus A17~A18 enable ‘0’ – gpio[10:11] enable (default)‘1’ – expansion bus A[17:18] enable

0 Expansion bus A15~A16 enable ‘0’ – gpio[8:9]enable (default)‘1’ – expansion bus A[15:16] enable

Table 30-8 General Control Register Field Definitions

Bit Description


4 USB1 user wakeup. When set, a "wakeup" event is generated to the USB controller, and the PHY's UTMI clock is restarted. Meaningful only if USB port is in suspend mode (but not due to force suspend configuration). This bit must be explicitly reset some time after it has been set.

‘0’ = no wakeup event generated (default)‘1’ = generate a wakeup event

3 USB1 force suspend. This control bypasses the Controller logic (except the suspend control module) and directly affects the PHY.

‘0’ = USB1 port is not forced into suspend mode‘1’ = USB1 port is forced into suspend mode (default)

2 USB0 user wakeup. When set, a "wakeup" event is generated to the USB controller, and the PHY's UTMI clock is restarted. Meaningful only if USB port is in suspend mode (but not due to force suspend configuration). This bit must be explicitly reset some time after it has been set.

‘0’ = no wakeup event generated (default)‘1’ = generate a wakeup event

1 USB0 force suspend. This control bypasses the Controller logic (except the suspend control module) and directly affects the PHY.

‘0’ = USB0 port is not forced into suspend mode‘1’ = USB0 port is forced into suspend mode (default)

0 UART loop back enable‘1’ = UART loopback enable‘0’ = UART loopback disable (default)

Table 30-7 IO Control Register Field Definitions (Continued)

M821xx Data Sheet


30.1.10 System Configuration Status Register[0x01C R]

Table 30-9 System Configuration Status Register

Bit Description

31 Reserved. Set to ‘1’.


19:15 Reserved

14 Status of PCI Bus Host mode enable control when PCI bus is enabled (could be status of either software control or hardware control, depends on configuration in IO Control Register)

‘0’ = PCI host disable‘1’ = PCI host enable

Status of HBBURSTEN when host bus is enabled (could be status of either software control or hardware control, depends on configuration in IO Control Register)

‘0’ = Host bus burst mode enabled‘1’ = Host bus burst mode disabled

13 Status of PCI_EN, generated from PCI bus enable control in IO Control Register‘0’ = Host bus mode‘1’ = PCI enable

12 :11 Status of General Purpose Bootstrap pin [2:1] (could be status of either software control or hardware control, depends on configuration in IO Control Register).

10 This bit is General Purpose Bootstrap pin[0] (could be status of either software control or hardware control, depends on configuration in IO Control Register).

9 :8 Status of HBUSSIZE_OUT[1:0] (could be status of either software control or hardware control, depends on configuration in IO Control Register)

7 Status of TDM_CK_OUT_EN_OUT (could be status of either software control or hardware control, depends on configuration in IO Control Register)

6 Status of General Purpose Bootstrap pin[3]. (could be status of either software control or hardware control, depends on configuration in IO Control Register).

5:4 Status of TM_MII1_MODE[1:0] (could be status of either software or hardware control, depends on configuration in IO control register)

3:2 Status of TM_MII0_MODE[1:0] (could be status of either software control or hardware control, depends on configuration in IO Control Register)

1 Status of BOOT_OP1 bootstrap pin


M821xx Data Sheet


30.1.11 ARM ID Register [0x030 R]

30.1.12 [0x040 R] Bootstrap Pin Status Register

Table 30-10 ARM ID Register Fields

Bit Description


0 ‘1’ = ARM1 is the master of the current AHB data phase to AAB address space‘0’ = ARM 0 is the master of the current AHB data phase to AAB address space.By reading this register, each ARM can determine which of 2 arms it is.

NOTE: All bootstrap pins are synchronized and sampled at reset.

Table 30-11 Bootstrap Pin Status Register

Bit Description


14 Status of HBBURST_EN_N bootstrap pin

13 Status of HBMODE_N bootstrap pin

12:11 Status of General Purpose Bootstrap pins [2:1].

10 This bit is General Purpose Bootstrap pin[0].

9:8 Status of HBUSSIZE[1:0] bootstrap pin

7 Status of TDM_CK_OUT_EN_bootstrap pin

6 This bit is General Purpose Bootstrap pin[3].

5:4 Status of TM_MII1_MODE[1:0] bootstrap pin

3:2 Status of TM_MII0_MODE[1:0] bootstrap pin



.


31.0 Interrupt Controller

31.1 Features• Status registers which identify specific interrupt conditions

• Mask registers to enable or disable IRQs and FIQs interrupts for the two ARM processors

• Software-based interrupt generation via registers

• Inter-processing signaling features

• Hardware support within Interrupt Priority Determination

• Mechanism to reset ARM1 (MSP)

31.2 Functional DescriptionThe Interrupt Controller provides the status and mask registers to create IRQs and FIQs for the two ARMs. It also provides means to reset ARM1 (MSP). This module also contains inter-processing signaling features. For a view of the Interrupt Controller within the top-level block diagram, see Figure 2-1.

31.2.1 OverviewThe Interrupt Controller device supports more than 32 peripheral interrupts and therefore, requires multiple interrupt status registers and associated mask registers. To handle over 32 interrupts, two sets of interuupt control registers are required: 0, and 1. Each includes:

• STATUS_REGISTER

• CLR_STATUS_BIT

• SET_STATUS REGISTER_BIT

• ARM0_IRQ_MASK

• ARM0_FIQ_MASK

• ARM1_IRQ_MASK

• ARM1_FIQ_MASK

IRQ0 (ARM0 IRQ) is created by “ANDING” the STATUS_REGISTER_0 register and ARM0_IRQ_MASK_0 register, STATUS_REGISTER_1 and ARM0_IRQ MASK_1 register then collapsing the result to a single bit. FIQ0 (ARM0 FIQ), IRQ1 (ARM1 IRQ) and FIQ1 (ARM1 FIQ) are created in a similar way with mask registers with offsets respectively.

M821xx Data Sheet


IRQ status and mask registers: The mask registers do not affect the reading of the status registers. Writing a ‘1’ to a corresponding bit location clears the status bit. It is important to know whether the source, which affects the status bit, is an event or a level. If the source is a level indication (e.g. PUI_IRQ and EMAC_IRQ) then the source must be cleared before the affected bit can be cleared.

31.2.2 Interrupt Generation ScenariosThere are 3 possible scenarios:

1. One of the blocks generates an interrupt. The relevant bit in STATUS_REGISTER_0 is being set, which notifies the relevant ARM interrupt service, which than clears the interrupt by setting the CLR_STATUS_0 register.

2. ARM software can simulate a specific interrupt by setting the relevant bit in SET_STATUS_REGSTER_0, which sets the relevant bit in the STATUS_REGISTER_0. The software is also responsible to clear the relevant bit setting the CLR_STATUS_0 register.

3. The ARM processor architecture provides only two interrupts: the IRQ and FIQ Interrupt. Therefore, there are four device level interrupts: ARM0_IRQ, ARM0_FIQ, ARM1_IRQ and ARM1_FIQ. The device permits each peripheral interrupt to be mapped to the IRQ or FIQ interrupt of a specific ARM processor.

Figure 31-1 Interrupt Priority

IRQ NUM PRI 0 (Highest)Bit31

Bit30

Bit29

Bit1

Bit0

IRQ STATUS0 REG IRQ PRIORITY REG

IRQ NUM PRI 1

IRQ NUM PRI 2

IRQ NUM PRI 30

IRQ NUM PRI 31 (Lowest)

Priority Encoder

6-bit EncodedINT Num IRQ WINNER REG

IRQ SELF-CLEARCTRL REG

Bit31

Bit30

Bit29

Bit1

5

6

Bit31

Bit30

Bit29

Bit1

Bit0

IRQ MASK REG

M821xx Data Sheet


31.3 Registers See Section 32.0 Interrupt Controller Registers.

.


32.0 Interrupt Controller Registers

All registers in this section are cleared on reset. Through the APB, all registers are word write only. Byte,half word, and word reads are permissible. IRQs are sampled on the rising edge of hclk.

All addresses in this section are offsets relative to a base offset, 0x0100A 0000.

32.1 Register MapTable 32-1 Interrupt Controller Registers

Description Offset Type

Status Register 0 0x00 R

Clear Status Register 0 (by writing ‘1’ to the relevant bits) (1)0x00 W

Set Status Register 0 (by writing ‘1’ to the relevant bits) (1)0x04 W

ARM0 IRQ MASK 0 (1)0x08 RW

ARM0 FIQ MASK 0 (1)0x0C RW

ARM1 IRQ MASK 0 (1)0x10 RW

ARM1 FIQ MASK 0 (1)0x14 RW

ARM1 Control Register 0x18 RW

Status Register 1 0x20 R

Clear Status Register 1 (by writing ‘1’ to the relevant bits) (1)0x20 W

Set Status Register 1 (by writing ‘1’ to the relevant bits) (1)0x24 W

ARM0 IRQ Mask 1 (1)0x28 RW

ARM0 FIQ Mask 1 (1)0x2C RW

ARM1 IRQ Mask 1 (1)0x30 RW

ARM1 FIQ Mask 1 (1)0x34 RW

Status Register Mask 1 (1)0x38 RW

ARM0 IRQ STATUS0 PRIORITY Registers 0x40-0x5C RW

ARM0 IRQ Winner Register 0x60 R

IRQ Self-Clear Control Register 0x64 RW

M821xx Data Sheet


1) Bit[0] is ignored during writes and equal to ‘0’ during reads.

32.2 IRQ Status and Mask RegistersIn the following Tables 32-2 and 32-3, “Level” refers to the the location of the interrupt source: when Level is ‘1’, clearing the interrupt status bit will end the interrupt condition and the status bit will remain at ‘0’. But when the Level is ‘2’, the source of the interrupt must be cleared in the originating block, otherwise the status bit in the IRQ_STATUS register will return to ‘1’ after having been cleared to ‘0’.

Offset: [0x00 — 0x14 R/W]

FIQ Priority Enable Register 0x68 RW

TDMA Status Register 0x70 RW

TDMA Control and Mask Register 0x74 RW

ARM1 IRQ STATUS0 PRIORITY Registers 0x80-0x9C RW

ARM1 IRQ Winner Register 0xA0 R

ARM0 IRQ Status0 Vector Address Register 0x100-0x17C RW

ARM1 IRQ Status0 Vector Address Register 0x180-0x1FC RW

Table 32-2 IRQ STATUS_0, IRQ_MASK_0, and FIQ MASK_0 Register Bit Definition

Bits Name Level Description

31 TIMERA_INT 1 TIMERA Interrupt Indication (Interrupt from timer0 only). See Section 33.2.1 Interrupt Generation.

30 TIMERB_IRQ 2 TIMERB Interrupt Request. Cleared by writing to Timer block.See Table 34-1, “Timer Block Register Map,” on page 557

29 RSVD 1 Reserved

28 RSVD 1 Reserved

27 MDMA_DONE_INT 1 Memory to memory DMA completed. Cleared by writing to MDMA block. See Section 41.0 Memory DMA Registers.

26 EDMA1TX_INT 1 EMAC1 DMA Transmit Channel. Indicates transfer from memory to Ethernet Interface 1 completed. See Section 39.0 I/O DMA Registers.

25 EDMA1RX_INT 1 EMAC1 DMA Receiver Channel. Indicates transfer from Ethernet Interface 1 to memory completed. See Section 39.0 I/O DMA Registers.

24 RSVD 1 Reserved

23 IPSEC_OI_IRQ 2 IPSEC Interrupt Request. Indicates IPSec Offload Interface conditions. Cleared through appropriate status register. See Section 17.0 IPSec Engine (0x0E04 0004 — 0xE04 0014).

22 DDRC_IRQ 2 DDR2 SDRAM Controller Interrupt Request. Interrupt status and acknowledge registers support this interrupt. See Section 10.0 DDR2 SDRAM Registers.

Table 32-1 Interrupt Controller Registers (Continued)

M821xx Data Sheet


21 APBB_IRQ 2 APBB Interrupt Request. This request comes from the PCI/uP interface block.

20 EDMA0TX_INT 1 EMAC0 DMA Transmit Channel. Indicates transfer from memory to Ethernet Interface 0 completed. See Section 39.0 I/O DMA Registers.

19 EDMA0RX_INT 1 EMAC0 DMA Receiver Channel. Indicates transfer from Ethernet Interface 0 to memory completed. See Section 39.0 I/O DMA Registers.

18 HITXFUL_INT 1 HI DMA TX Buffer Full. Indicates configurable number of bytes have moved from the PCI/uP block to the memory. See Section 39.0 I/O DMA Registers.

17 HIRXEMT_INT 1 HI DMA RX Buffer Empty. Indicates configurable number of bytes have moved from the memory to the PCI/uP block. See Section 39.0 I/O DMA Registers.

16 HI_IRQ 2 Host Interface Interrupt Request. From PCI/µP Interface. See Section 15.0 PCI/µP Interface.

15 TDM_TIMER_IRQ 2 TDM Timers Interrupt Request. From Timers block, see Section 33.2.2 TDM Timer.

14 SPI_INT 1 SPI Interrupt Indication. From SPI Interface, see Section 19.6 SPI Interrupts.

13 USB1_IRQ 2 USB1 Interrupt Request. From USB Interface, see Section 27.0 USB Interface.

12 EMAC1_IRQ 2 EMAC1 Interrupt Request. From Ethernet Interface 1. See Section 12.0 Ethenet Interface Registers.

11 USB0_IRQ 2 USB0 Interrupt Request. From USB Interface, see Section 27.0 USB Interface.

10 I2C_IRQ 2 I2C Interrupt Request. For details on I2C status register, see Section 26.1.6 STAT Register.

09 IPSEC_CORE_IRQ 2 IPSEC Interrupt Request0. From ESP/AH of IPsec block. See Section 18.3.2 Interrupt Status (INT_STAT).

08 TDMA_IRQ 1 TDMA Interrupt Request: result from status register in the INTC (refer to Section 32.8 TDMA Status, Control and Mask Register).

07 PUDMATX_INT 1 POS/UTOPIA DMA Transmit Channel. Indicates transfer from memory to PUI block is complete. See Section 39.0 I/O DMA Registers.

06 PUDMARX_INT 1 POS/UTOPIA DMA Receive Channel. Indicatestransfer from PUI block to memory is complete. See Section 39.0 I/O DMA Registers.

05 PUI_IRQ 2 POS/UTOPIA Interrupt Request. From Utopia/PoS Interface.See Section 14.0 PoS / UTOPIA Interface Registers.

04 EMAC0_IRQ 2 EMAC0 Interrupt Request. From Ethernet Interface 0. See Section 12.0 Ethenet Interface Registers.

03 PTP2 1 Processor to Processor Interrupt (set under firmware control) for inter processing signaling. These are set by writing to the respective bits in the SET STATUS REGSITER_0 [0x08].

Table 32-2 IRQ STATUS_0, IRQ_MASK_0, and FIQ MASK_0 Register Bit Definition (Continued)


M821xx Data Sheet


Offsets [0x20 — 0x34 R/W]

02 PTP1 1 Processor to Processor Interrupt (set under firmware control) for inter processing signaling. These are set by writing to the respective bits in the SET STATUS REGISTER_0 [0x08].

01 PTP0 1 Processor to Processor Interrupt (set under firmware control) for inter processing signaling. These are set by writing to the respective bits in the SET STATUS REGISTER_0 [0x08].

00 STATUS_REG_1 2 Indicates whether IRQs are pending in STATUS REGISTER_1 described in Table 32-3.

Table 32-3 IRQ STATUS_1, IRQ_MASK_1, and FIQ MASK_1 Register Bit Definition


31 MDMA_AHBErr_INT 1 AHB Error Indication. Indicates an error during a transfer from memory to memory. See Section 41.0 Memory DMA Registers.

30 IDMA_TxAHBErr_INT 1 AHB Error indication while DMA TX. Indicates an error from IDMA when reading. See Section 39.0 I/O DMA Registers.

29 IDMA_RxAHBErr_INT 1 AHB Error Indication while DMA RX. Indicates an error from IDMA when writing. See Section 39.0 I/O DMA Registers.

28 TDMA_TxAHBErr_INT 1 AHB Error Indication while DMA TDM TX. See Section 22.3 TDMA Registers.

27 TDMA_RxAHBErr_INT 1 AHB Error Indication while DMA TDM RX. See Section 22.3 TDMA Registers.

26 UART1_INT 1 UART1 Interrupt Indication. From UART Interface. Section 24.1.5 Interrupt Enable Register (IER)

25 RSVD 1 Reserved

24 RSVD 1 Reserved

23 RSVD 1 Reserved

22 RSVD 1 Reserved

21 RSVD 1 Reserved

20 RSVD 1 Reserved

19 RSVD 1 Reserved

18 ARM1_PMU_INT 1 ARM1: PMU Interrupt Indication. From ARM1.

17 ARM0_PMU_INT 1 ARM0: PMU Interrupt Indication. From ARM0.

16 L2_PARRT_INT 1 Parity error on L2 TAG RAM read Interrupt Indication. From L2 Cache block.

15 L2_PARRD_INT 1 Parity error on L2 DATA RAM read Interrupt Indication. From L2 Cache block.

14 L2_BWABT_INT 1 Buffered write abort Interrupt Indication. From L2 Cache block.



M821xx Data Sheet


32.3 ARM1 Control RegisterOffset: [0x18 R/W Bit 31]Table 32-4 ARM1 Control Register

32.4 ARM0 and ARM1 IRQ STATUS0 Priority RegistersOffsets: [0x40 — 0x5C R/W] [0x80 — 0x9C RW]The IRQ status0 priority register is used to define the priority sequence of the 32 bits in status0 register to generate an IRQ winner.

Note that bits are not specified in the following table should be treated as reserved.

13 RSVD 1 Reserved

12 RSVD 1 Reserved

11 RSVD 1 Reserved

10 TDMA_IRQ 2 TDMA Interrupt Indication (result of OR between over-flow, under-run, empty and full interrupts from the TDM DMA Controller block). For specific indication check the TDMA status register at 0x1002 000C. See Section 22.3.4 IRQ2TDMA Interrupt Status.

09 UART0_INT 1 UART0 Interrupt Indication. See Section 24.1.5 Interrupt Enable Register (IER).

08 IRQ_G7 1 GENERAL IRQ 7 also can be set by GPIO 7 change








00 STATUS_REG_0 2 IRQs are pending in STATUS REGISTER_0. See Table 32-2.

Bits Name Description

31 ARM1 Enable ARM1 enable. On reset this bit is cleared to disable ARM1. Writing a ‘1’ to this location enables the ARM1. Writing a ‘0’ disables it.

30-00 Reserved When writing, clear these bits to ‘0’.



M821xx Data Sheet


Table 32-5 ARM0 and ARM1 IRQ STATUS0 Priority Registers

ARM0ADDR

ARM1ADDR BIT Number Name Description

0x40 0x8028-24 PRI3 Priority 3 IRQ number

20-16 PRI2 Priority 2 IRQ number


4-0 PRI0 Highest priority 0 IRQ number









0x4C 0x8C28-24 PRI15 Priority 15 IRQ number
















M821xx Data Sheet


32.5 ARM0 and ARM1 IRQ Winner RegisterOffsets: [0x60 R bits 5-0] [0xA0 R bits 5-0]

The IRQ winner register is used for telling the winner bit number of IRQ status0 register which has the highest priority of set status bits. Number 32(0x20h) means no set bit in status0 register.

Table 32-6 ARM0 and ARM1 IRQ Winner Register

32.6 IRQ Self-Clear Control RegisterOffsets: [0x64 R/W bits 31-0]

The IRQ self-clear register is used to automatically clear set bits of IRQ STATUS0 register when the ARM0 or ARM1 winner register is read. The set bits in IRQ STATUS0 register can be only cleared when the corresponding bits in IRQ self-clear control register are enabled.

Each field of the IRQ priority register has its own IRQ number to setup. When one or more IRQ status bits are set, the priority encoder will generate the highest priority IRQ number (IRQ winner num 0~31, 32 means no interrupt) based on the given info from the IRQ priority registers. There are 32 priority levels to be programmed.

The TDMA self-clear (bit 8) only applies to TDMA RX group interrupt case.

Table 32-7 IRQ Self-Clear Control Registers

0x5C 0x9C28-24 PRI31 Lowest priority 31 IRQ number





31 – 6 Reserved

5 – 0 WINNER NUM IRQ STATUS0 INDEX WINNER (valid number 0 – 31)


31 – 1 Self-Clear CTRL IRQ STATUS0 SELF CLEAR CONTROL

0 Reserved

Table 32-5 ARM0 and ARM1 IRQ STATUS0 Priority Registers (Continued)

ARM0ADDR

ARM1ADDR BIT Number Name Description

M821xx Data Sheet


32.7 FIQ Priority Enable RegisterOffsets: [0x68 R/W bits 1-0]Table 32-8 IFIQ Priority Enable Register

32.8 TDMA Status, Control and Mask Register Offsets: [0x70 R/W bits 7-0, 0x74 R/W bits 8-0, 0x78 W bits 7-0]

TDMA status register bits can be read to know which TDMA channels have interrupts. Writing 1s to the TDMA status register clears the status bits. Refer to the TDMA specification.

TDMA mask register is to control the TDMA interrupt status bits going to the STATUS0 bit8 (TDMA). In addition, TDMA mask bit 16 is defined as TDMA RX group control enable. When this bit is 0, all the TDMA TX and RX status bits are anded with mask bits to STATUS0 bit8. When this bit is 1, only the TDMA TX is effective to the STATUS0 bit8.

Table 32-9 TDMA Status and Mask Register


31 – 02 Reserved

01 A1FIQPE ARM1FIQ Priority Enable1: Priority Encoder includes both ARM1’s IRQ and FIQ

enable mask.

0: Priority Encoder includes only ARM1’s IRQ.

00 A0FIQPE ARM1FIQ Priority Enable1: Priority Encoder includes both ARM0’s IRQ and FIQ

enable mask.

0: Priority Encoder includes only ARM0’s IRQ.


31-17 Reserved

16 TDRX GROUP TDMA RX GROUP BUFFER INTERVAL CONTROL (no status)

15-09 Reserved

08 TDTXCHK_0 TDMA0 TX BUFFER INTERVAL CHECK

07-01 Reserved

00 TDRXCHK_0 TDMA0 RX BUFFER INTERVAL CHECK

M821xx Data Sheet


32.9 ARM0 and ARM1 IRQ Status0 Vector Address RegisterOffsets: [0x100-0x17C R/W, 0x180-0x1FC R/W bits 31-2]All default values are 0x18.

Table 33. ARM0 and ARM1 IRQ Status0 Vector Address Register

Address Name Description

0x100 A0VA0 ARM0 Vector Interrupt Address Register for Status0 bit 0



0X10C A0VA3 ARM0 Vector Interrupt Address Register for Status0 bit 3




























M821xx Data Sheet











0x1A0 A1VA8 ARM1 Vector Interrupt Address Register for Status0 bit 8



0X1AC A1VA11 ARM1 Vector Interrupt Address Register for Status0 bit 11

0x1B0 A1VA12 ARM1 Vector Interrupt Address Register for Status0 bit 12



0X1BC A1VA15 ARM1 Vector Interrupt Address Register for Status0 bit 15

0x1C0 A1VA16 ARM1 Vector Interrupt Address Register for Status0 bit 16



0X1CC A1VA19 ARM1 Vector Interrupt Address Register for Status0 bit 19

0x1D0 A1VA20 ARM1 Vector Interrupt Address Register for Status0 bit 20



0X1DC A1VA23 ARM1 Vector Interrupt Address Register for Status0 bit 23

0x1E0 A1VA24 ARM1 Vector Interrupt Address Register for Status0 bit 24



0X1EC A1VA27 ARM1 Vector Interrupt Address Register for Status0 bit 27

0x1F0 A1VA28 ARM1 Vector Interrupt Address Register for Status0 bit 28



0X1FC A1VA31 ARM1 Vector Interrupt Address Register for Status0 bit 31

Table 33. ARM0 and ARM1 IRQ Status0 Vector Address Register (Continued)

Address Name Description

.


33.0 Timers

M821xx hardware resources include six general purpose timers, two timers driven by TDM frame synch, and a 32-bit watchdog timer. M821xx devices can source TDM frame synch and include two timer I/Os that can be independently configured as outputs or inputs. As outputs these I/Os can source a timer output to the surrounding system, while as inputs they can count the edges of external events.

For a view of the timer block within the top-level block diagram, see Figure 2-1.

33.1 Features

General Purpose Timers

• Six 32-bit timers (timer0, timer1, timer2, timer3, timer4, timer5) provide pulses to the interrupt controller.

• Two interrupts (timer_irqa and timer_irqb) can be driven by one or more of the six timer pulses: the interrupt mask register can be programmed to enable or disable one or more of the six timer status bits to generate an interrupt pulse to the interrupt controller. A secondary interrupt control register indicates which timer has driven the interrupt.

• When TIM_EVNT0 and TIM_EVNT1 are configured as outputs, they are driven by timer3 and timer5 repspectively. In this configuration, when the timer reaches its high bound value the I/O goes low.

• When TIM_EVNT0 and TIM_EVNT1 are configured as inputs, timer1 counts changes on TIM_EVNT0 and timer4 counts changes on TIM_EVNT1.

• A timer2 control register can be programmed to chain timer0 and timer2 together as one 64-bit long timer.



• Timer2, timer3, and timer5 have programmable low and high bound registers. When the current count reaches high bound value, the timeout status is asserted and the low bound value is loaded into the count register. Timer0, timer1 and timer4 have fixed 0 low bound value.

NOTE: Two M821xx general purpose timers are typically allocated to support the RTOS, so four are available for application support.For additional details, please refer to M821xx Linux BSP Technical Description (821xx-SWG-00) or contact your Mindspeed representative.

M821xx Data Sheet


TDM Frame Sync Timers

• Two16-bit TDM timers, driven by TDM frame sync timing, provide indications to the interrupt controller.

• One TDM interrupt (timer_tdmirq) can be programmed from one or more of the two TDM timer pulses. The TDM timer interrupt mask register can be programmed to enable or disable one or more of the two TDM timer status bits to generate an interrupt pulse to the interrupt controller.

• A TDM timer interrupt status register indicates which of the TDM timers had issued a timeout pulse to the interrupt controller. Writing to the TDM interrupt status register can clear the status bits.

Watch Dog Timer

• One 32-bit watch dog timer, driven by hclk, provides a hard reset capability.

• A watchdog control register can be programmed to enable or disable the watchdog timer.

33.2 Functional DescriptionThere are six general-purpose timers in the timer block. The counters are loaded with the value in the low bound registers on the rising edge of hclk one cycle after the low/bound registers are uploaded or when the counters time out.

In normal mode, the general purpose counters increment on every rising edge of hclk and the TDM timers increment on the rising edge of hclk only when TDM frame synch is high.

In TIM_EVNT counting enable mode, timer1 or timer4 increments on the rising edge of hclk only when a change is detected on TIM_EVNT0 or TIM_EVNT1 pin respectively.

In chain mode, timer2 increments when timer0 times out, timer3 increments when timer1 times out, timer5 increments timer4 times out.

M821xx Data Sheet


33.2.1 Interrupt GenerationAs shown in Figure 33-1, the IRQA and IRQB mask registers are used to selectively enable the timerout pulses to generate the IRQA and IRQB interrupts. Also an interrupt status register in the timer block can be read to check which of the timers had generated a timeout.

Figure 33-1 Timer Top-level Block Diagram

M821xx Data Sheet


33.2.2 TDM TimerThe TDM timer IRQ mask registers are used to selectively enable the timerout pulses to generate the TDMA IRQ interrupts. Also, a TDM interrupt status register in the timer block can be read to check which of the TDM timers had generated a timeout.

33.2.3 Counting or Driving TIM_EVNT0 and TIM_EVNT1These two pins can be either input or output, depending on the configuration. Refer to Tables 33-1 and 33-2 for behavior.

Figure 33-2 TDM Timer Top Level Block Diagram

Table 33-1 TIM_EVNT0 Behavior

TIM_EVNT0 Configuration Chain Mode Non-Chain Mode

TIM_EVNT0 is an input and is not ignored by the timer block.

Timer1 counts rising or falling edge on TIM_EVNT0. Timer3 is clocked by Timer1’s timeout.

Timer1 counts rising or falling edge on TIM_EVNT0. Timer3 is clocked by hclk.

TIM_EVNT0 is output. Timer3 is clocked by timer1’s timeout. TIM_EVNT0 is toggled by timer3’s timeout.

Timer3 is clocked by hclk.TIM_EVNT0 is toggled by timer3’s timeout. Timer1 counts with hclk and does not affect TIM_EVNT0.

M821xx Data Sheet


33.3 Timer Interface Signals

33.4 Registers

Table 33-2 TIM_EVNT1 Behavior

TIM_EVNT1 Configuration Chain Mode Non-Chain Mode

TIM_EVNT1 is an input and is not ignored by the timer block.

Timer4 counts rising or falling edge on TIM_EVNT1. Timer5 is clocked by Timer4’s timeout.

Timer1 counts rising or falling edge on TIM_EVNT0. Timer3 is clocked by hclk.

TIM_EVNT1 is output. Timer5 is clocked by timer4’s timeout. TIM_EVNT1 is toggled by timer5’s timeout.

Timer5 is clocked by hclk.TIM_EVNT1 is toggled by timer5’s timeout. Timer4 counts with hclk and does not affect TIM_EVNT1.

NOTE: In order for the timer to catch the rising of falling edge on TIM_EVNT0 or TIM_EVNT1, TIM_EVNT0 or TIM_EVNT1 has to stay high or low for at least 1 hclk cycle plus 3 ns.

Table 33-3 Timer Interface Signals


TIM_EVNT[1:0] B 2 Timer Event — These pins can be configured as output, to generate an external clock by the timer, or as input, to count external events (edges).

NOTE: For a detailed description of these registers, contact your Mindspeed representaive..

.


34.0 Timer Registers

NOTE: The memory addressing of the Timer registers is offset from the base address: 0x 1005 0000.

Table 34-1 Timer Block Register Map

Address: 0x10050000

Offset Bits Usage Default Function

0x00 31:0 R/W 0x00000000 Timer0 high bound register

0x04 31:0 R Timer0 current count (for testing)

0x04 31:0 W In this mode, user can write a specific value to the timer0.


0x0C 31:0 R Timer1 current count (for testing)

0x0C 31:0 W In this mode, user can write a specific value to the timer1.

0x10 31:0 R/W 0x00000000 Timer2 low bound register.

0x14 31:0 R/W 0x00000000 Timer2 high bound register.

0x18 0 R/W 0 Timer2 control register.(0: clocked by hclk, 1: clock by chained timer0’s timeout)

0x18 31:1 Reserved 0 Tied to all ‘0’

0x1C 31:0 R 0x00000000 Timer2 current count (for testing)

0x20 31:0 R/W 0x00000000 Timer3 low bound register


0x28 0 R/W 0x00000000 Timer3 control register (0: clocked by hclk, 1: clocked by chained timer1’s timeout)

0x28 2:1 R/W 00 TIM_EVNT0 input/output control:

“00” = TIM_EVNT0 is input, but its change does not increment timer1. Timer1 changes on every rising edge of hclk.

“01” = TIM_EVNT0 is input and its change does increment timer1.

“1x” = TIM_EVNT0 is output.

0x28 3 R/W 0 TIM_EVNT0 edge selection when it is an input

‘0’ = count rising edge

‘1’ = count falling edge

M821xx Data Sheet


0x28 31:4 Reserved. Tied to all ‘0’s.

0x2C 31:0 R 0x00000000 Timer3 current count (for testing)

0x30 31:0 R/W Timer4 high bound register


0x34 31:0 W In this mode, the user can write a specific value to the timer4.

0x38 31:0 R/W 0x00000000 Timer5 low bound register.

0x3C 31:0 R/W 0x00000000 Timer5 high bond register.


0x44 0 R/W 0 Timer5 control register(0: clocked by hclk, 1: clocked by chained timer4’s timeout)

0x44 2:1 R/W 00 TIM_EVNT1 input/output control

“00” = TIM_EVNT1 is input, but its change does not increment timer4. Timer4 changes on every rising edge of HCLK.

“01” = TIM_EVNT1 is input and its change does increment timer4

“1x” = TIM_EVNT1 is output

0x44 3 R/W 0 TIM_EVNT1 edge selection when it is an input

‘0’ = count rising edge

‘1’ = count falling edge

0x44 31:4 Reserved Tied to all ‘0’

0x48 5:0 R/W 0x01 Timer5 down to Timer0 IRQ Mask


0x50 5:0 R Timeout pulse status for (timerout5, timerout4, timerout3, timerout2, timerout1, timerout0)

0x50 5:0 W Status clear – writing ’1’ clears the status or (timerout5, timerout4, timerout3, timerout2, timerout1, timerout0)


0x80 15:0 R/W 0x00000000 TDM Timer0 high bound register

0x80 16 R/W 0x00000000 TDM Timer0 frame sync source (: 0: TX frame sync, 1: RX frame sync)


0x84 15:0 R TDM Timer0 current count (for testing)

0x84 15:0 W In this mode, user can write a specific value to this timer.


0x88 15:0 R/W 0x00000000 TDM Timer1 high bound register

0x88 16 R/W 1 TDM Timer1 frame sync source (0: TX frame sync, 1: RX frame sync)


0x8C 15:0 R TDM Timer1 current count (for testing)

Table 34-1 Timer Block Register Map (Continued)

Address: 0x10050000

M821xx Data Sheet


0x8C 15:0 W In this mode, user can write a specific value to this timer.

0x8C 31:18 Reserved Tied to all ‘0’

0xC0 1:0 R TDM Timer1 down to Timer0 IRQ status register

0xC0 1:0 W 00 Status clear – writing ’1’ clears the TDM status register

0xC0 31:2 Reserved Tied to all ‘0’

0xC4 1:0 R/W 00 TDM Timer1 down to Timer0 IRQ mask register

0xC4 31:2 Reserved

0xD0 31:0 R/W 0x00000000 Watch Dog Timer high bound register

0xD4 0 R/W 0 Watch Dog Timer control register (0: disable, 1: enable)

0xD4 31:1 Reserved Tied to all ‘0’

0xD8 31:0 R Watch Dog Timer current count (for testing)

0xD8 31:0 W In this mode, user can write a specific value to the watchdog timer

Table 34-1 Timer Block Register Map (Continued)

Address: 0x10050000

.


35.0 Test and Debug Interface Description

The JTAG interface provides access to the ARM embedded ICE (in-circuit emulation) unit and supports IEEE 1149.1 Boundary Scan for manufacturing and test.

There are two JTAG ports used for debug of the ARM11s and boundary scan.

For manufacturing board-level test, TRISTATE# input can be asserted to force all outputs to high impedance mode.

35.1 Test and Debug Interface Signals

35.1.1 JTAG Interface Signals JTAG0 supports debug of ARM0 and boundary scan of the entire device. JTAG1 enables debug of ARM1. If one connector needs to be connected to both, the two ports can be chained on a PCB.

To use the JTAG interface for boundary scan, assert TM_BSCN_JTAG. To use the JTAG interface for debug, allow TM_BSCN_JTAG to go low (held low internally).

JTAG interface signals are described below.

Table 35-1 JTAG Signals

Signal Name I/O Size Signal Name/Description

JTAG0_TRST#JTAG1_TRST#

I 2 JTAG Test Reset. A low signal forces the TAP controller into a logic reset state. TRST# must be open (i.e., unconnected) for normal (non-test) operation. This pin has an internal pull-up, and it conforms to IEEE 1149.1 JTAG specification.NOTE: TRST# may be held low for normal operation, but this prevents the use of the TAP as a debug port. Leaving TRST# open (pull-up internal) allows use of the debug port. The TRST# I/O type interfaces well with the corresponding ARM MultiICE output, an open collector driver with a pull-up.

JTAG0 _TCKJTAG1_TCK

I 2 JTAG Test Clock. This is the JTAG clock signal. This pin has an internal pull-up, and it conforms to IEEE 1149.1 JTAG specification.

JTAG0_TMSJTAG1_TMS

I 2 JTAG Test Mode Select. This is the control signal to the TAP controller. This pin has an internal pull-up, and it conforms to IEEE 1149.1 JTAG specification.

JTAG0_TDIJTAG1_TDI

I 2 JTAG Test Input Data. This is the boundary scan serial input signal, and it is shifted in on the rising edge of TCK. The pin has an internal pull-up, and it conforms to IEEE 1149.1 JTAG specification.

JTAG0_TDOJTAG1_TDI

O 2 JTAG Test Output Data. This is the three-stateable boundary scan data output signal, and it is shifted out on the falling edge of TCK. It conforms to IEEE 1149.1 JTAG specification.

M821xx Data Sheet


35.1.2 Test Interface Signals Test interface signals are described below.

35.2 JTAG Interface TimingThe JTAG Interface complies with the IEEE 1149.1 JTAG specification.

35.3 Tri-state Test ModePulling this input low at any time will cause all outputs to go into tri-sate mode. This supports PCB testing.

Table 35-2 Test Signals

Signal Name I/O Size Signal Description

TM_BSCN_JTAG I 1 Boundary Scan Mode. Indicates if JTAG ports are used for ARM debug or for boundary scan. When high, used for boundary scan. When low used for ARM debug. NOTE: For normal operation, TM_BSCAN_JTAG must be low (pulled down internally).

TRISTATE# I 1 Three-state All Outputs. Low input three-states all outputs. High input enables normal output drive states. May be used for board manufacturing test. Internal pull-up.

.


36.0 Power Management

This subsection overviews M821xx device power management options.

36.1 IntroductionM821xx power management options include stop-clock functionality, processor speed control, and sleep, power-down, or suspend modes for specific blocks, including external SDRAM.

36.2 Programmable Stop-Clock FunctionalitySignificant powers savings may be made by stopping clocks to unused blocks within M821xx devices.

By default, all clocks are enabled as the device boots.

Clocks to the following M821xx logic cores can be independently stopped:

• ARM0

• ARM1

• PCI / µP Bus Interface

• Utopia / PoS Interface

• Etherenet0 (WAN) Interface

• Ethernet1 (LAN) Interface

• USB0 Controller and Interface

• USB1 Controller and Interface

• TDM Interface and TDM DMA Controller

• I2C and SPI Controllers

• Memory DMA Controller

• IPSEC Security Co-Processor

36.2.1 Stop-Clock ProceduresLogic cores with input reference clocks that are driven from clocks generated from the device (e.g. TDM, Ethernet MACs) can be taken out of reset with the reference clock input stopped or they can be held in software reset. Unless the anticipated power-down period is short, stopping the input reference is more attractive for power savings.

36.2.1.1 Stopping Clocks

Logic blocks can be powered down by setting the apporpriate bit in the Clocks Power Down (CLK_PWR_DWN) register described on page 131.

M821xx Data Sheet


Table 36-1 shows which bit fields to set to ‘1’ to power down different M821xx logic blocks.

36.2.1.2 Holding Logic Blocks in Reset

Logic block can be held in reset by clearing specific bits in the Register: Block Reset (BLK_RESET) register ( see page 135 ) in reset.

Table 36-2 shows which fields to clear to ‘0’ to hold specific logic blocks in reset.

By default, all interface blocks are held in reset after boot.

Table 36-1 Clocks Power Down Bits (CLK_PWR_DWN)

Bits Description

21 ARM 0 Generated Clock Power Down. Active High.

20 ARM 1 Generated Clock Power Down. Active High.

19 External EPHY Generated Clock Power Down. Active High.

18 TDM IF Generated Clock Power Down. Active High.

17 PUI IF Generated Clock Power Down. Active High.

16 PCI IF Generated Clock Power Down. Active High.

10 MDMA AHB Clock Power Down. Active High.

9 I2C and SPI AHB Clock Power Down. Active High.

8 UART AHB Clock Power Down. Active High.

7 IPSEC AHB Clock Power Down. Active High.

6 TDM AHB Clock Power Down. Active High.

5 USB1 AHB Clock Power Down. Active High.

4 USB0 AHB Clock Power Down. Active High.

3 GEMAC1 AHB Clock Power Down. Active High.

2 GEMAC0 AHB Clock Power Down. Active High.

1 PUI AHB Clock Power Down. Active High.

0 PCI AHB Clock Power Down. Active High.

Table 36-2 Block Reset (BLK_RESET)

Bit Name Description12 RNG_Reset_N • 0 — Keep RNG block in Reset


11 IPSEC_Reset_N • 0 — Keep IPSEC block in Reset• 1 — De-activate Reset

10 DDR_Reset_N • 0 — Keep DDR block in Reset• 1 — De-activate Reset


M821xx Data Sheet


36.2.2 Output Clock ControlThe M821xx provides several internally generated clocks that can be used as the input clocks for some interfaces (PCI, POS/UTOPIA, etc.). Except for TDM clock (which is routed internally in the device), all of the other interface clocks need to be routed externally from the output to the input.

Clocks sourced by the M821xx to external devices internally can be stopped. Logic blocks affected include:

• UTOPIA/POS (TM_PUI_REFCLK0)

• PCI (TM_PCI_REFCLK0)

• TDM Interface (TM_TDM_REFCLK0)

• GEMAC0 and GEMAC1 Interfaces (TM_ETH_REFCLK0)

• Expansion Bus Interface (EXP_CLK)

All of the above clocks, except for the Expansion Bus clock can be disabled by setting bits 16 — 19 to ‘1’ in the Clocks Power Down (CLK_PWR_DWN) register described on page 131.

Disable the EXP_CLK output by clearing bit 0 of the Expansion Chip-Select Enable (EX_CS_EN_R) register to ‘0’. See page 157.




3 TDM_Reset_N • 0 — Keep TDM IF in Reset• 1 — De-activate Reset

2 PUI_Reset_ • 0 — Keep PUI IF in Reset• 1— De-activate Reset

1 HIF_Reset_N • 0 — Keep Host IF except PCI IF and all PCI Clock circuitry in Reset


0 PCI_IF_Reset_N • 0 — Keep PCI IF and all PCI Clock circuitry in Reset


Table 36-2 Block Reset (BLK_RESET) (Continued)

M821xx Data Sheet


36.3 Automatic Stop-Clock FunctionalityThe ARM processors and their L2 cache blocks automatically stop clocks and other inputs to unused modules. Through the extensive use of this approach, only the logic actively used to perform a calculation consumes power.

For more information, refer to the ARM1136JF-S and ARM1136J-S Technical Reference Manual.

36.4 ARM Clock Frequency ControlThe clocks driving the two ARM processors can be modified in tandem and independently.

• the clock frequency PLL output may be moved downward from 450 MHz — this will affect the frequency of both ARMs uniformly

• an integer divisor may be configured to reduce the clock for a specific ARM independent of the other ARM

36.4.1 Reducing the Clock Frequency of Both ARM ProcessorsRefer to Section 5.3.6 Rates Generation and Change Procedures for steps.

Set “W” divider value in bit 9:8 of the ARM Clock Control (ARM_CLK_CNTRL) register described on page 127.

36.4.2 Reducing the Clock Frequency of an ARM Procesor Refer to Section 5.3.6 Rates Generation and Change Procedures for steps.

Set ARM clock divider in bits 11:8 for ARM1 and 3:0 for ARM0 in the ARM Clk Control 2 (ARM_CLK_CNTRL2) register described on page 133.

36.5 ARM Sleep ModesThe two ARM processors may be independently moved in and out of power-down states.

ARM11 architecture supports three reduced power consumption modes:

• Standby

• Shutdown

• Dormant

For more information, refer to the ARM1136JF-S and ARM1136J-S Technical Reference Manual.

M821xx Data Sheet


36.6 DDR2 Power Down ModesThe M821xx can power-down DDR2 SDRAM. Refer to Section 10.3.3 POWER_DOWN, SREFRESH on page 167.

Two modes of SDRAM power down are supported:

36.6.1 Memory Power-DownThe memory controller sets the memory devices into power-down mode. In this mode, the controller and memory clocks are fully operational, but the CKE input bit to the memory devices is de-asserted. The controller will continue to monitor memory refresh needs and will automatically bring the memory out of the power-down mode to perform these refreshes. When a refresh is required, the CKE input bit to the memory devices will be re-enabled. This action brings the memory devices out of power-down. Once the refresh has been completed, the memory devices will be returned to power-down mode by de-asserting the CKE input bit.

36.6.2 Memory Self-RefreshThe memory controller sets the memory devices into self-refresh mode. In this mode, the controller and memory clocks are fully operational and the CKE input bit to the memory devices is de-asserted. Since the memory automatically refreshes its contents, the controller does not need to send explicit refreshes to the memory.

36.7 USB Suspend ModeWhen operating in host mode, the USB controller is capable of global and selective Suspend and Resume operations across attached USB devices as described in section 4.3 of the Intel EHCI specification. The USB controller presents a standard EHCI-compatible interface to software drivers. See Section 27.7 USB Power Management on page 481.

When operating in device mode, the USB controller supports Suspend and Resume functionality as described in the USB Specification, revision 2.0. When operating in device mode, the USB cotroller is capable of global and selective Suspend and Resume operations as described in section 7.1.7.6 of the USB 2.0 specification.

.


37.0 AHB – APB Bus Bridge

37.1 Features• The APB Bridge is a slave of the AHB, and the only master on the APB bus.

• Decodes the address and generates the peripheral select. Only one select signal is active during a data transfer.

• The data transfer is controlled by the select signal and the enable (strobe) signal.

• Supports the 64-bit AHB bus and the 32-bit APB bus.

• Low-Power interface during non-peripheral bus activity.

37.2 Functional DescriptionThe AAB (AHB-APB Bridge) block converts AHB transfers into a suitable format for the slave devices or peripheral registers on the APB. The bridge provides latching of address and control signals, as well as providing a second level of decoding to generate slave select signals for the APB peripherals. For a view of the AHB-APB Bridge within the top-level block diagram, see Figure 2-1.

When a non-valid address is accessed from the AHB master, the AAB block sends an error message to the AHB master.

The AAB block supports the 32-bit (word) or the 64-bit (double-word) data transactions through the 64-bit AHB bus. (It does not support the byte or half-word transactions.)

The AAB block has a single clock, HCLK. All signal transitions are related to the rising edge of this clock.

37.3 APB Address MappingAll registers mapped in APB bus are word address aligned. The APB address ranges from 0x10000000 to 0x10FFFFFF. The following table, Table 37-1 shows the preliminary address mapping for the peripheral registers of each block.

Table 37-1 APB Address Mapping

BaseAddress

Memory Size Block For further infromation

0x101F0000 64 KB RESERVED —

0x101E0000 64 KB MDMA Section 41.0 Memory DMA Registers

0x101D0000 64 KB TDMA2 Section 22.3 TDMA Registers

M821xx Data Sheet


0x101C0000 64 KB RESERVED —

0x101B0000 64 KB RESERVED —

0x101A0000 64 KB EXPANSION BUS Section 8.0 Expansion Bus Interface Registers

0x10190000 64 KB EMAC1 (Eth1) Section 12.0 Ethenet Interface Registers

0x10180000 64 KB

RESERVED —

0x10170000 64 KB

0x10160000 64 KB

0x10150000 64 KB

0x10140000 64 KB

0x10130000 64 KB

0x10120000 64 KB

0x10110000 64 KB

0x10108000 32 KBAHB —

0x10100000 32 KB

0x100F0000 64 KB ARAM —

0x100E0000 64 KB IDMA Section 39.0 I/O DMA Registers

0x100D0000 64 KB EMAC0 Section 12.0 Ethenet Interface Registers

0x100C0000 64 KB PUI Section 14.0 PoS / UTOPIA Interface Registers

0x100B0000 64 KB CLK Section 6.0 Clock and Reset Registers

0x100A0000 64 KB INTC Section 32.0 Interrupt Controller Registers

0x1009C000 16 KB I2C Section 26.0 I2C Interface Registers

0x10098000 16 KB SPI Section 20.0 Serial Peripheral Interface (SPI) Registers

0x10094000 16 KB UART1 Section 24.0 Universal Asynchronous Receiver Transmitter (UART) Registers0x10090000 16 KB UART0

0x10080000 64 KB RESERVED —

0x10070000 64 KB GPIO Section 30.0 General Purpose I/O Registers

0x10060000 64 KB AHB —

0x10050000 64 KB TIMER Section 34.0 Timer Registers

0x10048000 32 KBAHB —

0x10040000 32 KB

0x10030000 64 KB RESERVED —

0x10020000 64 KB TDMA Section 22.3 TDMA Registers

0x10010000 64 KB HIF (PCI/µP) Section 16.0 PCI/µP Interface Registers

0x10000000 64 KB TDM Section 22.2 TDM Bus Interface Registers

Table 37-1 APB Address Mapping (Continued)

M821xx Data Sheet


37.4 AHB–APB Bus Bridge RegistersThe one control register for the AHB–APB Bus Bridge is physically located in the GPIO block — see Section 30.1.4 APB Bus Access Wait State Register.

.


38.0 I/O DMA Controller

38.1 IntroductionThe I/O DMA controller transfers data blocks between the M821xx AHB and specific I/O blocks:

• POS / UTOPIA

• Ethernet Port 0

• Ethernet Port 1

• PCI / µProcessor Bus

For a view of the AHB-APB Bridge within the top-level block diagram, see Figure 2-1.

For register details see Section 39.0 I/O DMA Registers.

38.2 Features• Supports the following interfaces from the I/O side: PCI/ uProcessor interface, UTOPIA / POS L2

interface and two GEMAC interfaces. From the system side: a 64 bits AHB port as a master on that bus.

• Provides maskable interrupts to the ARM processor for AHB bus errors and data-frame-has-been-proccessed to different interface done indications.

• Arbitrates between interface masters according to configured priority level for AHB bus access.

• Supports a locked transfer request for each I/F. The length of the burst is configurable for each interface and is up to 255 cycles.

• Provides a lookup table for configurable and maskable VPI/VCI values in ATM mode only.

• Supports a direct access from the PCI to the internal memory as a slave.

• Configurable support for driving NSEQ transaction when crossing the 1K boundary

M821xx Data Sheet


38.3 Functional DescriptionThe I/O DMA controller transfers data from/to memory to / from PCI/µProcessor, POS/UTOPIA and the 2 Ethernet Ports via the AHB bus. Figure 38-1 shows the I/O DMA block diagram. Tx direction is defined from AHB to I/O and RX direction is defined from I/O to AHB.

Figure 38-1 I/O DMA Block Diagram

Because each of the peripherals devices can request to master the AHB bus to transfer or receive data, the I/O DMA controller also arbitrates between the devices to grant the bus to each one of them. The arbitration is done according to a configure priority list. The following priority is the default one listed from high priority device to low:

• Ethernet Port 0 to Memory Highest

• Ethernet Port 1 to Memory

• Memory to Ethernet Port 0

• Memory to Ethernet Port 1

• PCI / µProcessor to Memory, direct access

IODSTRUC

Gen

eral

(clo

cks,

res

ets,

&

c.)

IDMACORE

DMAIO (Arbiter)AHM

AHBBUS

IODSTRUC

IODSTRUC

IODSTRUC

IODSTRUC

HDMA

IODSTRUCG EMAC

G EMAC

PUI

HIF

Rx

Rx

Rx

Tx

Tx

Tx

APBBUS

IDMAREG

HMDMA

VPI/VCI

M821xx Data Sheet


• POS / UTOPIA to Memory

• Memory to POS / UTOPIA, non-direct access

• PCI/µProcessor to Memory, non-direct access

• Memory to PCI/µProcessor, non-direct access Lowest

The I/O DMA arbitrates again when the current master is giving up its request or when the I/O DMA looses the AHB bus.

Each master has a 'LOCK' configuration, which guarentees him at least the configure number amount of cycles on the AHB bus. Once the 'LOCK' is deasserted, a higher priority master that requests the bus can take the bus from the current master even if not all data was transferred.

Most interfaced peripherals store their data in the memory as a chained list using frame and buffer descriptors and data buffers.

The only peripheral that does not use a chained list is the PCI/µP interface. This block stores its data in a contiguous buffer form.

The PCI/µProcessor non-direct access to the memory uses HDMA sub-block, while the direct access uses HMDMA sub-block.

Except for the memory direct access by the PCI/µProcessor interface, both directions of each interface, can assert an interrupt, if enabled, when a frame transfer ends. Also available, are interrupts in case an error occured on the AHB bus.

38.3.1 I/O Data Structure POS / UTOPIA and the two Ethernet interfaces use a chained list data structure for their data.

I/O DMA controller exchanges control information and data with the system via three data structures:

• Frame descriptors

• Buffer descriptors

• Data buffers

Figure 38-2 shows how these data structures are related:

M821xx Data Sheet


Figure 38-2 DMA Data Structure

Frame descriptors have a four-byte pointer to the next frame, a field for the system or applications program to use exclusively, a frame status field, a control field for the entire frame, and an array of associated buffer descriptors. Buffer descriptors have a pointer to a data buffer and control field for the buffer. A data buffer is an array of bytes, which can be stored in the memory.

The DMA engine supports transfers of data buffer data on byte boundaries. Frame descriptors must be aligned on 8-byte boundaries in order to enable us to locate the next frame descriptors after the current frame buffer descriptor when we have only 1 buffer but still always be able to read a full 64 bits of descriptor in 1 transaction. Buffer descriptors must be aligned on 8-byte boundaries for the same reason as in the frame descriptors. The DMA engine employs bursts of full data bus width, aligned transfers whenever possible. The DMA engine avoids doing unaligned or partial word accesses, except at the beginning or end of block transfers.

The DMA supports multi buffer descriptors for scattering and gathering. This feature helps to avoid copying data buffers around the memory by ARM to boost performance.

QueueAccess

FrameDiscriptors

DataBuffers

BufferDescriptors

Next

System

FStatus

FControl

BPointer

BControl

BPointer

BControl

BPointer

BControl

Head Next

System

FStatus

FControl

BPointer

BControl

BPointer

BControl

Next

System

FStatus

FControl

BPointer

BControl

BPointer

BControl

BPointer

BControl

M821xx Data Sheet


38.3.2 I/O DMA Transfers with Ethernet InterfaceThe following subsections summarize I/O DMA engine interaction with the Ethernet0 and Ethernet1 interfaces.

38.3.2.1 I/O DMA — Ethernet Operating Sequence

Section 38.3.2.1.1 lists the sequence for TX data transfers towards the network.Section 38.3.2.1.2 presents steps for RX data transfers towards the AHB.

38.3.2.1.1 TX DMA Operation Sequence (Outbound)

1. ARM builds the data structure in the memory as shown in Figure 38-2.

2. ARM writes the address location of the data structure into the DMA’s HEAD Pointer register.

3. ARM can write to LOCKSZ register if required to make an undisturbed transaction (will assert the lock signal on the AHB).

4. ARM sets the START bit in the DMA control register.

5. DMA uses the HEAD pointer to fetch the frame descriptor and get the NEXT pointer and the FControl.

6. DMA examines the frame ready (FReady) field in the FControl, if not set, DMA will stop, reset the START bit, and interrupt the ARM if the IRQEN bit in the FControl is on. It’s the ARM responsibility to set the START bit again. Else, it will go on to the next step.

7. DMA fetches the first buffer descriptor.

8. DMA loads the memory address pointer with the BPointer and stores the BControl.

9. DMA loads the DMA block length counter with the block length field (BLen) in the BControl.

10. When GMAC is ready, it raises DREQW. DMA will transfer data from the memory to GMAC’s TX FIFO until the block length counter expired, then go to the next step. During this process, if GMAC asserts TXSRDY, DMA will cease transferring and notify GMAC with WLAST. Also, if Retransmit (bit TXSOUT[4]) is True, DMA will go to Step 7. If not, it goes to Step 13. The GMAC can stop the IDMA by deasserting the DREQW signal.

11. DMA examines the last block (BLast) field of the Bcontrol. If it is not set, DMA fetches the next buffer descriptor and goes to Step 8. If it is set, DMA will notify GMAC with WLAST and go on to the next step.

12. DMA waits until the GMAC finishes transmission of the current frame as indicated by the GMAC’s status ready (TXSRDY.) If Retransmit (bit TXSOUT[4]) is True, DMA will go to Step 7.

13. DMA obtains the status of the frame from the TXSOUT and writes it to the FStatus of the current frame descriptor in the memory. The frame done (FDone) field of the FStatus will be set to mark the frame as done and transmitted. (FDONE should always be initialized to 0 when the ARM builds the data structures in the memory.)

14. DMA interrupts ARM, if the interrupt enable (IRQEn) field in the FControl is set.

15. If FLAST is deasserted, DMA moves its NEXT pointer register to its HEAD pointer register then goes to Step 5. If FLAST is asserted, START will be reset to zero and we move to step 1.

38.3.2.1.2 RX DMA Operation Sequence (Inbound)



M821xx Data Sheet


3. ARM can write to LOCKSZ register if required to make an undisturbed transaction (will assert the lock signal on the AHB).



6. DMA examines the frame ready (FReady) field in the FControl, if not set, DMA will stop, reset the START bit, and interrupt the ARM if the IRQEN bit in the FControl is on. It’s the ARM responsibility to set the START bit again. Else, it will go on to the next step.


8. DMA loads the memory address pointer with the BPointer and stores the BControl. If the Scatter bit in the FControl is true, DMA keeps the block length field (BLen) of the Bcontrol and goes to Step 10. Else, next step.

9. DMA waits for RXSREQ signal from GMAC to obtain the package count in bytes from bits RXSOUT[8:0]. If RXSOUT[28:27] = 00, it transfers RXSOUT[8:0] number of bytes from GMAC RX FIFO to the memory location pointed by BPointer. DMA stays at this current step until RXSOUT[28:27] = 01 which indicates the end of transfer then goes to Step 12. The GMAC can stop the IDMA by deasserting the RXSREQ signal.

10. DMA waits for RXSREQ signal from GMAC to obtain the package count in bytes from bits RXSOUT[8:0].

11. If RXSOUT[28:27] = 00, DMA attempts to fill the allocated memory block length as indicated by Blen. If more bytes are needed, it goes to Step 10. If the block is full, it fetches the next buffer descriptor for another memory location and size. If BLast is True, BLen is assumed to be infinite. DMA stays at this current step until RXSOUT[28:27] = 01 which indicates the end of transfer.

12. DMA writes the packet size to the BLEN field in Bcontrol register of the current buffer descriptor in the memory.

13. DMA writes the status RXSOUT[26:0] to the Fstatus of the current frame descriptor in the memory. The frame done (FDone) field of the FStatus willd be set to mark the frame as done and received. This field is initialized to 0 when the ARM builds the data structures in the memory.

14. DMA interrupts ARM, if the interrupt enable (IRQEn) filed in the FControl pointer of the current frame is set.

15. If FLAST is deasserted, DMA moves its NEXT pointer register to its HEAD pointer register then goes to Step 5. If FLAST is asserted, START will be reset to zero and we move to step 1.

38.3.2.2 I/O DMA — Ethernet Data Structures

38.3.2.2.1 Next Field Bit Description

Offset: x0

NOTE: Each allocated memory block is limited to 64K-1 bytes. If not, overflow will happen. No recovery logic.

Table 38-1 Next Field Bit Data Structure Description

BIT No. Name Description31 – 3 NEXT Pointer of the next Frame Descriptor.

2 – 0 Don’t care These bits are ignored and forced to 0.

M821xx Data Sheet


38.3.2.2.2 System Field Bit Description

Offset: x4

38.3.2.2.3 Frame Status Field Bit Description Offset: x8

38.3.2.2.4 Frame Control Field Bit Description (Both directions) Offset: xC

Table 38-2 System Field Bit Data Structure Description

BIT No. Name Description31 – 0 Not used by hardware (IDMA)

Table 38-3 Memory to GMAC (Outbound) Data Structure Description

BIT No. Name Description31 FDone Frame done.

30 – 5 Not used. Read as Hex 1000000.

4 – 0 EM_TXSOUT Same as G EMAC IP Tx_Stat Register bit [4..0]. Indicating transmitted frame status information to be relay back to frame structure.

Please refer to the G EMAC Interface Specification for the latest and most accurate definition.

Table 38-4 GMAC to Memory (Inbouned) Data Structure Descritpion



25 – 00 EM_RXSOUT Same as G EMAC IP Rx_Stat Register. Indicating received frame status to be relayed back to frame structure.

Please refer to the G EMAC Interface Specification for the latest and most accurate definition.

Table 38-5 Frame Control Field Bit Description (Both directions)

BIT No. Name Description31 – 8 Not Used

7– 4 Reserved Not Used.

3 SCATTER If set, scatter inbound receiving data to different memory locations. This bit is ignored on the outbound.

2 IRQEN Interrupts the ARM when DMA finishes transferring a frame or when a frame descriptor is not ready (FREADY = 0). Also see FLAST, FREADY, and BLAST.

1 FLAST Last frame. DMA stops after executing this frame. Interrupts if the IRQEN bit is on. ARM needs to set the START bit in the APB register to restart.

M821xx Data Sheet


38.3.2.2.5 Buffer Pointer Field Bit Description.

Offset: x10 + 8N, where N is non-negative integer.

38.3.2.2.6 Buffer Control Field Bit Description. Offset: x14 + 8N, where N is non-negative integer.

0 FREADY Frame ready. If not set, DMA stops as soon as this bit is read and issues an interrupt if IRQEN is on. ARM needs to set the START bit in the APB register to restart.

Table 38-6 Buffer Pointer Field Bit Data Structure Description

BIT No. Name Description31 – 0 BPOINTER Location of a data buffer.

Table 38-7 Memory to GMAC (Outboud) Data Structure Description

BIT No. Name Description31 – 17 Not used

16 BLAST Last block. No more data buffer. Assert IO_WLAST signal to I/O; Go to the next frame descriptor if FLAST is off, else end operation; IRQ if enabled. BLAST = 1 and BLEN = 0 is an illegal setting.

15 – 0 BLEN Number of bytes to be transferred from memory to I/O. Zero means none.

Maximum 64K – 1 bytes. BLAST = 1 and BLEN = 0 is an illegal setting.

Table 38-8 GMAC to Memory Data Structure Description

BIT No. Name Description31 BDONE Buffer Done. When a frame is finished, IDMA writes a 1 to BDONE of the last BControl.

30 - 17 Not used.

16 BLAST In Scatter mode, Software sets this bit to 1 to indicate the last memory area for scattering. A zero means more memory space at the next BPOINTER.

In Non-Scatter mode, BLAST is not used and Software does not need to set it.

• When a frame is finished, IDMA writes a 0 to BLAST of the last BControl.

15 – 0 BLEN In Scatter mode, Software sets BLEN to be the size of the memory block where IDMA will store the receiving data. Maximum 64K – 1 bytes. The sum of all BLENs should be at least 1 word more than the receiving data.

In Non-Scatter mode, BLEN is not used and Software does not need to set it.

When a frame is finished, IDMA writes the number of receiving data bytes to BLEN of the last BControl.

Table 38-5 Frame Control Field Bit Description (Both directions)

M821xx Data Sheet


38.3.3 I/O DMA Transfers with POS/UTOPIA InterfaceThe following subsections summarize I/O DMA engine interaction with the POS / UTOPIA interfaces.

38.3.3.1 I/O DMA — POS/UTOPIA Operating Sequence

Section 38.3.3.1.1 lists steps for transfer of data towards the POS / UTOPIA interface. Section 38.3.3.1.2 lists steps for transfer of data towards the AHB.

38.3.3.1.1 Tx DMA Operation Sequence (Outbound)





5. DMA examines the frame ready (FReady) field in the FControl, if not set, DMA will stop, reset the START bit, and interrupt the ARM if the IRQEN bit in the FControl is on. Else, it will go on to the next step.



8. DMA loads the DMA block length counter with the block length field (BLen) in the BControl.

9. When PU is ready, it raises DREQW. DMA will transfer data from the memory to PU’s TX FIFO until the block length counter expired, then go to the next step.

10.DMA examines the last block (BLast) field of the Bcontrol. If it is not set, DMA fetches the next buffer descriptor and goes to Step 7. If it is set, DMA will notify PU with WLAST and go on to the next step.

11. DMA waits until the PU finishes transmission of the current frame as indicated by the PU’s status ready (TXSRDY.)

12. DMA obtains the status of the frame from the TXSOUT and writes it to the FStatus of the current frame descriptor in the memory. The frame done (FDone) field of the FStatus will be set to mark the frame as done and transmitted. (FDONE should always be initialized to 0 when the ARM builds the data structures in the memory.)

13. DMA interrupts ARM, if the interrupt enable (IRQEn) field in the FControl is set.

14. DMA moves its NEXT pointer register to its HEAD pointer register then goes to Step 4.

M821xx Data Sheet


38.3.3.1.2 RX DMA Operation Sequence (Inbound)





5. DMA examines the frame ready (FReady) field in the FControl, if not set, DMA will stop, reset the START bit, and interrupt the ARM if the IRQEN bit in the FControl is on. Else, it will go on to the next step.



8. DMA waits for RXSREQ signal from PU to obtain the package count in bytes from bits RXSOUT[8:0]. If RXSOUT[9] = 0, it transfers RXSOUT[8:0] number of bytes from PU’s RX FIFO to the memory location pointed by Bpointer. DMA stays at this current step until RXSOUT[9] = 1 which indicates the end of transfer then goes to Step 11.

9. DMA waits for RXSREQ signal from PU to obtain the package count in bytes from bits RXSOUT[8:0].

10. If RXSOUT[9] = 0, DMA attempts to fill the allocated memory block length as indicated by Blen. If more bytes are needed, it goes to Step 9. If the block is full, it fetches the next buffer descriptor for another memory location and size. If BLast is True, BLen is assumed to be infinite. DMA stays at this current step until RXSOUT[9] = 1 which indicates the end of transfer.

11. DMA writes the packet size to the BControl field of the current buffer descriptor in the memory.

12. DMA writes the status RXSOUT[15:0] to the Fstatus of the current frame descriptor in the memory. The frame done (FDone) field of the FStatus will be set to mark the frame as done and received. This field is initialized to 0 when the ARM builds the data structures in the memory.

13. DMA interrupts ARM, if the interrupt enable (IRQEn) filed in the FControl pointer of the current frame is set.

14. DMA moves its NEXT pointer register to its HEAD pointer register then goes to Step 4.

38.3.3.2 I/O DMA — POS/UTOPIA Data Structures

38.3.3.2.1 Next Field Bit Description

Offset: x0

NOTE: Each allocated memory block is limited to 64K-1 bytes. If not, overflow will happen. No recovery logic.

Table 38-9 Next Field Bit Data Structure Description

BIT No. Name Description31 – 3 NEXT Pointer of the next Frame Descriptor.


M821xx Data Sheet


38.3.3.2.2 System Field Bit Description.

Offset: x4

38.3.3.2.3 Frame Status Field Bit Description

Offset: x8S

38.3.3.2.4 Frame Control Field Bit Description (Both Directions)

Offset: xC

Table 38-10 System Field Bit Data Structure Description

BIT No. Name Description31 – 0 CORRESPVAL VPI/VCI value in case of a match, zero in case of no match and unchanged

otherwise.

Table 38-11 PU to Memory Frame Status Field Bit Data Structure Description



20 – 18 PT PT bits from the ATM cell header

17 CLP CLP bit from the ATM cell header

16 Not used. Read as Hex 0.

15 – 13 Status Calendar Num

12 Status Frame Error

11 Status Abort Error

10 Status Parity Error

9 Status End of Frame

8 – 0 Not used. Value varies.

Table 38-12 Frame Control Field Bit Data Structure Description


6 – 4 ID Channel ID. Max 8 channels. Not used in Rx direction

3 SCATTER If set, scatter inbound receiving data to different memory locations. This bit is ignored on the outbound.

2 IRQEN Interrupts the ARM when DMA finishes transferring a frame or when a frame descriptor is not ready (FREADY = 0). Also see FLAST, FREADY, and BLAST.

1 FLAST Last frame. DMA stops after executing this frame and interrupts if the IRQEN bit is on. ARM needs to set the START bit in the APB register to restart.

0 FREADY Frame ready. If not set, DMA stops as soon as this bit is read and interrupts if IRQ is enable. ARM needs to set the START bit in the APB register to restart.

M821xx Data Sheet


38.3.3.2.5 Buffer Pointer Field Bit Description.


38.3.3.2.6 Buffer Control Field Bit Description.


Table 38-13 Buffer Pointer Field Bit Description

BIT No. Name Description31 – 0 BPOINTER Location of a data buffer.

Table 38-14 Memory to PU Data Structure Description


16 BLAST Last block. No more data buffer. Assert IO_WLAST signal to I/O; Go to the next frame descriptor if FLAST is off, else end operation; IRQ if enabled. BLAST = 1 and BLEN = 0 is an illegal setting.

15 – 0 BLEN Number of bytes to be transferred from memory to I/O. Zero means none.Maximum 64K – 1 bytes. BLAST = 1 and BLEN = 0 is an illegal setting.

Table 38-15 PU to Memory Data Structure Description

BIT No. Name Description31 BDONE Buffer Done. When a frame is finished, IDMA writes a 1 to BDONE of the last BControl.

30 - 17 Not used.

16 BLAST In Scatter mode, Software sets this bit to 1 to indicate the last memory area for scattering. A zero means more memory space at the next BPOINTER. In Non-Scatter mode, BLAST is not used and Software does not need to set it.

•When a frame is finished, IDMA writes a 0 to BLAST of the last BControl.

15 – 0 BLEN In Scatter mode, Software sets BLEN to be the size of the memory block where IDMA will store the receiving data. Maximum 64K – 1 bytes. The sum of all BLENs should be at least 1 word more than the receiving data. In Non-Scatter mode, BLEN is not used and Software does not need to set it.

•When a frame is finished, IDMA writes the number of receiving data bytes to BLEN of the last BControl.

M821xx Data Sheet


38.3.4 VPI/VCI MechanismOn the POS/UTOPIA interface, the IDMA will be able to classify ATM cells. This feature is used only in the receive direction (i.e. I/O to Memory) and up to 8 VPI/VCI values can be configured.

38.3.4.1 VPI/VCI Behavior

Each ATM cell has a 5 bytes header, when the 5th byte is the HEC, which is not used to classify the ATM cell. The 1st 4 bytes holds data in the following format:

Here are the descriptions of each field:

• GFC — generic flow control bits, present only in UNI cells

• VPI - virtual path identifier, NNI uses GFC bits for 12 total bits for VPI

• VCI - virtual circuit identifier

• PT - payload type information

• CLP - cell loss priority

The IDMA will hold an 8 rows by 64 bits of lookup table, the 32 MSBits will hold the possible values of the expected 4 bytes and the 32 LSBits will hold the value that should be written to the system frame descriptor in case of match. For each received cell, the 4 header bytes will be masked with a configurable mask register and compared with all possible configured 4 bytes values and if a match is found, the 32 LSBits of that entry will be written to the system frame descriptor, if a match is not found, then zeroes will be written to the system frame descriptor.

The PT and CLP bits will always be written to the frame status descriptor bits [20:17], regardless of match found or mechanism disable, however when the mechanism is disabled, the written value is unknown.

An enable/disable configuration per table entry is available in order to be able to disable an entry in order to configure new values to it, while the mechanism keeps working comparing to the other enabled entries. Disabling all entries will disable the mechanism (for POS mode for example). When disabled (before the last data), no compare will be done and the System Frame descriptor will remain unchanged in the memory, otherwise zeroes will be written.

Figure 38-3 shows the flow of the process:

Table 38-16 VPI / VCI Fields

Description GFC/VPI VPI VCI PT CLP

bit length 4 8 16 3 1

NOTE: GFC is currently unused in ATM networks, and set to 0000 default value.

M821xx Data Sheet


Figure 38-3 VPI/VCI Comparison Process

GFP/VPI

0000 0101

VPI

XXXX 0000 0000 0010 0001

VCI PT

XXX

CLP

X

1111 11110000 1111 1111 1111 1111 000 0

0000 01010000 0000 0000 0010 0001 000 0

LOOKUP TABLE

VPI/VCI VALUE

0000 0000 0111 0001 0001 1111 1111 0000

0000 0001 0101 0001 0001 1111 1101 0000

0000 0000 0101 0000 0001 1111 1111 0000

0000 0000 0111 0001 0001 1111 1111 0000

0000 0000 0000 0000 0000 0000 0000 0000

0000 0000 0101 0000 0000 0010 0001 0000

0000 0000 0000 0000 0000 0000 0000 0000

0000 0000 0000 0000 0000 0000 0000 0000

Corresponding 32 Bits Handle

0x15255856

0x15257786

0x15254444

0x15255856

0x00000000

0x12345678

0x00000000

0x00000000

Received Data(1st 4 bytes)

Programmable Mask

Value To Compare

Value To Be Written In FSystem

AND

Matching Value

M821xx Data Sheet


38.3.4.2 VPI/VCI Limitations

To ensure proper function, the following limitations should be met:

1. The configuration of any value in the lookup table will be done when the equivalent entry in the table is disabled.

2. If an entry is not used, one should configure the corresponding entry to disable.

3. In order for the mechanism to work properly, each cell must be stored in a separate frame in the memory.

4. No more than 1 enabled LUT entry can hold the same VPI/VCI value for proper mechanism work.

.


39.0 I/O DMA Registers

39.1 IntroductionFollowing are the register map and description of each register. Unless noted, all registers are cleared to ‘0’ upon system reset. Addressing a reserved address will return 0xBADDBADD.

The soft reset register is a synchronic reset, which resets the registers on rising edge of HCLK.

39.2 I/O DMA Register MapThe APB base address is: 0x100E 0000.

Table 39-1 I/O DMA Register Map

APB AddressOffset

Register Description

0000 HDMA Soft Reset

000C HI Rx (MMHI) DMA Enable

0010 HI Tx (HIMM) DMA Enable

0040 HI Rx Base Memory Address

0044 HI Tx Base Memory Address

0048 HI Rx Block size

004C HI Tx Block size

0050 HI Tx and Rx Locked Transfer Size

0060 Priority Assignment

0064 Priority Assignment

006C NSEQ drive enable

0070 HMDMA Soft Reset (write only)

0074 HMDMA Locked Transfer Size

0080 1st VPI/VCI Value

0084 1st Corresponding Value

0088 2nd VPI/VCI Value

008C 2nd Corresponding Value

M821xx Data Sheet


0090 3rd VPI/VCI Value

0094 3rd Corresponding Value

0098 4th VPI/VCI Value

009C 4th Corresponding Value

00A0 5th VPI/VCI Value

00A4 5th Corresponding Value

00A8 6th VPI/VCI Value

00AC 6th Corresponding Value

00B0 7nt VPI/VCI Value

00B4 7th Corresponding Value

00B8 8th VPI/VCI Value

00BC 8th Corresponding Value

00C0 Programmable Mask

00C4 VPI/VCI Enable

0100 Mem to G EMAC0: Start

0104 Mem to G EMAC0: Head Pointer

0108 Mem to G EMAC0: Locked Transfer Size

0110 Mem to G EMAC0: IDMA Control

0114 Mem to G EMAC0: IRQ Status (read transaction)Mem to G EMAC0: IRQ Clear (write transaction)

0120 Mem to G EMAC0: Soft Reset (write only)

0180 G EMAC0 to Mem: Start

0184 G EMAC0 to Mem: Head Pointer

0188 G EMAC0 to Mem: Locked Transfer Size

0190 G EMAC0 to Mem: IDMA Control

0194 G EMAC0 to Mem: IRQ Status (read transaction)G EMAC0 to Mem: IRQ Clear (write transaction)

01A0 G EMAC0 to Mem: Soft Reset (write only)

0200 Mem to PU: Start

0204 Mem to PU: Head Pointer

0208 Mem to PU: Locked Transfer Size

Table 39-1 I/O DMA Register Map (Continued)

APB AddressOffset


M821xx Data Sheet


0210 Mem to PU: IDMA Control

0214 Mem to PU: IRQ Status (read transaction)Mem to PU: IRQ Clear (write transaction)

0220 Mem to PU: Soft Reset (write only)

0280 PU to Mem: Start

0284 PU to Mem: Head Pointer

0288 PU to Mem: Locked Transfer Size

0290 PU to Mem: IDMA Control

0294 PU to Mem: IRQ Status (read transaction)PU to Mem: IRQ Clear (write transaction)

02A0 PU to Mem: Soft Reset (write only)

0300 Mem to G EMAC1: Start

0304 Mem to G EMAC1: Head Pointer

0308 Mem to G EMAC1: Locked Transfer Size

0310 Mem to G EMAC1: IDMA Control

0314 Mem to G EMAC1: IRQ Status (read transaction)Mem to G EMAC1: IRQ Clear (write transaction)

0320 Mem to G EMAC1: Soft Reset (write only)

0380 G EMAC1 to Mem: Start

0384 G EMAC1 to Mem: Head Pointer

0388 G EMAC1 to Mem: Locked Transfer Size

0390 G EMAC1 to Mem: IDMA Control

0394 G EMAC1 to Mem: IRQ Status (read transaction)G EMAC1 to Mem: IRQ Clear (write transaction)

03A0 G EMAC1 to Mem: Soft Reset (write only)

03A4-03FF Reserved

Table 39-1 I/O DMA Register Map (Continued)

APB AddressOffset


M821xx Data Sheet


39.3 HDMA Registers

39.3.1 HDMA Soft ResetOffset 0000

39.3.2 Transmit DMA EnableOffset 000C

39.3.3 Receive DMA EnableOffset 0010

Table 39-2 HDMA Soft Reset Register


31 – 1 Reserved

0 SRESET Soft Reset. Write only. Active high. Self cleared. This bit resets HIRXDMAEN and HITXDMAEN.

Table 39-3 Transmit DMA Enable Register


31 – 1 Reserved

0 HITXDMAEN HI Tx DMA Enable. This bit is reset when HITXBLSZ becomes 0 after a DMA transfer.

Table 39-4 Receive DMA Enable Register


31 – 1 Reserved

0 HIRXDMAEN HI Rx DMA Enable. This bit is reset when HIRXBLSZ becomes 0 after a DMA transfer..

M821xx Data Sheet


39.3.4 Transmit Base Address RegisterOffset 0040

39.3.5 Receive Base Address Register Offset 0044

39.3.6 Tx Block SizeOffset 0048

39.3.7 Rx Block SizeOffset 004C

Table 39-5 Transmit Base Address Register


31 – 0 HITXBAS Memory Address for HI Transmit Buffer in the core memory. Byte aligned.

Table 39-6 Receive Base Address Register


31 – 0 HIRXBAS Memory Address for HI Receive Buffer in the core memory. Byte aligned.

Table 39-7 Tx Block Size Register


31 – 16 Not used

15 – 0 HITXBLSZ HI Tx Block Size: Number of bytes -1. Maximum 64K bytes. When this register is counted down to zero, the DMA enable is turned off.

Table 39-8 Rx Block Size Register


31 – 16

15 – 0 HIRXBLSZ HI Rx Block Size: Number of bytes -1. Maximum 64K bytes. When this register is counted down to zero, the DMA enable is turned off.

M821xx Data Sheet


39.3.8 Locked Transfer SizeOffset 0050

39.4 Priority

39.4.1 Priority assignment 1Offset 0060

39.4.2 Priority assignment 2Offset 0064

Table 39-9 Locked Transfer Size Register


31 – 16 Not used

15 – 8 HIRXLOKZ HI Rx Locked Transfer Size. Number of data transfers in an indivisible transfer. Max 255.

7 – 0 HITXLOKZ HI Tx Locked Transfer Size. Number of data transfers in an indivisible transfer. Max 255.

Table 39-10 Priority Assignment Register 1


31 – 28 PRTY7 Programmed with a Master number. Default is 4: HI to MEM

27 – 24 PRTY6 Programmed with a Master number. Default is 3: MEM to PU

23 – 20 PRTY5 Programmed with a Master number. Default is 2: PU to MEM

19 – 16 PRTY4 Programmed with a Master number. Default is 8: Host Mem Bridge

15 – 12 PRTY3 Programmed with a Master number. Default is 7: MEM to G EMAC1

11 – 8 PRTY2 Programmed with a Master number. Default is 1: MEM to G EMAC0

7 – 4 PRTY1 Programmed with a Master number. Default is 6: G EMAC1 to MEM

3 – 0 PRTY0 Programmed with a Master number. Default is 0: G EMAC0 to MEM

Table 39-11 Priority Assignment Register 2


31 – 4 Not Used

3 – 0 PRTY8 Programmed with a Master number. Default is 5: MEM to HI

M821xx Data Sheet


39.4.3 NSEQ Drive EnableOffset 006C

39.5 HMDMA Registers

39.5.1 Host Mem Bridge: Soft Reset (write only)Offset 0070

39.5.2 Host Mem Bridge Locked Transfer Size.Offset 0074

Table 39-12 NSEQ Drive Enable


31 – 2 Not Used

1 CROSS_1K Enable driving NSEQ transfer when crossing 1K boundary

0 1ST_TRANS Enable driving NSEQ transfer on the 1st transaction after request assertion

Table 39-13 Host Mem Bridge: Soft Reset Register


31 – 1 Reserved

0 SRESET Soft Reset. Write only. Active high. Self cleared.

Table 39-14 Host Mem Bridge Locked Transfer Size


31 – 16 Not used

15 – 8 Reserved

7 – 0 LOCKSZ Locked Transfer Size. Number of data transfers in an indivisible transfer. Max 255.

M821xx Data Sheet


39.6 VPI/VCI Registers

39.6.1 1st VPI/VCI Value: Offset 0080

39.6.2 1st Corresponding Value: Offset 0084

39.6.3 2nd VPI/VCI Value: Offset 0088

39.6.4 2nd Corresponding Value:Offset 008C

Table 39-15 VPI/VCI Registers


31 – 0 VPIVCIVAL1

1st configured VPI/VCI value.

Table 39-16 1st Corresponding Value Register


31 – 0 CORRESP1 1st Corresponding value to be written to System Frame descriptor.

Table 39-17 2nd VPI/VCI Value


31 – 0 VPIVCIVAL2

2nd configured VPI/VCI value.

Table 39-18 2nd Corresponding Value


31 – 0 CORRESP2 2nd Corresponding value to be written to System Frame descriptor.

M821xx Data Sheet


39.6.5 3rd VPI/VCI Value: Offset 0090

3rd Corresponding Value: Offset 0094

4th VPI/VCI Value: Offset 0098

39.6.6 4th Corresponding Value: Offset 009C

Table 39-19 3rd VPI/VCI Value


31 – 0 VPIVCIVAL3

3rd configured VPI/VCI value.

Table 39-20 3rd Corresponding Value


31 – 0 CORRESP3 3rd Corresponding value to be written to System Frame descriptor.

Table 39-21 4th VPI/VCI Value


31 – 0 VPIVCIVAL4

4th configured VPI/VCI value.

Table 39-22 4th Corresponding Value


31 – 0 CORRESP4 4th Corresponding value to be written to System Frame descriptor.

M821xx Data Sheet


39.6.7 5th VPI/VCI Value: Offset 00A0

39.6.8 5th Corresponding Value: Offset 00A4

39.6.9 6th VPI/VCI Value:Offset 00A8

39.6.10 6th Corresponding Value:Offset 00AC



31 – 0 VPIVCIVAL5







31 – 0 VPIVCIVAL6





M821xx Data Sheet


39.6.11 7th VPI/VCI Value: Offset 00B0

39.6.12 7th Corresponding Value: Offset 00B4

39.6.13 8th VPI/VCI Value: Offset 00B8

39.6.14 8th Corresponding Value: Offset 00BC



31 – 0 VPIVCIVAL7







31 – 0 VPIVCIVAL8





M821xx Data Sheet


39.6.15 Programmable Mask: Offset 00C0

39.6.16 VPI/VCI Enable: Offset 00C4

Table 39-31 Programmable Mask


31 – 0 MASK Programmable mask, used to mask any number of bits in the received ATM cell header bytes.

Table 39-32 VPI/VCI Enable


31 – 1 Reserved.

7 VPIVCIEN7 VPI/VCI enable for entry 7. When set, The 1st 4 bytes of a cell (header) are compared against this entry value. When reset, no compare is done.








M821xx Data Sheet


39.7 GEMAC0 Registers

39.7.1 Mem to GEMAC0 StartOffset 0100

39.7.2 Mem to GEMAC0: Head PointerOffset 0104

39.7.3 Mem to GEMAC0: Locked Transfer SizeOffset 0108

Table 39-33 Mem to GEMAC0 Start


31 – 1 Reserved

0 START Mem to GMAC Start. This bit is reset when FREADY is 0 or when FLAST is 1 and End of Frame

Table 39-34 Mem to GEMAC0: Head Pointer


31 – 3 HEAD Location of a frame descriptor


Table 39-35 Mem to GEMAC0: Locked Transfer Size


31 – 8 Not used


M821xx Data Sheet


39.7.4 Mem to GEMAC0: IDMA Control RegisterOffset 0110

These controls apply to all frames regardless of the IRQEN bit in any Frame Control Descriptor.

39.7.5 Mem to GEMAC0: IRQ Status Register (read transaction)Offset 0114.

Table 39-36 Mem to GEMAC0: IDMA Control Register


31 – 9 Not Used

8 STOPDONE When a frame is started but the FDONE bit in the Frame Status Descriptor is on, IDMA will stop and reset the START bit (see APB registers).

7 – 3 Reserved. Must be 0.

2 IRQDONEN DONE Interrupt Enable: IDMA will assert a level interrupt when a frame is started but the FDONE bit in the Frame Status Descriptor is on. Before setting this bit, please reset IRQFCTRL to 0 (see IRQ Clear Register.)

1 IRQFLSTEN FLAST Interrupt Enable: IDMA sets a level interrupt when it finishes a frame and the FLAST bit in the Frame Control Descriptor is on (i.e. last frame.) Before setting this bit, please reset IRQFCTRL to 0 (see IRQ Clear Register.)

0 IRQFRDYEN FREADY Interrupt Enable: IDMA sets a level interrupt when a frame is started but the FREADY bit in the Frame Control Descriptor is off. Before setting this bit, please reset IRQFCTRL to 0 (see IRQ Clear Register.)

Table 39-37 Mem to GEMAC0: IRQ Status Register (read transaction)


31 – 9 Not Used

8 STOPDONE Read only bit. This is a copy of the STOPDONE bit in the IDMA Control Register.

7 – 4 Reserved.

3 IRQFCTRL Frame Control IRQ. This bit is set to 1 when the IRQEN bit in the Frame Control Descriptor is on and either when a frame is completed or when a frame is started but the FREADY bit in the Frame Control Descriptor is off.

2 IRQDONE DONE IRQ: This bit is set to 1 when IRQDONEN is on and when a frame is started but the FDONE bit in the Frame Status Descriptor is on.

1 IRQFLST FLAST IRQ. This bit is set to 1 when IRQFLSTEN is on and the last frame has been completed.

0 IRQFRDYN Not-FREADY IRQ. This bit is set to 1 when IRQFRDYEN is on and when a frame is started but the FREADY bit in the Frame Control Descriptor is off.

M821xx Data Sheet


39.7.6 Mem to GEMAC0: IRQ Clear Register (write transaction)Offset 0114 .

39.7.7 Mem to GEMAC0: Soft Reset (write only)Offset: 0120

39.7.8 GEMAC0 to Mem: Start Offset: 0180

Table 39-38 Mem to GEMAC0: IRQ Clear Register (write transaction)


31 – 4 Reserved

3 IRQFCTRL Frame Control IRQ. Write a 1 to set this bit to 0 (clear.) Normally, this bit does not need to be cleared because IRQEN causes a pulse interrupt. However, if IRQDONEN, IRQFLSTEN, or IRQFRDYEN is on, this bit must be set to 0 to clear the interrupt.

2 IRQDONE DONE IRQ: Write a 1 to set this bit to 0 (clear.) This bit must be set to 0 to clear the interrupt.

1 IRQFLST FLAST IRQ. Write a 1 to set this bit to 0 (clear.) This bit must be set to 0 to clear the interrupt.

0 IRQFRDYN Not-FREADY IRQ. Write a 1 to set this bit to 0 (clear.) This bit must be set to 0 to clear the interrupt.

Table 39-39 Mem to GEMAC0: Soft Reset (write only)


31 – 1 Reserved

0 SRESET Soft Reset. Write only. Active high. Self cleared. This bit resets START and DMA.

Table 39-40 GEMAC to Mem: Start


31 – 1 Reserved

0 START GMAC to Mem Start. This bit is reset when FREADY is 0 or when FLAST is 1 and End of Frame

M821xx Data Sheet


39.7.9 GEMAC0 to Mem: Head PointerOffset: 0184

39.7.10 GEMAC0 to Mem: Locked Transfer SizeOffset: 0188

Table 39-41 GEMAC0 to Mem: Head Pointer




Table 39-42 GEMAC to Mem; Locked Transfer Size


31 – 8 Not used


M821xx Data Sheet


39.7.11 GEMAC0 to Mem: IDMA ControlOffset 0190.

39.7.12 GEMAC0 to Mem: IRQ Status Register (read transaction)Offset 0194.

Table 39-43 GEMAC0 to Mem: IDMA Control


31 – 9 Not Used

8 STOPDONE When a frame is started but the FDONE bit in the Frame Status Descriptor is on, IDMA will stop and reset the START bit (see APB registers).

7 – 3 Reserved. Must be 0.

2 IRQDONEN DONE Interrupt Enable: IDMA will assert a level interrupt when a frame is started but the FDONE bit in the Frame Status Descriptor is on. Before setting this bit, please reset IRQFCTRL to 0 (see IRQ Clear Register.)

1 IRQFLSTEN FLAST Interrupt Enable: IDMA sets a level interrupt when it finishes a frame and the FLAST bit in the Frame Control Descriptor is on (i.e. last frame.) Before setting this bit, please reset IRQFCTRL to 0 (see IRQ Clear Register.)

0 IRQFRDYEN FREADY Interrupt Enable: IDMA sets a level interrupt when a frame is started but the FREADY bit in the Frame Control Descriptor is off. Before setting this bit, please reset IRQFCTRL to 0 (see IRQ Clear Register.)

Table 39-44 GEMAC0 to Mem: IRQ Status Register (read transaction)


31 – 9 Not Used

8 STOPDONE Read only bit. This is a copy of the STOPDONE bit in the IDMA Control Register.

7 – 4 Reserved.

3 IRQFCTRL Frame Control IRQ. This bit is set to 1 when the IRQEN bit in the Frame Control Descriptor is on and either when a frame is completed or when a frame is started but the FREADY bit in the Frame Control Descriptor is off.

2 IRQDONE DONE IRQ: This bit is set to 1 when IRQDONEN is on and when a frame is started but the FDONE bit in the Frame Status Descriptor is on.

1 IRQFLST FLAST IRQ. This bit is set to 1 when IRQFLSTEN is on and the last frame has been completed.

0 IRQFRDYN Not-FREADY IRQ. This bit is set to 1 when IRQFRDYEN is on and when a frame is started but the FREADY bit in the Frame Control Descriptor is off.

M821xx Data Sheet


39.7.13 GEMAC0 to Mem: IRQ Clear (write transaction)Offset 0194 .

39.7.14 GEMAC0 to Mem: Soft Reset (write only)Offset 01A0

39.8 PU RegistersOffset 02nn. The definitions of these registers are the same as of the GEMAC0 registers. See “GMAC Overview” on page 190.

39.9 GMAC1 RegistersOffset 03nn. The definitions of these registers are the same as of the GEMAC0 registers. See “GMAC Overview” on page 190.

Table 39-45 GEMAC0 to Mem: IRQ Clear (write transaction)


31 – 4 Reserved

3 IRQFCTRL Frame Control IRQ. Write a 1 to set this bit to 0 (clear.) Normally, this bit does not need to be cleared because IRQEN causes a pulse interrupt. However, if IRQDONEN, IRQFLSTEN, or IRQFRDYEN is on, this bit must be set to 0 to clear the interrupt.

2 IRQDONE DONE IRQ: Write a 1 to set this bit to 0 (clear.) This bit must be set to 0 to clear the interrupt.

1 IRQFLST FLAST IRQ. Write a 1 to set this bit to 0 (clear.) This bit must be set to 0 to clear the interrupt.

0 IRQFRDYN Not-FREADY IRQ. Write a 1 to set this bit to 0 (clear.) This bit must be set to 0 to clear the interrupt.

Table 39-46 GEMAC to Mem: Soft Reset (write only)


31 – 1 Reserved


.


40.0 Memory DMA Controller

40.1 IntroductionThe Memory DMA controller (MDMA), assures low-latency transfers of data from one AHB slave to another or for CRC calculation on a data block. The option to move data from one AHB slave to another or to another place in the same AHB slave, can be used for scattering and gathering of data.

For a view of the AHB-APB Bridge within the top-level block diagram, see Figure 2-1.

For details on MDMA registers, see Section 41.0 Memory DMA Registers.

40.2 Features• Provides an option for CRC calculation on data moved from the Memory to the MDMA using internal FIFO.

Supports 32 or 16 bits CRC

• Supports data management using a 2 dimensional chained list. A chained list of frames and each frame can have a chained list of data buffers.

• Configurable support for driving NSEQ transactions when crossing the 1K boundary.

40.3 Functional DescriptionThe Memory DMA controller block transfers data from / to memory to / from memory.

Figure 40-1 shows the MDMA internal block diagram, when the Rx is defined as the data flow from FIFO to Memory and Tx is defined as the opposite..

Each IODSTRUC has 2 requests, one to do a read transaction and one to do a write transaction on the AHB.

The MDMAIO, which receives the read requests gives a higher priority to a read request from the Rx side, the reason for that is because the Rx side mostly does writes and not reads so when he needs the bus to read he will interrupt the Tx side reads to do his.

The MDMAIO, which receives the write request does the opposite and gives the higher priority to a write request from the Tx side for the same reason as before.

For a successful operation a read and write transactions should be done together.

Because the read and the write are both masters on the AHB, it is possible for them to work in parallel in case the read target slave and the write target slave are different slaves. The MDMA sub-block will request the write IODSTRUC to write data to the FIFO when it has less than 92 bytes (not configurable) of data in the FIFO. Once the number of bytes in the FIFO crosses the 64 bytes (not configurable), the MDMA sub-block will request the read

M821xx Data Sheet


IODSTRUC to start and read data from the FIFO. The process continues until all data was read and written from/to the Memory. There’s an exception in CRC calculation, please see section CRC Calculation.

Figure 40-1 Memory DMA Block Diagram

This sub-block holds an internal FIFO (of 128 Bytes), which can be used to do an internal loop from the memory to the FIFO and back to the memory.

40.3.1 CRC CalculationThe MDMA sub-block can generate Cyclic Redundancy Check (CRC) while moving data from memory to FIFO. It supports either 16-bit or 32-bit CRC signatures.

The two CRC polynomial algorithms are shown below.

• CRC-32 : X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1

• CRC-CCITT : X16+X12+X5+1

The CRC can be initialized with either all 1's or all 0's. Also the CRC can be initialized to any other initial value for debug or continuing partial CRCs.

Input data bytes can be in 0-7 or 7-0 format. The input data is assumed to be in little endian format.

Output CRC can be read in 0-7, 7-0 format. You can also read the CRC in big-endian and/or inverted format. Hence, the engine can be used to compute the AAL5 FCS without any post-processing.

The above features can be programmed in the Frame Control field of the Frame descriptors.

When calculating the CRC, there’s an option to configure in the frame control descriptor, whether we want to write the data back to the Memory or toss it. In case a toss is configured, the data will not be written to the FIFO and

Gen

eral

(clo

cks,

res

ets,

&

c.)

MDMACORE

MDMAIO (Write

Arbiter)AHM

AHBBUS

IODSTRUCRx (Write)

Tx (Read)

APBBUS

MDMAIO (Read

Arbiter)AHM IODSTRUC

MDMA

FIFORead Req

Read Req

Write Req

Write Req

M821xx Data Sheet


when the CRC calculation is done only the CRC will be written to the system frame descriptor and an interrupt will be asserted. In case the toss is not enabled, the data will be written to the FIFO and then to the Memory with the CRC written to the system frame descriptor.

40.3.2 Data Scattering And GatheringIn case the ARM processor wants to free a certain area in the memory occupied with data by one of the peripherals, it can use the internal FIFO to read data from the current location and write it back to a new location. This action also requires from the ARM processor to update the data descriptors accordingly.

40.3.2.1 Memory To Memory DMA Operation Sequence

40.3.2.1.1 Read Memory DMA

1. ARM builds the data structure in the memory as shown in the Figures 38-2 on page 573.

2. ARM writes the HEAD pointer into the DMA CURRENT pointer register.

3. ARM sets the DMA START bit in the DMA control register.

4. DMA uses the HEAD pointer to fetch the frame descriptor and stores the NEXT pointer, the FControl and in case of CRC calculation if a configurable initial value is to be used, the DMA set the CRC calculator initial value to the value, which is held in the system frame descriptor.

5. DMA examines the frame ready (FReady) field in the FControl, if not set, DMA will stop, will reset the START bit to zero and will NOT interrupt the ARM. It’s the ARM responsibility to set the START bit again. If the FReady is set, it will go on to the next step.



8. DMA loads the DMA block length counter with value of the block length field (BLen) in the BControl.

9. When the MDMA sub-block is ready, it asserts DREQW. DMA starts transferring data pointed by the Base Address Pointer to the internal FIFO, in case FControl[8] is deasserted (don’t toss data), until the block length counter expires. In case FControl[8] is asserted (toss data, used in CRC mode only), only the CRC is calculated and the data is not written to the FIFO. The MDMA sub-block can stop the data transfer by deasserting the DREQW signal.

10. DMA examines the last block (BLast) field of the BControl, if not set, it will fetch the next BPointer and Bcontrol and goes to step 7. If set, it marks the end of the data patch and go on to the next following step.

11. DMA writes to the FStatus of the current frame descriptor in the memory. The frame done (FDone) field of the FStatus would be set to mark the frame as done and transmitted. This field is initialized to 0 when the ARM builds the data structures in the memory.

12. DMA will NOT interrupt the ARM.

13. If FLAST is deasserted, DMA moves its NEXT pointer register to its CURRENT pointer register and moves to step 4. If FLAST is asserted, START will be reset to zero and we move to step 1.

40.3.2.1.2 Write Memory DMA

1. ARM builds the data structure in the memory as shown in the Figures 38-2 on page 573.

2. ARM writes the HEAD pointer into the DMA CURRENT pointer register.

3. ARM sets the DMA START bit in the DMA control register.

4. DMA uses the HEAD pointer to fetch the frame descriptor and stores the NEXT pointer and the FControl.

M821xx Data Sheet


5. DMA examines the frame ready (FReady) field in the FControl, if not set, DMA stops all operation, will reset the START bit to zero and interrupts ARM if the IRQEN bit in the FControl is on. It’s the ARM responsibility to set the START bit again. If the FReady is set, it will go on to the next step.



8. IODSTRUC sub-block waits for RXSREQ signal from the MDMA sub-block to obtain the package count in bytes from bits RXSOUT[8:0]. If RXSOUT[9] is zero, it starts transferring RXSOUT[8:0] number of bytes from the internal FIFO to the memory pointed by BPointer. DMA stays in this current step until RXSOUT[9] = 1, which indicates the end of the transfer, then goes to step 11. The MDMA sub-block can stop the data transfer by deasserting the RXSREQ signal.

9. DMA waits for RXSREQ signal from the MDMA to obtain the package count in bytes from bits RXSOUT[8:0].

10. If RXSOUT[9] is zero, DMA attempts to fill the allocated memory block length as indicated by BLen. If more bytes are needed’ it goes to step 9. If the block is full, it fetches the next buffer descriptor for another memory location and size. If Blast is set to 1, BLen is assumed to be infinite. DMA stays in this current step until RXSOUT[9] = 1, which indicates the end of the transfer, then it goes to step 11.

11. DMA writes the frame size to the BLen field in the BControl register of the current buffer descriptor in the memory.

12. In case of CRC calculation DMA writes CRC to the Fsystem of the current frame descriptor if instructed by the Fcontrol. It also writes a 1 to the frame done (FDone) field of the Fstatus. This field should have been initialized to 0 when the ARM builds the data structures in the memory.

13. DMA interrupts ARM, if the interrupt enable (IRQEn) filed in the FControl pointer of the current frame is set AND the read sequence is also finished.

14. If FLAST is deasserted, DMA moves its NEXT pointer register to its CURRENT pointer register then goes to step 4. If FLAST is asserted, START will be reset to zero and we move to step 1.

40.3.2.2 Memory To Memory DMA Data Structure

40.3.2.2.1 Frame and Buffer Descriptors - Memory to FIFO (Outbound)

40.3.2.2.1.1 Frame Next

Offset: x0

40.3.2.2.1.2 Frame System (Fsystem)

Offset: x4

Table 40-1. Frame Next Register


31 – 4 NEXT Pointer of the next Frame Descriptor.


Table 40-2. Frame System (Fsystem) Register


M821xx Data Sheet


40.3.2.2.1.3 Frame Status (Fstatus)

Offset: x8

40.3.2.2.1.4 Frame Control (FControl)

Offset: xC

40.3.2.2.1.5 Buffer Pointer

Offset: x10 + 8n, where n is a non-negative number.

31 – 0 CRC_InitVlu Initial CRC value. Valid when CRC_init = 1x.

Table 40-3. Frame Status (Fstatus) Register


31 Fdone Frame done. Set by the hardware.

30 – 0 Not used

Table 40-4. Frame Control (FControl) Register


31 – 9 Not used

8 DMA_Cntl 0 = Transfer data from Mem to FIFO and then from FIFO to Mem.1 = Transfer data from Mem to FIFO only. Discard the data in FIFO.

7 CRC_Type CRC Type: 0 = CCITT (16-bit CRC), 1 = 32-bit CRC

6 – 5 CRC_Init CRC initial value:1x = Value is in the System word (see above). 00 = All 0’s01 = All 1’s

4 CRC_InputFlip Input data bit orientation per byte:0 = Bit 0 is LSB, bit 7 is MSB 1 = Bit 7 is LSB, bit 0 is MSB

3 Not used

2 Not Used

1 FLAST Last frame. DMA stops after executing this frame. ARM needs to set the START bit in the APB register to restart.

0 FREADY Frame ready. If not set, DMA stops as soon as this bit is read. ARM needs to set the START bit in the APB register to restart.

Table 40-5. Buffer Pointer


31 – 0 BPOINTER Location of a data buffer.


M821xx Data Sheet


40.3.2.2.1.6 Buffer Control

Offset: x14 + 8n, where n is a non-number

40.3.2.2.2 Frame and Buffer Descriptors - FIFO to Memory (Inbound)

40.3.2.2.2.1 Frame Next

Offset: x0

40.3.2.2.2.2 Frame System (Fsystem)

Offset: x4

40.3.2.2.2.3 Frame Status (Fstatus)

Offset: x8

Table 40-6. Buffer Control Register


31 – 17 Not used

16 BLAST Last block. No more data buffer. Go to the next frame descriptor if FLAST is off, else end operation. BLAST = 1 and BLEN = 0 is an illegal setting.

15 – 0 BLEN Number of bytes to be transferred from memory to FIFO. Zero means none.Maximum 64K – 1 bytes. BLAST = 1 and BLEN = 0 is an illegal setting.

Table 40-7. Frame Next Register


31 – 4 NEXT Pointer of the next Frame Descriptor.




31 – 0 CRC_Sig CRC signature. If using 16-bit CRC, the upper half-word equals the lower half-word.

Table 40-9. Frame Status (Fstatus) Register


31 Fdone Frame done. Set by the hardware.

30 – 0 Not used

M821xx Data Sheet


40.3.2.2.2.4 Frame Control (FControl)

Offset: xC

40.3.2.2.2.5 Buffer Pointer

Offset: x10 + 8n, where n is a non-negative number

40.3.2.2.2.6 Buffer Control

Offset: x14 + 8n, where n is a non-negative number

Table 40-10.Frame Control (FControl)


31 – 8 Not used

7 CRC_Rpt •0 = Report CRC•1 = No CRC needed

6 CRC_Flip CRC bit orientation per byte:

•0 = Bit 0 is LSB, bit 7 is MSB•1 = Bit 7 is LSB, bit 0 is MSB

5 CRC_Endian CRC Endian Format:

•0 = Little Endian: LSByte is at lowest address of the FStatus word•1 = Big Endian: LSByte is at highest address of the FStatus word

4 CRC_Invert Invert the CRC signature

3 SCATTER If set, scatter inbound receiving data to different memory locations. This bit is ignored on the read side.

2 IRQEN Interrupt the ARM when done. See bit FLAST, FREADY. The memory to FIFO frame must also be finished.

1 FLAST Last frame. DMA stops after executing this frame and interrupts if the IRQEN bit is set. ARM needs to set the START bit in the APB register to restart.

0 FREADY Frame ready. If not set, DMA stops as soon as this bit is read and interrupts if IRQ is enable. ARM needs to set the START bit in the APB register to restart.

Table 40-11.Buffer Pointer


31 – 0 BPOINTER Location of a data buffer.

Table 40-12.Buffer Control


31 – 17 Not Used Read as 1.

16 BLAST Valid only when SCATTER is True. When set, indicates the last memory area on scattering.

15 – 0 BLEN Number of bytes transferred from FIFO to Memory. Maximum 64K – 1 bytes.

.


41.0 Memory DMA Registers

41.1 IntroductionFollowing are the register map and description of each register. Unless noted, all registers are 0 upon system reset. Addressing a reserved address will return BADDBADD on the read data bus.

41.2 MDMA Register MapThe APB base address for accessing the MDMA block is: 0x101E 0000.

Table 41-1 Memory DMA Register Map

APB AddressOffset Register Description

0080 NSEQ drive enable

0100 Mem to FIFO: Start

0104 Mem to FIFO: Head Pointer

0108 Mem to FIFO: Locked Transfer Size

0120 Mem to FIFO: Soft Reset (write only)

0180 FIFO to Mem: Start

0184 FIFO to Mem: Head Pointer

0188 FIFO to Mem: Locked Transfer Size

01A0 FIFO to Mem: Soft Reset (write only)

01A4-01FF Reserved

M821xx Data Sheet


41.3 MDMA Registers

41.3.1 MDMA NSEQ Drive EnableOffset: x80

41.3.2 Mem to FIFO: StartOffset: x100

41.3.3 Mem to FIFO: Head PointerOffset: x104

41.3.4 Mem to FIFO: Locked Transfer SizeOffset: x108

Table 41-2 MDMA NSEQ Drive Enable Register


31 – 2 Not Used

1 CROSS_1K Enable driving NSEQ transfer when crossing 1K boundary

0 1ST_TRANS Enable driving NSEQ transfer on the 1st transaction after request assertion

Table 41-3 Mem to FIFO: Start Register


31 – 1 Reserved

0 START Mem to FIFO Start. This bit is reset when FREADY is 0 or when FLAST is 1 and End of Frame

Table 41-4 Mem to FIFO: Head Pointer




Table 41-5 Mem to FIOF: Locked Transfer Size


31 – 8 Not used

7 – 0 LOCKSZ Locked Transfer Size. Number of cycles in an indivisible transfer. Max 255.

M821xx Data Sheet


41.3.5 Mem to FIFO: Soft Reset (Write Only)Offset: x120

41.3.6 FIFO to Mem: StartOffset: x180

41.3.7 FIFO to Mem: Head PointerOffset: x184

41.3.8 FIFO to Mem: Locked Transfer SizeOffset: x188

Table 41-6 Mem to FIFO: Soft Reset (Write Only)


31 – 8 Not used


Table 41-7 FIFO to Mem: Start


31 – 1 Reserved

0 START FIFO to Mem Start. This bit is reset when FREADY is 0 or when FLAST is 1 and End of Frame

Table 41-8 FIFO to Mem: Head Pointer




Table 41-9 FIFO to Mem: Locked Transfer Size


31 – 8 Not used


M821xx Data Sheet


41.3.9 FIFO to Mem: Soft Reset (write only)Offset :0x1A0Table 41-10 FIFO to Mem: Soft Reset (write only)


31 – 1 Reserved


.


42.0 Hardware Initialization

This section describes the sequence in which operating voltages must be applied and what conditions must be met before device reset. Subsection 21.3 describes the selection of device operating modes.

42.1 Power Supply SequencingTo avoid damage to device ESD structures DC power must be applied in a specific order. This is summarized in Figure 42-1.

VDDO_B and VDDO_C may be configured as +2.5 or +3.3 VDC depending on Ethernet transceivers in use.

The following subsections present power application rules and procedures.

Figure 42-1 S/W Block Diagram

V_diff

Time

V_diff > 0 VDC at all times

T_diff > 0 ms

Volts

+ 3.3 VDC for VDDO_PCI, VDDO_EXP, VDDA_USB

+ 2.5 VDC for VDDO_GMII0 and VDDO_MII1

+ 1.8 VDC for VDDO_DDR2

+ 1.2 VDC for VDD, VDD_PRE,

V_diff

V_diff

T_diff

T_diff

T_diff

+ 1.2 VDC for PLLT_diff

VDDO_GMII0 VDDO_MII1 (when +3.3 V)

(when +2.5 V)

and VDD_USB_P

M821xx Data Sheet


42.1.1 Power Sequencing Rules

Power domains:

• VCORE — VDD (+1.2 V)

• CMOS — VDDO_PCI (+3.3 V)VDDO_EXP (+3.3 V)VDDO_GMII0 (+2.5 or 3.3 V)VDDO_MII1 (+2.5 or 3.3 V)VDD (+1.2 V)

CMOS +3.3 V must be powered on before +2.5 VDC (when used) and both before +1.2 V.

• USB — VDDA_USB0 and VDDA_USB1 (+3.3 V)VDD_USB0_P and VDD_USB1_P (+1.2 V)

USB +3.3 V must be powered up before +1.2V.

• SSTL — VDDO_DDR2 (1.8 V)VDD_PRE (1.2 V)

SSTL +1.8 V must be powered up before +1.2V.

• PLL — VDDO_PLL_0 (+1.2 V)VDDO_PLL_1 (+ 1.2 V)

PLL +1.2 V must be powered up after all CMOS power including VDD (+1.2V).

Note that there are no power-up sequence requirements between the separate power domains: CMOS, SSTL, and USB.

42.1.2 Power Up Procedure

Initialize the power supplies in this sequence:

1. +3.3 V — VDDO_PCI VDDO_EXP VDDO_GMII0 (when +3.3 V)VDDO_MII1 (when +3.3 V)VDDA_USB0 and VDDA_USB1

2. +2.5 V — VDDO_GMII0 (when +2.5 V)VDDO_MII1 (when +2.5 V)

NOTE: Designers must consider the ramp rates of various power supplies and board-level parasitics to ensure this power-up sequence is met. Try to slow the ramp rate or introduce sufficient delay to meet these requirements.

M821xx Data Sheet


3. +1.8 V — VDDO_DDR2

4. +1.2 V — VDDVDD_USB0_P and VDD_USB1_PVDD_PRE

5. PLL +1.2 — VDDO_PLL_0 VDDO_PLL_1

42.1.3 Power Down ProcedureThe power down sequence is the reverse of the power up sequence.

42.2 Power Rail Assignments

This subsection describes typical consolidation of power and reference inputs.

• +3.3 V — VDDO_PCI VDDO_EXP VDDO_GMII0 (when +3.3 V)VDDO_MII1 (when +3.3 V)VDDA_USB0 and VDDA_USB1USB1_REFUSB0_REF

• +2.5 V — VDDO_GMII0 (when +2.5 V)VDDO_MII1 (when +2.5 V)

• +1.8 V — VDDO_DDR2

• +1.2 V — VDDVDD_USB0_P and VDD_USB1_PVDD_PRE

• PLL +1.2 — VDDO_PLL_0 VDDO_PLL_1

M821xx Data Sheet


42.3 Reset Specifications

After power up and other pre-requisites are met, the reset input puts the M821xx device into a known state for software initialization.

42.3.1 RESET# TimingPrior to de-assertion of RESET#, the following conditions must be met:

• All DC power inputs must be with their specifications.

• Analog reference voltages and PLL power inputs must be with their specifications.

• REFCLK must be within its specifications.

REFCLK must be within its specificatins (see Section 43.5 Reference Clock) for the M821xx device to perform a valid reset operation.

Figure 42-2 Reset Timing

VDC Inputs Stable

REFCLK Stable

2 ms min.

DC Power

REFCLK

RESET#

M821xx Data Sheet


42.3.2 Latching of Configuration Inputs after RestThere are several I/Os which are latched at reset time and affect various modes of operation for the device. These configuration pins are mux’ed with the lower bits of the Expansion Bus addresses.

During reset, the block does not drive these pins, and they can be set to any configured value via external pull-ups or pull-downs. Note that most of these I/Os have internal pull-up/pull-down resistors, so an external pull is required only if the default value (via the internal pull) is not the desired one.

The following table presents these inputs

Table 42-1 Configuration Inputs

NOTE: To be recognized and latched at reset, these signals must be stable 20 nanoseconds before and after the rising edge of RESET#.

Signal Name Signal Name/Description

TM_MII0_MODE[1:0] WAN and LAN Interface Configuration: Refer to Section 11.4 for details.

TM_MII1_MODE[1:0]

TM_BOOT_OP[1:0] Boot Option Configuration. See Section 42.4.1 Boot Source Options.

TM_GPBT_OP[3:0] General Purpose Boot Option Configuration. Available to application developers.

TM_TDM_CLKSRC_EN TDM Clock Source Enable. Controls if device sources TDM_CK.

HBBSIZE[1:0] Bus Width. Defines external uP Bus width as 8-, 16- or 32-bits.

PCI_HOST# / HBBURSTEN# Enables PCI mode as opposed to peripheral mode, or, when in uP Bus mode, enables burst functionality.

PCIMODE / HBMODE# PCI / Host Bus Mode Select. Determines bus type.

M821xx Data Sheet


42.4 Boot Sequence

42.4.1 Boot Source OptionsThere are two boot options: internal and external.

In the case of external boot, code is executed directly from NOR. The NOR device may be a large one, in which case the full code may be on the NOR device, or it may be a small one, in which case enough code will be on it to setup the NAND interface, copy code from the NAND device to the DDR2 SDRAM, and continue executing directly from DDR2 SDRAM.

In internal boot, a configuration pin selects if a memory device is present on SPI or I2C. Code is executed directly from the Internal Boot ROM (IBR). This code in turn copies code from external memory through the SPI or I2C interfaces in ARAM, and it is then executed directly from the ARAM. This ARAM code operates as a secondary boot loader and goes on to copy code from external sources into the DDR2 SDRAM, and then commence execution from the DDR2 SDRAM.

The two configuration pins TM_BOOT_OP[1:0] define the boot sequence.

Table 42-2 Boot Configuration Lands

42.4.2 Boot ScenariosThe following subsections explore the requirements from software and hardware to achieve proper boot.

42.4.2.1 External Boot

This sequence requires a single-stage boot load process, executing off the NOR flash code, and copying program code from the NOR flash (or from anywhere else) to the DDR.

This sequence is executed if the bootstrap configuration is for an external boot.

1. The low 64kB of memory (0x0000 0000 — 0x0000 FFFF), is mapped to the low 64kB of the Expansion Bus CS0 memory space where an external NOR device is connected. Note that only the lower 64kB of the CS0 memory space is remapped, and not the entire 4MB.

2. The PLL is in bypass, following reset, and therefore the clock frequency of the AHB and of the ARMs is REFCLK (24 MHz).

3. At the de-assertion of RESET#, the hardware continues to hold MSP at reset, while the ACP is brought out of reset. It jumps to address 0x0000 0000, which is mapped to the low address of the external NOR. ACP executes commands directly off the external NOR. The defaults for the Expansion Bus allow it to access even the slowest possible NOR. The hardware automatically uses an external 8- or 16-bit data bus, according to the bootstrap configuration.

TM_BOOT_OP1 TM_BOOT_OPT0 BOOT OUTCOME

0 0 Internal boot, copy code from SPI device.

0 1 Internal boot, copying code from I2C device

1 0 External boot, directly from 8-bit NOR device.

1 1 External boot, directly from 16-bit NOR device.

M821xx Data Sheet


4. The ACP brings the PLLs out of bypass mode. This must be done before the DDR2 SDRAM or the DDR2 SDRAM memory controller configurations are accessed, since the DDR2 SDRAM has minimal frequency requirements (for which 24 MHz is too slow). The entire process is not described here (see clocking document), but it is a twofold process, where in the first step the PLLs are configured for their correct frequency, and the ACP then pends for their lock, and in the second step it disables the PLL bypass for the two PLLs. The second step should be performed for the ARMs’ PLL and then for the AHB’s PLL.

5. The ACP must configure the DDR memory regions in the AHB, then the DDR2 controller. It must then wait for the DDR2’s DLL to lock and its initialization to complete. It may then access the DDR2 SDRAM itself.

6. The ACP must configure any additional interfaces and blocks. It may also take out of reset the internal blocks which are still being held in reset. This could also be done at a later stage as necessary.

7. The ACP may copy program code (from wherever) onto DDR2 SDRAM, at this point.

8. The ACP needs to jump to a location within the DDR memory space (0x80000 0000 — 0xBFFF FFFF). From this point on, the ACP executes commands (from the downloaded program code) directly off the DDR2 SDRAM.

9. The ACP will unmap the low 64kB of memory from the Expansion Bus CS0. This is done in the AHB block. This will cause remapping of the lower 64kB to DDR memory space addresses (0x0000 0000 — 0x0000 FFFF.

10. The ACP needs to remap its exception vector table. It may set it to use the high memory region, or it may use the memory management unit to point it anywhere else. Only following this, may ACP interrupts be enabled. Interrupt support during the boot sequence up to this point is not available.

11. The ACP needs to set up an initial jump point for the MSP by writing to address 0x0000 0000 (which is now mapped to DDR2 SDRAM as a remapped version of address 0x8000 0000).

12. The ACP needs to bring the MSP out of reset by writing to a configuration register, thus causing it to start executing code as specified in 0x0000 000.

13. In case the ARMs’ functionality/responsibility is swapped and the MSP acts as the master processor (besides the initialization described above) then after the MSP completes its initialization, the MSP needs to remap its exception vector table (to use the high memory region or elsewhere through the memory management unit) and address 0x0000 0000 needs to be set up as an initial jump point for the ACP.

M821xx Data Sheet


42.4.2.2 Internal Boot

This sequence requires a two-stage boot load process. In the first stage, executing off the IBR code, and copying the second-stage program code from the I2C / SPI EEPROM to internal ARAM. In the second stage, executing off ARAM code, and copying the program code from the expansion bus NAND flash (or from anywhere else) to the DDR2 SDRAM. The reason two stages are required in this sequence is because the DDR2 SDRAM setup (and the preceding PLL setup) should not be hard-coded in the IBR.

This sequence is executed if the bootstrap configuration is for an internal boot.

1. Initially, the low 64KB of memory (0x0000 0000 — 0x0000 FFFF) is mapped to the low 64kB of the IBR’s memory space (0x1100 0000 — 0x1100 FFFF), where the internal hard-coded boot ROM is located.

2. The PLL s in bypass, following reset, and therefore the clock frequency of the AHB and of the ARMs is REFCLK (24 MHz).

3. At de-assertion of RESET#, the hardware continues to hold the MSP at reset, while the ACP is brought out of reset. It jumps to address 0x0000 0000, which is mapped to the low address of the IBR. ACP executes commands directly from the IBR.

4. The ACP must read a status register in the GPIO block indicating the location (i.e. I2C or SPI) of the first-stage boot load program code. It must also read an additional status to check for test mode. In case of test mode, a different boot sequence is commenced. The test mode boot sequence is defined elsewhere (see testing document).

5. The ACP must set up the appropriate interface (i.e. I2C or SPI) for read transactions from the external EPROM.

6. The ACP may copy second-stage boot load program code (from I2C or SPI EPROM) into the ARAM at this point. It must not access the DDR2 SDRAM or the memory controller at this point.

7. The ACP needs to jump to a location within the actual ARAM memory space (0x0A00 0000 — 0x0A00 FFFF). From this point on, the ACP executes commands (from the downloaded second-stage boot load program codes) directly from the ARAM.

8. The following steps are the same as steps 4 through 12 of the external boot sequence.

.


43.0 Electrical and Environmental Specifications

43.1 Operating Conditions

NOTE: The specifications in the following tables are based on estimates and simulations. Updates based on characterized data from silicon measurements will be provided later.

Table 43-1 Voltage Requirments

Parameter Symbols Min. Typ. Max. Units

Digital

Core Supply Voltage (1.2V ± 5%) VDDVDD_PRE

1.14 1.20 1.26 VDC

External Memory Interface Supply Voltage (1.8V ± 5%) VDDO_DDR2 1.71 1.80 1.89 VDC

Ethernet Interface Supply Voltage (2.5V ± 5%) VDDO_GMII0, VDDO_MII1

2.375 2.50 2.625 VDC

I/O and Alternate Ethernet Interface Supply Voltage (3.3V ± 5%) VDDO_PCIVDDO_EXPVDDO_GMII0VDDO_MII1

3.14 3.30 3.47 VDC

Analog

3.3 V analog supply for USB 2.0 Interface VDDA_USB_0VDDA_USB_1

3 3.3 3.6 V

1.2 V analog supply for USB 2.0 Interface VDD_USB0_PVDD_USB1_P

1.14 1.2 1.26 V

Reference

SSTL2 Reference Voltage VDD_REF 0.85 0.9 0.95 V

PLL Reference Voltage VDD_PLL_0VDD_PLL_1

1.14 1.2 1.25 V

Table 43-2 Temperature Conditions


Operating Temperature — M82152, M82154, M82170, M82172, M82174, M82190, M82192, M82194

TA 0 — 70 °C

Operating Temperature — M82104 , M82108 (voice-only devices)

TA -40 — 85 °C

M821xx Data Sheet


43.2 Absolute Maximum RatingsAbsolute Maximum Ratings specify conditions under which there will be no device damage, but device operation is not guaranteed.

Table 43-3 Absolute Maximum Ratings

Parameter Symbol Limits Units

Core Supply Voltage (+1.2V) VDDVDD_PRE

-0.4 to +1.4 V

External Memory Interface Supply Voltage (+1.8V) VDDO_DDR2 -0.5 to +4.6 V

External Interface Supply Voltage (+2.5V) VDDO_GMII01 VDDO_MII11

-0.5 to +3.0 V

I/O and Alternate Ethernet Interface Supply Voltage (3.3V) VDDO_PCIVDDO_EXPVDDO_GMII02

VDDO_MII12

-0.5 to +4.0 V

Input Voltage VIN -0.5 to (VDD + 0.5) V

Storage Temperature TSTG -65 to +110 °C

Voltage Applied to Outputs in High Impedance (Off) State VHZ -0.5 to (VDD + 0.5) V

DC Input Clamp Current IIK ±20 mA

DC Output Clamp Current IOK ±20 mA

Static Discharge Voltage HBM (25°C) VESD ±2000 V

Latch-up Current (85°C) ITRIG ±150 mA

Junction Temperature TJ 125 °C

Notes:1. These VDDO_GMII0 and VDDO_MII1 must be connected to +2.5V when +2.5V Ethernet transceivers are used.2. VDDO_GMII0 and VDDO_MII1 must be connected to +3.3V for +3.3V Ethernet transceivers

M821xx Data Sheet


43.3 Power ConsumptionTable 43-4 Power Consumption


Power Consumption: Voice Only (M82104 and M82108)

Core Supply Power (1.2V, operating) PCORE – ~1.22, 4 ~2.03. 4 W

External Memory Interface Supply (1.8V, operating) PMEM – ~0.122, 4 ~0.143, 4 W

I/O Supply Power (VDDO_A,VDDO_B1, and VDDO_C

1 operating) PDDO_A,B,C – ~0.182, 4 ~0.263, 4 W

Total Power Consumption (operating) Pt – ~1.52, 4 ~2.43,4 W

Power Consumption: Voice + Data (M82152, M82154, M82170, M82172, M82174, M82190, M82192, M82194)

Core Supply Power (1.2V, operating) PCORE – ~1.92, 4 ~2.83. 4 W

External Memory Interface Supply (1.8V, operating) PMEM – ~0.112, 4 ~0.143,4 W

I/O Supply Power (VDDO_A,VDDO_B1, and VDDO_C

1 operating) PDDO_A,B,C – ~0.192, 4 ~0.263, 4 W

Total Power Consumption (operating) Pt – ~2.22, 4 ~3.23,4 W

Notes: 1. VDDO_B and VDDO_C support separate Ethernet interfaces at either 2.5V or 3.3V. VDDO_A supports non-Ethernet interface logic.2. Estimate of typical power consumption with typical voice gateway software at nominal VDC levels and ambient temperature =

23°C.3. Estimated of maximum power consumption with power test-case software at maximum VDC in ‘Voice-Only’ mode with

ambient temperature of 85°C and in ‘Voice + Data’ mode with ambient temperature of 70°C.4. All estimates of power consumption based on averaging of simulated test cases.

M821xx Data Sheet


43.4 I/O Characteristics

43.4.1 LVCMOS CharacteristicsTable 43-5 LVCMOS Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions1

VDDO_A, VDDO_B, VDDO_C = 3.3VDC

Input Voltage Low VIL -0.3 – 0.8 VDC

Input Voltage High VIH 2.0 – 5.5 VDC

Input Current Low 2 IIL – – -10 µA VIN = 0

Input Current High 2 IIH – – +10 µA VIN = 3.3V

Input Current Low (with internal pull-downs) 2 IIL – – -10 µA VIN = 0

Input Current High (with internal pull-downs) 2 IIH – – +100 µA VIN = 3.3V

Input Current Low (with internal pull-ups) 2 IIL – – -100 µA VIN = 0

Input Current High (with internal pull-ups) 2 IIH – – +10 µA VIN = 3.3V

Output Voltage Low VOL – – 0.4 VDC

Output Voltage High VOH 2.4 – VCC VDC

Three-State (Off) Current Low2 IOTL – – -10 µA VIN = 0V

Three-State (OFF) Current High2 IOTH – – +10 µA VIN = 3.3V

Threshold point VT 1.21 1.27 1.31 V

Schmitt trigger threshold point Low to High VT+ 1.55 1.64 1.68 V

Schmitt trigger threshold point High to Low VT- 0.94 1.00 1.05 V

VDDO_B, VDDO_C = 2.5VDC

Input Voltage Low VIL -0.3 – 0.8 VDC

Input Voltage High VIH 2.0 – 5.5 VDC

Input Current Low 2 IIL – – -10 µA VIN = 0V

Input Current High 2 IIH – – +8 µA VIN = 2.5V

Output Voltage Low VOL – – 0.4 VDC

Output Voltage High VOH 2.0 – – VDC

Three-State (Off) Current Low2 IOTL – – -10 µA VIN = 0V

Three-State (OFF) Current High2 IOTH – – +10 µA VIN = 2.5V

Threshold point VT 1.01 1.08 1.12 V

Notes:1. Test Conditions (unless otherwise stated):

VCORE = +1.2 ± 0.06 VDC VMEM = +1.8 ± 0.09 VDCVDDO_A = +3.3 ± 0.165 VDCVDDO_B,C = +3.3 ± 0.165 VDC when +3.3V Ethernet transceiver is usedVDDO_B,C = +2.5 ± 0.125 VDC when +2.5V Ethernet transceiver is usedVIN (MAX)= +3.6VTj = -40°C to 125°C

2. Current flow out of the device is shown as minus.

M821xx Data Sheet


43.4.2 SSTL18 CharacteristicsThese apply to the DDR2 SDRAM interface powered by VMEM (1.8V, operating).

Table 43-6 SSTL2 Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions1

SSTL18 I/O power VDDQ 1.71 1.80 1.89 V

Low level output current IOL 13.4 – – mA

High level output current2 IOH -13.4 – – mA

High level input voltage, DC VIH VREF + 0.125

– VDDQ + 0.3

V

Low level input voltage, DC VIL -0.3 – VREF - 0.125

V

Input reference voltage VREF 0.85 0.9 0.95 V

Termination voltage VTT VREF- 0.04

VREF VREF+ 0.04

V

Notes:1. Test Conditions (unless otherwise stated):

VCORE = +1.2 ± 0.06 VDC VMEM = +1.8 ± 0.09 VDCVDDO_A = +3.3 ± 0.165 VDCVDDO_B,C = +3.3 ± 0.165 VDC when +3.3V Ethernet transceiver is usedVDDO_B,C = +2.5 ± 0.125 VDC when +2.5V Ethernet transceiver is usedVIN (MAX)= +3.6VTj = -40°C to 125°C

2. Current flow out of the device is shown as minus

M821xx Data Sheet


43.5 Reference ClockThis applies to the REFCLK input. Sections on specific interfaces specify output reference clocks.

43.6 Thermal CharacteristicsFor thermal data, please refer to M821xx Thermal App Note (821xx-APP-001).

Figure 43-1 Reference Clock Waveform Requirements

Table 43-7 Reference Clock Timing Requirements

Parameter Symbol Min. Max. Units

Clock Period tCKperiod 41.6646 41.6686 ns

Duty Cycle 40 60 Percentage high

Clock Frequency = 1/tCK period = 24 MHz ± 0.005% (50 ppm).Jitter tolerance: the value (in ps) for the maximum tolerated period-jitter for the PLL_REFCLK input is less than 50 ps peak to peak.

NOTE: This clock is specified as 50 ppm to support output of RMII and GMII clock signals for which the standard specification is 50 ppm. For designs not requiring that the M821xx device output clocks this precise, 100 ppm applies.

tCKHmin tCKLmin

3.0 V

2.0 V

0 V

0.8 V

2.0 V

0.8 V

tCKperiod

2.0 V

100735 019

.


44.0 Package Dimensions

One package, a 672-contact TEPBGA, supports all Comcerto M821xx devices. The following pages give detailed presentation of package dimensions and tolerances using standard (ASME Y15.4M-1994) conventions.

.


Appendix A: Revision Summary

A.1 Changes incorporated in 821xx-DSH-002-G1. In 2.2 Top-Level Block Diagram on page 52, a new diagram presents all internal logic blocks.

2. Two corrections in Table 4-4, “Pin List — 4-Row — M82104, M82108, M82152, M82154, M82170, M82172, M82174.,” on page 63.

• C1 VDDO_GMII0 O PWR is corrected to C1 VDDO_GMII0 — PWR

• T19 VSS_USB0 — PWR is corrected to T19 VSS_USB0 — GND

3. In Table 4-8, “I/O Type Descriptions,” on page 91, parameters are added for internal pull-down and pull-high resistance and input capacitance:

• I — Digital input, CIN = 8pF

• Id/Ots8 — Digital Input, 75 kΩ pull-down, CIN = 8pF / Digital output, 3-State, slew rate, 8mA

• Ihd/Ots8 — Digital Input with hysterisis, 75 kΩ pull-down, CIN = 8pF / Digital output, 3-State, slew rate, 8mA

• Iu/Ots8 — Digital Input, 75 kΩ pull-up, CIN = 8pF / Digital output, 3-state, slew rate, 8mA

• Ihu/Ots8 — Digital Input with hysterisis, 75 kΩ pull-up, CIN = 8pF / Digital output, 3-state, slew rate, 8mA

• Ihu/Ots16 — Digital Input with hysterisis, 75 kΩ pull-up. CIN = 8pF / Digital output, 3-state, slew rate, 16mA

• I/Ot8 — Digital input, CIN = 8pF / Digital output, 3-State, 8mA

• Ih/Ot16 — Digital input with hysteresis, CIN = 8pF / Digital output, 3-State, 16mA

• I/Ots8 — Digital input, CIN = 8pF / Digital output, 3-State, Slew Rate, 8mA

• Ih/Ots12 — Digital input,CIN = 8pF / Digital output, 3-State, Slew Rate, 12mA

• Id/Ot8 — Digital input, 75 kΩ pull-down, CIN = 8pF / Digital output, 3-State, 8mA

• Ihd — Digital input with hysteresis, 75 kΩ pull-down, CIN = 8pF

• Iu — Digital input, 75 kΩ pull-up, CIN = 8pF

• Ihu — Digital input with hysteresis, 75 kΩ pull-up, CIN = 8pF

4. A new section. 4.13 Unused Interface Termination Recommendations, presents laysout recommendations.

5. In 3.2 Comcerto M821xx Memory Map, note (4) has been revised to indicate that the five 16 MB Chip Select regions are interspersed with 48 MB default regions.

6. The Clock/Reset block is now documented in 5.0 Clock and Reset and 6.0 Clock and Reset Registers.

M821xx Data Sheet


7. In 7.0 Expansion Bus Interface changes:

• Figure 7-2 Expansion Bus Chip Select Region now shows the locations of the chip select areas within the Expansion Bus region.

•I In 7.9 Expansion Interface AC Timing, a note now clarifies that the timing requirements present apply to the M821xx and note Expansion Bus peripherals.

• In 7.10 Notes Regarding Asynchronous Interface, a cross-reference indicates Figure 7-4 as an example of asynchronous timing.

8. in: 8.0 Expansion Bus Interface Registers

• The base address register has been corrected.

• In 8.2.3 Expansion Memory Segment Size (EX_CSx_SEG_R); Where x = 0 – 4 the register description has been improved.

9. In 11.0 Ethernet Interface:

• In Table 11-3, “RMII Signals,” on page 178 a note has been added regarding RMII_RX_ER:

NOTE: In the WAN port (Eth0) this pin is not used, and must be driven to a constant low when in RMII mode.

• In Table 11-10, “RMII Interface Timing Parameters,” on page 185, note (2) at the end of the table has been revised to clarify that PHYs and switches used with this interface must provide 0.5 to 2 nanoseconds of clock delay in both RX and TX directions.

10. In 12.0 Ethenet Interface Registers, notes have been place to explain register operations:

• In 12.3.2 Network Configuration Register, a note is placed in the bit 29 description:

NOTE: For proper operation, this bit must be set to ‘1’.

• In 12.3.49 Deferred Tansmission Frames Register and 12.3.50 Carrier Sense Errors Register:


• In 12.5.6 TXFF HTH: a note is added.

NOTE: For 10 Mbps mode this register is typically set to 0x1C0. For 100 and 1000 Mbps modes, it is typically set to 0x1D0.

11. A new section, 14.0 PoS / UTOPIA Interface Registers, details registers supporting these interfaces.

12. In 15.0 PCI/µP Interface:

• In 15.6.1 PCI Host Memory Bridge (HMB) Functions a note is added:


• In 15.8 PCI Host Mode Operations the register names have changed (from “HI BME” to “PCI” for consistency with existing register descriptions).

• In 15.9.2 mP Bus General Description the following note is added:

NOTE: In asynchronous mode only one slave can be connected without external logic.

13. In16.0 PCI/µP Interface Registers additional interface registers are now described:

• 16.4 HMB Interface Registers (Including HICORE Host Side Register)

• 16.5 APB Accessible Registers

14. 21.0 TDM Bus Interface Description now also refers to the TDMA engine.

• It is now noted in 21.2 Signal Description that the TDM clock output will halt when the device is reset.

15. A new section, 22.0 TDM Registers, details TDM and TDMA registers.

M821xx Data Sheet


16. In 23.0 Universal Asynchronous Receiver Transmitter (UART), 4.125 Mbps has been removed as a maximum baud rate.

17. In 25.9 Troubleshooting, a procedure for recovering when booting from I2C EEPROMs is given.

18. 27.0 USB Interface has changed to show support for device mode:

• Limitations of the interface are resetated at the start of the section.

• New subsection include:

– 27.4 Device Operational Mode.

– 27.5 EHCI Deviations

– 27.6 Device Data Structures

– 27.7 USB Power Management

19. A new section, 28.0 USB Registers, details EHCI and non-EHCI standard registers.

20. Subsection 30.1.4 APB Bus Access Wait State Register presents additional details on control fo the AHB – APB Bus Bridge by this register.

21. Two new sections describe the Interrupt Controller:

• 31.0 Interrupt Controller

• 32.0 Interrupt Controller Registers

22. 35.0 Test and Debug Interface Description now includes

23. 36.0 Power Management has been expanded to detail specific registers and modes of operation.

24. A new section, 37.0 AHB – APB Bus Bridge describes the bridge linking the multi-layer AMBA Advanced Host Bus with the Advanced Peripheral Bus.

25. Two new sections describe the I/O DMA engine:

• 38.0 I/O DMA Controller

• 39.0 I/O DMA Registers

26. Two new sections describe the Memory DMA engine:

• 40.0 Memory DMA Controller

• 41.0 Memory DMA Registers

27. In 44.0 Package Dimensions, the actual mechanical drawings used to specify the package are now presented.

28. Appendix B: Device Modifications presents key differences between M821xx silicon releases.

.


Appendix B: Device Modifications

B.1 Changes in Silicon Revision C1. Improvements in design have improved reliability and performance of PCI transactions in

windowing mode as described in 15.6 PCI – SDRAM Windowing Operations.

2. Design corrections enable reliable USB device mode fuctionality.

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