Teseda Confidential

An Introduction to Teseda Fast and Intuitive Scan Defect Isolation

Teseda Confidential

Who Is Teseda?

• Teseda’s products accelerate first silicon debug and shorten failure analysis and yield improvement turn-around time

• Teseda Solutions deliver:

Fast Silicon Debug (Time To Market) Rapid Failure Analysis - Impacts time to production release and yield

improvement

Ensuring rapid diagnosis of design, process, or use related failures is the core of our business!

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V520 Engineering Test System • 348 I/O pins

50Mhz force and compare 300 I/O pins, 32 clock pins,

16 scan enable pins Full per-pin timing capability

• 32M Per Pin Vector Depth • DC Parametric

Source/Measure Option Continuity, Leakage and Voltage

measurements Fully automated SW control

• 4 Internal DUT Power Supplies 2 High Current (2A) 2 Low Current (100mA)

• Driven by Teseda’s powerful Teseda WorkBench (TWB) DFT-Enabled Software

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V550 Engineering Test System • 512 I/O pins

100Mhz force and compare Higher clock and data rates can be

created with multiple edges per cycle Any pin can be I, O, I/O or Clock Full per-pin timing capability

• 64M Per Pin Vector Depth • DC Parametric Source/Measure Option

Continuity, Leakage and Voltage measurements

Fully automated SW control

• 7 Internal DUT Power Supplies 4 High Current (4A) 2 Low Current (250mA) 1 High Voltage (25V)

• Driven by Teseda’s powerful Teseda WorkBench (TWB) DFT-Enabled Software

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Capabilities of Teseda Workbench

Create New Tests Quickly • Import STIL files • Set DC values • Compile and download tests • Manage projects • Interactive, easy-to use

Execute Tests • Functional or Scan Tests • Map failing scan cells to chain

and design instance • DC Tests (Continuity, IiL, VoH) • Iddq Tests • Shmoo Plots and Test Flows

Export Scan Fail Logs • Save cycle or pattern format • Synopsys or Mentor format • Feed fail result logs to

diagnosis tools like NetXY, YieldAssist and TetraMAX

Perform Failure Analysis • Compare expect with actual • Loop on specific vectors • Trigger output on events • Designed to interface with

Emission Microscopes, LADA, and other SDA tools

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Teseda Workbench Features • Manages V550 or V520 hardware • STIL compiler • Set DC and AC timing values • Vector and timing waveform

display • Run test settings – P/F mode, fail

capture mode, full capture mode, loop vectors, set triggers, run with timing scale, etc.

• Scan fail results processing and logging

• Debug / Characterization Tools Chain plot tool Scan view / design view tool Shmoo plot tool DC measurement screen Iddq measurement screen

• Manage test projects, archive, delete, etc.

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Diagnostic Manager NetXY

• Diagnostic Manager NetXY diagnoses the cause of scan-captured failures within the physical design of the device Analyzes design, STIL vectors and scan failures Identifies the location of the fault on the physical layout

• Utilizes industry standards Standard Test Interface Language (STIL) Design Exchange Format (DEF) Library Exchange Format (LEF)

• Interoperable with all major EDA DFT and diagnostic tools and flows

Failures

STIL

STIL - Test Pattern

Scan Failures- From Test Pattern results

LEF/DEF

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Real Customer Example Mapping Logical Fails to Physical • Four scan cells failing frequently

A few neighboring infrequent failures Scan cells located in same logic block

TWB Diagnostic Manager NetXY

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Scan Fail Diagnosis with NetXY • Show scan chain stitching order on the

physical layout • Overlay scan flip flops capturing failures

on the physical scan chain along with color map of fail density

• Pathfinder design navigation tool - enables logic trace back from failing scan flip flops

• Automated logic cone tracing back from failing scan flip flop

• Automated scan chain tracing of the physical nets that connect between scan flip flops (useful in diagnosing chain fails)

• Automated cone convergence identify the common intersection of multiple failing

logic cones

• Automated identification of the failing net

Rapidly find the root cause of scan fails regardless of EDA vendor. Diagnose failures without requiring support from the design team.

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Teseda in Failure Analysis Diagnose = Localize + Isolate + Confirm

Map test fail logs onto the physical design

Identify scan cells with highest failure rates

Trace circuit cones of selected scan cells

Diagnostic Manager NetXY

Fault Isolation

Teseda Workbench (TWB) Fault Localization

V550 V520

Defect Confirmation Emission, LIVA, TIVA, OBIRCH, LADA

Physical (destructive) Confirmation FIB, SEM, TEM

Defect Localization

Defect Isolation

Find cone intersections

Prune nets off non relevant fan outs

Correlate state transitions to test results and test patterns in isolated circuits

V550 or V520 coupled with FA imaging equipment to dynamically confirm isolated defects - ideal for soft defects

Use Diagnostic Manager NetXY to determine probe points for FIB physical confirmation