Bpsk Demodulation

Download Bpsk Demodulation

Post on 28-Nov-2014

170 views

Category:

Documents

8 download

Embed Size (px)

TRANSCRIPT

<p>Digitally Demodulating Binary Phase Shift Keyed Data SignalsCornelis J. Kikkert, Craig Blackburn Electrical and Computer Engineering James Cook University Townsville, Qld, Australia, 4811. E-mail: Keith.Kikkert@jcu.edu.au, Craig.Blackburn@jcu.edu.au.</p> <p>AbstractThis paper describes the realisation of a differential BPSK demodulator using a high speed ADC, an EPLD and an EPROM. By incorporating both I and Q data in the demodulation process, a significant improvement in performance is obtained. Computer simulation shows the Bit Error Rate (BER) performance versus Received Carrier to Noise Ratio (CNR) is virtually identical to the theoretical performance of a differential phase shift keyed (DPSK) detector. This paper also describes the realisation of the special PLL required, to recover the data clock. This PLL uses an EPLD, a DAC, a conventional loop filter and a conventional VCO.</p> <p>2. Practical BPSK demodulatorBSPK Input Demodulated Output</p> <p>Integrate Over One Data Bit</p> <p>Delay of One Data Bit</p> <p>Figure 1. Differential BPSK demodulator.</p> <p>Communication texts [3] suggest the use of differential phase detection, based on the block diagram of figure 1. However these texts do not mention the strict synchronisation requirements. If the input waveform is a carrier: X(t) = Sin(ct) The delayed signal will be: Y(t) = Sin (ct + ) Eqn. 1b where is the phase shift of the delayed waveform with respect to the present waveform. The output from the multiplier will then be:Sin( c t ) Sin( c t + )dt = Sin 2 ( c t ) Cos( ) Sin( c t ) Cos( c t ) Sin( ) 1 1 = [1 Cos(2 c t )] Cos( ) Sin(2 c t ) Sin( ) 2 2</p> <p>1. IntroductionThe transmission of data from the GMS weather satellite is a BPSK signal, at a carrier frequency of 1.6871 GHz with a 660 kbit/sec data rate. Because of the &gt;200 dB free space loss of the transmitted signal, the received CNR is only a few dB above the minimum value required to demodulate the data with acceptable error rates. To receive these signals, a low cost BPSK demodulator is required, which can accurately demodulate BPSK signals at these low carrier to noise ratios. The reception of Binary Phase Shift Keyed (BPSK) signals has traditionally been difficult. The carrier has either a 0 degree or a 180 degree phase shift depending on the data and the carrier amplitude is zero during the data transitions. As a result, a conventional Phase Locked Loop (PLL) demodulator cannot be used. Differential detection of BPSK signals is easy in theory, but difficult in practice. A Costas Loop [1] or a Phase Locked Loop (PLL) with special phase detectors[2], can be used to recover the carrier. That carrier is then used to synchronously demodulate the received signal. From theory, synchronous demodulation of BPSK data gives the best BER performance. In practice a Costas Loop will only perform accurately at a high Carrier to Noise Ratio (CNR). At a low CNR the loop will tend to loose lock. The BPSK demodulator described here remains locked under noisy conditions. The new BPSK demodulator uses digital technology, resulting in a lower production cost and simpler hardware than the Costas Loop.</p> <p>Eqn. 1a</p> <p>Eqn. 2</p> <p>For a typical BPSK system, there are many carrier cycles per data period. For ideal operation is 0 or 180 and then the second term can be ignored, leaving a DC component plus a large ripple.</p> <p>2.1 RealisationThe signal at the multiplier output in Figure 1 and shown in equation 2 must be used as the input for the data clock recovery circuitry. This large ripple causes problems, with the stability of the clock recovery hardware. Using In-Phase (I) and Quadrature (Q) components as shown in Figure 2, removes most of the ripple. The Analogue to Digital Converter (ADC) digitises the input carrier waveform of equation 1a. The digital delay line then delays this waveform by one data bit. The signals at the tapping points 1 and 16 then correspond to those that are multiplied in figure 1. The delay line is clocked</p> <p>1.00 0.90</p> <p>to PLL1 2 16 17</p> <p>0.80 0.70</p> <p>Output Ripple I2 Out I2 Ripple</p> <p>Input</p> <p>Output</p> <p>ADC</p> <p>EPLD Delay Line 17 bit long, 8 wide</p> <p>Integrate and Dump Data</p> <p>0.60 0.50 0.40 0.30</p> <p>Figure 2. New BPSK demodulator.</p> <p>0.20 0.10</p> <p>with the sampling clock that is also used for the ADC. The sampling frequency is chosen such that one sampling period delay corresponds to 90 phase shift of the carrier waveform. If a sine waveform is present at tapping point 1, then a cosine waveform is present at tapping point 2. The signals at tapping points 1 and 16 will thus be InPhase (I) components and those at tapping points 2 and 17 will thus be Quadrature (Q) components. At the adder in figure 2, the following waveform will thus be present: X(t) = Sin(ct)Sin(ct+)+Cos((ct+)Cos(ct++) Eqn. 4. Where is the phase shift of the carrier over one data bit period, including the BPSK modulation and is the variation from the 90 phase shift. In practice will be zero, and will be either 0 or 180 depending on the BPSK data. The resulting waveform at the adder will thus be either: X(t) = Sin2(ct) + Cos2(ct) = 1 or X(t) =- Sin2(ct) - Cos2(ct) = -1 Eqn. 5.</p> <p>0.00 0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% Frequency Error wrt Data Frequency</p> <p>Figure 4. Frequency Tolerance of BPSK demodulator.</p> <p>of 660 kHz, or 165 kHz of the 18.48 MHz BPSK carrier for a 3 dB drop in output. This frequency stability requirement is quite feasible, even for down conversion from a 1.6871 GHz satellite signal.</p> <p>Integrate and Dump</p> <p>to PLL</p> <p>Decision Logic1 2 16 17</p> <p>Q I</p> <p>EPLD Delay Line 17 bit long, 8 wide</p> <p>Integrate and Dump</p> <p>to PLL</p> <p>depending on the value of the BPSK data. Note that the ripple at 2c has been removed completely. The resulting waveforms are shown in Figure 3. By calculating the variation of and resulting from the BPSK carrier frequency and the sampling frequency being not correctly related, the tolerance of this BPSK demodulator can be plotted as shown in figure 4. Using both the I and Q tapping points, doubles the output signal and results in a minimal ripple. For an IF frequency shift of 25% of the data rate, the ripple is less than 10% and the data output is more than 70% of the ideal output voltage. For hardware realisation of the BPSK demodulator, one can thus have a frequency shift of 25%1.2 0.8</p> <p>Figure 5. QPSK Demodulator.</p> <p>By adding two more multipliers and an adder to the block diagram of Figure 2, the technique can be extended to demodulate QPSK signals as well, as shown in Figure 5. A phase locked loop (PLL) is required to recover the 660 kHz data clock. The 10.56 MHz sampling frequency for the ADC and delay line is 16 times the 660 kHz data clock and is produced by this same PLL.</p> <p>2.2 HardwareAn 8 bit ADC is used as this has been demonstrated by computer simulation to give a satisfactory performance. The delay line is thus 17 bit long and 8 bit wide. This requires 136 flip-flops and is programmed into a Lattice ispLSI1032 EPLD. The multipliers shown in figure 2 need to be able to multiply two 8 bit numbers inside the 94.7 ns period of the 10.56 MHz sampling clock. This is achieved by using a 512 kbyte EPROM as a look-up table. The 16 EPROM data inputs are formed by the two 8 bit inputs to be multiplied. Since the multiplied I data is the same as the multiplied Q data one clock pulse later, only one EPROM is required if the EPLD is used to store and delay the multiplied value for one clock period.</p> <p>I +Q</p> <p>2</p> <p>2</p> <p>Amplitude</p> <p>0.4 0.0 -0.4I I2</p> <p>Q</p> <p>2</p> <p>Q</p> <p>-0.8 -1.2</p> <p>TimeFigure 3. Demodulator Waveforms.</p> <p>A second ispLSI1032 EPLD is used to add the I and Q multiplier outputs and to perform the integrate and dump data detection using an adder for the integrator. The added I and Q multiplier output is the raw digital data output required for the data synchronisation PLL. This signal is turned into an analogue signal using a Digital to Analogue converter (DAC), the output of which is then filtered to provide some smoothing. This filtered raw demodulated data is then used as reference input to a PLL, to recover the 660 kHz clock and hence the 10.56 MHz sampling clock. The whole block diagram shown in figure 2 is thus realised using two low cost EPLDs, one EPROM a low cost ADC and a low cost DAC. Figure 6 shows the resulting hardware. The left board is the BPSK demodulator and the right board is the Phase Locked loop described later. Figure 7 shows the binary input data, the BPSK data and the demodulated output obtained with this hardware. The top trace is the binary data, the second trace is the differentially encoded signal, which is then modulated with a carrier. The bottom trace is the demodulated output. The system performs very well, even under noisy signal conditions.</p> <p>1.E+00Baseband Simulated Baseband Theoretical IF Simulated</p> <p>1.E-01</p> <p>1.E-02 BER</p> <p>1.E-03</p> <p>1.E-04</p> <p>1.E-05</p> <p>1.E-06 0 2 4 6 Eb/No 8 10 12</p> <p>Figure 8. Frequency Tolerance of BPSK Demodulator.</p> <p>2.3 Error performanceSince the system has to operate under poor Carrier to Noise conditions, the performance of the system under noisy conditions must be investigated. Figure 8 shows the error performance obtained from a computer simulation of the system, described above. There is an excellent agreement between the theoretical results [3] for the ideal differential decoder and the computer simulation of the actual system. The calculated error performance for an IF simulation, incorporating the hardware filters used in the simulation, shows a slight degradation in the error performance due to more noise being passed by the non-ideal IF filter. The bandwidth of the IF filter indicated, is that of an ideal filter with the same total noise output. The noise spectral density (N0) indicated in Figure 8 is the total noise, obtained from the computer simulation, divided by this bandwidth. The simulated performance of the system at a BER less than 10-4 has a larger error tolerance, as a very large computer simulation is required in order to have sufficient errors for the results to be statistically valid. In the computer simulation, the effects of the finite length and width of the EPLD delay line and the realisation of the multipliers using EPROMs was included. A slightly worse, but satisfactory performance was obtained, even with a 4 bit wide delay line and multipliers. For 4 bit wide multipliers, both multipliers can be included in one EPROM. The adder of Figure 2 can then also be included in the EPROM as part of the look-up table, reducing the cost even further. Since the cost of the 8 bit wide realisation is small, and there is an improvement in performance, an 8 bit wide realisation is used in the hardware.</p> <p>Figure 6. BPSK Demodulator Harware.</p> <p>Data in Differential data</p> <p>BPSK Data</p> <p>3. Phase Locked Loop3.1 Phase DetectionThe demodulator requires that the ADC and Digital Delay line clock frequency is exactly 16 times the data rate. A PLL is required to recover the data clock and generate the 10.56 MHz ADC sampling frequency. To minimise hardware production costs, a complete digital realisation of this phase detector is required.</p> <p>Data out</p> <p>Figure 7. Frequency Tolerance of BPSK Demodulator.</p> <p>Clock Data 192 128 64 0 51 64 Period/Phase Counter Phase Det O/P</p> <p>This will occur 25% of the time on average, which is sufficient to keep the PLL phase locked. Since the analogue Phase Detector Output is produced by a DAC, no drift occurs in-between Phase Detector Output updates.</p> <p>3.2 Frequency detectionThe time interval between zero crossings of the data is obtained from the Phase and Period counter shown in Figure 9 and is a measure of the frequency difference between the input data and the VCO. The counter contains the data period, just before the counter is set to zero. For the hardware described here, the data period should be 128 clock pulses of the 84.48 MHz VCO. The counter contents can thus be used as a frequency indication and used to provide frequency locking. Since on average one quarter of the number of data bits have transitions 1.515 s apart, the VCO frequency is controlled often enough to ensure proper locking of the VCO. Figure 10 shows the resulting block diagram of the PLL. The output of the frequency control counter and the phase detector output are added in the correct proportions to provide the input to a DAC, which provides the analogue voltage of the VCO after filtering. For the hardware realisation the Phase detector produces 128 different levels for a 360 range of operation. In order to produce a good overlap between the frequency detector and the phase detector, the frequency step size is 64 times larger than the phase step size. The 84.48 MHz VCO has a 10 MHz tuning range. Since a 16 bit DAC is connected to this control counter, each counter step is thus 152 Hz, which is well within the frequency tolerance required as shown in Figure 4. The Phase Frequency detector and the VCO frequency dividers can be realised using one EPLD. The right hand board shown in figure 6 contains the Phase/Frequency detector, VCO and loop filter. The second EPLD on that board is for further processing of the received data.</p> <p>Figure 9. Waveforms for Phase/Frequency Detector.</p> <p>The binary data has a time between zero crossings that varies in multiples of 1.515 s. Since the zero crossings do not occur every data bit, a conventional phase detector cannot be used. One of the authors [4] has developed an analogue phase detector, which is suitable for this application. This phase detector will however only lock if the free running frequency of the PLL is very close to the 660 kHz data rate. That cannot always be guaranteed. To ensure reliable operation of the receiver system, frequency detection is required to ensure that the PLL always locks. Figure 9 shows the waveforms used in the Phase/Frequency detector developed for the Data Clock recovery. The Clock is the 660 kHz data clock, which is derived from a 84.48 MHz voltage controlled oscillator (VCO) by dividing by 128. The data signal is the raw binary data, obtained by digital to analogue conversion and filtering of the adder output of Figure 2 (to PLL). At a transition of the data, a Phase and Period Counter is set to zero. The 84.48 MHz VCO increments that counter and its output ramps up as shown. When the falling edge of the Clock occurs, the content of this counter is latched and transferred to the Phase Detector Output. This Phase Detector Output is converted to an analogue voltage, the filtered value of which controls the VCO. If more than one ones or zeros are being transmitted in succession, there will not be a second transition 1.515 s after the first one and the counter simply keeps ramping up until the maximum count of 192 is obtained, where the counter limits. If this happens, the Phase &amp; Period Counter contents are not transferred to the Phase Detector Output. The next data transition will then reset the Phase and Period Counter back to zero. The p...</p>