BIST using Cellular Automata as Test Pattern Generator and Response Compaction

Lixin Gao, Yongliang Zhang, Jinhong ZhaoSchool of Information Engineering

Guangdong Jidian PolytechnicGuangzhou, China

e-mail: g_lixin@gdmec.edu.cn

Abstract—In the Built-in self-test (BIST), a pseudo-random

generator is used to apply test vectors to the circuit under test and a

data compactor is used to produce a signature. This paper verifies

that a linear hybrid Cellular Automata (CA) as a test pattern

generator has a maximum length cycle and better random

properties, and such CA as a signature analyzer have the same

aliasing properties as linear feedback shift registers.

Keywords-BIST; cellular automata; maximal length cycle;

random; fault coverage; aliasing

I. INTRODUCTION

Built-in self-test (BIST) refers to those testing techniques where additional hardware is added to a design so that testing is accomplished without the aid of external hardware. Usually, a pseudo-random generator is used to apply test vectors to the circuit under test and a data compactor is used to produce a signature.

The typical BIST process is shown in the Figure 1.

Figure 1. BIST process[1].

A BIST design requires a mechanism for generating an appropriate set of test vectors. For some combinational blocks, it is possible to exhaustively apply all the possible input patterns and compare the circuit response to a known "good circuit" response. For the conventional stuck-at fault model, an exhaustive test set ensures that every testable fault will be covered. However, if there are more than 20 inputs to the circuit under test then the time to provide the test patterns ( 220 per circuit ) and the memory to store the circuit responses ( m*220

II. CELLULAR AUTOMATA

bits, m- number of circuit outputs ) becomes excessive [2]. For cases where an exhaustive test set is prohibitive, a pseudo-randomly selected subset of possible inputs to the circuit under test is used.

A Cellular Automata is a cell collection with regular connections. Each cell can only connect to its local neighbors. The connections are expressed as rules, which determine the next state based on the state of the cell's neighbors. If cell c only connect with its neighbors , c-1 and c+1, shown in the Figure 2, then the following rule, called rule 90, can be established based on the following state transition function: Xc(t+1)= Xc-1(t) Xc+1(t).

200978-1-4577-1415-3/12/$26.00 ©2012 IEEE

Q QS

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Rule 90

Figure 2. CA Rule 90.

Another relation, rule 150, shown in the Figure 3, is

implemented as Xc(t+1) = Xc-1(t) Xc(t) Xc+1(t).

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Rule 150

Figure 3. FCA Rule 150.

Figure 4 shows a hybrid Cellular Automata alternately using rules 90 and 150 in its cells. The hybrid 90/150 CA with null boundary conditions will lead to maximal length cycle structures.

Figure 4. Example of hybrid CA.

CA has attracted considerable interest because each cell can only connect to its local neighbors. Therefore, unlike LFSR, where expansion in size requires major changes to feedback loop

connections, CA are easily scalable. It is enough to simply connect more cells at the end of existing CA.

III. CELLULAR AUTOMATA AS TEST PATTERN GENERATION

A. Maximal cycle length

A CA has maximal cycle length if, when run in autonomous mode (no external input), it cycles through all 2k

The following table gives the hybrid constructions (not unique) necessary to achieve a CA with maximal cycle length. (for n<=10) (a 1 for a stage with a rule 150 connection and a 0 for a rule 90 stage)

-1 nonzero states.

Hybrid constructions necessary to achieve a CA with maximal cycle length (for n<=10) is shown below:

TABLE I. HYBRID CONSTRUCTIONS CA WITH MAXIMAL CYCLE LENGTH

CA Construction Cycle length3 011 84 0101 155 11001 316 010101 637 1101010 1278 11010101 2559 110010101 51110 0101010101 1023…

B. Pseudo-random

If the test vectors generated by the CA are pseudo-random, the test set will contain appropriate vectors to active enough faults inCUT. A number of experiments have performed to assess fault coverage [3][4]. The result of the experiments is that stuck at fault coverage offered by the linear CA is satisfying, similar to the LFSR. Therefore, the test vectors generated by the CA are pseudo-random.

IV. CELLULAR AUTOMATA AS RESPONSE COMPACTION

A. Signature analysis

Signature analysis is a method of circuit response compaction during BIST, which reduces the huge number of bits in the original responses into a very small size that represents a statistical circuit property. However, some information in the

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original response is lost during the process of compacting. As a result, there is a small probability that a signature of a faulty circuit may match that of the fault free circuit after response compaction. This problem is known as aliasing. In the following, we describe the implementation of signature analyzers and their aliasing properties.

B. LFSR signature analysis

The LFSR as a data compacter has already been researched extensively in many years[5]. It is now a popular choice as a data compacter because of its easy of implementation and its degree of effectiveness[6]. It can be implemented using the exclusive-OR gates and a set of Flip Flops. The operation of LFSR is related to the mathematics of polynomials and Galois field theory[7]. Every LFSR has a characteristic polynomial that describes its behavior. When the LFSR acts as a signature analyzer, the input data stream polynomial divided by LFSR characteristic polynomial. At the end of clock cycles, the last state of the LFSR or the remainder polynomial forms the signature of the circuit under test[8].

Figure 5. Four-stage LFSR.

Single input LFSR compacter receives the serial output vector of circuit under test (CUT). For a test bit stream of length k, there are 2k possible output vectors. If there is a fault in the CUT and the output vector can reflect with some changes in its bit patterns, these changes may or may not cause a different signature at the output of the LSFR compacter. We assume that each of data stream patterns is evenly likely to produce any of 2n

1212

k

nk

p

possible signatures, where n is the size of the LFSR compacter. So the proportion of error streams that correspond to the correct signature is independent of the actual signature, given by:

Furthermore, if we assume all erroneous bit streams are equally likely then p is the probability of aliasing of the LFSR

signature analyzer. For k >> n >> 1 the error probability is p = 2-n

C. Cellular Automata signature analysis

.

Figure 6 shows a four-stage hybrid CA.

Figure 6. Four-stage hybrid CA.

Although linear hybrid 90/150 CA sequencing and the signature are different from that of LFSR, they have the same cycle structure. Therefore, those linear hybrid 90/150 CA has their aliasing probabilities on the order of 2-n

V. COMPUTER SIMULATIONS AND RESULTS

, which are the same as the corresponding LFSR exhibit, when acting as single input response compactor.

In addition to the implementation and property of the LFSRand CA, we have also studied their performances by computer simulation of a Schneider’s example circuit in presence of single stuck-at faults. The testing circuits are shown in Figure 7.

Figure 7. Circuit under test.

In our simulation, we consider the conventional single stuck-at faults model, i.e. two faults per line, stuck-at-0 (sa0) and stuck-at-1 (sa1). The circuit is simulated with 3-bit length LFSR and CA test pattern generators with maximal cycle length. The characteristic polynomial is f(x) =1+ x + x3.

To find undetectable or redundant faults and measure the fault coverage of the pattern generators, we initialize LFSR and CA test

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pattern generators to state “001” and run the fault simulator for each test vector.

In this experiment, we found: there are two stuck-at fault, F5: B-d sa1 and F16: k sa1, are undetected by any possible test vector, fu = 2; we need seven test vectors produced by LFSR with initial state “001” in order to test other 24 stuck-at faults; However, the CA test pattern generator produces the same test vectors but in the different order: {“001”, “011”, “100”, “010”, “111”, “110”, “101”}. Instead of using seven test vectors, we need only apply the first five vectors to achieve the same fault coverage as the LFSR.

Test vector compaction. If we reinitialize the LFSR to state “111”, we have the test vector set in the following order: {“111”, “011”, “001”, “100”, “010”, “101”, “110”}. So now the number of needed test vectors reduces to 5 too.

In the next experiment, we firstly use exhaustive test in our simulations. For each single stuck-at fault in the CUT, both LFSR and CA test pattern generators are initialized by the same seed “001”, and then the circuit is clocked for seven periods to produce all possible (23

In our experiments with the simple Schneider’s circuit, we practice implementing BIST with the LFSR and CA test pattern

generators and data compactors in software, and testing single stuck-at faulty circuits by computer simulations.

-1) test patterns. The signature is formed as RCout(0..2) seven clock edges after the “start” signal is enabled. Every faulty circuit signature will be compared with the fault-free circuit signature, which is “100” or hex 4. From the waveform, we find that there are five signatures of faulty circuits are the same as a good circuit. So fal = 5, and PLF = (5-2)/(26-2) = 0.125.

VI. CONCLUSION

A linear hybrid Cellular Automata (CA) as a test pattern generator has a maximum length cycle and better random properties, and such CA as a signature analyzer have the same aliasing properties as linear feedback shift registers.

REFERENCES

[1] Bushnell and Agrawal, “Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits” New York: Kluwer Academic Publishers, 2002

[2] Paul H. Bardell, “Analysis of Cellular Automata Used as Pseudorandom Pattern Generators ”, 1990 International Test Conference.

[3] Serra, M.; Slater, T.; Muzio, J.C.; Miller, D.M., “The analysis of one-dimensional linear cellular automata and their aliasing properties,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume: 9 , Issue: 7 , July 1999, Pages:767 – 778.

[4] Cheng-Wen Wu; Hun-Song Chen(2010).Modular-addition signature analysis for built-in self-test,” Proceedings of ETC 93, Third, 19-22 April 1993, Pages:457 – 465.

[5] Miller, D.M., “Estimating aliasing in CA and LFSR based signature registers,” Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on , 17-19Sept.1990,Pages:157–160.

[6] Jianbing Zhao., “A Novel FPGA Manufacture-oriented Interconnect Fault Test,” 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008

[7] Fiser,P.,“Pseudo-random pattern generator design for column -matching bist,” Proceedings of the 10th Euromicro Confeence on Digital SystemDesign Architectures, Methods and Tools IEEE Computer Society, Washington, DC, USA, pp.657-663, 2007.

[8] Garbolino,T. and Papa,G., “Genetic algorithm for test pattern generator design,” Applied Intelligence 32(2): 193-204, 2010.

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