bis, smp & pcinterlock software activities during ls1
DESCRIPTION
BIS, SMP & PcInterlock Software activities during LS1. Maxime Audrain On behalf of the MS-Software team: Arkadiusz , Jacek, Jean-Christophe and Kajetan. Menu. Overview BIS & SMP activities PcInterlock activities. Overview (1/3). Description of the activity: - PowerPoint PPT PresentationTRANSCRIPT
MPE workshop for LS1 - [email protected]
BIS, SMP & PcInterlockSoftware activities during LS1
Maxime AudrainOn behalf of the MS-Software team: Arkadiusz, Jacek, Jean-Christophe and Kajetan.
MPE workshop for LS1 - [email protected] 2
Menu
Overview
BIS & SMP activities
PcInterlock activities
MPE workshop for LS1 - [email protected] 3
Overview (1/3) Description of the activity:
Software developments for the BIS, SMP and PcInterlock during LS1. It involves follow-up of the Hardware upgrades and implementation of new requirements from operators and experts.
Why during LS1: Mostly to be able to monitor the systems correctly when the machines restart
at the end of LS1.
Risks and impacts if not done during LS1: Unable to properly monitor and diagnose protection systems.
MPE workshop for LS1 - [email protected] 4
Overview (2/3) Activity time estimation:
Around 200 story points for BIS, SMP and common components Around 65 story points for the PcInterlock Activities does not depend on the LS1 general schedule.
Manpower: Internal man power, Software coordination team (around 5 persons) Potential missing resources has to be identified In MPE : Support from MPE/EP for specifications, milestones and HW
deployments (Stephane).
MPE workshop for LS1 - [email protected] 5
Overview (3/3) Contributions from the other groups:
DIAMON monitoring, Sequencer task deployment, PM modules deployments from BE/CO
Andrea Moscatelli (SPS operator) for developments on the BIS project No potential issues are identified (if follow-up is performed).
Safety measures: Not relevant
Potential showstoppers: Same office as Arek! (time is shared between projects)
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CISVCIBG MPE Generic FESA class:
- Contains getter for all registers + History Buffers. - Contains generic needs for all FESA classes..
BIS & SMP server :
Decode data from the FESA class and process it. Publish it for clients
inherit
CISXCIBM
Provide board specific properties (like operator
parameter settings)
BIS & SMPFESA classes :(Linux compatibles)
BIS GUI Logging DB
QPS PowerCycle tool
… other clients …
Configuration DB
Presentation layer
Subscribe and send requested commands
Retrieve needed information and/or send commands
Retrieve critical parameters for systems
SMP GUI
BIS & SMP architecture overview
FESA 3prototype
Common functionalities
MPE workshop for LS1 - [email protected] 7
Common Software Common GUI Components +
Software components for board communications
General server infrastructure for BIS/SMP monitoring services
Generic FESA class design if FESA 3 provides Object features.
MPE workshop for LS1 - [email protected] 8
BIS activities before LS1 Follow-up of BICs deployment
on the Linac 4 + Transfer line + Booster : Deploy CIBM FESA class
(Linux compatible) Allow monitoring from the
Linac 4 BIS supervision.
MPE workshop for LS1 - [email protected] 9
BIS activities during LS1 Deploy CIBM FESA class to all front-ends. Redefine the CIBG FESA class under Linux
Generic server specialization for identified clients : BIS GUI, SMP GUI, logging DB, QPS power-cycle tool,…
New GUI that fits operator and expert needs, with different views depending on the accelerator timing domains
Adaptation of the Pre-Current-Post operational checks
BIS 2 specificities to be foreseen during GUI re-definition.
MPE workshop for LS1 - [email protected] 10
SMP Modify SMP FESA classes for CISX
and CISV boards to work under Linux controller.
Plug the GUI to the BIS&SMP server (Could be done after LS1).
MPE workshop for LS1 - [email protected] 11
PcInterlock Improve analysis
functionalities.
Extends the interlocking to other Power Converters.
Log interlocking decisions.
Reinforce RBAC protection.
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Summary 190 story points to be done during LS1 :
~54 % of total capacity.
Complete redesign of the BIS supervision for Operators and Experts.
A server to publish and log information from BIS & SMP.
Abstract software design for BIS & SMP.
Improvements to make the PC Interlock more flexible.
MPE workshop for LS1 - [email protected] 13
Fin
Thank you for your attention
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