The full-adder forms the sum of two bits and a previous carry.

Two binary numbers of n bits each can be added by means of this circuit.

When pair of bits are added through the full-adder, the circuit produces a carry to be used with the pair of bits one higher significant position

The bits are added with full-adders, starting from the lest significant position, to from the sum bit and carry bit.

The sum of two n-bit binary numbers A and B, can be generated in two ways: either in serial fashion or in parallel.

The serial addition method uses only one full-adder circuit and a storage device to hold the generated output carry and sum.

The parallel method uses n full-adder circuit.

A binary parallel adder is a digital function that produces the arithmetic sum of two binary numbers in parallel.

Example :-

FA FA FA FA

B4 A4 B3 A3 B2 A2 B1 A1

C1C2C3C4C5

S3 S2 S1S4

An n-bit parallel adder requires n full-adders

It can be constructed from 4-bit, 2-bit and 1-bit full-adders ICs by cascading several packages.

The 4-bit binary parallel adder is a typical example of an MSI function.

It can be used in many applications involving arithmetic operations.

The application of this MSI function to the design of a combinational circuit is demonstrated in the example of BCD to excess-1 code converter.

Example:- BCD to excess-1 code converter

CARRY PROPAGATION

The addition of two binary numbers in parallel implies that all the bits of the augend and the addend are available for computation at the same time.

As in any combinational circuit, the signal must propagate through gates before the correct output sum is available in output terminals.

The total propagation time is equal to the propagation delay of typical gate times the number of gate levels in the circuit.

The longest propagation delay time in a parallel adder is the time it takes the carry to propagate through the full-adders

The number of gate levels for the carry propagation can be found from the circuit of the full adder.

The signal from the carry to the output carry (Ci+1) propagates through 2 gate levels

If there are four full-adders in the parallel adder, the output carry C5 would have 2*4=8 gate levels from C1 to C5.

The total propagation time in the adder would be the propagation time in one half adder plus eight gate levels.

For an n-bit parallel adder, there are 2n gate levels for the carry to propagate through.

The carry propagation time is a limiting factor on the speed with which two numbers are added in parallel.

All other arithmetic operations are implemented by successive additions, the time consumed during the addition process is very critical.

One way to reduce the carry propagation delay time is to employ faster gates with reduced delays

Another solution is to increase the equipment complexity in such a way that the carry delay time is reduced.

The most widely used technique employs the principle of look-ahead carry.

Look-ahead carry

If we define two variables:

Gi is called a carry generated and it produced an output carry when both Ai and Bi one.

Pi is called a carry propagate because it is the term associated with the propagation of the carry

to

The output sum and carry can be expressed as:

The boolean functions for the carry output of each stage are:

Circuit diagram of a look–ahead carry generator

4-bit Full-adders with look-ahead carry