Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

1 NITTTR, Chandigarh EDIT-2015

Binary Division Algorithms based on VedicMathematics: A Review

1Satnam Singh Shergill, 2Arvind Kumar1,2Dept. of Electronics and Communication, U.I.E.T., P.U., Chandigarh

ABSTRACT – With ever increasing demand of speed,accuracy and space we need better hardware and software.Software can be made better by making faster algorithms. Asfar as arithmetic algorithms are concerned in digitalhardware, division is the least used one, computers experienceperformance degradation if division is ignored. There arevarious fields in digital world which demand excessivemultiplication and division. For them algorithms based onVedic Mathematics have proved to be much faster than otheralgorithms and there is further room for improvement also,which attracts further attention from researchers working onthese algorithms.

I. INTRODUCTIONToday the computers have evolved very much since theircreation. However, one thing has not changed. The mainfunction of computers is to do the mathematical operationsto run programs. Computers process lots of binary numbersbased addition, multiplication and division. In comparisonto other mathematical operations, division is the least usedoperation. However, if we ignore division, there will beperformance.With increasing reliance on technology in every field likepayment through NFC, cloud data storage etc. we needbetter cryptographic solutions, and elliptic curvecryptography is one of them. But elliptic curvecryptography involves calculations on about 200-600 digitsand for those calculations to be economical we needarithmetic algorithms to be fast and less space consuming.Improving division algorithm is one those tasks.Also, with the ever rising quality of image and videosignals, we need faster algorithms to absorb the effect ofmore calculation delays associated with their processing.Digital Signal Processing is another area which requiresfaster processing of high number of bits.So, there is always need for faster and better algorithms incomputing world.And algorithms based on Vedic Mathematics have provedto be much faster than other algorithms and there is furtherroom for improvement also, which attracts further attentionfrom researchers working on these algorithms.

II. RELATED WORKPrabir Saha et al [1] used Nikhilam NavatascaramamDasatah (NND) sutra of Vedic Mathematics to develop aVedic Divider Architecture for binary numbers and it wasimplemented on spice spectre through existing 90nmCMOS technology. Comparison of new architecture wasdone with digit recurrence, convergence and seriesexpansion based architectures and found improvement of50%, 45% and 41% respectively in vedic architecture.Furthermore power consumption was less by 44%, 35%and 27% respectively. They calculated that EDP(EnergyDelay Product) was reduced by 73% compared with series

expansion based architecture(the best architecture reportedso far).Diganta Sengupta et al[2] used Nikhilam NavatascaramamDasatah (NND) sutra and Parvartya Yojayet sutra todevelop a division algorithm for BCD numbers. Theirwork involved adjusting the divisor and then carrying outother steps of algorithm in which each partial remainderneeded to be normalized. To calculate the time taken fordivision, each division was iterated 10,000 times at eachrun of the program and compared the time taken by thealgorithm with that of Non Restore Type divisionalgorithm for the same set of divisors and dividends. It wasfound that for 2 digit divisor and dividend vedic divisiontook 0.150µs whereas Non Restore Type division took0.800µs. For 15 digit dividend and 6 digit divisor vedicdivision took 2.490µs and Non Restore Type division took49.290µs. It was seen that the difference in time takenincreased with the increase in number of digits provingvedic division much better in division involving largenumber of digits.Soma BhanuTej[3] of IBM Systems and Technology Groupapplied Parvartya Yojayet sutra of Vedic Mathematics todevelop a high performance divider and comparison ofstatic timing analysis was done between vedic divider andconventional divider. A 32 bit dividend and 16 bit divisorbinary vedic divider was synthesised using 180nm and32nm standard cell libraries on Cadence nclauch andcomparison was done with conventional divider and it wasfound that vedic divider saved power in the range of109mW and was ~7 times faster and area occupied was~13 times lesser than conventional divider.Ratiranjan Senapati et al[4] implemented Parvartya Yojayetsutra vedic divider using Xilinx ISE on 90nm CMOStechnology. They implemented 8 bit binary dividend by 4bit binary divisor circuitry and found that propagationdelay was only ~19.9ns and consumed ~34mW power.Compared to repetitive subtraction method this algorithmhad ~46% less propagation delay and consumed ~27% lesspower.Shantanu Oke et al[5] used another Vedic Mathematicssutra called Dhwajam sutra to develop Distinctive DivisionAchitecture and the algorithms was implemented on Xilinx8.1 ISE and they tested the results on Spartan 3 FPGAplatform also. Comparing their algorithm with Newton-Raphson algorithm, it was stated that their algorithm wasmuch less complex and needed less number of steps andtheir was no need of look up table in their algorithm as wastheir in Newton-Raphson and SRT algorithm.R. Thamil Chelvan and S. Roobini Priya[6] implementedRSA encryption/ decryption algorithm using Dhvajankasutra also called Dhwajam sutra for fixed and floatingpoint binary numbers. They implemented the algorithm onFPGA using Xilinx Spartan library using Verilog HDL. Itwas found that gate delay for RSA circuitry using 8x8

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

NITTTR, Chandigarh EDIT -2015 2

overlay multiplier architecture and 16 bit by 16 bit vedicdivision was 1.507 µs whereas for Restoring Type divisionalgorithm the gate delay was 2.838 µs and for Non RestoreType division algorithm it was 2.828 µs.Najib Ghatte et al[7] used Vedic Mathematics to implementa IEEE 754 single precision floating point divisionalgorithm using Verilog HDL and simulations were doneusing ModelSim SE Plus 6.5. It was then synthesised forVirtexTM -5 FPGA family device XC5VLX30. It wasfound that there was about 12% improvement in utilizationof the resources as compared to Restoring/ Non Restoringtype division algorithms. The combinational delay was just5.405ns and power consumption was reduced to 2mWwhereas traditional ALU’s consume more power.Surabhi Jain et al[8] developed high speed deconvolutionalgorithm using Binary division algorithms based on VedicMathematics. They used Nikhilam and Parvartya sutra andimplementation was done on Xilinx ISE using VerilogHDL. Simulated results showed a reduction in delay of19% as compared to conventional methods.

III. CONCLUSIONIn this work, our focus was on the application of VedicMathematics for binary fixed point and floating pointdivisions. The work done by the authors referred to in thiswork has proven that Vedic Division algorithms can beused for the development of faster and less powerconsuming devices and also it has been shown that the areaconsumed is less in Vedic Division implementations ascompared to other algorithms which makes thesealgorithms more suitable for mobile application becausemobile devices need to have required functionality at theleast possible power and space consumption.

REFERENCESPrabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat(2011) ‘Vedic Divider: Novel Architecture (ASIC) for High Speed VLSIApplications’, International Symposium on Electronic System Design.Diganta Sengupta, Mahamuda Sultana and Atal Chaudhuri (2013) ‘Vedivision – A Fast BCD Division Algorithm Facilitated by VedicMathematics’, International Journal of Computer Science & InformationTechnology, Vol. 5, No. 4, pp.67-80.Soma BhanuTej, IBM Systems and Technology Group, Bangalore, India.Ratiranjan Senapati, Bandan Kumar Bhoi, Manoranjan Pradhan (2013)‘Novel Binary Divider Architecture for high speed VLSI applications’,Proceedings of 2013 I.E.E.E. Conference on Information andCommunication Technologies.Shantanu Oke, Suraj Lulla, Prathamesh Lad (2014) ‘VLSI (FPGA)Design for Distinctive Division Architecture using the Vedic Sutra‘Dhwajam’’, International Conference on Devices, Circuits andSystems(ICDCS).R. Thamil Chelvan, S. Roobini Priya (2013), ‘Implementation of FixedAnd Floating Point Division Using Dhvajanka Sutra’, InternationalJournal of VLSI and Embedded Systems-IJVES, Vol. 04, Issue 02, pp.234-237.Najib Ghatte, Shilpa Patil, Deepak Bhoir (2014) ‘Single PrecisionFloating Point Division’, IRF International Conference.Surabhi Jain, Mukul Pancholi, Harsh Garg, Sandeep Saini (2014) ‘BinaryDivision Algorithm and High Speed Deconvolution Algorithm(Based onAncient Indian Vedic Mathematics)’, IEEE.