Benefits of cryo-implantation for 28 nm NMOS advanced junction formation

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2012 Semicond. Sci. Technol. 27 045003

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Semicond. Sci. Technol. 27 (2012) 045003 (4pp) doi:10.1088/0268-1242/27/4/045003

Benefits of cryo-implantation for 28 nmNMOS advanced junction formationC L Yang1, C I Li1, G P Lin1, R Liu1, B C Hsu1, M Chan1, J Y Wu1,B Colombeau2, B N Guo2, H J Gossmann2, T Wu2, W Feng2, H L Sun2

and S Lu2

1 United Microelectronics Corp., Advanced Technology Development Division, Tainan 744, Taiwan2 Applied Materials - Varian Semiconductor Equipment, 35 Dory Road, Gloucester, MA 01930, USA

E-mail: Chan_Lon_Yang@umc.com and Baonian_Guo@amat.com

Received 14 October 2011, in final form 4 December 2011Published 22 February 2012Online at stacks.iop.org/SST/27/045003

AbstractIn this paper, the integration benefits from cryogenic NMOS source drain extension implantson a state-of-the-art 28 nm logic flow are demonstrated and discussed. It is shown that devicebenefits, such as improved short channel effect, drain-induced barrier lowering and staticrandom access memory yield improvement, can be achieved via damage engineering andenhanced dopant halo activation.

(Some figures may appear in colour only in the online journal)

1. Introduction

Ultra shallow junction (USJ) formation in the source/drainextension (SDE) is one of the main challenges ascomplementary metal-oxide-semiconductor devicesdownscaled into the 28 nm technology and beyond. Totake full advantage of device enhancement from high-k/metalgate with stress-induced carrier mobility, there is a clearneed to continuously improve the short channel effect (SCE).The impact of USJ formation process on pocket profileredistribution is critical for SCE and threshold voltage (Vth)variability. For channel dopant, n-type field effect transistor(nFET) devices use p-type dopant and boron transientenhanced diffusion (TED) in the channel region plays animportant role in nFET Vth variation. Continuous USJ scalingrequires lower spike rapid thermal process (RTP) temperature,which induces inactive boron clustering and TED in thechannel/halo region. To maintain acceptable SCE, a higherboron pocket dose is required, but this results in degraded Vthvariation for scaled USJ devices [1].

Defects from pre-amorphization implant (PAI) remaineven after the source/drain (SD) anneal with RTP andmillisecond laser anneal (msec LSA). These residue defectsare responsible for device leakage. The aggressive USJ scalingcan often lead to an increase in junction leakage and staticrandom access memory (SRAM) yield loss, especially when

combining NiPt–silicide integration. This represents a majorchallenge for low operating power technologies. A variety ofprocesses, such as msec LSA anneal or ultra-low temperatureannealing with microwave for NiPt–silicide formation [2, 3],have been evaluated to overcome the junction leakage issue.

In this paper, the challenges for 28 nm node SCEimprovement and junction leakage are discussed. The SCEimprovement with drain-induced barrier lowering (DIBL)reduction from better halo activation and NiPt-silicide-related junction leakage reduction are achieved through cryo-implantations with conventional integration processes. Thisnovel cryo-implantation technique minimizes process changesand is extendable to future technology nodes.

2. NMOS USJ formation and device fabrication

For device DIBL and junction leakage studies, the cryo-implants for SDE formation followed by thermal annealtreatments (including RTA and msec LSA) are evaluated.Figure 1 describes the process steps and implant sequencesfor NMOS formation.

To maintain abrupt junction profiles, Ge PAI and carbonco-implants were applied before the BF2 halo implant.The incorporated carbon helps to suppress boron TEDand enhances dopant activation as carbon forms interstitialclusters and reduces the formation of extended defects [4, 5].

0268-1242/12/045003+04$33.00 1 © 2012 IOP Publishing Ltd Printed in the UK & the USA

Semicond. Sci. Technol. 27 (2012) 045003 C L Yang et al

Figure 1. 28 nm nFET device flow with advanced stress formationand anneals for device evaluation and leakage measurements.

Cryo-implantation (at −100 ◦C) for amorphization from Geand As implant steps is evaluated with the same process flowto compare with normal room temperature (RT) implantation.The amorphous layer thickness and interface roughness aremeasured using transmission electron microscopy (TEM).Dopant diffusion is evaluated by secondary ion massspectroscopy (SIMS) profile measurements. End of range(EOR) defect positions and density can be monitored by carbonpeak depth/concentration in SIMS profiles.

Process simulations using Synopsys Sentaurus software[6] have been employed to get further physical understandingon the benefits of low temperature implant for junctionengineering. This advanced technology computer-aided design(TCAD) simulation accounts for the impact of point defects,impurity and interaction with dopants upon annealing.

As shown in figures 2(a) and (b), after annealed SIMSprofiles for baseline Ge + C + BF2 + As and Ge(cryo) + C + BF2 + As (cryo) implants are measured andsimulated, profiles are plotted against depth. SIMS profilesclearly indicate that the cluster carbon peak position has shifteddeeper and further away from the surface, which reflectsthe thicker amorphous layer thickness as previously reported[7]. In the near As peak implant area, the cryo-implant hasless boron segregation than the RT amorphization implant.It is well known that carbon traps silicon interstitials [8].Upon annealing, both boron interstitial movement and inactiveboron interstitial cluster (BIC) formation will be reduced [9].Figure 2(b) shows that all observed major SIMS features can bereproduced by TCAD simulation. Figure 2(c) shows simulateddefect profiles from RT and cryo-temperature amorphizationimplants. It is indicated that cryo-implants reduce the netexcess of interstitials available for EOR nucleation.

(a) (b)

(c)

Figure 2. nSDE arsenic, carbon and boron profile comparisons with RT versus only Ge/As cryo-implants. (a) SIMS profiles on bare wafers,(b) simulated profiles and (c) simulated defect profiles showing reduced net excess of interstitial with cryo-implants.

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Semicond. Sci. Technol. 27 (2012) 045003 C L Yang et al

(a) (b)

Figure 3. Comparisons of (a) Vth roll-off, (b) DIBL for RT versus cryo-implants with different halo dosage.

The modulation of boron dopant distribution and implant-induced defect profiles has been included in the 28 nm deviceflow as described in figure 1. Improvement in short channelcharacteristics is obtained with cryo-implants compared to RTcontrol conditions. The SCE improvement is in agreementwith the interstitial reduction and better pocket implant boronactivation. As shown in figure 2(c), >35% interstitial density

reduction (RT implant at 7.2 × 14 cm–2 versus −100 ◦Cimplant at 4.5 × 14 cm–2) can be obtained from theprocess TCAD simulation. Higher Vth and improved SCEwere observed with cryo-implants which indicate betterBF2 halo activation from defect reduction. Approximately,10% BF2 dosage reduction for halo pocket implant was appliedto achieve the same Vth target and capacitance overlap. The

(a) (b)

(c) (d )

Figure 4. TEM (a, b) and TCAD (c, d) amorphization thickness comparison using either RT (a, c) or cryo-temperature (b, d) implants forSDE formation (RT baseline Ge + C + BF2 + As versus Ge (cryo) + C + BF2 + As (cryo)). Cryo-implants were done at −100 ◦C.Amorphization thickness is in good agreement between TCAD and TEM results for both RT and cryo-implants.

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Semicond. Sci. Technol. 27 (2012) 045003 C L Yang et al

(a)

(b)

Figure 5. (a) Typical image for defects caught by electron beammetrology. (b) Comparisons of defect counts (Arb. Unit) from RTand cryo-implant.

halo dose reduction indirectly results in mobility improvement,as shown in figure 3(a). Figure 3(b) highlights the reduction ofDIBL using cryo-implants. The Vth variation can also benefitfrom the lower halo BF2 dosage [1], and the results will bereported in future.

Figures 4(a) and (b) show TEM images of NMOS crosssection and 2D process simulation results (figures 4(c) and (d))for RT and cryo-temperature implants for NMOS formation.The measured TEM amorphization thickness comparisonbetween the RT and cryo-implants is in good agreementwith 2D simulation results. We believe that the above devicebenefits are due to the reduction of EOR defects (thanksto the deeper amorphization layer thickness with smootheramorphous/crystalline interface) [10], and the potential Vthvariation benefits by reduced BF2 halo dosage from theimprovements of boron activation.

3. Junction leakage with NiPt–silicide integration

Another indicator for implant defect reduction can beseen from junction leakage, resulting from NiPt–silicideintegration. It is known that nickel silicide-related ‘pipe’defects are formed from the source to the gate and fromthe gate to the drain, especially in the NMOS devices. Theanomalous lateral growth of the Ni silicide toward the channelregion occurs during the rapid-thermal-annealing process inthe presence of highly damaged Si lattice. The Si defectenhances the diffusion of the Ni, and the Ni piping formationcan be significantly reduced as the Si defect pathways aredecreased [11].

For the Ni-piping-related defects and N+/P-well junctionleakage, we have used inline metrology with an electron

beam inspection system by detection of the gray level of thetungsten plug (W-plug) in the defect images of post-tungstenchemical mechanical polish inspection [12]. Leakage resultsof wafer acceptance tests show a strong correlation with thee-beam inspection results. Failure analysis results reveal thatthe junction leakage is caused by lateral diffusion of nickelsilicide underneath the spacer. The extrusion length correlateswith the gray level of the tungsten plug [12]. Figure 5(a) is atypical EBI contrast defect image obtained from post-tungstenCMP inspection. Figure 5(b) shows that the EBI contrastdefect counts have been significantly reduced with the cryo-implantation, indicating a significant Si defect reduction withNiPt–silicide integration.

4. Conclusions

The integration benefits of cryogenic temperature ionimplant on a state-of-the-art 28 nm logic device have beendemonstrated. It is shown that higher BF2 halo pocket implantactivation and EOR defect reduction using cryo-implants resultin both DIBL and NiPt–Silicide integration-related junctionleakage reduction. The lower pocket dosage with the sametarget Vth indirectly improves the SCE, lower DIBL, bettermobility, as well as reduced Vth variations. The NiPt–silicidejunction leakage reduction was also demonstrated via the inlinee-beam inspection. Cryo-implants appear to be a powerfultechnique to meet 28 nm NMOS device, SRAM leakage andmargin requirements.

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