benchtop logic analyzersproduct

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The HP 1660-Series Benchtop Logic Analyzers Product Specifications and Characteristics Technical Data Finding the cause of difficult problems fast. There is little room for error in the schedules for design projects today. You need test equipment that can locate the cause of a problem quickly and with certainty. The HP 1660-series logic analyzers help you rapidly troubleshoot elusive hardware failures, verify proper bus operation, and debug software during real-time execution. Choose a model with 34, 68, 102 or 136 logic analyzer channels. They all have enough timing and state analysis speed to handle even high-performance applications. Then consider adding a built-in, 2-channel oscilloscope to show signal parametrics – especially when the logic analyzer locates a failure. We think you will agree that these logic analyzers have the right combination of performance, flexibility, and ease of use to help you solve difficult problems fast. Oscilloscope Key Specifications and Characteristics ____________________________________ Model Number HP 1660AS, HP 1661AS, HP 1662AS & HP 1663AS ____________________________________ Channels 2 ____________________________________ Maximum Sample 1 GSa/s per channel Rate ____________________________________ Bandwidth dc to 250 MHz (dc coupled) ____________________________________ Rise Time 1.4 ns ____________________________________ Vertical Resolution 8 bits ____________________________________ Memory Depth per 8k samples Channel _____________________________________ Logic Analyzer Key Specifications and Characteristics _______________________________________________________________________ Model Number HP 1660A,AS HP 1661A,AS HP 1662A,AS HP 1663A,AS HP 1664A _______________________________________________________________________ State and Timing 136 102 68 34 34 Channels _______________________________________________________________________ Timing Analysis Conventional: 250 MHz all channels, 500 MHz half channels Transitional: 125 MHz all channels, 250 MHz half channels Glitch: 125 MHz half channels _______________________________________________________________________ State Analysis 100 MHz, all channels 50 MHz Speed _______________________________________________________________________ State Clocks/ 6 6 4 2 2 Qualifiers _______________________________________________________________________ Memory Depth 4K per channel, 8K in half-channel modes per Channel _______________________________________________________________________ • Graphical menus are displayed on a gray-scale CRT • Front-panel keypad, mouse and optional keyboard human interfaces • 3.5 inch high-density flexible disk drive supports LIF and DOS formats • New, advanced inverse assem- blers • Store data as ASCII files and screen images in TIFF, PCX and PostScript TM formats • New, graphical trigger macros make trigger setup easier • Fully programmable H PostScript TM is a trademark of Adobe Systems Incorporated. Figure 1 14.5” (367 mm) 8.1” (205 mm) 17.3” (440 mm) Weight 26 lbs. (11.8 kg) 13.0” (330 mm)

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Page 1: Benchtop Logic AnalyzersProduct

The HP 1660-SeriesBenchtop Logic Analyzers

Product Specificationsand Characteristics

Technical Data

Finding the cause of difficult problems fast.There is little room for error in the schedules for design projectstoday. You need test equipment thatcan locate the cause of a problemquickly and with certainty.

The HP 1660-series logic analyzershelp you rapidly troubleshoot elusive hardware failures, verifyproper bus operation, and debugsoftware during real-time execution.

Choose a model with 34, 68, 102 or136 logic analyzer channels. Theyall have enough timing and stateanalysis speed to handle even high-performance applications.Then consider adding a built-in, 2-channel oscilloscope to showsignal parametrics – especiallywhen the logic analyzer locates a failure.

We think you will agree that theselogic analyzers have the right combination of performance, flexibility, and ease of use to helpyou solve difficult problems fast.

Oscilloscope Key Specifications and Characteristics

____________________________________Model Number HP 1660AS, HP 1661AS,

HP 1662AS & HP 1663AS____________________________________Channels 2____________________________________Maximum Sample 1 GSa/s per channelRate____________________________________Bandwidth dc to 250 MHz

(dc coupled)____________________________________Rise Time 1.4 ns____________________________________Vertical Resolution 8 bits____________________________________Memory Depth per 8k samplesChannel_____________________________________

Logic Analyzer Key Specifications and Characteristics_______________________________________________________________________Model Number HP 1660A,AS HP 1661A,AS HP 1662A,AS HP 1663A,AS HP 1664A_______________________________________________________________________State and Timing 136 102 68 34 34Channels_______________________________________________________________________Timing Analysis Conventional: 250 MHz all channels, 500 MHz half channels

Transitional: 125 MHz all channels, 250 MHz half channelsGlitch: 125 MHz half channels_______________________________________________________________________

State Analysis 100 MHz, all channels 50 MHzSpeed_______________________________________________________________________State Clocks/ 6 6 4 2 2Qualifiers_______________________________________________________________________Memory Depth 4K per channel, 8K in half-channel modesper Channel_______________________________________________________________________

• Graphical menus are displayedon a gray-scale CRT

• Front-panel keypad, mouse andoptional keyboard human interfaces

• 3.5 inch high-density flexibledisk drive supports LIF andDOS formats

• New, advanced inverse assem-blers

• Store data as ASCII files andscreen images in TIFF, PCXand PostScriptTM formats

• New, graphical trigger macrosmake trigger setup easier

• Fully programmable

H

PostScriptTM is a trademark of AdobeSystems Incorporated.

Figure 1

14.5” (367 mm)

8.1”(205 mm)

17.3” (440 mm)

Weight 26 lbs. (11.8 kg)

13.0” (330 mm)

Page 2: Benchtop Logic AnalyzersProduct

HP 1660-SeriesGeneral Product Information

___________________________________________

Human Interface___________________________________________

Front Panel A knob and keypads makeup the front-panel humaninterface. Keys includecontrol, menu, display nav-igation, and alpha-numericentry functions.

___________________________________________

Mouse An HIL, 3-button mouse(HP p/n A2838A) is shippedas standard equipment. Itprovides full instrumentcontrol. Knob functionalityis replicated by holdingdown the center buttonand moving the mouse leftor right.

___________________________________________

Keyboard The logic analyzer can alsobe operated using an HILkeyboard. Order the HPLogic Analyzer KeyboardKit, model number E2427A.

___________________________________________

Input/Output, Control, and Printing___________________________________________

I/O Ports The HP 1664A ships with aparallel (Centronics) print-er port as standard equip-ment; RS-232 and HP-IBports are optional. All othermodels ship with RS-232and HP-IB as standardequipment but do not havea parallel port.

___________________________________________

Program- Each instrument is fullymability programmable from a com-

puter via HP-IB and RS-232connections. This featureis standard on all modelsexcept the HP 1664A.Order option 020 for HP 1664A programmability.

___________________________________________

___________________________________________

HP Printers which use the Printer HP Printer Control Support Language (PCL) and have

an HP-IB, RS-232 or paral-lel* interface are support-ed: HP DeskJet, LaserJet,QuietJet, PaintJet, andThinkJet models.* HP 1664A only

___________________________________________

Alternate The Epson FX80, LX80 and Printer MX80 printers with anSupported RS-232 interface are

supported in the Epson 8-bit graphics mode.

___________________________________________

Hard Copy Screen images can be Output printed in black and white

from all menus using thePrint field. State or timinglistings can be also beprinted in full or part (start-ing from center screen)using the Print All selection.

___________________________________________

Mass Storage Files and Software___________________________________________

Updating the For models other than the Operating HP 1664A, the operating System system resides in Flash

ROM and can be updatedfrom the flexible disk drive.The HP 1664A boots fromdisk and requires only adisk change to update theoperating system.

___________________________________________

Mass Storage A high density (1.44-Mbyte), 3.5" flexible diskdrive supports LIF and DOSformats.

___________________________________________

Screen Image An image file of any display Files screen can be stored to

disk via the display's Printfield. Black & white TIFF,PCX, PostScript, and gray-scale TIFF file for-mats are available.

___________________________________________

___________________________________________

ASCII Data State or timing listingsFiles can be stored as ASCII files

on a flexible disk via the dis-play's Print field. These filesare equivalent in characterwidth and line length to hard-copy listings printed via thePrint All selection.

___________________________________________

Configuration Logic analyzer and oscillo-and Data scope files that includeFiles configuration and data infor-

mation (if present) are encod-ed in a binary format. Theycan be stored to or loadedfrom a flexible disk.

___________________________________________

Recording of Binary format Acquisition and configuration/data files areStorage Times stored with the time of

acquisition and the time ofstorage for all models exceptthe HP 1664A, which does nothave a real-time clock.

___________________________________________

Acquisition Arming___________________________________________

Initiation Arming is started by Run,Group Run, or the Port InBNC.

___________________________________________

Cross Arming Analyzer machines and the oscilloscope can cross-arm each other.

___________________________________________

Output An output signal is provid-ed at the Port Out BNC.

___________________________________________

Port In/Out___________________________________________

PORT IN Port In is a standard BNC Signal and connection. The input Connection operates at TTL logic

signal levels. Rising edgesare valid input signals.

___________________________________________

PORT OUT Port Out is a standard BNCSignal and connection with TTL logic Connection signal levels. A rising edge

is asserted as a valid output.___________________________________________

Skew Adjustmentand Arming Times___________________________________________

Skew Correction factors for Adjustment nominal skew between

displayed timing and oscil-loscope signals are builtinto the operating system.Additional correction forunit-by-unit variation canbe made using the Skewfield. An entered skewvalue affects the next (notthe present) acquisitiondisplay.

___________________________________________

________________________________________________________________________________Model Number Logic Analyzer Built-in, 2-Channel

Channels Oscilloscope________________________________________________________________________________HP 1660A 136 No________________________________________________________________________________HP 1660AS 136 Yes________________________________________________________________________________HP 1661A 102 No________________________________________________________________________________HP 1661AS 102 Yes________________________________________________________________________________HP 1662A 68 No________________________________________________________________________________HP 1662AS 68 Yes________________________________________________________________________________HP 1663A 34 No________________________________________________________________________________HP 1663AS 34 Yes________________________________________________________________________________HP 1664A 34 No________________________________________________________________________________

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Page 3: Benchtop Logic AnalyzersProduct

___________________________________________

PORT IN Arms 15 ns typical delay from Logic signal input to a don't Analyzer [1] care logic analyzer

trigger.___________________________________________

PORT IN Arms 40 ns typical delay from Oscilloscope signal input to an immedi-

ate oscilloscope trigger;not available when oscillo-scope is in time-qualifiedpattern triggering mode.

___________________________________________

Logic Analyzer 120 ns typical delay from Arms PORT logic analyzer trigger to OUT [1] signal output.___________________________________________

Oscilloscope 60 ns typical delay fromArms PORT oscilloscope trigger to OUT signal output.___________________________________________

Operating Environment___________________________________________

Power 115 Vac or 230 Vac, –22% to+10%, single phase, 48-66Hz, 320 VA max

___________________________________________

Temperature Instrument, 0° to 50° C (+32° to 122° F). Disk media,10° to 40° C (+50° to 104°F).Probes and cables, 0° to65° C (+32° to 149° F)

___________________________________________

Humidity Instrument, up to 95%, relative humidity at +40° C(+140° F). Disk media, 8% to80% relative humidity.

___________________________________________

Altitude To 460 m (15,000 ft)___________________________________________

Vibration: Random vibrations 5-500Hz,Operating 10 minute per axis,

~ 0.3 g (rms).___________________________________________

Vibration: Random vibrations 5-500Hz,Non Operating 10 minutes per axis,~ 2.41 g

(rms); and swept sine reso-nant search, 5-500 Hz, 0.75 g (0-peak), 5 minuteresonant dwell @ 4 reso-nances per axis.

___________________________________________

Physical Factors___________________________________________

Weight 26 lbs.. (11.8 kg)_________________________________Dimensions See figure 1 on pg. 1_________________________________Safety IEC 348/ HD 401,

UL 1244, andCSA Standard C22.2 No. 231 (series M-89)_________________________________

___________________________________________

EMCCISPR 11:1990/EN 55011 (1991):

Group 1 Class AIEC 801-2:1991/EN 50082-1 (1992):

4kV CD, 8 kV ADIEC 801-3:1984/EN 50082-1 (1992): 3 V/mIEC 801-4:1988/EN 50082-1 (1992): 1kV___________________________________________

Logic Analyzer Probes___________________________________________

Input 100 kΩ ±2%Resistance___________________________________________

Input approx. 8 pF (see figure)Capacitance___________________________________________

___________________________________________

Minimum Input 500 mV peak-to-peakVoltage Swing___________________________________________

Minimum Input 250 mV or 30% of input Overdrive amplitude, whichever is

greater___________________________________________

Threshold –6.0 V to +6.0 V in 50-mV Range increments___________________________________________

Threshold Threshold levels may beSetting defined for pods

(17-channel groups) on an individual basis

___________________________________________

Threshold ± (100 mV +3% of Accuracy* threshold setting)___________________________________________

Input Dynamic ± 10 V about the thresholdRange___________________________________________

Maximum ± 40 V peakInput Voltage___________________________________________

+5 V Accessory 1/3 amp maximum per podCurrent ___________________________________________

Channel Each group of 34 channelsAssignment (a pod pair) can be

assigned to Analyzer 1, Analyzer 2 or remain unassigned.

___________________________________________

___________________________________________

State Analysis___________________________________________

Maximum State 100 MHz all models exceptSpeed* HP 1664A, which is 50 MHz___________________________________________

Channel Count HP 1660A, AS 136/68[1] HP 1661A, AS 102/51

HP 1662A, AS 68/34HP 1663A, AS 34/17HP 1664A 34/17

___________________________________________

Memory Depth 4096/8192 samplesper Channel [1]____________________________________________

State Clocks HP 1660A, AS 6 clocksHP 1661A, AS 6 clocksHP 1662A, AS 4 clocksHP 1663A, AS 2 clocksHP 1664A 2 clocks

Clocks can be used byeither one or two state ana-lyzers at any time, exceptfor the 1663A, 1663AS, and1664A models, which canhave only one state ortiming analyzer. Clockedges can be ORed togeth-er and operate in singlephase, two-phase demulti-plexing, or two-phasemixed mode. Clock edge isselectable as positive, neg-ative, or both edges foreach clock.

___________________________________________

State Clock The high or low of up to 4 Qualifier of the 6 clocks can be

ANDed or ORed with theclock specification._________________________________

Setup/Hold* [2] one clock, 3.5/0 ns to 0/3.5 ns one edge (in 0.5 ns increments)

one clock, 4.0/0 ns to 0/4.0 ns both edges (in 0.5 ns increments)

multi-clock, 4.5/0 ns to 0/4.5 ns multi-edge (in 0.5 ns increments)_________________________________

Minimum 3.5 nsState Clock Pulse Width* [2]_________________________________Minimum 10.0 nsMaster to Master Clock Time* [2]_________________________________Minimum 10.0 nsSlave to SlaveClock Time [2]_________________________________Minimum 0.0 nsMaster to SlaveClock Time [2]_________________________________

HP 1660-seriesLogic Analyzer Specificationsand Characteristics

[1] Time may vary depending upon themode of logic analyzer operation.

RT = 250Ω

High Frequency Model for Probe Inputs

RIN = 100kΩCTG = 1 pF Z0 = 150Ω

CCOMP = 7.5 pF

* Warranted Specification

3

Page 4: Benchtop Logic AnalyzersProduct

_________________________________Minimum 4.0 nsSlave to Master Clock Time [2]_________________________________

Clock 4.0/0 ns (fixed)Qualifiers Setup/Hold [3]_________________________________

State Counts the number of Tagging [3] qualified states between

each stored state.Measurement can be shownrelative to the previous stateor relative to trigger. Max.count is 4.29

× 109.

State Tag 0 to 4.29 × 109 (± 0 counts)Count

State Tag 1 countResolution___________________________________________

Time Measures the time betweenTagging [3] stored states, relative to

either the previous state orto the trigger. Max. timebetween states is 34.4 sec.Min. time between states is8 ns.

Time Tag 8 ns to 34.4 secondsCount ± (8 ns + 0.01% of time tag

value)

Time Tag 8 ns or 0.1%Resolution (whichever is greater)___________________________________________

Timing Analysis___________________________________________

Conventional Data stored at selected Timing sample rate across all

timing channels.

Maximum 250 MHz / 500 MHzTiming Speed [1]

Channel HP 1660A, AS 136/68Count [1] HP 1661A, AS 102/51

HP 1662A, AS 68/34HP 1663A, AS 34/17HP 1664A 34/17

Sample 4 ns/2 ns minimum, Period [1] 8.38 ms maximum

Memory Depth 4096/8192 samplesper Channel [1]

Time Covered Sample period × memory by Data [1] depth 16.3 µs min,

34.3 sec/68.6 sec max_________________________________

___________________________________________

Transitional Sample is stored in acqui-Timing sition memory only when

the data changes. A timetag stored with eachsample allows reconstruc-tion of waveform display.Time covered by a fullmemory acquisition varieswith the number of patternchanges in the data.

Maximum 125 MHz/250 MHzTiming Speed [1]

Channel HP 1660A, AS 136/68Count [1] HP 1661A, AS 102/51

HP 1662A, AS 68/34HP 1663A, AS 34/17HP 1664A 34/17

Sample 8 ns/4 nsPeriod [1]

Time Covered 16.3 µs minimum,by Data [1] 9.7 hrs./6.5 hrs. maximum

Maximum Time 34.3 sBetween Transitions

Number of 1023-2047/682-4094Captured Depending on input signalsTransitions [1]___________________________________________

Glitch Data sample and glitch Capture Mode information is stored every

sample period

Maximum 125 MHz Timing Speed

Channel Count HP 1660A, AS 68HP 1661A, AS 51HP 1662A, AS 34HP 1663A, AS 17HP 1664A 17

Sample Period 8 ns minimum, 8.38 msmaximum

Minimum Glitch 3.5 nsWidth*

Maximum Sample Period – 1 nsGlitch Width

Memory Depth 2048 samplesper Channel

Time Covered Sample Period × 2048:by Data 16.3 µs minimum,

17.1 sec maximum___________________________________________

Time Interval Accuracy___________________________________________

Sample Period ± 0.01%Accuracy___________________________________________

Channel-to- 2 ns typical,Channel Skew 3 ns maximum___________________________________________

Time Interval ± (Sample Period Accuracy + channel-to-channel

skew + 0.01% of timeinterval reading)

___________________________________________

Maximum Sample Period 2-8 ns : Delay 8.389 msAfter Sample Period > 8 ns:Triggering 1,048,575 × sample period___________________________________________

Trigger Specifications___________________________________________

Trigger Macros Trigger setups can beselected from a catego-rized list of triggermacros. Each macro isshown in graphical formand has a written descrip-tion. Macros can bechained together tocreate a custom triggersequence.

___________________________________________

Pattern Each recognizer is the Recognizers AND combination of bit

(0,1, or X) patterns in eachlabel.

Pattern 10Recognizers

Pattern Width HP 1660A, AS 136 (in channels) HP 1661A, AS 102

HP 1662A, AS 68 HP 1663A, AS 34 HP 1664A 34

___________________________________________

Minimum 250 MHz and 500 MHz Pattern Timing Modes: 13 ns +and Range channel-to-channel Recognizer skew ≤ 125 MHz TimingPulse Width Modes : 1 sample period

+ 1 ns + channel-to-chan-nel skew + 0.01%

___________________________________________

Range Recognize data which is Recognizers numerically between or on

two specified patterns(ANDed combination ofzeros and/or ones).

Range 2Recognizers

Range Width 32 channels___________________________________________

4

Page 5: Benchtop Logic AnalyzersProduct

____________________________________________

Trace Mode Single mode acquiresdata once per trace spec-ification; repetitive moderepeats single modeacquisitions until Stop ispressed or until patterntime interval or comparestop criteria are met._________________________________

Trigger Displayed as a verticaldashed line in the timingwaveform, state wave-form and X-Y chart dis-plays and as line 0 in thestate listing and statecompare displays._________________________________

Activity Provided in the Indicators Configuration, State

Format, and TimingFormat menus for moni-toring device-under-testactivity while setting upthe analyzer._________________________________

Labels Channels may be groupedtogether and given a 6-character name called alabel. Up to 126 labels ineach analyzer may beassigned with up to 32channels per label. Triggerterms may be given an 8-character name.

___________________________________________

Measurement Functions___________________________________________

Markers Two markers (x and o) areshown as dashed lines inthe display.__________________________________

Time The x and o markers Intervals measure the time interval

between events occur-ring on one or morewaveforms or states (onlyavailable when time tag-ging is on)._________________________________

Delta States The x and o markers mea-sure the number oftagged states betweenany two states._________________________________

Patterns The x or o marker can beused to locate the nthoccurrence of a specifiedpattern before or aftertrigger, or after the begin-ning of data. The o markercan also find the nthoccurrence of a patternbefore or after the xmarker.

_________________________________

____________________________________________

Edge/Glitch Trigger on glitch or edge Recognizers on any channel. Edge can

be specified as rising,falling or either.

Edge/Glitch 2 (in timing mode only)Recognizers

Edge/Glitch HP 1660A, AS 136Width (in HP 1661A, AS 102channels) HP 1662A, AS 68

HP 1663A, AS 34HP 1664A 34

Edge/Glitch Sample Period 2-8 ns: 28 nsRecovery Time Sample Period > 8 ns:

20 ns + sample period____________________________________________

Greater than Sample period 2-8 ns:Duration 8 ns to 8.389 ms. Accuracy (timing only) is –2 ns to +10 ns

Sample period > 8 ns(1 to 2 × 10^20) × sampleperiod. Accuracy is –2 ns+ sample period + 2 ns ±0.01%

____________________________________________

Less than Sample period 2-8 ns:Duration 8 ns to 8.389 ms. Accuracy (timing only) is –2 ns to +10 ns.

Sample period > 8 ns: (1 to2×10^20) × sample period.Accuracy is 2 ns + sampleperiod – 2 ns ± 0.01%

____________________________________________

Qualifier A user-specified term thatcan be any state, no state,any recognizer, (pattern,ranges or edge/glitch), anytimer, or the logical combi-nation (NOT, AND, NAND,OR, NOR, XOR, NXOR) ofthe recognizers and timers.

____________________________________________

Branching Each sequence level has abranching qualifier. Whensatisfied, the analyzer willbranch to the sequencelevel specified.

____________________________________________

Occurrence Sequence qualifier may be Counters specified to occur up to

1,048,575 times beforeadvancing to the next level.Each sequence level hasits own counter.

Maximum 1,048,575Occurrence Count____________________________________________

___________________________________________

Storage Each sequence level has a Qualification storage qualifier that (state only) specifies the states that

are to be stored.____________________________________________

Maximum 125 MHzSequencer Speed

State Sequence 12Levels

Timing 10Sequence Levels____________________________________________

Timers Timers may be Started,Paused, or Continued atentry into any sequencelevel after the first.

Timers 2

Timer Range 400 ns to 500 seconds

Timer 16 ns or 0.1% whichever is Resolution greater

Timer ± 32 ns or ± 0.1%,Accuracy whichever is greater

Timer Recovery 70 nsTime___________________________________________

Data In to 110 ns typicalTrigger OutBNC Port____________________________________________

Acquisition, Measurement and Display Functions___________________________________________

Arming Each analyzer can bearmed by the Run key, theother analyzer, the oscillo-scope (AS models only), orthe Port In. _________________________________

Run Starts acquisition of datain specified trace mode._________________________________

Stop In single trace mode orthe first run of a repetitiveacquisition, Stop haltsacquisition and displaysthe current acquisitiondata. For subsequent runsin repetitive mode, Stophalts acquisition of dataand does not change cur-rent display._________________________________

5

Page 6: Benchtop Logic AnalyzersProduct

_________________________________Statistics x to o marker statistics are

calculated for repetitiveacquisitions. Patternsmust be specified for bothmarkers, and statistics arekept only when both pat-terns can be found in anacquisition. Statistics areminimum x to o time, maxi-mum x to o time, averagex to o time, and ratio ofvalid runs to total runs._________________________________

Compare Performs post-processing Mode bit-by-bit comparison of Functions the acquired state data

and Compare Image data.

Compare Created by copying a Image state acquisition into the

compare image buffer.Allows editing of any bit inthe Compare Image to a 1,x or o.

Compare Each channel (column) in Image the compare image can be Boundaries enabled or disabled via bit

masks in the CompareImage. Upper and lowerranges of states (rows) inthe compare image canbe specified. Any data bitsthat do not fall within theenabled channels and thespecified range are notcompared.

Stop Repetitive acquisitions Measurement may be halted when the

comparison between thecurrent state acquisitionand the current CompareImage is equal or not equal._________________________________

Compare Compare Listing display Mode shows the Compare ImageDisplays and bit masks; Difference

Listing display highlightsdifferences between thecurrent state acquisitionand the Compare Image._________________________________

___________________________________________

Data Entry/Display___________________________________________

Display Modes State Listing, StateWaveforms, State Chart,State Compare Listing,Compare DifferenceListing, Timing Waveforms,Timing Listing, interleavedtime-correlated listing oftwo state analyzers (timetags on), and time-corre-lated State Listing withTiming Waveforms on thesame display._________________________________

State X-Y Plots value of a specified Chart Display label (on y-axis) versus

states or another label (onx-axis). Both axes can bescaled.

Markers Correlated to State Listing,State Compare, and StateWaveform displays.Available as pattern, time,or statistics (with timecounting) and states (withstate counting on).

Accumulate Chart display is not erasedbetween successiveacquisitions._________________________________

State Waveform Displays state acquisitions Display in waveform format.

States/division 1 to 1000 states.

Delay – 8191 to + 8192 states.

Accumulate Waveform display is noterased between succes-sive acquisitions.

Overlay Mode Multiple channels can bedisplayed on one wave-form display line.

Displayed 24 lines maximum on one Waveforms screen. Up to 96 lines may

be specified and scrolledthrough._________________________________

Timing Displays timing acquisi-Waveform tion in waveform format.Display

Sec/div 1 ns to 1000 s; 0.01% resolution.

Delay – 2,500 s to + 2,500 s___________________________________________

___________________________________________

Accumulate Waveform display is noterased between succes-sive acquisitions.

Overlay Mode Multiple channels can be displayed on one wave-form display line. Whenwaveform size set tolarge, the value repre-sented by each waveformis displayed inside thewaveform in the selectedbase.

Displayed 24 lines maximum on one Waveforms screen. Up to 96 lines may

be specified and scrolledthrough._________________________________

Bases Binary, Octal, Decimal,Hexadecimal, ASCII (dis-play only), User-definedsymbols, two's compli-ment._________________________________

Symbols

Pattern User can define a Symbols mnemonic for the specific

bit pattern of a label.When data display isSYMBOL, mnemonic isdisplayed where the bitpattern occurs.

Range User can define a Symbols mnemonic covering a

range of values. Whendata display is SYMBOL,values within the speci-fied range are displayedas mnemonic + offsetfrom base of range.

Number of 1000 maximum.Symbols___________________________________________

[1] Full Channel /Half Channel Modes

[2] Specified for an input signal VH= – 0.9V, VL = – 1.7V, slew rate = 1V/ns, andthreshold = –1.3V

[3] Time or-state-tagging (Count Time or Count State) is available in the full-channel state mode. There is no speedpenalty for tag use. Memory is halvedwhen time or state tags are usedunless a pod pair (34-channel group)remains unassigned in theConfiguration menu.

6

Page 7: Benchtop Logic AnalyzersProduct

__________________________________General Information__________________________________Model HP 1660AS, 1661AS, Numbers 1662AS, 1663AS__________________________________Number of 2Channels__________________________________Maximum 1 GSa/s per channelSample Rate__________________________________Bandwidth dc to 250 MHz[1] [5] (real time, dc coupled)__________________________________Rise Time 1.4 ns[2] [5]__________________________________Vertical 8 bitsResolution__________________________________Memory Depth 8k samples__________________________________

Oscilloscope Probing__________________________________Input Coupling 1 MΩ: ac,dc

50 Ω: dc only__________________________________Input R [5] 1MΩ ± 1%

50Ω ± 1%__________________________________Input C ~ 7pF__________________________________Probes Two HP 10430A probes;Included 10:1, 1 MΩ 6.5 pF__________________________________

Vertical (at BNC)___________________________________________

Maximum Safe 1 MΩ : ±250 VInput Voltage 50 Ω : 5 V rms__________________________________Vertical 1 MΩ: ±250 V Sensitivity (ac + dc, <10 kHz)Range 50 Ω: 5 V rms(1:1 Probe)__________________________________Probe Factors Any integer ratio from

1:1 to 1000:1__________________________________Vertical (dc) ± 1.25% of full scaleGain Accuracy [3]__________________________________dc Offset ± 2V to ± 250VRange (depending on the(1:1 probe) vertical sensitivity)__________________________________dc Offset ± [1.0% of channel offsetAccuracy [5] + 2.0% of full scale]__________________________________Voltage ± [1.25% of full scaleMeasurement + offset accuracyAccuracy [5] + 0.016 V/div]__________________________________Channel-to- dc to 50 MHz – 40 dBChannel 50 MHz to 250 MHz – 30 dBIsolation__________________________________

__________________________________Horizontal__________________________________Time Base 1 ns/div to 5 s/divRange__________________________________Time Base 20 ps ± [(0.005% of ∆t)Resolution + (2 × 10– 6 × delay

setting) + 150 ps]__________________________________Maximum – 4 µs to – 40 sNegative (depending on theAcquisition sample rate)Delay__________________________________

Maximum 16.7 ms to 2.5 ksPositive (depending onAcquisition sample rate)Delay__________________________________Time Interval ± [(0.005% of ∆t)Measurement + (2×10 – 6 × delay setting)Accuracy [4] [5] + 150 ps ]__________________________________Oscilloscope Triggering__________________________________Trigger Level Bounded within channelRange display window__________________________________Trigger dc to 50 MHz: Sensitivity [5] 0.063 × Full Scale

50 MHz to 250 MHz:0.125 × Full Scale__________________________________

Trigger Modes

Immediate Triggers immediately afterarming condition is met.(Arming condition is Run,Group Run, cross armingsignal, or Port In BNCsignal).

Edge Triggers on rising or fallingedge from channel 1 or 2.

Pattern Triggers on entering orexiting logical patternspecified across channels1 or 2. Each channel canbe specified as high (H),low (L), or don't care (X)with respect to the levelsettings in the edge triggermenu. Patterns must be>1.75 ns in duration to be recognized.__________________________________

__________________________________Time-Qualified Triggers on the exiting Pattern edge of a pattern which

meets the user-specifiedduration criterion. Greaterthan, less than, or withinrange duration criterioncan be used. Durationrange is 20 ns to 160 ns.Recovery time after validpatterns with invalid dura-tion is <12 ns.

Events Delay Triggers on the nth edge orpattern as specified by theuser. Time-qualification isapplied only to the 1st of npatterns.__________________________________

Auto-Trigger Self-triggers if no triggercondition is found ~ 50 msafter arming.__________________________________

Measurement Functions__________________________________Time Markers Two markers (x and o)

measure time intervalsmanually, or automaticallywith statistics.__________________________________

Voltage Two markers (a and b) Markers measure voltage and volt-

age differences.__________________________________Automatic Period, frequency, Measurements rise time, fall time, +width,

–width, peak-to-peak voltage, overshoot, and undershoot.__________________________________

[1] Upper bandwidth reduces by 2.5 MHzfor every degree C above 35°C.

[2] Rise time calculated as tr = 0.35 bandwidth

[3] Vertical gain accuracy decreases0.08% per degree C from software calibra-tion temperature.

[4] Specification applies at the maximumsampling rate. At lower rates, replace 150ps in the formula with ( 0.15 × sampleinterval) where sample interval is definedas 1/sample rate.

[5] Specifications (valid within ± 10°C of auto-calibration temperature)

HP 1660-SeriesOscilloscope Specifications and Characteristics

7

Page 8: Benchtop Logic AnalyzersProduct

For more information, call your local HP sales office listed in your telephone directory, or an HP regional office listed below for the location of your nearest sales office.

United States:Hewlett-Packard CompanyTest and Measurement Organization5301 Stevens Creek Blvd.Bldg. 51L-SCSanta Clara, CA 95052-80591 800 452 4844

Canada:Hewlett-Packard Canada Ltd.5150 Spectrum WayMississauga, Ontario L4W 5G1(905) 206 4725

Europe:Hewlett-PackardEuropean Marketing CentreP.O. Box 9991180 AZ AmstelveenThe Netherlands

Japan:Yokogawa-Hewlett-Packard Ltd.Measurement Assistance Center9-1, Takakura-Cho, Hachioji-Shi,Tokyo 192, Japan(81) 426 48 0722

Latin America:Hewlett-PackardLatin American Region Headquarters5200 Blue Lagoon Drive9th FloorMiami, Florida 33126U.S.A.(305) 267 4245/4220

Australia/New Zealand:Hewlett-Packard Australia Ltd.31-41 Joseph StreetBlackburn, Victoria 3130AustraliaMelbourne Caller 272 2555(008) 13 1347

Asia Pacific:Hewlett-Packard Asia Pacific Ltd.17-21/F Shell Tower, Time Square,1 Matherson Street, Causeway Bay,Hong Kong(852) 599 7070

Technical information in thisdocument is subject to changewithout notice.

5963-2172 E 10/94Printed in the U.S.A.

_______________________________________________________________________HP 1660A136-channel benchtop logic analyzerHP 1660AS136-channel analyzer with a built-in, 2-channel oscilloscope_______________________________________________________________________HP 1661A102-channel benchtop logic analyzerHP 1661AS102-channel analyzer with a built-in, 2-channel oscilloscope_______________________________________________________________________HP 1662A68-channel benchtop logic analyzerHP 1662AS68-channel analyzer with a built-in, 2 channel oscilloscope_______________________________________________________________________HP 1663A34-channel benchtop logic analyzerHP 1663AS34-channel analyzer with a built-in, 2-channel oscilloscope_______________________________________________________________________HP 1664AValue-priced 34-channel benchtop logic analyzerOption 020*RS-232 and HP-IB interfaces with programming manualOption 0B5*Quick-Start Training Kit_______________________________________________________________________Option 0B3Service ManualOption 908 or 1CMRackmount KitOption UK9Front panel coverOption W30Three-year extended repair service_______________________________________________________________________HP E2427A HIL Keyboard for logic analyzersHP E2460AS, E2460B, E2461B and E2462BHewlett-Packard-installed upgrade kits (add an oscilloscope or more channels to selected models)_______________________________________________________________________HP 1180B TestmobileHP 35183A Work SurfaceAttaches to HP 1180B Testmobile as a platform for mouse operation_______________________________________________________________________* This option is standard equipment on all models except the HP 1664A.

Ordering InformationH